U.S. patent application number 13/904895 was filed with the patent office on 2013-10-03 for process to improve transistor drive current through the use of strain.
The applicant listed for this patent is Texas Instruments Incorporated. Invention is credited to Dennis D. Buss.
Application Number | 20130260518 13/904895 |
Document ID | / |
Family ID | 35059672 |
Filed Date | 2013-10-03 |
United States Patent
Application |
20130260518 |
Kind Code |
A1 |
Buss; Dennis D. |
October 3, 2013 |
PROCESS TO IMPROVE TRANSISTOR DRIVE CURRENT THROUGH THE USE OF
STRAIN
Abstract
The present invention provides, in one embodiment, a P-type
Metal Oxide Semiconductor (PMOS) device (100). The device (100)
comprises a tensile-strained silicon layer (105) located on a
silicon-germanium substrate (110) and silicon-germanium
source/drain structures (135, 140) located on or in the
tensile-strained silicon layer (105). The PMOS device (100) further
includes a channel region (130) located between the
silicon-germanium source/drain structures (135, 140) and within the
tensile-strained silicon layer (105). The channel region (130) has
a compressive stress (145) in a direction parallel to an intended
current flow (125) through the channel region (130) Other
embodiments of the present invention include a method of
manufacturing the PMOS device (200) and a MOS device (300).
Inventors: |
Buss; Dennis D.; (Dallas,
TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Texas Instruments Incorporated |
Dallas |
TX |
US |
|
|
Family ID: |
35059672 |
Appl. No.: |
13/904895 |
Filed: |
May 29, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11338549 |
Jan 24, 2006 |
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13904895 |
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10818731 |
Apr 6, 2004 |
7023018 |
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11338549 |
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Current U.S.
Class: |
438/199 |
Current CPC
Class: |
H01L 21/823807 20130101;
H01L 29/7848 20130101; H01L 29/7842 20130101; H01L 21/8238
20130101; H01L 21/823814 20130101; H01L 29/1054 20130101 |
Class at
Publication: |
438/199 |
International
Class: |
H01L 21/8238 20060101
H01L021/8238 |
Claims
1. A method of manufacturing Complementary Metal Oxide
Semiconductor (CMOS) integrated circuit include a P-type Metal
Oxide Semiconductor (PMOS) device and an N-type Metal Oxide
Semiconductor (NMOS) device, comprising: epitaxially growing a
tensile-strained silicon layer on a silicon-germanium substrate;
removing portions of the tensile-strained silicon layer and also
removing a volume of material that was part of the underlying
silicon germanium substrate that is outside of a channel region
within the PMOS device of the CMOS, but not removing a volume of
material that was part of the underlying silicon germanium
substrate that is outside of a channel region within the NMOS
device of the CMOS; and epitaxially growing silicon-germanium
source/drain structures on or in the tensile-strained silicon layer
including the volume that was removed of the silicon germanium
substrate.
2. The method as recited in claim 35, wherein the tensile-strained
silicon layer before the removal of the volume has a thickness
between 10 and about 20 nanometers.
3. The method as recited in claim 35, wherein removing includes
removing between one to ten nanometer thickness of the
tensile-strained silicon layer.
4. The method as recited in claim 35, wherein epitaxially growing
the germanium source/drain structures includes depositing a mixture
of silicon and germanium atoms, the mixture having between 30 atom
percent and 50 atom percent germanium.
5. The method as recited in claim 39, further comprising
epitaxially growing silicon-germanium source/drain structures to be
free of physical contact with the silicon-germanium substrate.
Description
TECHNICAL FIELD OF THE INVENTION
[0001] The present invention is directed, in general, to the
manufacture of semiconductor devices and, more specifically, to a
method of fabricating transistor devices having improved drive
currents.
BACKGROUND OF THE INVENTION
[0002] The continuing push to produce faster semiconductor devices
with lower power consumption has resulted in device
miniaturization. In particular, smaller gate oxide thickness and
silicon channel width are conducive to the low voltage and faster
operation of transistor devices, such as complementary metal oxide
(CMOS) transistors. With shrinking process geometries, the use of
new materials is being explored to further reduce power consumption
and increase device switching speeds.
[0003] In an N-type metal Oxide Semiconductor (NMOS) transistor,
for instance, a channel made from a silicon layer that is
epitaxially grown on a silicon-germanium substrate has an increased
electron mobility. This, in turn, allows the production of NMOS
transistors having faster transistor switching speed and higher
drive current.
[0004] Increased electron mobility is thought to be due to the
presence of biaxial tensile strain in the NMOS channel. It is known
that the wider lattice spacing of the silicon-germanium substrate
causes the lattice spacing of silicon atoms in the silicon layer to
be stretched or strained to match that of the silicon-germanium
substrate. Strain in the channel occurs biaxially, that is, in
directions parallel and perpendicular to the flow of current
through the channel.
[0005] In contrast, the use of biaxially tensile-strained silicon
in a P-type Metal Oxide Semiconductor (PMOS) transistor is much
less beneficial. A PMOS channel formed in biaxially tensile
strained silicon has little, if any, improvement in hole mobility
compared to an equivalent channel formed in unstrained silicon.
This is a major barrier to preparing CMOS semiconductor devices on
strained silicon layers, where both PMOS and NMOS transistors are
present. This follows because the drive current of both types of
transistors must be increased to realize an improvement in device
performance. One approach to increase the drive current of PMOS
transistors is to form epitaxial silicon-germanium source/drain
structures that provide uniaxial compressive stress to the channel
in a direction parallel to the electron flow.
[0006] Accordingly, what is needed in the art is an improved method
of manufacturing MOS transistors on strained-silicon that improves
the drive current for both NMOS and PMOS transistors while not
suffering the deficiencies of previous approaches.
SUMMARY OF THE INVENTION
[0007] To address the above-discussed deficiencies of the prior
art, the present invention provides a PMOS device. The PMOS device
comprises a tensile-strained silicon layer located on a
silicon-germanium substrate and silicon-germanium source/drain
structures on or in the tensile-strained silicon layer. The device
also has a channel region located between the silicon-germanium
source/drain structures and within the tensile-strained silicon
layer. The channel region has a compressive stress in a direction
parallel to an intended current flow through the channel
region.
[0008] Another embodiment of the present invention is a method of
manufacturing a PMOS device. The method includes epitaxially
growing a tensile-strained silicon layer on a silicon-germanium
substrate and removing portions of the tensile-strained silicon
outside of a channel region. The method also includes epitaxially
growing silicon-germanium source/drain structures on or in the
tensile-strained silicon layer.
[0009] Still another embodiment of the present invention is
directed to a Metal Oxide Semiconductor (MOS) device. The metal
oxide device includes a PMOS transistor, which in turn, comprises a
tensile-strained silicon layer located on a silicon-germanium
substrate and p-doped silicon-germanium source/drain structures on
or in the tensile-strained silicon layer. The PMOS transistor also
includes an n-type channel region located between the p-doped
silicon-germanium source/drain structures and within the
tensile-strained silicon layer. The n-type channel region further
has a compressive stress in a direction parallel to an intended
current flow through the n-type channel region. The MOS device also
includes an N-type metal Oxide Semiconductor (NMOS) transistor. The
NMOS transistor comprises n-doped source/drain structures located
in or on the tensile-strained silicon layer. The NMOS transistor
also includes a p-type channel region located between the n-doped
source/drain structures and within the tensile-strained silicon
layer. The p-type channel has a tensile strain in directions
parallel and perpendicular to an intended current flow through the
p-type channel region.
[0010] The foregoing has outlined preferred and alternative
features of the present invention so that those of ordinary skill
in the art may better understand the detailed description of the
invention that follows. Additional features of the invention will
be described hereinafter that form the subject of the claims of the
invention. Those skilled in the art should appreciate that they can
readily use the disclosed conception and specific embodiment as a
basis for designing or modifying other structures for carrying out
the same purposes of the present invention. Those skilled in the
art should also realize that such equivalent constructions do not
depart from the scope of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The invention is best understood from the following detailed
description when read with the accompanying FIGUREs. It is
emphasized that, in accordance with the standard practice in the
semiconductor industry, various features may not be drawn to scale.
In fact, the dimensions of the various features may be arbitrarily
increased or reduced for clarity of discussion. Reference is now
made to the following descriptions taken in conjunction with the
accompanying drawings, in which:
[0012] FIG. 1 illustrates a partial perspective view of an
exemplary PMOS device of the present invention;
[0013] FIGS. 2A to 2E illustrate partial sectional views of
selected steps in a method for manufacturing a PMOS device
according to the principles of the present invention; and
[0014] FIG. 3 illustrates a partial sectional view of an MOS device
of the present invention.
DETAILED DESCRIPTION
[0015] The present invention benefits from studying the effects
that strain has on the mobility of charge carriers in silicon. In
particular, the effect of biaxially tensile-strained silicon was
analyzed by studying the individual effects of uniaxial tensile
strain in directions parallel and perpendicular to the direction of
current flow in the silicon. The present studies reveal that
tensile strain in a direction parallel to the direction of current
flow through the channel region of a PMOS device decreases carrier
mobility. In addition, tensile strain in a direction perpendicular
to the direction current flow increases carrier mobility.
Consequently, for practical germanium concentrations in a
silicon-germanium substrate (e.g., less than about 30%), there is
no net improvement, and in some instances a decrease, in the
mobility of Holes in biaxially tensile-strained silicon in PMOS
devices. Thus, the reason why biaxially tensile-strained silicon
does not improve drive current in PMOS devices is that a uniaxial
stress parallel to current flow degrades current flow and
substantially cancels an improvement in current flow from uniaxial
stress perpendicular to current flow. These observations lead to
the realization that the mobility in such strained-silicon could be
improved by reducing the extent of tensile strain in the direction
parallel, but not in the direction perpendicular, to current
flow.
[0016] The present invention combines epitaxial silicon-germanium
source/drain structures and biaxial tensile-strained silicon to
provide a PMOS device. The compressive stress from the
silicon-germanium source/drain structures partially reduces or
cancels the deleterious uniaxial stress parallel to current flow.
This occurs without impeding the beneficial effects that result
from uniaxial tensile stress perpendicular to current flow.
[0017] One embodiment of the present invention is illustrated in
FIG. 1, which illustrates a partial perspective view of an
exemplary PMOS device 100. A tensile-strained silicon layer 105, is
located on a silicon-germanium substrate 110. In certain
embodiments the tensile-strained silicon layer 105 has a thickness
112 between about 10 and about 20 nanometers. There is biaxial
tensile strain in the silicon layer 105 because the silicon layer
105 is epitaxially grown on the silicon-germanium substrate
1.sup.10. The tensile-strained silicon layer 105 has parallel and
Perpendicular tensile strain 115, 120, where the directions of
strain are designated with respect to the intended direction of
current flow 125 through a channel region 130 in the
tensile-strained silicon layer 105.
[0018] The magnitude of biaxial tensile strain in the silicon layer
105 can be varied by changing the composition of the
silicon-Germanium substrate 110. In general, higher amounts of
germanium in the silicon-germanium substrate 110 cause the silicon
layer 105 to have a higher magnitude of tensile strain in both
parallel and perpendicular directions 115, 120. For example, in
some embodiments of the PMOS device 100, the silicon-germanium
substrate 110 comprises a silicon alloy having between about 2 atom
percent and about 50 atom percent germanium. In some preferred
embodiments, the germanium content of the substrate 110 is between
about 20 and about 30 atom Percent. In addition, the extent of
biaxial tensile strain in the tensile-strained silicon layer 105
depends on the crystal orientation of the silicon layer 105. The
Present invention is advantageous when the tensile-strained silicon
layer has a (110) orientation relative to the direction of current
flow.
[0019] As further illustrated in FIG. 1, the PMOS device also
includes silicon-germanium source/drain structures 135, 140 located
on or in the tensile-strained silicon layer 105. Although the
silicon-germanium source/drain structures 135, 140 could refer to
deep source/drains, they could also refer to source/drain
extensions, or both structures. Additionally, the deep source/drain
structures 135, 140 could extend down into the silicon-germanium
substrate 110. The channel region 130 is located substantially
between the silicon-germanium source/drain structures 135, 140. The
silicon-germanium source/drain structures 135, 140 transmit a
uniaxial compressive stress 145 to the channel region 130 in the
direction parallel to the intended `current flow 125.
[0020] The net strain 150 in the channel region 130 in the
direction parallel to the intended direction of current flow 125 is
governed by the sum of compressive stress 145 and parallel tensile
stress 115. As previously noted, the compressive stress 145 is
imparted to the channel region 130 via the silicon-germanium
source/drain structures 135, 140. The parallel tensile stress 115
in the channel 130 is imparted to the tensile-strained silicon
layer 105, including the channel region 130, via the
silicon-germanium substrate 110.
[0021] In some instances, the magnitude of the compressive stress
145 is substantially greater than the magnitude of the parallel
tensile stress 115. The magnitude of the compressive stress 145,
for example, can be about 10 percent greater than the magnitude of
the parallel tensile stress 115. Of course, in other instances, the
magnitude of the compressive stress 145, can be less than the
magnitude of the parallel tensile stress 115. Thus, in some
instances, the net strain 150 can be a tensile strain while in
other instances the net strain 150 can be a compressive strain. In
either of these instances, however, the net strain 150 in the
parallel direction 125 is less tensile or more compressive than the
perpendicular tensile strain 120. In other instances, the
compressive stress 145 is substantially equal (e.g., within about
10 percent) in magnitude to a parallel tensile stress 115. In these
embodiments, the net strain 150 is substantially zero, while the
tensile strain in the perpendicular direction 120 is non-zero.
[0022] The magnitude of the compressive stress 145 can be adjusted
as desired in the direction parallel to intended current flow 125,
by changing the composition of the silicon-germanium source/drain
structures 135, 140. In some devices 100, the silicon-germanium
source/drain structures 135, 140 comprise a silicon alloy having
between about 30 atom percent and about 50 atom percent germanium.
In certain device configurations, the magnitude of compressive
stress 145 is at least about 1 GPa, while in other configurations
the compressive stress 145 is between about 1 and about 1.5
GPa.
[0023] The magnitude of the compressive stress 145 can also be
adjusted by controlling the amount of the silicon-germanium
source/drain structures 135, 140 that are located on sides 160 the
channel region 130. The compressive stress 145 increases as more of
the silicon-germanium source/drain structures 135, 140 contacts the
channel's sides 160. In some embodiments, to increase the extent of
contact between the source/drain structures 135, 140, and the
channel region 130, portions of the tensile strained-silicon layer
105 are removed, and the silicon-germani=source/drain structures
135, 140 are formed on the portions of the strained-silicon layer
thereby exposed 165. In other instances, however, sufficient
portions of the strained-silicon layer 105 are removed to allow the
silicon-germanium source/drain structures 135,140 to be on the
underlying silicon-germanium substrate 110. For example, in certain
cases, the thickness of the portion of the strained-silicon layer
removed 170 is between about 1 and about 10 nanometer thickness,
while in other cases, the entire thickness 112 of the portion is
removed.
[0024] For a tensile stress 120 equal to about 1 GPa in a direction
perpendicular to the direction of current flow 125, carrier
mobility can be at least about 60 percent greater than carrier
mobility in a substantially similar channel made of unstrained
silicon. This can advantageously result in the PMOS device 100
having a drive current that is substantially higher than a drive
current of a substantially similar PMOS device having a channel
made of unstrained silicon. In some cases, for example, the drive
current of the PMOS device of the present invention is at least
about 15 percent higher than the above-mentioned substantially
similar PMOS device.
[0025] As further illustrated in FIG. 1, the PMOS device 100 can
include other conventional semiconductor device components, such as
a gate structure 180, comprising a gate dielectric 185 and gate
electrode 190. Although not shown, one skilled in the art would
also understand how to add other components, including gate
sidewalls, source/drain extensions and isolation structures, to
form the operative PMOS transistor device 100.
[0026] Yet another aspect of the present invention is a method of
manufacturing a PMOS device. FIGS. 2A and 2E illustrate selected
steps in an exemplary method of manufacturing a PMOS device 200
according to the principles of the present invention. Any of the
above-described embodiments of the PMOS device 100, such as
depicted in FIG. 1, may be manufactured according to the method of
the present invention.
[0027] Turning first to FIG. 2A, illustrated is the partially
completed P-type Metal Oxide Semiconductor (PMOS) device after
enitaxially growing a tensile-strained silicon layer 205 on a
silicon-germanium substrate 210. Those skilled in the art are
familiar with conventional procedures used to epitaxially grow the
tensile-strained silicon layer 205. In some advantageous
embodiment, chemical vapor deposition (CVD) or molecular beam
epitaxy is used to form the silicon layer 205. In certain
embodiments, it is desirable to ebitaxially grow the
tensile-strained silicon layer 205 to a thickness 212 of about 20
nanometers, although other thicknesses can be used. FIG. 2A also
illustrates the partially completed PMOS device 200 after forming
device isolation regions 215 by using conventional lithography
processes to form a trench 217 in the tensile-strained silicon
layer 205 and silicon-germanium substrate 210 and then depositing a
field oxide 219 in the trench 217.
[0028] FIG. 22 shows the partially completed PMOS device 200 after
forming an n-well 220 in the tensile-strained silicon layer 205 and
silicon-germanium substrate 210. Those skilled in the art are
familiar with the procedures used to implant and anneal n-type
dopants, such as phosphorus or arsenic, to form the n-well 220.
Suitable n-dopant concentrations range between about 1.times.10'
and about 5.times.10' atoms/cm'. Of course, the selection of dopant
type and concentration depends on the desired performance
characteristics of the PMOS device 200 being manufactured.
[0029] Referring now to FIG. 2C, illustrated is the partially
completed PMOS device 200 after forming a gate structure 225.
Conventional oxidation, deposition and lithographic procedures can
be used to deposit and pattern oxide and polysilicon layers to form
a gate dielectric 227 and gate electrode 229, respectively. Of
course, other well-known materials may also be used to form the
gate structure 225. In certain submicron applications, the gate
structure 225 has a length 230 of less than about 50 nanometers,
and more preferably, between about 10 and 40 nanometers. Of course,
other gate lengths 230 are also within the scope of the present
invention.
[0030] Turning now to FIG. 2D, shown is the Partially completed
PMOS device 200 after removing portions 235 of the tensile-strained
silicon layer 205 and silicon-germanium substrate 210 outside of a
channel region 240. Alternatively, in some instances, the portion
removed 235 is in the tensile-strained silicon layer 205 only. In
some embodiments, the thickness 245 of the tensile-strained silicon
layer 205 removed is between about 1 to about 10 nanometers. In
certain advantageous embodiments, the thickness 245 removed is
about 5 to 6 nanometers. In other embodiments, the thickness 245
removed is substantially the same as the tensile-strained silicon
layer's 205 thickness 212. In yet other embodiments, no portions of
the strained silicon layer are removed.
[0031] Depicted in FIG. 2E is the partially completed PMCS device
200 after epitaxially growing silicon-germanium source/drain
structures 250, 255 on or in the tensile-strained silicon layer 205
and outside the channel region 240. As illustrated in FIG. 2E, in
some instances, the source/drain structures 250,255 are grown cm a
surface 260 of the substrate 210. Any conventional expitaxial
growth procedure can be used to form the silicon-germanium
source/drain structures 250, 255. In certain preferred embodiments,
as discussed above, the silicon-germanium source/drain structures
250, 255 are adjacent sides 262 of the channel region 240 so as to
impart compressive stress into the channel region 240. In some
embodiments, the epitaxial growth procedure includes depositing a
mixture of silicon, a p-type dopant, such as boron, and germanium
atoms, where the mixture has between about 30 atom percent and
about 50 atom percent germanium. One skilled in the art would
understand that forming the silicon-germanium source/drain
structures 250, 255 refers to forming deep
source/drains,source/drain extensions or both. Although not
depicted in FIGS. 2A-2E, one skilled in the art would also
understand that the manufacture of the PMOS device could also
include conventional steps to form other device components, such as
gate sidewall structures.
[0032] Still another embodiment of the present invention, a metal
oxide semiconductor (MOS) device 300, is illustrated in FIG. 3. In
certain preferred embodiments, the MOS device 300 includes a PMOS
transistor 305 and an NMOS transistor 310. Any of the
above-described embodiments of the PMOS device 100 and methods for
manufacturing the PMOS device 200 illustrated in FIGS. 1 and 2A-2E,
respectively, may be used to fabricate the PMOS transistor 305 of
the MOS device 300.
[0033] For instance, as depicted in FIG. 3, the PMOS transistor 305
includes a tensile-strained silicon layer 315 located on a
silicon-germanium substrate 320 and p-doped silicon-germanium
source/drain structures 325, 330 located on or in the
tensile-strained silicon layer 315. The silicon-germanium
source/drain structures 325, 330 could be located on the
tensile-strained silicon layer 315 or the silicon-germanium
substrate 320. The PMOS transistor 305 also includes an n-type
channel region 335 located between the p-doped silicon-germanium
source/drain structures 325, 330 and within the tensile-strained
silicon layer 315. Similar to that discussed above, the n-type
channel region 335 has a compressive stress 340 in a direction
parallel to an intended current flow 345 through the n-type channel
region 335. As also discussed above, this results in an improved
mobility of holes through the n-type channel region 335 and a
higher drive current for the PMOS transistor, as compared to an
analogous PMOS transistor having a channel made of unstrained
silicon.
[0034] Of course, the PMOS and NMOS transistors 305, 310 can
include other conventional structures to form operative
transistors, such as doped wells 350 in the tensile-strained
silicon layer 315, gate structures 352, gate sidewalls 354, and
source/drain extensions 356. Also, the MOS device 300 can include
isolation structures 360, analogous to that described above, and
the PMOS and NMOS transistors 305, 310 can be coupled via
interconnects 362 in one or more dielectric layers 364 so as to
form the operative complementary metal oxide semiconductor (CMOS)
transistor device 300.
[0035] The NMOS transistor 310 also includes n-doped source/drain
structures 365, 367 located in or on the tensile-strained silicon
layer 315, or on the substrate 320. The NMOS transistor 310 also
includes a p-type channel region 370 located between the n-doped
source/drain structures 365, 367 and within the tensile-strained
silicon layer 315. Unlike the n-type channel region 335, however,
the p-type channel region 370 has tensile stresses in directions
parallel 375 and perpendicular 377 to an intended current flow 380
through the p-type channel region 370. This follows from the fact
that the n-doped source/drain structures 365, 367 are preferably
designed to not apply a substantial compressive stress to the
p-type channel region 370.
[0036] For example, in some preferred embodiments such as
illustrated in FIG. 3, the n-doped source/drain structures 365, are
formed by conventional implantation and annealing procedures. For
instance, n-type dopants such as arsenic or phosphorus can be
implanted and thermally diffused into a portion of the
tensile-strained silicon layer 315, to form the source/drain
structures 365, 367. Such source/drain structures 365, 367 do not
apply a substantial compressive stress to the p-type channel region
370.
[0037] Alternatively, the n-doped source/drain structures 365, 367
can be formed in a fashion similar to that described above to form
the source/drain structures 325, 330 for the PMOS transistor 305.
That is, a portion of the tensile-strained silicon layer 315 can be
removed, and the n-doped source/drain structures 365, 367, are
epitaxially grown on or in the tensile-strained silicon layer
thereby exposed. In some cases, the source/drain structures are
365,367 grown on the silicon layer 315, while in other cases, it is
grown on the substrate 320. Although the n-doped source/drain
structures 365, 367 could comprise a silicon-germanium alloy, in
some instances, the compressive stress imparted to the p-type
channel region 370 by such an alloy could undesirably decrease
strain in the direction parallel to the intended direction of
current flow 380. Rather, in certain preferred embodiments, the
n-doped source/drain structures 365, 367 comprise a silicon-carbon
alloy. Silicon-carbon source/drain structures 365, 367 cause an
increase in tensile stress 375 in the direction parallel to the
intended direction of current flow 380, and thereby increase
tensile strain in the parallel direction. This, in turn,
beneficially increases the mobility of electrons through the p-type
channel region 370.
[0038] Consequently, preferred embodiments of the p-type channel
region 370 of the NMOS transistor 310 have biaxial strain,
comprising tensile strain in directions parallel and perpendicular
to the intended direction of current flow 380. This, in turn,
improves the carrier mobility and drive current of the NMOS
transistor 310. For example, the NMOS transistor's 310 p-type
channel region 370 can have a mobility of electrons per GPa of
tensile stress in directions parallel 375 and perpendicular 377
17.0 an intended current flow 380 that is at least about 50 percent
greater than a mobility in an analogous NMOS transistor having a
channel region in an unstrained silicon layer. As another example,
similar to the PMOS transistor 305, the NMOS transistor 310 can
have a drive current that is substantially higher (e.g., at least
about 15 percent) than a drive current of a substantially 314
similar NMOS device having a channel made of an unstrained silicon
layer.
[0039] Although the present invention has been described in detail,
one of ordinary skill in the art should understand that they can
make various changes, substitutions and alterations herein without
departing from the scope of the invention.
* * * * *