U.S. patent application number 13/780435 was filed with the patent office on 2013-09-19 for display device.
This patent application is currently assigned to Semiconductor Energy Laboratory Co., Ltd.. The applicant listed for this patent is SEMICONDUCTOR ENERGY LABORATORY CO., LTD.. Invention is credited to Jun KOYAMA.
Application Number | 20130241965 13/780435 |
Document ID | / |
Family ID | 49157190 |
Filed Date | 2013-09-19 |
United States Patent
Application |
20130241965 |
Kind Code |
A1 |
KOYAMA; Jun |
September 19, 2013 |
DISPLAY DEVICE
Abstract
Display defects of a display device are suppressed. The display
device includes in each pixel, a light-emitting element, a driving
transistor which supplies current to the light-emitting element,
and transistors in each of which a channel is formed in an oxide
semiconductor layer. A transistor which controls whether to
electrically connect a gate and a source of the driving transistor
provided in each pixel is provided. The above transistor and a
transistor which controls electrical connection between the gate of
the driving transistor and another node are transistors in each of
which a channel is formed in an oxide semiconductor layer.
Accordingly, charge stored in the node electrically connected to
the gate of the driving transistor can be arbitrarily retained or
released. Consequently, display defects of the display device can
be suppressed.
Inventors: |
KOYAMA; Jun; (Sagamihara,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
Atsugi-shi |
|
JP |
|
|
Assignee: |
Semiconductor Energy Laboratory
Co., Ltd.
Atsugi-shi
JP
|
Family ID: |
49157190 |
Appl. No.: |
13/780435 |
Filed: |
February 28, 2013 |
Current U.S.
Class: |
345/690 ;
345/82 |
Current CPC
Class: |
G09G 2300/0852 20130101;
G09G 3/3406 20130101; G09G 2300/0861 20130101; G09G 2300/0842
20130101; G09G 3/32 20130101 |
Class at
Publication: |
345/690 ;
345/82 |
International
Class: |
G09G 3/34 20060101
G09G003/34 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 14, 2012 |
JP |
2012-056909 |
Claims
1. A display device including a plurality of pixels, each pixel
comprising: a light-emitting element; a driving transistor
supplying a current corresponding to a voltage between a gate and a
source of the driving transistor to the light-emitting element; a
first transistor selecting whether to supply a potential to the
gate of the driving transistor; and a second transistor selecting
whether to electrically connect the gate and the source of the
driving transistor, wherein each channel of the first transistor
and the second transistor includes an oxide semiconductor
layer.
2. The display device according to claim 1, wherein a channel of
the driving transistor includes an oxide semiconductor layer.
3. The display device according to claim 1, wherein a current
output from the source of the driving transistor is supplied to an
anode of the light-emitting element.
4. The display device according to claim 3, wherein the pixel has a
means that controls the current supplied to the light-emitting
element without dependence on a threshold voltage of the driving
transistor.
5. The display device according to claim 1, wherein the display
device is incorporated in one selected from the group consisting of
a portable game machine, a television receiver, a laptop personal
computer, and a personal digital assistant.
6. A display device including a plurality of pixels, each pixel
comprising: a light-emitting element including a pair of
electrodes; and a driving transistor, a first transistor and a
second transistor, each including a gate, a source and a drain,
wherein one of the source and the drain of the first transistor is
electrically connected to the gate of the driving transistor, and
one of the source and the drain of the second transistor, wherein
one of the source and the drain of the driving transistor is
electrically connected to one of the pair of electrodes of the
light-emitting element, and the other of the source and the drain
of the second transistor, and wherein each channel of the first
transistor and the second transistor includes an oxide
semiconductor layer.
7. The display device according to claim 6, wherein a channel of
the driving transistor includes an oxide semiconductor layer.
8. The display device according to claim 6, wherein the display
device is incorporated in one selected from the group consisting of
a portable game machine, a television receiver, a laptop personal
computer, and a personal digital assistant.
9. A display device including a plurality of pixels, each pixel
comprising: a light-emitting element including a pair of
electrodes; a driving transistor, a first transistor and a second
transistor, each including a gate, a source and a drain; and a
capacitor including a pair of electrodes, wherein one of the source
and the drain of the first transistor is electrically connected to
the gate of the driving transistor, one of the pair of electrodes
of the capacitor, and one of the source and the drain of the second
transistor, wherein one of the source and the drain of the driving
transistor is electrically connected to one of the pair of
electrodes of the light-emitting element, the other of the pair of
electrodes of the capacitor, and the other of the source and the
drain of the second transistor, and wherein each channel of the
first transistor and the second transistor includes an oxide
semiconductor layer.
10. The display device according to claim 9, wherein a channel of
the driving transistor includes an oxide semiconductor layer.
11. The display device according to claim 9, wherein the display
device is incorporated in one selected from the group consisting of
a portable game machine, a television receiver, a laptop personal
computer, and a personal digital assistant.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a display device.
Specifically, the present invention relates to an active matrix
display device provided with a transistor which is provided in each
pixel and includes a channel formed in an oxide semiconductor
layer.
[0003] 2. Description of the Related Art
[0004] Since display devices using light-emitting elements have
high visibility, are suitable for reduction in thickness, and do
not have limitations on viewing angles, they have attracted
attention as display devices which can take the place of CRTs
(cathode ray tubes) or liquid crystal display devices. Specifically
proposed structures of active matrix display devices using
light-emitting elements are different depending on manufacturers.
However, in general, at least a light-emitting element, a
transistor which controls input of video signals to pixels, and a
transistor (a driving transistor) which controls current supplied
to the light-emitting elements are provided in each pixel.
[0005] When all the transistors in pixels have the same polarity,
it is possible to reduce the number of manufacturing steps of the
transistors. Patent Document 1 discloses a display device in which
transistors included in pixels are all n-channel transistors.
REFERENCE
Patent Document
[0006] [Patent Document 1] Japanese Published Patent Application
No. 2003-195810
SUMMARY OF THE INVENTION
[0007] Now, as an n-channel transistor included in a pixel, a
transistor in which a channel is formed in an oxide semiconductor
layer has been expected. This is because the transistor has higher
field-effect mobility than a transistor in which a channel is
formed in an amorphous silicon layer and a display device provided
with the transistor in each pixel can be made larger.
[0008] Further, the transistor in which a channel is formed in an
oxide semiconductor layer has characteristics of extremely small
off-state current. This means that the transistor is preferable as
a switch. However, defects may occur when supply of power supply
voltage to a display device including the transistor is stopped.
Specifically, charge is kept held in a particular node of a pixel
even in the case where the supply of power supply voltage is
stopped. Thus, display defects might occur in the case where, for
example, the supply of power supply voltage to the display device
is resumed.
[0009] In view of the above problem, it is an object of one
embodiment of the present invention to suppress display defects in
a display device.
[0010] One embodiment of the present invention is a display device
including a plurality of pixels arranged in matrix. Each pixel
includes a light-emitting element, a driving transistor which
supplies current corresponding to voltage between a gate and a
source to the light-emitting element, a first transistor which
selects whether to supply a desired potential to the gate of the
driving transistor, and a second transistor which selects whether
to electrically connect the gate and the source of the driving
transistor. The first transistor and the second transistor are
transistors in each of which a channel is formed in an oxide
semiconductor layer.
[0011] In the case where current output from the source of the
driving transistor is supplied to the light-emitting element, the
pixel is preferably provided with a means that controls current
supplied to the light-emitting element without dependence on the
threshold voltage of the driving transistor. For example, the pixel
is preferably provided with the means in the case where an
n-channel transistor whose drain is electrically connected to a
wiring for supplying a high power supply potential is used as the
driving transistor.
[0012] In the display device of one embodiment of the present
invention, it is possible to select whether to electrically connect
the gate and the source of the driving transistor provided in each
pixel. Further, electrical connection between the gate of the
driving transistor and another node is controlled by the
transistors in each of which a channel is formed in an oxide
semiconductor layer. Accordingly, charge stored in the node
electrically connected to the gate of the driving transistor can be
arbitrarily retained or released. For example, the driving
transistor can be turned off by electrical connection between the
gate and the source of the driving transistor before supply of
power supply voltage to the display device is stopped, or after the
supply of power supply voltage is resumed and before current is
supplied to the light-emitting element. Accordingly, display
defects that may occur when the supply of power supply voltage to
the display device is resumed can be suppressed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 is a circuit diagram illustrating a configuration
example of a pixel.
[0014] FIGS. 2A and 2B are circuit diagrams each illustrating a
configuration example of a pixel.
[0015] FIG. 3 is a diagram illustrating an example of a timing
chart.
[0016] FIGS. 4A to 4D are diagrams each illustrating operation of a
pixel.
[0017] FIG. 5 is a diagram illustrating an example of a timing
chart.
[0018] FIGS. 6A to 6D are diagrams each illustrating operation of a
pixel.
[0019] FIG. 7 is a circuit diagram illustrating a configuration
example of a pixel.
[0020] FIG. 8 is a diagram illustrating an example of a timing
chart.
[0021] FIG. 9 is a cross-sectional view illustrating a structure
example of a display device.
[0022] FIG. 10 is a perspective view illustrating an example of a
display device.
[0023] FIGS. 11A to 11D are diagrams illustrating specific examples
of electronic devices.
DETAILED DESCRIPTION OF THE INVENTION
[0024] Embodiments of the present invention will be described below
in detail. Note that the present invention is not limited to the
description below, and a variety of changes can be made without
departing from the spirit and scope of the present invention.
Therefore, the invention should not be construed as being limited
to the description below.
[0025] Note that in this specification, being "electrically
connected" corresponds to a state in which current, voltage, or a
potential can be supplied or transmitted. Therefore, the state of
being "electrically connected" does not necessarily mean the state
of direct connection, but includes in its category, the state of
indirect connection through an element such as a wiring, a
conductive film, a resistor, a diode, or a transistor so that
current, voltage, or a potential can be supplied or
transmitted.
[0026] In addition, even when different components are connected to
each other in a circuit diagram, there is actually a case where one
conductive film has functions of a plurality of components such as
a case where part of a wiring serves as an electrode. The term
"connection" also means such a case where one conductive film has
functions of a plurality of components.
Embodiment 1
[0027] FIG. 1 is a circuit diagram illustrating a configuration
example of a pixel 10 included in a display device of this
embodiment. The pixel 10 in FIG. 1 includes transistors 1 to 3, a
capacitor 4, and a light-emitting element 5. Note that the
transistors 1 to 3 are n-channel transistors in each of which a
channel is formed in an oxide semiconductor layer.
[0028] The transistor 1 has a function of supplying current
corresponding to voltage between a gate and a source of the
transistor 1 to the light-emitting element 5. The transistor 2 has
a function of selecting whether to electrically connect a wiring SL
and the gate of the transistor 1. The transistor 3 has a function
of selecting whether to electrically connect the gate and the
source of the transistor 1. The capacitor 4 has a function of
holding voltage between the gate and the source of the transistor
1. The light-emitting element 5 has a function of emitting light at
a luminance corresponding to current supplied from the transistor
1.
[0029] Further, a drain of the transistor 1 is electrically
connected to a wiring VDD_W for supplying a high power supply
potential (VDD). Further, a gate of the transistor 2 is
electrically connected to a wiring GL for supplying a selection
signal or a non-selection signal. A gate of the transistor 3 is
electrically connected to a wiring RL for supplying a reset signal.
A cathode of the light-emitting element 5 is electrically connected
to a wiring VSS_W for supplying a low power supply potential
(VSS).
[0030] Next, operation of the pixel 10 in FIG. 1 will be
described.
[0031] In the pixel 10, whether a potential of the wiring SL is
supplied to the gate of the transistor 1 is selected by switching
of the transistor 2. Specifically, when a selection signal is
supplied to the gate of the transistor 2, the potential of the
wiring SL is supplied to the gate of the transistor 1, and when a
non-selection signal is supplied to the gate of the transistor 2,
the potential of the wiring SL is not supplied to the gate of the
transistor 1. The voltage between the gate and the source of the
transistor 1 is changed in accordance with the potential of the
gate of the transistor 1. Accordingly, current corresponding to the
potential supplied to the gate of the transistor 1 is supplied to
the light-emitting element 5. That is, emission luminance of the
light-emitting element 5 is controlled in accordance with the
potential. In the display device of this embodiment, desired
display is performed by the control of emission luminance of each
of the light-emitting elements provided in a plurality of pixels in
accordance with the potential.
[0032] Further, in the pixel 10, whether the gate and the source of
the transistor 1 are electrically connected is selected by
switching of the transistor 3. For example, the transistor 3 is
turned on for a certain period just before supply of power supply
voltage to the display device is stopped, and the transistor 3 is
turned off for the other periods. Accordingly, the charge
accumulated in a node electrically connected to the gate of the
transistor 1 can be discharged just before the supply of power
supply voltage to the display device is stopped. That is, the
transistor 1 can be surely turned off. Thus, in the display device
of this embodiment, current is not supplied to the light-emitting
element 5 when the supply of power supply voltage is resumed, and
display defects can be suppressed.
[0033] The same effect can be obtained by turning on the transistor
3 for a certain period after the supply of power supply voltage is
resumed and before the current could be supplied to the
light-emitting element 5 (before a high power supply potential
(VDD) is supplied to the wiring VDD_W and a low power supply
potential (VSS) is supplied to the VSS_W).
Embodiment 2
[0034] FIGS. 2A and 2B are circuit diagrams each illustrating a
configuration example of a pixel 100 that is different from the
pixel 10 described in Embodiment 1.
Configuration Example 1 of Pixel
[0035] The pixel 100 illustrated in FIG. 2A includes transistors 11
to 16, a capacitor 17, and a light-emitting element 18. Note that
the transistors 11 to 16 are n-channel transistors in each of which
a channel is formed in an oxide semiconductor layer.
[0036] The transistor 12 has a function of selecting whether to
electrically connect a wiring SL and one of electrodes of the
capacitor 17. The transistor 13 has a function of selecting whether
to electrically connect a wiring IL and a gate of the transistor
11. The transistor 14 has a function of selecting whether to
electrically connect the one electrode of the capacitor 17 and the
gate of the transistor 11. The transistor 15 has a function of
selecting whether to electrically connect the one electrode and the
other electrode of the capacitor 17. The transistor 16 has a
function of selecting whether to electrically connect a source of
the transistor 11 and an anode of the light-emitting element
18.
[0037] A drain of the transistor 11 is electrically connected to a
wiring VDD_W. A gate of the transistor 12 and a gate of the
transistor 13 are electrically connected to a wiring G1 for
supplying a selection signal or a non-selection signal. A gate of
the transistor 14 is electrically connected to a wiring G2 for
supplying a selection signal or a non-selection signal. A gate of
the transistor 15 is electrically connected to a wiring RL for
supplying a reset signal. A gate of the transistor 16 is
electrically connected to a wiring G3 for supplying a selection
signal or a non-selection signal. A cathode of the light-emitting
element 18 is electrically connected to a wiring VSS_W.
Configuration Example 2 of Pixel
[0038] The pixel 100 illustrated in FIG. 2B includes transistors 11
to 15, a transistor 19, a capacitor 17, and a light-emitting
element 18. Note that the transistors 11 to 15 and the transistor
19 are n-channel transistors in each of which a channel is formed
in an oxide semiconductor layer.
[0039] The transistors 12 to 15 in the pixel 100 illustrated in
FIG. 2B have functions similar to those of the transistors 12 to 15
in the pixel 100 illustrated in FIG. 2A. The transistor 19 in the
pixel 100 illustrated in FIG. 2B has a function of selecting
whether to electrically connect a source of the transistor 11 and a
wiring Vcom_W for supplying a common potential (Vcom). Note that
the common potential (Vcom) is lower than the sum of a low power
supply potential (VSS) and a forward voltage drop of the
light-emitting element 18. The low power supply potential (VSS) can
be used as the common potential (Vcom), for example.
Operation Example 1 of Pixel
[0040] Next, operation of the pixel 100 illustrated in FIG. 2A will
be described.
[0041] FIG. 3 is a timing chart illustrating potentials of the
wirings G1 to G3, a potential supplied to the wiring RL, and a
signal (Vdata) supplied to the wiring SL; the wirings G1 to G3, the
wiring RL, and the wiring SL are connected to the pixel 100 in FIG.
2A. As illustrated in FIG. 3, the operation of the pixel 100
illustrated in FIG. 2A can be mainly divided into operation in a
period A and operation in a period B which are included in one
horizontal scanning period, operation in a period C in which an
image is displayed, and operation in a reset period.
[0042] First, the operation in the period A is described. In the
period A, a low-level potential is applied to the wiring G1, a
low-level potential is applied to the wiring G2, a high-level
potential is applied to the wiring G3, and a low-level potential is
applied to the wiring RL. Thus, the transistor 16 is turned on, and
the transistors 12 to 15 are turned off.
[0043] FIG. 4A illustrates the operation of the pixel 100 in the
period A. In FIG. 4A, the transistors 12 to 16 are represented as
switches (the same applies to FIGS. 4B to 4D). In the period A, by
the above operation, a node (illustrated as a node a in FIGS. 4A to
4D) electrically connected to the source of the transistor 11 has a
potential which is the sum of the low power supply potential (VSS)
and the forward voltage drop of the light-emitting element 18.
[0044] Next, the operation in the period B is described. In the
period B, a high-level potential is applied to the wiring G1, a
low-level potential is applied to the wiring G2, a low-level
potential is applied to the wiring G3, and a low-level potential is
applied to the wiring RL. Thus, the transistors 12 and 13 are
turned on, and the transistors 14 to 16 are turned off.
[0045] In transition from the period A to the period B, it is
preferable that the potential applied to the wiring G3 be switched
from a high-level potential to a low-level potential after the
potential applied to the wiring G1 is switched from a low-level
potential to a high-level potential, in which case the potential of
the node a can be prevented from being changed.
[0046] A potential (V0) is applied to the wiring IL, and a
potential (Vdata) of an image signal is applied to the wiring SL.
Note that the potential (V0) is preferably higher than the
potential which is the sum of the low power supply potential (VSS),
the threshold voltage (Vth) of the transistor 11, and the forward
voltage drop of the light-emitting element 18.
[0047] FIG. 4B illustrates the operation of the pixel 100 in the
period B. In the period B, by the above operation, the potential
(V0) is applied to a node (illustrated as a node b in FIGS. 4B to
4D) electrically connected to the gate of the transistor 11; thus
the transistor 11 is turned on. Thus, the potential of the node a
increases to a potential (V0-Vth). In other words, the transistor
11 is turned off at the time when a voltage (Vgs (11)) between the
gate and the source of the transistor 11 becomes the threshold
voltage (Vth). Further, a potential (Vdata) is applied to a node
(illustrated as a node c in FIGS. 4B to 4D) electrically connected
to the one electrode of the capacitor 17.
[0048] Next, the operation in the period C is described. In the
period C, a low-level potential is applied to the wiring G1, a
high-level potential is applied to the wiring G2, a high-level
potential is applied to the wiring G3, and a low-level potential is
applied to the wiring RL. Thus, the transistors 14 and 16 are
turned on, and the transistors 12, 13, and 15 are turned off.
[0049] In transition from the period B to the period C, it is
preferable that the potential applied to the wirings G2 and G3 be
switched from a low-level potential to a high-level potential after
the potential applied to the wiring G1 is switched from a
high-level potential to a low-level potential, in which case the
potential of the node a can be prevented from being changed.
[0050] FIG. 4C illustrates the operation of the pixel 100 in the
period C. In the period C, the potential of the gate of the
transistor 11 rises to (Vdata) since the potential (Vdata) is
applied to the node b by the above operation. Thus, the voltage
(Vgs (11)) between the gate and the source of the transistor 11
becomes a potential difference (Vdata-V0+Vth) between the potential
(Vdata) and the potential of the node a (V0-Vth). As described
above, in the case where the voltage between the gate and the
source of the transistor 11 is a value including the threshold
voltage of the transistor 11, current supplied to the
light-emitting element 18 can be controlled without dependence on
variation in the threshold voltage (Vth) of the transistor 11.
Further, even in the case where the transistor 11 deteriorates and
the threshold voltage (Vth) changes, the current supplied to the
light-emitting element 18 can be controlled without dependence on
the change. Therefore, display unevenness can be reduced, and
high-quality images can be displayed.
[0051] Next, the operation in the reset period is described. In the
reset period, a low-level potential is applied to the wiring G1, a
high-level potential is applied to the wiring G2, a high-level
potential is applied to the wiring G3, and a high-level potential
is applied to the wiring RL. Thus, the transistors 14 to 16 are
turned on, and the transistors 12 and 13 are turned off.
[0052] FIG. 4D illustrates the operation of the pixel 100 in the
reset period. In the reset period, the gate and the source of the
transistor 11 are electrically connected to each other by the above
operation. Accordingly, the charge accumulated in the gate of the
transistor 11 and the one electrode of the capacitor 17 is
discharged through the transistors 14 to 16 and the light-emitting
element 18. As a result, the transistor 11 is turned off. As
described above, the supply of the power-supply voltage is stopped
after surely turning off the transistor 11, so that current is not
supplied to the light-emitting element 18 when the supply of the
power-supply voltage is resumed, and display defects can be
suppressed.
[0053] Note that in the case where the reset period is provided
after the supply of the power supply voltage is resumed and before
current could be supplied to the light-emitting element 18, the
same effect can be obtained.
Operation Example 2 of Pixel
[0054] Next, the operation of the pixel 100 illustrated in FIG. 2B
will be described.
[0055] FIG. 5 is a timing chart illustrating potentials of the
wirings G1 to G3, a potential supplied to the wiring RL, and a
signal (Vdata) supplied to the wiring SL; the wirings G1 to G3, the
wiring RL, and the wiring SL are connected to the pixel 100 in FIG.
2B. As illustrated in FIG. 5, the operation of the pixel 100
illustrated in FIG. 2B can be mainly divided into operation in a
period A and operation in a period B which are included in one
horizontal scanning period, operation in a period C in which an
image is displayed, and operation in a reset period.
[0056] First, the operation in the period A is described. In the
period A, a low-level potential is applied to the wiring G1, a
low-level potential is applied to the wiring G2, a high-level
potential is applied to the wiring G3, and a low-level potential is
applied to the wiring RL. Thus, the transistor 19 is turned on, and
the transistors 12 to 15 are turned off.
[0057] FIG. 6A illustrates the operation of the pixel 100 in the
period A. In FIG. 6A, the transistors 12 to 15, and the transistor
19 are represented as switches (the same applies to FIGS. 6B to
6D). In the period A, by the above operation, the potential of a
node (illustrated as a node a in FIGS. 6A to 6D) electrically
connected to the source of the transistor 11 becomes a common
potential (Vcom).
[0058] Next, the operation in the period B is described. In the
period B, a high-level potential is applied to the wiring G1, a
low-level potential is applied to the wiring G2, a low-level
potential is applied to the wiring G3, and a low-level potential is
applied to the wiring RL. Thus, the transistors 12 and 13 are
turned on, and the transistors 14, 15, and 19 are turned off.
[0059] In transition from the period A to the period B, it is
preferable that the potential applied to the wiring G3 be switched
from a high-level potential to a low-level potential after the
potential applied to the wiring G1 is switched from a low-level
potential to a high-level potential, in which case the potential of
the node a can be prevented from being changed.
[0060] The potential (V0) is applied to the wiring IL, and the
potential (Vdata) of an image signal is applied to the wiring
SL.
[0061] FIG. 6B illustrates the operation of the pixel 100 in the
period B. Note that in the period B, the pixel 100 in FIG. 2B
operates in the same way as the pixel 100 in FIG. 2A; thus, the
above description is referred to here.
[0062] Next, the operation in the period C is described. In the
period C, a low-level potential is applied to the wiring G1, a
high-level potential is applied to the wiring G2, a low-level
potential is applied to the wiring G3, and a low-level potential is
applied to the wiring RL. Thus, the transistor 14 is turned on, and
the transistors 12, 13, 15, and 19 are turned off.
[0063] In transition from the period B to the period C, it is
preferable that the potential applied to the wiring G2 be switched
from a low-level potential to a high-level potential after the
potential applied to the wiring G1 is switched from a high-level
potential to a low-level potential, in which case the potential of
the node a can be prevented from being changed.
[0064] FIG. 6C illustrates the operation of the pixel 100 in the
period C. Note that the pixel 100 in FIG. 2B operates in the same
way as the pixel 100 in FIG. 2A; thus, the above description is
referred to here.
[0065] Next, the operation in the reset period is described. In the
reset period, a low-level potential is applied to the wiring G1, a
high-level potential is applied to the wiring G2, a low-level
potential is applied to the wiring G3, and a high-level potential
is applied to the wiring RL. Thus, the transistors 14 and 15 are
turned on, and the transistors 12, 13, and 19 are turned off.
[0066] FIG. 6D illustrates the operation of the pixel 100 in the
reset period. In the reset period, the gate and the source of the
transistor 11 are electrically connected to each other by the above
operation. Accordingly, the charge accumulated in the gate of the
transistor 11 and the one electrode of the capacitor 17 is
discharged through the transistors 14 and 15 and the light-emitting
element 18. As a result, the transistor 11 is turned off. As
described above, the supply of the power supply voltage is stopped
after surely turning off the transistor 11, so that current is not
supplied to the light-emitting element 18 when the supply of the
power-supply voltage is resumed, and display defects can be
suppressed.
[0067] Note that in the case where the reset period is provided
after the supply of the power supply voltage is resumed and before
current could be supplied to the light-emitting element 18, the
same effect can be obtained.
Embodiment 3
[0068] FIG. 7 is a circuit diagram illustrating a configuration
example of a pixel 200 that is different from the pixels described
in the above Embodiments. The pixel 200 illustrated in FIG. 7
includes transistors 20 to 26, capacitors 27 and 28, and a
light-emitting element 29. Note that the transistors 20 to 26 are
n-channel transistors in each of which a channel is formed in an
oxide semiconductor layer.
[0069] One of a source and a drain of the transistor 20 is
electrically connected to a wiring SL, and a gate of the transistor
20 is electrically connected to a wiring G3.
[0070] One of a source and a drain of the transistor 21 is
electrically connected to a wiring V1_W for supplying a potential
(V1), and a gate of the transistor 21 is electrically connected to
a wiring G2. Here, assume that the potential V1 is lower than a
high power supply potential (VDD) and higher than a low power
supply potential (VSS).
[0071] A drain of the transistor 22 is electrically connected to a
wiring VDD_W for supplying the high power supply potential (VDD),
and a gate of the transistor 22 is electrically connected to the
other of the source and the drain of the transistor 21.
[0072] One of a source and a drain of the transistor 23 is
electrically connected to the other of the source and the drain of
the transistor 20; the other of the source and the drain of the
transistor 23 is electrically connected to a source of the
transistor 22; and a gate of the transistor 23 is electrically
connected to the wiring G2.
[0073] One of a source and a drain of the transistor 24 is
electrically connected to a wiring V0_W for supplying a potential
V0; the other of the source and the drain of the transistor 24 is
electrically connected to the source of the transistor 22 and the
other of the source and the drain of the transistor 23; and a gate
of the transistor 24 is electrically connected to the wiring G1.
Here, assume that the potential (V0) is lower than the potential
(V1) and higher than the low power supply potential (VSS).
[0074] One of a source and a drain of the transistor 25 is
electrically connected to the other of the source and the drain of
the transistor 21 and the gate of the transistor 22; the other of
the source and the drain of the transistor 25 is electrically
connected to the source of the transistor 22, the other of the
source and the drain of the transistor 23, and the other of the
source and the drain of the transistor 24; and a gate of the
transistor 25 is electrically connected to a wiring RL.
[0075] One of a source and a drain of the transistor 26 is
electrically connected to the source of the transistor 22, the
other of the source and the drain of the transistor 23, the other
of the source and the drain of the transistor 24, and the other of
the source and the drain of the transistor 25; and a gate of the
transistor 26 is electrically connected to a wiring G4.
[0076] One electrode of the capacitor 27 is electrically connected
to the other of the source and the drain of the transistor 21, the
gate of the transistor 22, and the one of the source and the drain
of the transistor 25; and the other electrode of the capacitor 27
is electrically connected to the other of the source and the drain
of the transistor 20 and the one of the source and the drain of the
transistor 23.
[0077] One electrode of the capacitor 28 is electrically connected
to the other of the source and the drain of the transistor 20, the
one of the source and the drain of the transistor 23, and the other
electrode of the capacitor 27; and the other electrode of the
capacitor 28 is electrically connected to the source of the
transistor 22, the other of the source and the drain of the
transistor 23, the other of the source and the drain of the
transistor 24, the other of the source and the drain of the
transistor 25, and the one of the source and the drain of the
transistor 26.
[0078] An anode of the light-emitting element 29 is electrically
connected to the other of the source and the drain of the
transistor 26; a cathode of the light-emitting element 29 is
electrically connected to a wiring (VSS_W) for supplying the low
power supply potential (VSS).
[0079] Hereinafter, a node where the other of the source and the
drain of the transistor 21, the gate of the transistor 22, the one
of the source and the drain of the transistor 25, and the one
electrode of the capacitor 27 are electrically connected is
referred to as a node D. A node where the other of the source and
the drain of the transistor 20, the one of the source and the drain
of the transistor 23, the other electrode of the capacitor 27, and
the one electrode of the capacitor 28 are electrically connected is
referred to as a node E. A node where the source of the transistor
22, the other of the source and the drain of the transistor 23, the
other of the source and the drain of the transistor 24, the other
of the source and the drain of the transistor 25, the one of the
source and the drain of the transistor 26, and the other electrode
of the capacitor 28 are electrically connected is referred to as a
node F.
Operation Example of Pixel
[0080] An operation example of the above pixel will be described
with reference to FIG. 8. Specifically, FIG. 8 illustrates changes
of potentials of the wirings G1 to G4, the wiring RL, and the nodes
D, E, and F.
[0081] In a period ta, a high-level potential is applied to the
wiring G1, low-level potentials are applied to the wirings G2 to
G4, and a low-level potential is applied to the wiring RL. Thus,
the transistor 24 is turned on, and the transistors 20, 21, 23, 25,
and 26 are turned off.
[0082] In a period tb, a high-level potential is applied to the
wiring G2. Thus, the transistors 21 and 23 are turned on. As a
result, the potentials of the node D and the node E become (V1) and
(V0), respectively. In response to the change of the potential of
the node D to the potential (V1), the transistor 22 is turned
on.
[0083] In a period tc, a low-level potential is applied to the
wiring G1. Thus, the transistor 24 is turned off. Here, the
transistor 22 remains on until the voltage between the gate and the
source becomes lower than or equal to the threshold voltage. In
other words, the transistor 22 remains on until the potential of
the node F (the source of the transistor 22) becomes lower than the
potential (potential (V1)) of the node D by the threshold voltage
(Vth) of the transistor 22. As a result, the potential of the node
F becomes a potential (V1-Vth). Note that in the period tc, the
potential of the node N1 also rises to the potential (V1-Vth).
[0084] In a period td, a low-level potential is applied to the
wiring G2. Accordingly, the transistors 21 and 23 are tuned
off.
[0085] In a period te, a high-level potential is applied to the
wiring G3. Accordingly, the transistor 20 is turned on. Note that
in the period te, a potential (Vdata) of an image signal is
supplied to the wiring SL. As a result, the potential of the node E
becomes the potential (Vdata). In addition, the potentials of the
nodes D and F are also changed owing to the potential of the node
E. Specifically, the potential of the node D in a floating state is
raised or lowered by the amount of change in potential of the node
E (the difference between the potential (Vdata) of the image signal
and the potential lower than the potential (V1) by the threshold
voltage (Vth) of the transistor 22 owing to the capacitive coupling
between the node D and the node E through the capacitor 27 (the
potential of the node D becomes V1+[Vdata-(V1-Vth)]=Vdata+Vth); and
the potential of the node F in a floating state is raised or
lowered by the amount of change in potential of the node E owing to
the capacitive coupling between the node E and the node F through
the capacitor 28 (the potential of the node F becomes
V1-Vth+[Vdata-(V1-Vth)]=Vdata).
[0086] In a period tf, a high-level potential is applied to the
wiring G1. Thus, the transistor 24 is turned on. As a result, the
potential of the node F becomes (V0).
[0087] In a period tg, a low-level potential is applied to the
wiring G1. Thus, the transistor 24 is tuned off.
[0088] In a period th, a high-level potential is applied to the
wiring G4. Thus, the transistor 26 is turned on. As a result, a
current corresponding to the voltage between the gate and the
source of the transistor 22 is supplied to the light-emitting
element 29. Here, the voltage corresponds to the difference between
the potential (Vdata+Vth) of the node D and the potential of the
node F. In this case, the current supplied to the light-emitting
element 29 (the drain current in a saturated region of the
transistor 22) is not dependent on the threshold voltage of the
transistor 22.
[0089] In a period ti, a high-level potential is applied to the
wiring RL. Thus the transistor 25 is turned on. As a result, the
transistor 22 is turned off.
[0090] After the period ti, the supply of the power supply voltage
to the display device is stopped. As described above, the supply of
the power supply voltage is stopped after surely turning off the
transistor 22, so that current is not supplied to the
light-emitting element 29 when the supply of the power-supply
voltage is resumed, and display defects can be suppressed.
[0091] Note that in the case where the period ti is provided after
the supply of the power supply voltage is resumed and before
current could be supplied to the light-emitting element 29, the
same effect can be obtained.
Embodiment 4
[0092] In this embodiment, a structure example of a display device
will be described. Specifically, a display device with a top
emission structure is described as an example in this embodiment.
Needless to say, the structure of the display device disclosed in
this specification is not limited to the top emission structure,
and can be a bottom emission structure or a dual emission
structure. Note that the dual emission structure means a structure
in which light from a light-emitting element is emitted from two
sides of the display device.
Cross-Sectional Structure Example
[0093] FIG. 9 is a cross-sectional view illustrating an example of
the display device disclosed in this specification. Specifically,
the display device in FIG. 9 is a cross-sectional view illustrating
an example of the transistors 11 and 16, the capacitor 17, and the
light-emitting element 18 which are shown in FIG. 2A.
[0094] The transistor 11 includes, over a substrate 800 having an
insulating surface, a conductive film 812 functioning as a gate, a
gate insulating film 802 over the conductive film 812, an oxide
semiconductor layer 813 positioned over the gate insulating film
802 to overlap with the conductive film 812, and conductive films
814 and 815 that are positioned over the oxide semiconductor layer
813 and function as a source and a drain. Note that the conductive
film 814 is the wiring VDD_W in FIG. 2A.
[0095] The transistor 16 includes, over the substrate 800 having an
insulating surface, a conductive film 816 functioning as a gate,
the gate insulating film 802 over the conductive film 816, an oxide
semiconductor layer 817 positioned over the gate insulating film
802 to overlap with the conductive film 816, and the conductive
film 815 and a conductive film 818 that are positioned over the
oxide semiconductor layer 817 and function as a source and a drain.
Note that the conductive film 816 is the wiring G3 in FIG. 2A.
[0096] The capacitor 17 includes, over the substrate 800 having an
insulating surface, a conductive film 819, the gate insulating film
802 over the conductive film 819, and the conductive film 815
positioned over the gate insulating film 802 to overlap with the
conductive film 819.
[0097] Insulating films 820 and 821 are formed over the conductive
films 814, 815, and 818. In addition, a conductive film 822
functioning as the anode of the light-emitting element 18 is formed
over the insulating film 821. The conductive film 822 is
electrically connected to the conductive film 818 through a contact
hole 823 that is formed in the insulating films 820 and 821.
[0098] In addition, an insulating film 824 having an opening where
part of the conductive film 822 is exposed is provided over the
insulating film 821. An EL layer 825 and a conductive film 826
functioning as the cathode of the light-emitting element 18 are
stacked in this order over the part of the conductive film 822 and
the insulating film 824. A region where the conductive film 822,
the EL layer 825, and the conductive film 826 overlap one another
corresponds to the light-emitting element 18.
Specific Example of Oxide Semiconductor Layers 813 and 817
<(1) Material>
[0099] A film containing at least indium can be used as each of the
oxide semiconductor layers 813 and 817. In particular, a film
containing indium and zinc is preferably used. In addition, as a
stabilizer for reducing the variation in electric characteristics
of a transistor, a film containing gallium in addition to indium
and zinc is preferably used.
[0100] Alternatively, a film which contains, as a stabilizer, one
or more of tin, hafnium, aluminum, zirconium, and lanthanoid such
as lanthanum, cerium, praseodymium, neodymium, samarium, europium,
gadolinium, terbium, dysprosium, holmium, erbium, thulium,
ytterbium, or lutetium can be used as each of the oxide
semiconductor layers 813 and 817.
[0101] As each of the oxide semiconductor layers 813 and 817, for
example, a film of any of the following oxides can be used: indium
oxide; a two-component metal oxide such as an In--Zn-based oxide,
an In--Mg-based oxide, or an In--Ga-based oxide; a three-component
metal oxide such as an In--Ga--Zn-based oxide, an In--Al--Zn-based
oxide, an In--Sn--Zn-based oxide, an In--Hf--Zn-based oxide, an
In--La--Zn-based oxide, an In--Ce--Zn-based oxide, an
In--Pr--Zn-based oxide, an In--Nd--Zn-based oxide, an
In--Sm--Zn-based oxide, an In--Eu--Zn-based oxide, an
In--Gd--Zn-based oxide, an In--Tb--Zn-based oxide, an
In--Dy--Zn-based oxide, an In--Ho--Zn-based oxide, an
In--Er--Zn-based oxide, an In--Tm--Zn-based oxide, an
In--Yb--Zn-based oxide, or an In--Lu--Zn-based oxide; and a
four-component metal oxide such as an In--Sn--Ga--Zn-based oxide,
an In--Hf--Ga--Zn-based oxide, an In--Al--Ga--Zn-based oxide, an
In--Sn--Al--Zn-based oxide, an In--Sn--Hf--Zn-based oxide, or an
In--Hf--Al--Zn-based oxide.
[0102] Note that here, for example, an "In--Ga--Zn-based oxide"
means an oxide containing In, Ga, and Zn as its main component, in
which there is no particular limitation on the ratio of In:Ga:Zn.
The In--Ga--Zn-based oxide may contain a metal element other than
the In, Ga, and Zn.
[0103] Nitrogen may be substituted for part of constituent oxygen
of the oxide semiconductor layers 813 and 817.
<(2) Crystal Structure>
[0104] For each of the oxide semiconductor layers 813 and 817, a
film having a single crystal state, a polycrystalline (also
referred to as polycrystal) state, an amorphous state, or the like
can be used. In addition, a CAAC-OS (c-axis aligned crystalline
oxide semiconductor) film can be used as each of the oxide
semiconductor layers 813 and 817. The CAAC-OS film is described in
detail below.
[0105] The CAAC-OS film is not completely single crystal nor
completely amorphous. The CAAC-OS film is an oxide semiconductor
film with a crystal-amorphous mixed phase structure where a crystal
region and an amorphous region are included in an amorphous phase.
Note that in many cases, the crystal region fits inside a cube
whose one side is less than 100 nm. In an observation image
obtained with a transmission electron microscope (TEM), a boundary
between the amorphous region and the crystal region in the CAAC-OS
film is not clear. Thus, in the CAAC-OS film, a reduction in
electron mobility, due to the grain boundary, is suppressed.
[0106] In each of crystal regions included in the CAAC-OS film, a
c-axis is aligned in a direction parallel to a normal vector of a
surface where the CAAC-OS film is formed or a normal vector of a
surface of the CAAC-OS film, triangular or hexagonal atomic
arrangement which is seen from the direction perpendicular to the
a-b plane is formed, and metal atoms are arranged in a layered
manner or metal atoms and oxygen atoms are arranged in a layered
manner when seen from the direction perpendicular to the c-axis.
Note that the directions of the a-axis and the b-axis of one
crystal region may be different from those of another crystal
region. In this specification, a simple term "perpendicular"
includes a range from 85.degree. to 95.degree.. In addition, a
simple term "parallel" includes a range from -5.degree. to
5.degree..
[0107] In the CAAC-OS film, distribution of crystal regions is not
necessarily uniform. For example, in the case where crystal growth
occurs from the surface side of an oxide semiconductor film in a
formation process of the CAAC-OS film, the proportion of crystal
regions in the vicinity of a surface of the CAAC-OS film is higher
than that in the vicinity of the surface where the CAAC-OS film is
formed in some cases.
[0108] Since the c-axes of the crystal regions included in the
CAAC-OS film are aligned in the direction parallel to a normal
vector of a surface where the CAAC-OS film is formed or a normal
vector of a surface of the CAAC-OS film, the directions of the
c-axes may be different from each other depending on the shape of
the CAAC-OS film (the cross-sectional shape of the surface where
the CAAC-OS film is formed or the cross-sectional shape of the
surface of the CAAC-OS film). Note that when the CAAC-OS film is
formed, the direction of c-axis of the crystal region is the
direction parallel to a normal vector of the surface where the
CAAC-OS film is formed or a normal vector of the surface of the
CAAC-OS film. The crystal region included in the CAAC-OS is formed
by deposition or by performing treatment for crystallization such
as heat treatment after deposition.
[0109] With the use of the CAAC-OS film in a transistor, change in
electric characteristics of the transistor due to irradiation with
visible light or ultraviolet light is small. Thus, the transistor
has high reliability.
<(3) Layer Structure>
[0110] For the oxide semiconductor layers 813 and 817, not only a
single-layer oxide semiconductor film but also a layer formed of a
stack having plural kinds of oxide semiconductor films may be used.
For example, a layer including at least two of an amorphous oxide
semiconductor film, a polycrystalline oxide semiconductor film, and
a CAAC-OS film can be used as each of the oxide semiconductor
layers 813 and 817.
[0111] It is also possible to use a layer formed of a stack of
oxide semiconductor films with different compositions as each of
the oxide semiconductor layers 813 and 817. Specifically, a layer
including a first oxide semiconductor film (also referred to as a
lower layer) which has a surface in contact with the gate
insulating film 802 and a second oxide semiconductor film (also
referred to as an upper layer) which is in contact with the
insulating film 820 and has a different composition from the first
oxide semiconductor film can be used as each of the oxide
semiconductor layers 813 and 817. Note that in this case, a region
in which a channel is formed is largely included in the lower
layer. This is because the lower layer is closer to the conductive
films 812 and 816 functioning as a gate than the upper layer
is.
[0112] For example, in the case where the lower layer and the upper
layer both contain indium, gallium, and zinc, concentrations are
preferably set such that the indium concentration in the lower
layer is higher than that in the upper layer and the gallium
concentration in the upper layer is higher than that in the lower
layer, or/and such that the indium concentration in the lower layer
is higher than the gallium concentration in the lower layer and the
gallium concentration in the upper layer is higher than the indium
concentration in the upper layer.
[0113] Thus, it is possible to improve mobility of a transistor
including the oxide semiconductor layers 813 and 817 and suppress
formation of a parasitic channel in the transistor. Specifically,
the mobility of the transistor can be improved by an increase in
the indium concentration in the lower layer. This is because, in an
oxide semiconductor, the s orbitals of heavy metal mainly
contribute to carrier transfer, and when the In content in the
oxide semiconductor is increased, overlaps of the s orbitals are
increased. Further, a high gallium concentration of the upper layer
leads to prevention of release of oxygen, which can prevent
formation of a parasitic channel in the upper layer. This is
because, in Ga, the formation energy of oxygen vacancies is larger
and thus oxygen vacancies are less likely to occur, than in In.
<(3) Specific Example of Gate Insulating Film 802
[0114] An inorganic insulating film such as a silicon oxide film, a
silicon nitride film, a silicon oxynitride film, a silicon nitride
oxide film, an aluminum oxide film, an aluminum oxynitride film, a
gallium oxide film, or the like can be used as the gate insulating
film 802. A stack formed using these materials can also be used.
The aluminum oxide film has a high shielding (blocking) effect of
preventing penetration of both oxygen and impurities such as
hydrogen and moisture. Thus, the use of the layer including an
aluminum oxide film as the gate insulating film 802 makes it
possible to prevent release of oxygen from the oxide semiconductor
layers 813 and 817 and prevent the entry of an impurity such as
hydrogen to the oxide semiconductor layers 813 and 817.
[0115] The gate insulating film 802 can be formed using a film
including a hafnium oxide film, a yttrium oxide film, a hafnium
silicate (HfSi.sub.xO.sub.y (x>0, y>0)) film, a hafnium
silicate film to which nitrogen is added, a hafnium aluminate
(HfAl.sub.xO.sub.y (x>0, y>0)) film, or a lanthanum oxide
film (i.e., a film formed of what is called a high-k material),
whereby gate leakage current can be reduced.
Specific Example of Conductive Films 812, 816, and 819
[0116] A film containing an element selected from aluminum, copper,
titanium, tantalum, tungsten, molybdenum, chrome, neodymium, and
scandium or a film of an alloy containing any of these elements as
its component can be used for each of the conductive films 812,
816, and 819. Alternatively, a metal oxide film containing
nitrogen, specifically, an In--Ga--Zn--O film containing nitrogen,
an In--Sn--O film containing nitrogen, an In--Ga--O film containing
nitrogen, an In--Zn--O film containing nitrogen, a Sn--O film
containing nitrogen, an In--O film containing nitrogen, or a metal
nitride (e.g., InN or SnN) film can be used for each of the
conductive films 812, 816, and 819. Such a nitride film has a work
function of 5 eV (electron volts) or higher, preferably 5.5 eV
(electron volts) or higher, which enables the threshold voltage of
the transistor to be positive when used as the gate, so that what
is called a normally-off switching element can be achieved. A stack
including these films can also be used.
Specific Example of Conductive Films 814, 815, and 818
[0117] A film containing an element selected from aluminum, copper,
titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and
scandium; a film of an alloy containing any of these elements; a
film of a nitride containing any of these elements; or the like can
be used for the conductive films 814, 815, and 818. A stack
including these films can also be used.
Specific Example of Insulating Film 820
[0118] For the insulating film 820, an inorganic insulating
material such as a silicon oxide film, a silicon nitride film, a
silicon oxynitride film, a silicon nitride oxide film, an aluminum
oxide film, an aluminum oxynitride film, or a gallium oxide film
can be used. A stack formed using these films can also be used. The
aluminum oxide film has a high shielding (blocking) effect of
preventing penetration of both oxygen and impurities such as
hydrogen and moisture. Therefore, when the layer including an
aluminum oxide film is used as the insulating film 820, it is
possible to prevent release of oxygen from the oxide semiconductor
layers 813 and 817 and entry of an impurity such as hydrogen to the
oxide semiconductor layers 813 and 817.
Specific Example of Insulating Film 821
[0119] For the insulating film 821, an inorganic insulating
material such as a silicon oxide film, a silicon nitride film, a
silicon oxynitride film, a silicon nitride oxide film, an aluminum
oxide film, an aluminum oxynitride film, or a gallium oxide film
can be used. Alternatively, the insulating film 821 can be formed
using an organic insulating material film such as polyimide or
acrylic. A stack formed using these films can also be used.
Specific Example of Conductive Film 822
[0120] For the conductive film 822, a film containing an element
selected from aluminum, copper, titanium, tantalum, tungsten,
molybdenum, chromium, neodymium, and scandium; a film of an alloy
containing any of these elements; a film of a nitride containing
any of these elements; or the like can be used. A stack including
these films can also be used. In particular, for the conductive
film 822, a metal having high reflectance (e.g., aluminum or
silver), or an alloy containing the metal is preferably used.
Specific Example of EL Layer 825
[0121] For the EL layer 825, a single layer or a stack including a
light-emitting layer containing a light-emitting organic material
can be used.
Specific Example of Conductive Film 826
[0122] For the conductive film 826, a light-transmitting conductive
film such as indium oxide-tin oxide, indium oxide-tin oxide
containing silicon or silicon oxide, indium oxide-zinc oxide, or
indium oxide containing tungsten oxide and zinc oxide can be
used.
Specific Example of Insulating Film 824
[0123] For the insulating film 824, an organic insulating material
film such as polyimide or acrylic can be used.
Example 1
[0124] FIG. 10 is a perspective view illustrating an example of a
display device.
[0125] The display device illustrated in FIG. 10 includes a panel
1601, a circuit substrate 1602, and a connecting portion 1603. The
panel 1601 includes a pixel portion 1604 including a plurality of
pixels, a scan line driver circuit 1605 that selects pixels per
row, and a signal line driver circuit 1606 that controls input of
an image signal to the pixels in a selected row. Specifically,
signals input to the wiring GL illustrated in FIG. 1, the wirings
G1 to G3 illustrated in FIGS. 2A and 2B, and the wirings G1 to G4
illustrated in FIG. 7 are generated in the scan line driver circuit
1605.
[0126] Various signals and power supply potentials are input from
the circuit board 1602 to the panel 1601 through the connecting
portion 1603. For the connecting portion 1603, a flexible printed
circuit (FPC) or the like can be used. In the case where a COF tape
is used as the connecting portion 1603, part of the circuit in the
circuit board 1602 or part of the scan line driver circuit 1605 or
the signal line driver circuit 1606 included in the panel 1601 may
be formed on a chip separately prepared, and the chip may be
connected to a COF tape by a COF (chip on film) method.
Example 2
[0127] The display device according to one embodiment of the
present invention can be applied to television receivers, displays
for electronic calculator, image reproducing devices provided with
recording media (typically devices which reproduce the content of
recording media such as DVDs (digital versatile disc) and have
displays for displaying the reproduced images). Other examples of
electronic devices that can include the display device according to
one embodiment of the present invention are mobile phones, game
machines including portable game machines, personal digital
assistants, e-book readers, cameras such as video cameras and
digital still cameras, goggle-type displays (head mounted
displays), navigation systems, audio reproducing devices (e.g., car
audio systems and digital audio players), copiers, facsimiles,
printers, multifunction printers, automated teller machines (ATM),
and vending machines. Specific examples of such electronic devices
are shown in FIGS. 11A to 11D.
[0128] FIG. 11A is a portable game machine, which includes a
housing 5001, a housing 5002, a display portion 5003, a display
portion 5004, a microphone 5005, speakers 5006, operation keys
5007, a stylus 5008, and the like. The display device according to
one embodiment of the present invention can be used for the display
portion 5003 and the display portion 5004. Although the portable
game machine in FIG. 11A has the two display portions 5003 and
5004, the number of display portions included in the portable game
machine is not limited to this.
[0129] FIG. 11B is a television receiver, which includes a housing
5201, a display portion 5202, a support 5203, and the like. The
display device according to one embodiment of the present invention
can be used for the display portion 5202.
[0130] FIG. 11C is a laptop personal computer, which includes a
housing 5401, a display portion 5402, a keyboard 5403, a pointing
device 5404, and the like. The display device according to one
embodiment of the present invention can be used for the display
portion 5402.
[0131] FIG. 11D illustrates a personal digital assistant, which
includes a housing 5601, a display portion 5602, operation keys
5603, and the like. In the personal digital assistant in FIG. 11D,
a modem may be incorporated in the housing 5601. The display device
according to one embodiment of the present invention can be used
for the display portion 5602.
[0132] This application is based on Japanese Patent Application
serial No. 2012-056909 filed with Japan Patent Office on Mar. 14,
2012, the entire contents of which are hereby incorporated by
reference.
* * * * *