U.S. patent application number 13/412714 was filed with the patent office on 2013-09-12 for integrated circuit and method for fabricating the same.
This patent application is currently assigned to UNITED MICROELECTRONICS CORPORATION. The applicant listed for this patent is Ke-Chi Chen, Chi-Cheng Huang, Hsiang-Chen LEE, Ping-Chia Shih, Chih-Ming Wang. Invention is credited to Ke-Chi Chen, Chi-Cheng Huang, Hsiang-Chen LEE, Ping-Chia Shih, Chih-Ming Wang.
Application Number | 20130234252 13/412714 |
Document ID | / |
Family ID | 49113334 |
Filed Date | 2013-09-12 |
United States Patent
Application |
20130234252 |
Kind Code |
A1 |
LEE; Hsiang-Chen ; et
al. |
September 12, 2013 |
INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME
Abstract
An integrated circuit includes a substrate, a first
semiconductor device, a second semiconductor device and an
interlayer dielectric layer. At least one isolation structure has
been formed in the he substrate so as to separate the substrate
into a first active region and a second active region. The first
semiconductor device disposed on the first active region of the
substrate includes a first gate insulating layer and a poly-silicon
gate stacked on the substrate sequentially. The second
semiconductor device disposed on the second active region of the
substrate includes a second gate insulating layer and a metal gate
stacked on the substrate sequentially. The material of the second
gate insulating layer is different from that of the first gate
insulating layer. The thickness of the metal gate is greater than
that of the poly-silicon gate. The interlayer dielectric layer is
disposed on the substrate and covering the first semiconductor
device.
Inventors: |
LEE; Hsiang-Chen; (Kaohsiung
City, TW) ; Shih; Ping-Chia; (Tainan City, TW)
; Chen; Ke-Chi; (Taoyuan County, TW) ; Wang;
Chih-Ming; (Tainan City, TW) ; Huang; Chi-Cheng;
(Kaohsiung City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
LEE; Hsiang-Chen
Shih; Ping-Chia
Chen; Ke-Chi
Wang; Chih-Ming
Huang; Chi-Cheng |
Kaohsiung City
Tainan City
Taoyuan County
Tainan City
Kaohsiung City |
|
TW
TW
TW
TW
TW |
|
|
Assignee: |
UNITED MICROELECTRONICS
CORPORATION
HSINCHU
TW
|
Family ID: |
49113334 |
Appl. No.: |
13/412714 |
Filed: |
March 6, 2012 |
Current U.S.
Class: |
257/368 ;
257/E21.409; 257/E27.06; 438/294 |
Current CPC
Class: |
H01L 21/823857 20130101;
H01L 21/82345 20130101; H01L 21/823807 20130101; H01L 21/823835
20130101; H01L 21/823842 20130101 |
Class at
Publication: |
257/368 ;
438/294; 257/E27.06; 257/E21.409 |
International
Class: |
H01L 27/088 20060101
H01L027/088; H01L 21/336 20060101 H01L021/336 |
Claims
1. An integrated circuit, comprising: a substrate with at least one
of isolation structures formed therein so as to separate the
substrate into a first active region and a second active area; a
first semiconductor device disposed on the first active region of
the substrate and comprising: a first gate insulating layer having
a first dielectric constant disposed on the substrate the first
gate insulating layer; and a poly-silicon gate disposed on the
first gate insulating layer; a second semiconductor device disposed
on the second active region of the substrate and comprising: a
second gate insulating layer disposed on the substrate, wherein the
material of the second gate insulating layer is different from that
of the first gate insulating layer; a metal gate having a second
thickness disposed on the second gate insulating layer, wherein the
second thickness is greater than the first thickness; and an
interlayer dielectric layer disposed on the substrate and covering
the first semiconductor device.
2. The integrated circuit according to claim 1, wherein the first
gate insulating layer has a first dielectric constant and the
second agate insulating layer has a second dielectric constant
greater than the first dielectric constant.
3. The integrated circuit according to claim 1, wherein the first
semiconductor device further comprises a first spacer disposed on
sidewalls of the poly-silicon gate, and the second semiconductor
device further comprises a second spacer disposed on sidewalls of
the metal gate.
4. The integrated circuit according to claim 3, wherein the first
semiconductor device further comprises a plurality of first
source/drain regions disposed in the substrate beside the first
spacer, the second semiconductor device further comprises a
plurality of second source/drain disposed in the substrate beside
the second spacer.
5. The integrated circuit according to claim 3, further comprises a
plurality of source/drain metal salicides disposed in the substrate
and located on the first source/drain regions and the second
source/drain regions.
6. The integrated circuit according to claim 1, wherein the first
semiconductor device further comprises a metal salicide pattern
disposed on the poly-silicon gate.
7. The integrated circuit according to claim 1, wherein the first
gate insulating layer comprises at least one of oxide layer and
nitride layer.
8. A method for fabricating an integrated circuit, comprising the
steps of: providing a substrate with at least one isolation
structure formed therein so as to separate the substrate into a
first active region with a first stacked structure formed thereon
and a second active region with a second stacked structure formed
thereon; forming an interlayer dielectric layer covering the first
stacked structure and the second stacked structure; and planarizing
the interlayer dielectric layer to expose the top surface of the
first stacked structure, wherein the second stacked structure is
still covered by the interlayer dielectric layer after
planarizing.
9. The method for fabricating the integrated circuit according to
claim 8, wherein the second stacked structure comprises a second
gate insulating layer and a dummy gate sequentially formed on the
substrate, and after planarizing the interlayer dielectric layer,
the method further comprises the steps of: removing the dummy gate
so as to form an opening; and forming a metal gate in the
opening.
10. The method for fabricating the integrated circuit according to
claim 8, wherein the method for forming the first stacked structure
and the second stacked structure comprises the steps of: forming a
second dielectric material layer on the substrate; forming a first
poly-silicon layer on the second dielectric material layer;
removing a portion of the second dielectric material layer and a
portion of the first poly-silicon layer to expose the first active
region; forming a first dielectric material layer on the first
active region; forming a second poly-silicon layer conformally on
the substrate, wherein the second poly-silicon layer has a first
thickness and constructs a gate material layer with the first
poly-silicon, a first portion of the gate material layer is the
portion of the second poly-silicon layer located on the first
active region and a second portion of the gate material layer is
constructed from the portion of the first poly-silicon layer
remained on the substrate and the portion of the second
poly-silicon layer located on the second active region, the second
portion of the gate material layer has a second thickness greater
than the first thickness; and patterning the gate material layer,
the first dielectric material layer and the second dielectric
material layer to form the first stacked structure on the first
active region and the second stacked structure on the second active
region, wherein the first stacked structure comprises a first gate
insulating layer and a poly-silicon gate sequentially stacked on
the substrate, and the second stacked structure comprises a second
gate insulating layer and a dummy gate sequentially stacked on the
substrate.
11. The method for fabricating the integrated circuit according to
claim 10, wherein the first dielectric material layer has a first
dielectric constant and the second dielectric material layer has a
second dielectric constant greater than the first dielectric
constant.
12. The method for fabricating the integrated circuit according to
claim 10, further comprising the step of forming a mask layer on
the gate material layer conformally before patterning the gate
material layer, the first dielectric material layer and the second
dielectric material layer, wherein the mask layer is patterned with
the gate material layer, the first dielectric material layer and
the second dielectric material layer.
13. The method for fabricating the integrated circuit according to
claim 12, wherein before forming the interlayer dielectric layer,
further comprising the steps of: removing a portion of the mask
layer to expose the poly-silicon gate; and doping the poly-silicon
gate.
14. The method for fabricating the integrated circuit according to
claim 13, further comprising the step of forming a plurality of
first source/drain regions in the substrate beside the dummy gate
and a plurality of second source/drain regions in the substrate
beside the poly-silicon gate while doping the poly-silicon
gate.
15. The method for fabricating the integrated circuit according to
claim 14, further comprising the step of forming a plurality of
source/drain metal silicides in the substrate and on the first
source/drain regions and the second source/drain regions.
16. The method for fabricating the integrated circuit according to
claim 8, wherein the method for forming the first stacked structure
and the second stacked structure comprises the steps of: forming a
first dielectric material layer and a gate material layer on the
substrate sequentially, wherein the first dielectric material layer
covers the first active region and the second active region, the
gate material has a first portion with a first thickness located
above the first active region and the second portion with a second
thickness located above the second active region greater than the
first thickness; and patterning the gate material layer and the
first dielectric material layer to form the first stacked structure
on the first active region and the second stacked structure on the
second active region, wherein the first stacked structure comprises
a first gate insulating layer and a poly-silicon gate sequentially
stacked on the substrate, and the second stacked structure
comprises a patterning first dielectric material layer and a dummy
gate sequentially stacked on the substrate.
17. The method for fabricating the integrated circuit according to
claim 16, wherein after planarizing the interlayer dielectric
layer, the method further comprises the steps of: removing the
dummy gate so as to form an opening exposing the patterning first
dielectric material layer; removing the patterning first dielectric
material layer; forming a second gate insulating layer in the
opening; and forming a metal gate in the opening.
18. The method for fabricating the integrated circuit according to
claim 17, wherein the first dielectric material layer has a first
dielectric constant and the second gate insulating layer has a
second dielectric constant greater than the first dielectric
constant.
19. The method for fabricating the integrated circuit according to
claim 18, wherein the method of forming the gate material layer
comprises the steps of: forming a poly-silicon layer with the
second thickness on the first dielectric material layer; and
thinning a portion of the poly-silicon layer located on the first
active region to the first thickness.
20. The method for fabricating the integrated circuit according to
claim 8, further comprises the step of forming a first spacer on
the sidewalls of the first stacked structure and a second spacer on
the sidewalls of the second stacked structure before forming the
interlayer dielectric layer.
21. The method for fabricating the integrated circuit according to
claim 20, further comprises the step of forming a plurality of
first source/drain regions in the substrate beside the first spacer
and a plurality of second source/drain regions in the substrate
beside the second spacer before forming the interlayer dielectric
layer.
22. The method for fabricating the integrated circuit according to
claim 8, further comprising the step of forming a metal silicides
pattern on the poly-silicon gate.
Description
BACKGROUND
[0001] 1. Technical Field
[0002] The present invention relates to an integrated circuit and
method for fabricating the same, more particularly to an integrated
circuit integrating the high-k/metal gate semiconductor device with
the poly-silicon semiconductor device and method for fabricating
the same.
[0003] 2. Description of the Related Art
[0004] As the dimension of a semiconductor device is getting less,
the dimension of the gate structure and the thickness of the gate
insulation layer are reduced accordingly. However, a leakage
current occurs when the gate insulation layer of silicon oxide
becomes thinner. To reduce the leakage current, a high dielectric
constant (high-k) material is used to replace silicon oxide for
forming the gate insulation layer. The gate of polysilicon may
react with the high-k material to generate a Fermi-level pinning,
so that the threshold voltage is increased and the performance of
the device is affected. Therefore, a metal layer is used as a gate,
so as to avoid an increase in the threshold voltage and reduce the
resistance of the device.
[0005] However, for the high voltage device, electrostatic
discharge (ESD) device, flash device and non-volatile memory (NVM)
device, the gate insulating layer should has specific thickness to
avoid from being breakdown by the high operation voltage.
BRIEF SUMMARY
[0006] The invention is directed to an integrate circuit and method
for fabricating the same for integrating the high-k/metal gate
semiconductor device with the poly-silicon semiconductor
device.
[0007] The invention provides an integrated circuit including a
substrate, a first semiconductor device, a second semiconductor
device and an interlayer dielectric layer. Moreover, at least one
isolation structure has been formed in the he substrate so as to
separate the substrate into a first active region and a second
active region. The first semiconductor device disposed on the first
active region of the substrate includes a first gate insulating
layer and a poly-silicon gate. The first gate insulating layer is
disposed on the substrate the first gate insulating layer. The
poly-silicon gate having a first thickness is disposed on the first
gate insulating layer. The second semiconductor device disposed on
the second active region of the substrate includes a second gate
insulating layer and a metal gate. The second gate insulating layer
is disposed on the substrate, and the second dielectric constant is
less than the first dielectric constant. The metal gate having a
second thickness is disposed on the second gate insulating layer,
and the second thickness is less than the first thickness. The
interlayer dielectric layer is disposed on the substrate and
covering the first semiconductor device.
[0008] In some embodiments of the present invention, the first gate
insulating layer has a first dielectric constant and the second
gate insulating layer has a second dielectric constant greater than
the first dielectric constant.
[0009] In some embodiments of the present invention, the first
semiconductor device further includes a first spacer disposed on
sidewalls of the poly-silicon gate, and the second semiconductor
device further includes a second spacer disposed on sidewalls of
the metal gate.
[0010] In some embodiments of the present invention, the first
semiconductor device further includes a plurality of first
source/drain regions disposed in the substrate beside the first
spacer, and the second semiconductor device further includes a
plurality of second source/drain disposed in the substrate beside
the second spacer.
[0011] In some embodiments of the present invention, the integrated
circuit further includes a plurality of source/drain metal
salicides disposed in the substrate and located on the first
source/drain regions and the second source/drain regions.
[0012] In some embodiments of the present invention, the first
semiconductor device further includes a metal salicide pattern
disposed on the poly-silicon gate.
[0013] In some embodiments of the present invention, the first gate
insulating layer includes at least one of oxide layer and nitride
layer.
[0014] The invention further provides a method for fabricating the
integrated circuit including the following steps. First, a
substrate with at least one isolation structure formed therein so
as to separate the substrate into a first active region and a
second active region is provided. Further, a first stacked
structure has been formed on the first active region and a second
stacked structure has been formed on the second active region.
Next, an interlayer dielectric layer is formed and covers the first
stacked structure and the second stacked structure. Afterward, the
interlayer dielectric layer is planarized to expose the top surface
of the first stacked structure. Accordingly, the second stacked
structure is still covered by the interlayer dielectric layer after
planarizing.
[0015] In some embodiments of the present invention, the second
stacked structure includes a second gate insulating layer and a
dummy gate sequentially formed on the substrate, and after
planarizing the interlayer dielectric layer, the dummy gate is
removed so as to form an opening and then a metal gate is formed in
the opening.
[0016] In some embodiments of the present invention, the method for
forming the first stacked structure and the second stacked
structure includes the following steps. First, a second dielectric
material layer is formed on the substrate. Next, a first
poly-silicon layer is formed on the second dielectric material
layer. Later, a portion of the second dielectric material layer and
a portion of the first poly-silicon layer are removed to expose the
first active region. Afterward, a first dielectric material layer
is formed on the first active region. Then, a second poly-silicon
layer is conformally formed on the substrate with a first
thickness. Moreover, the second poly-silicon layer constructs a
gate material layer with the first poly-silicon. Further, a first
portion of the gate material layer is the portion of the second
poly-silicon layer located on the first active region and a second
portion of the gate material layer with a second thickness greater
than the first thickness is constructed from the portion of the
first poly-silicon layer remained on the substrate and the portion
of the second poly-silicon layer located on the second active
region. After that, the gate material layer, the first dielectric
material layer and the second dielectric material layer are
patterned to form the first stacked structure on the first active
region and the second stacked structure on the second active
region. Accordingly, the first stacked structure includes a first
gate insulating layer and a poly-silicon gate sequentially stacked
on the substrate, and the second stacked structure includes a
second gate insulating layer and a dummy gate sequentially stacked
on the substrate.
[0017] In some embodiments of the present invention, the first
dielectric material layer has a first dielectric constant and the
second dielectric material layer has a second dielectric constant
greater than the first dielectric constant.
[0018] In some embodiments of the present invention, the method for
fabricating the integrated circuit further includes the step of
forming a mask layer on the gate material layer conformally before
patterning the gate material layer, the first dielectric material
layer and the second dielectric material layer. Furthermore, the
mask layer is patterned with the gate material layer, the first
dielectric material layer and the second dielectric material
layer.
[0019] In some embodiments of the present invention, before forming
the interlayer dielectric layer, the method for fabricating
integrated circuit further includes the following steps. First, a
portion of the mask layer located on the poly-silicon gate is
removed to expose the poly-silicon gate. Then, the poly-silicon
gate is doped.
[0020] In some embodiments of the present invention, a plurality of
first source/drain regions are further formed in the substrate
beside the dummy gate and a plurality of second source/drain
regions are further formed in the substrate beside the poly-silicon
gate while the poly-silicon gate is doped.
[0021] In some embodiments of the present invention, a plurality of
source/drain metal salicides are further formed in the substrate
and on the first source/drain regions and the second source/drain
regions.
[0022] In some embodiments of the present invention, the method for
forming the first stacked structure and the second stacked
structure includes the following steps. First, a first dielectric
material layer and a gate material layer are formed on the
substrate sequentially. Moreover, the first dielectric material
layer covers the first active region and the second active region,
and the gate material has a first portion with a first thickness
located above the first active region and the second portion with a
second thickness located above the second active region greater
than the first thickness. Then, the gate material layer and the
first dielectric material layer are patterned to form the first
stacked structure on the first active region and the second stacked
structure on the second active region. Moreover, the first stacked
structure includes a first gate insulating layer and a poly-silicon
gate sequentially stacked on the substrate, and the second stacked
structure includes a patterning first dielectric material layer and
a dummy gate sequentially stacked on the substrate.
[0023] In some embodiments of the present invention, after
planarizing the interlayer dielectric layer, the dummy gate is
removed to form an opening exposing the patterning first dielectric
material layer and then the patterning first dielectric material
layer is also removed. Afterward, a second gate insulating layer
and a metal gate are formed in the opening sequentially.
[0024] In some embodiments of the present invention, the first
dielectric material layer has a first dielectric constant and the
second gate insulating layer has a second dielectric constant
greater than the first dielectric constant.
[0025] In some embodiments of the present invention, the method of
forming the gate material layer includes the following steps.
First, a poly-silicon layer with the second thickness is formed on
the first dielectric material layer. Then, a portion of the
poly-silicon layer located on the first active region is thinned to
the first thickness.
[0026] In some embodiments of the present invention, before forming
the interlayer dielectric layer, a first spacer is further formed
on the sidewalls of the first stacked structure and a second spacer
is further formed on the sidewalls of the second stacked
structure.
[0027] In some embodiments of the present invention, before forming
the interlayer dielectric layer, a plurality of first source/drain
regions are further formed in the substrate beside the first spacer
and a plurality of second source/drain regions are further formed
in the substrate beside the second spacer.
[0028] In some embodiments of the present invention, a metal
silicides pattern is further formed on the poly-silicon gate.
[0029] The integrated circuit of the invention integrated
high-k/metal gate semiconductor device with poly-silicon
semiconductor device which have different heights is fabricated
with simple process, therefore the process cost and the consuming
time can be decreased.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The above objects and advantages of the present invention
will become more readily apparent to those ordinarily skilled in
the art after reviewing the following detailed description and
accompanying drawings, in which:
[0031] FIGS. 1A-1K illustrate cross-section views of an integrated
circuit during the fabricating process thereof according to an
embodiment of the present invention; and
[0032] FIGS. 2A-2E illustrate cross-section views of an integrated
circuit during the fabricating process thereof according to an
embodiment of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0033] Hereinafter, preferred embodiments of the present invention
will be described in detail with reference to the accompanying
drawings. Here, it is to be noted that the present invention is not
limited thereto. Furthermore, the step serial numbers concerning
the saturation adjustment method are not meant thereto limit the
operating sequence, and any rearrangement of the operating sequence
for achieving same functionality is still within the spirit and
scope of the invention. The like numbered numerals designate
similar or the same parts, regions or elements. It is to be
understood that the drawings are not drawn to scale and are served
only for illustration purposes.
[0034] FIGS. 1A-1K illustrate cross-section views of an integrated
circuit during the fabricating process thereof according to an
embodiment of the present invention. Referring to FIGS. 1A-1E, a
substrate 102, such as a silicon substrate, a silicon-containing
substrate, or a silicon-on-insulator (SOI) substrate, with a
plurality of isolation structures 101 formed therein is provided.
Moreover, a first active region 103 and a second active region of
the substrate 102 are defined by the isolation structures 101.
Accordingly, one of the isolation structures 101 is located between
the first active region 103 and the second active region 105. In
this embodiment, the isolation structures 101 are, for example,
shallow trench isolation (STI) structures or filed oxide isolation
structures.
[0035] As shown in FIG. 1E, a first stacked structure 104 has been
formed on the first active region 103 of the substrate 102 and a
second stacked structure 104a has been formed on the second active
region 105. The first stacked structure 104 includes a first gate
insulating layer 110a and a poly-silicon gate 112a stacked on the
substrate 102 sequentially. The second stacked structure 104a
includes a second gate insulating layer 110b and a dummy gate 112b
stacked on the substrate 102 sequentially.
[0036] In detail, as shown in FIG. 1B, the method of forming the
first stacked structure 104 and the second stacked structure 104a
includes the following steps. Firstly, a second dielectric material
layer 107b and a first poly-silicon layer 109a are sequentially
formed on the substrate 102. In this embodiment, the second
dielectric material layer 107b has a second dielectric constant,
which may be greater than 4. The materials of the second dielectric
material layer 107b may include hafnium dioxide (HfO.sub.2),
zirconium dioxide (ZrO.sub.2), aluminum oxide (Al.sub.2O.sub.3),
aluminum nitride (AlN), titanium dioxide (TiO.sub.2), lanthanum
oxide (La.sub.2O.sub.3), yttrium oxide (Y.sub.2O.sub.3), gadolinium
oxide (Gd.sub.2O.sub.3), tantalum pentoxide (Ta2O.sub.5) or a
combination thereof, for example. The method of forming the second
dielectric material layer 107b includes performing a chemical vapor
deposition (CVD) process, for example. Further, according to an
embodiment of the present invention, the second dielectric material
layer 107b can be a single dielectric layer or a structure
including multiple dielectric layers, but the invention is not
limited hereto.
[0037] Referring to FIG. 1C, a portion of the first poly-silicon
layer 109a and a portion of the second dielectric material layer
107b disposed on the first active region 103 are removed to expose
the first active region 103 of the substrate 102. Then, a first
dielectric material layer 107a is formed on the first active region
103. Moreover, the first dielectric material layer 107a has a first
dielectric constant less than the second dielectric constant.
[0038] In this embodiment, a conformal dielectric material layer
(not shown) is formed on the substrate 102 at first, and then the
portions of the dielectric material layer located out of the first
active region 103 are removed so as to remain the first dielectric
material layer 107a on the first active region 103. Furthermore, in
other embodiment, the portions of the dielectric material layer
located out of the first active region 103 may be removed with
other layers in later processes.
[0039] Referring to FIG. 1D, a second poly-silicon layer 109b
having a first thickness h1 is conformally formed on the substrate
102 to construct the gate material layer 106 with the first
poly-silicon layer 109a. In detail, the portion of the second
poly-silicon layer 109b disposed above the first active region 103
is used as the first portion 106a of the gate material layer 106.
The remained portion of the first poly-silicon layer 109a is
stacked by a portion of the second poly-silicon layer 109b disposed
above the second active region 105 to construct the second portion
106b of the gate material layer 106 with a second thickness h2
greater than the first thickness h1. In this embodiment, the second
thickness h2 is about 500 angstroms and the difference between that
and the first thickness h1 is about 100 to 150 angstroms, but the
invention is not limited hereto.
[0040] Further, a mask layer 108 may be optionally and conformally
formed on the gate material layer 106 in this embodiment. The hard
mask layer 108 includes a material having an etching selectivity
high enough with respect to the gate material layer 106, such as
silicon nitride or silicon oxynitride (SiON). The method of forming
the hard mask layer 132 includes performing a chemical vapor
deposition process or a physical vapor deposition process, for
example.
[0041] Referring to FIG. 1E, the first dielectric material layer
107a, the second dielectric material layer 107b and the gate
material layer 106 are patterned to form a first stacked structure
104 on the first active region 103 and form a second stacked
structure 104a on the second active region 105. Moreover, before
patterning the first dielectric material layer 107a, the second
dielectric material layer 107b and the gate material layer 106, the
mask layer 108 may be patterned to respectively form a mask pattern
108a and a mask pattern 108b above the first active region 103 and
the second active region 105. After that, the first dielectric
material layer 107a, the second dielectric material layer 107b and
the gate material layer 106 are patterned by using the same photo
mask (not shown). In this embodiment, the patterning process
includes performing general lithography and etching processes, for
example.
[0042] After the patterning process is completed, lightly doped
regions 114 may be formed in the substrate 102 beside the first
stacked structure 104 in the first active region 103 and the second
stacked structure 104a in the second active region 105 according to
an embodiment. When the first active region 103 is for forming an
NMOS transistor, the lightly doped regions 114 in the first active
region 103 are N-type lightly doped regions. When the first active
region 103 is for forming a PMOS transistor, the lightly doped
regions 114 in the first active region 103 are P-type lightly doped
regions.
[0043] According to another embodiment, after forming the lightly
doped regions 114, a first spacer 116a may be optionally formed on
sidewalls of the first stacked structure 104 and a second spacer
116b may be optionally formed on sidewalls of the second stacked
structure 104a.
[0044] In details, the first spacer 116a is formed on the sidewalls
of the mask pattern 108a, the poly-silicon gate 112a and the first
gate dielectric layer 110a. The second spacer 116b is formed on the
sidewalls of the mask pattern 108b, the dummy gate 112b and the
second gate dielectric layer 110b. The first spacer 116a and the
second spacer 116b include silicon oxide, silicon nitride or
silicon oxynitride (SiON), for example. The method of forming the
first spacer 116a and the second spacer 116b includes forming a
spacer material layer (not shown) on the substrate 102 by a CVD
process, and then removing a portion of the spacer material layer
by an anisotropic etching process. Each of the first spacer 116a
and second spacer 116b can be a single layer or a multi-layer
structure, and only a single layer is shown in FIG. 1E. The present
invention does not limit to this embodiment. According to another
embodiment, the first spacer 116a and the second spacer 116b are
not formed.
[0045] Thereafter, as shown in FIG. 1F, first source/drain regions
118a are formed in the substrate 102 beside the first stacked
structure 104, and second source/drain regions 118b are formed in
the substrate 102 beside the second stacked structure 104a. In an
embodiment, the method of forming the first source/drain regions
118a and the second source/drain regions 118b includes performing
an ion implantation process, for example. When the first active
region 103 is for forming an NMOS transistor, the first
source/drain regions 118a are N-type heavily doped regions. When
the first active region 103 is for forming a PMOS transistor, the
first source/drain regions 118a are P-type heavily doped regions.
Moreover, the mask pattern 108b formed on the poly-silicon gate
112a is removed before forming the first source/drain regions 118a
and the second source/drain regions in this embodiment, so that the
poly-silicon gate 112a can be doped during the ion implantation
process of the first source/drain regions 118a and the second
source/drain regions, but the invention is not limited hereto.
[0046] Referring to FIG. 1G, according to a preferred embodiment of
the present invention, the method further includes forming a metal
salicide pattern 120a on the poly-silicon gate 112a, and forming a
plurality of source/drain metal salicides 120b on the surface of
the substrate 102 beside the dummy gate 112b and the poly-silicon
gate 112a. The source/drain metal salicides 120b are formed on the
surface of the first source/drain regions 118a and the second
source/drain regions 118b which are previously formed. The method
of forming the metal salicide pattern 120a and the source/drain
metal salicides 120b includes forming a metal layer (not shown) on
the substrate 102. Thereafter, an annealing process is performed,
so that metal salicidation occurs between the metal layer and the
poly-silicon gate 112a and between the metal layer and the first
source/drain regions 118a and the second source/drain regions 118b,
and thus, the metal salicide pattern 120a is formed on the surface
of the poly-silicon gate 112a, and the source/drain metal salicides
120b are formed on the surface of the first source/drain regions
118a and the second source/drain regions 118b. Afterwards, the
unreacted metal layer is removed. The metal salicide pattern 120a
and the source/drain metal salicides 120b include TiSi, CoSi, NiSi,
PtSi, WSi, TaSi, MoSi or a combination thereof.
[0047] Referring to FIG. 1H, according to a preferred embodiment of
the present invention, the method further includes optionally
forming a protection layer 130 on the substrate 102, so as to cover
the formed structures in the first active region 103 and the second
active region 105. The protection layer 130 includes silicon
nitride or silicon oxynitride (SiON), and the forming method
thereof includes performing a CVD or PVD process, for example. The
protection layer 130 conformally covers the surface of the formed
structures on the substrate 102 and selectively applies tension
stress or compress stress on the NMOS transistor or PMONS
transistor. Thereafter, an ILD layer 140 is formed on the
protection layer 130. The ILD layer 140 includes SiO, SiN, SiON or
a combination thereof, and the forming method thereof includes
performing a CVD process, for example.
[0048] Referring to FIG. 1I, a planarization process is performed,
so as to remove a portion of the interlayer dielectric layer 140
and the protection layer 130 until the surface of the dummy gate
112b is exposed. Since there is a height difference exist between
the poly-silicon gate 112a and the dummy gate 112b, after the step
of performing the planarization process in FIG. 1I, the surface of
the dummy gate 112b is exposed while the poly-silicon gate 112a
(and the metal salicide layer 120a) is not exposed and still
covered by the protection layer 130 and the interlayer dielectric
layer 140. In this embodiment, the planarization process is a
chemical mechanical polishing (CMP) process, for example.
[0049] Thereafter, the exposed dummy gate 112b is removed to form
an opening 142, as shown in FIG. 1J. The method of removing the
dummy gate 112b includes performing an etching process, for
example. The poly-silicon gate 112a is unexposed and covered by the
protection layer 130 and the interlayer dielectric layer 140, so
that removal or peeling of the poly-silicon gate 112a is not
observed.
[0050] Referring to FIG. 1K, a metal gate 150 is formed in the
opening 142, therefore an integrated circuit 100 is substantially
completed. The metal gate 150 includes work function metal and/or
low-resistance metal and the material thereof is, for example, Ti,
TiAl.sub.x, Ti rich TiN, Al or a combination thereof, for example.
The method of forming the metal gate 150 includes forming a metal
material layer (not shown) to cover the interlayer dielectric layer
140 and fill up the opening 142. Thereafter, a CMP process or an
etching back process is performed, so as to remove a portion of the
metal material layer outside the opening 142. Thus, a first
semiconductor device 160a and a second semiconductor device 160b
are formed on the substrate 102. Specifically, the first
semiconductor device 160a is a transistor or memory device having
the poly-silicon gate 112a, and the second semiconductor device
160b is a MOS transistor having the metal gate 150.
[0051] After that, a plurality of interconnect layers may be formed
on the structure of FIG. 1K to cover the metal gate 150 and the
interlayer dielectric layer 140. The plurality of interconnect
layers are usually comprised of a plurality of interlayer
dielectric layers and a plurality of interconnect structures in the
interlayer dielectric layers.
[0052] As shown in FIG. 1K, the integrated circuit 100 formed by
the above-mentioned method includes a substrate 102, a first
semiconductor device 160a, a second semiconductor device 160b and
an interlayer dielectric layer 140. According to a preferred
embodiment, a plurality of isolation structures 101 have been
formed in the substrate 102 of the integrated circuit 100 so as to
separate the substrate 102 to a first active region 103 and a
second active region 105.
[0053] The first semiconductor device 160a is disposed on the first
active region 103 of the substrate 102 and includes a first gate
dielectric layer 110a and a poly-silicon gate 112a. Preferably, the
first semiconductor device 160a further includes a first spacer
116a. In details, the first gate dielectric layer 110a is disposed
on the substrate 100 and has a first dielectric constant. The
poly-silicon gate 112a is disposed on the first gate dielectric
layer 110a and has a first thickness hl. The first spacer 116a is
disposed on the sidewall of the poly-silicon gate 112a.
[0054] The first semiconductor device 160a further includes the
light doped drain regions 114, the first source/drain regions 118a
and the source/drain silicides 120b. Moreover, the first
semiconductor device 160a also can include a metal salicide pattern
120a. The light doped drain regions 114 are disposed in the
substrate 102 beside the metal gate 150. The first source/drain
regions 118a are disposed in the substrate 102 beside the first
spacers 116a. The lightly doped regions 114 and the first
source/drain 118a can be N-type or P-type doped regions depending
on the conductivity type of the first semiconductor device 160a.
The source/drain metal salicides 120b are disposed on the surface
of the first source/drain regions 118a, and the metal salicide
pattern 120a is disposed on the poly-silicon gate 112a.
[0055] The second semiconductor device 160b is disposed on the
second active region 105 of the substrate 102. The second
semiconductor device 160b includes a second gate dielectric layer
110b and a metal gate 150, and preferably the second semiconductor
device 160b further includes a second spacer 116b. In details, the
second gate dielectric layer 110b is disposed on the substrate 102.
The metal gate 150 is disposed on the second gate dielectric layer
110b with a second thickness h2 greater than the first thickness h1
of the poly-silicon gate 112a. According to a preferred embodiment
of the present invention, the thickness difference between the
metal gate 150 of the second semiconductor device 160b and the
poly-silicon gate 112a of the first semiconductor device 160a is
about 100 to 150 angstroms. In other words, the difference between
the top surface of the metal gate 150 and that of the poly-silicon
gate 112a is about 100 to 150 angstroms. The second spacer 116b is
disposed on the sidewall of the metal gate 150.
[0056] The second semiconductor device 160b further includes the
light doped drain regions 114 and the second source/drain regions
118b. The light doped drain regions 114 are disposed in the
substrate 102 beside the metal gate 150. The second source/drain
regions 118b are disposed in the substrate 102 beside the second
spacers 116b. The lightly doped regions 114 and the second
source/drain 118b can be N-type or P-type doped regions depending
on the conductivity type of the second semiconductor device 160b.
The source/drain metal salicides 120b are disposed on the surface
of the second source/drain regions 118b.
[0057] The interlayer dielectric layer 140 covers the first
semiconductor device 160a but exposes the metal gate 150 of the
second semiconductor device 160b. Further, the integrated circuit
100 further includes the protection layer 130 covers the first
semiconductor device 160a and is disposed between the interlayer
dielectric layer 140 and the first semiconductor device 160a.
Specifically, the protection layer 130 covers the second spacer
116b of the second semiconductor device 160b but exposes the metal
gate 150 of the second semiconductor device 160b.
[0058] According to an embodiment, a plurality of interconnect
layers may be disposed on the structure of FIG. 1K to cover the
metal gate 150 and the interlayer dielectric layer 140. The
plurality of interconnect layers are usually comprised of a
plurality of interlayer dielectric layers and a plurality of
interconnect structures in the interlayer dielectric layers.
[0059] Accordingly, the second semiconductor device 160b is a
high-k/metal gate transistor. Further, the second gate dielectric
layer 110b with high dielectric constant is formed on the substrate
102 before removing dummy gate 112b, but the invention is not
limited hereto. In other embodiment, the second gate dielectric
layer 110b and the metal gate 150 of the second semiconductor
device 160b can be formed after removing the dummy gate 112b. The
details would be described in the following embodiment.
[0060] FIGS. 2A-2E illustrate cross-section views of an integrated
circuit during the fabricating process thereof according to an
embodiment of the present invention. Referring to FIG. 2A, in this
embodiment, the method of forming the gate material layer includes,
for example, forming a first dielectric material layer 107a and a
poly-silicon layer 206 sequentially on the substrate 102 to cover
the first active region 103 and the second active region 105. The
poly-silicon layer 206 has the second thickness h2. The first
dielectric material layer 107a may be, for example, at least one of
oxide layer and nitride layer.
[0061] Referring to 2B, a portion of the poly-silicon layer 206 is
removed for thinning the portion of the poly-silicon layer 206
located above the first active region 103 to the first thickness
h1. Therefore, the gate material layer 106 having a first portion
106a and the second portion 106b is formed. Then, a mask layer 108
is optional formed on the gate material layer 106.
[0062] After that, the processes described in the FIG. 1E to FIG.
1I are performed to form the structure shown in FIG. 2C. Then, as
shown in FIG. 2D, the dummy gate 112b is removed by using the first
dielectric material layer 107a as an etching stop layer. The first
dielectric material layer 107a is removed after removing the dummy
gate 112b to form an opening 242 exposing a portion of the
substrate 102.
[0063] Referring to FIG. 2E, a high-k dielectric layer is formed in
the opening 242 to as a second gate dielectric layer 210b.
Specifically, the second gate dielectric layer 210b covers the
bottom and the sidewalls of the opening 242. Last, the metal gate
250 is formed in the opening 242. Therefore, the integrated circuit
200 is substantially completed. After that, a plurality of
interconnect layers may be formed on the structure of FIG. 2E to
cover the metal gate 150 and the interlayer dielectric layer 140.
The plurality of interconnect layers are usually comprised of a
plurality of interlayer dielectric layers and a plurality of
interconnect structures in the interlayer dielectric layers.
[0064] Referring to FIG. 1K and FIG. 2E, the integrated circuit 200
is similar to or the same with the integrated circuit 100 except
for the second gate dielectric layer 210b. In detail, the second
gate dielectric layer 210b of the integrated circuit 200 covers the
bottom and sidewalls of the opening 242. The second gate dielectric
layer 110b of the integrated circuit 100 is disposed on the bottom
of the opening 142.
[0065] In summary, the process of high-k/metal gate semiconductor
device is integrated with the process of poly-silicon semiconductor
device in the embodiments of the invention, therefore an integrated
circuit having at least two different semiconductor devices can be
fabricated to increase the flexible of use of the integrated
circuit. Furthermore, the method of the invention can simplify the
process of forming two gates with different heights, so that the
process cost and the consuming time can be decreased.
[0066] While the invention has been described in terms of what is
presently considered to be the most practical and preferred
embodiments, it is to be understood that the invention needs not be
limited to the disclosed embodiment. On the contrary, it is
intended to cover various modifications and similar arrangements
included within the spirit and scope of the appended claims which
are to be accorded with the broadest interpretation so as to
encompass all such modifications and similar structures.
* * * * *