U.S. patent application number 13/854319 was filed with the patent office on 2013-08-29 for semiconductor devices with graded dopant regions.
The applicant listed for this patent is G.R. Mohan Rao. Invention is credited to G.R. Mohan Rao.
Application Number | 20130221488 13/854319 |
Document ID | / |
Family ID | 35995339 |
Filed Date | 2013-08-29 |
United States Patent
Application |
20130221488 |
Kind Code |
A1 |
Rao; G.R. Mohan |
August 29, 2013 |
SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS
Abstract
Most semiconductor devices manufactured today, have uniform
dopant concentration, either in the lateral or vertical device
active (and isolation) regions. By grading the dopant
concentration, the performance in various semiconductor devices can
be significantly improved. Performance improvements can be obtained
in application specific areas like increase in frequency of
operation for digital logic, various power MOSFET and IGBT ICS,
improvement in refresh time for DRAM's, decrease in programming
time for nonvolatile memory, better visual quality including pixel
resolution and color sensitivity for imaging ICs, better
sensitivity for varactors in tunable filters, higher drive
capabilities for JFET's, and a host of other applications.
Inventors: |
Rao; G.R. Mohan;
(Richardson, TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Rao; G.R. Mohan |
Richardson |
TX |
US |
|
|
Family ID: |
35995339 |
Appl. No.: |
13/854319 |
Filed: |
April 1, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11622496 |
Jan 12, 2007 |
8421195 |
|
|
13854319 |
|
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Current U.S.
Class: |
257/591 ;
257/655 |
Current CPC
Class: |
H01L 27/10844 20130101;
H01L 27/14643 20130101; H01L 27/0214 20130101; H01L 29/36 20130101;
H01L 29/7395 20130101; H01L 27/11521 20130101; H01L 27/11524
20130101; H01L 29/1095 20130101 |
Class at
Publication: |
257/591 ;
257/655 |
International
Class: |
H01L 29/36 20060101
H01L029/36 |
Claims
1-8. (canceled)
9. A semiconductor device comprising: a surface layer; a substrate;
an active region including at least one emitter, at least one base
and at least one collector disposed in the above said device; at
least one drift layer positioned between said emitter and said
collector, said drift layer having at least one graded
concentration of dopants, said drift layer further having a first
static unidirectional electric field to aid movement of carriers
from said emitter to said collector; and at least one isolation
region disposed in the semiconductor device, said isolation region
having a graded concentration of dopants and a second static
unidirectional electric field to aid isolation between active
regions.
10. The semiconductor device of claim 9 wherein said static
unidirectional electric fields are adapted to respective grading of
dopants to aid movements of carriers in respective active
regions.
11. A semiconductor device comprising: at least one active region
with a channel conduction surface; at least one active device with
a vertical conduction; a first static unidirectional electric field
in said channel conducting region; said first unidirectional
electric field having a graded dopant concentration; a second
static unidirectional electric field in said vertical conduction;
said second static unidirectional electric field having a graded
dopant concentration; and a third static unidirectional electric
field; said third static unidirectional electric field having a
graded dopant concentration.
12. The semiconductor device of claim 9 wherein the semiconductor
device is a silicon substrate.
13. The semiconductor device of claim 9 wherein the semiconductor
device is an III-V compound substrate.
14. The semiconductor device of claim 9 wherein the semiconductor
device is an II-VI compound substrate.
15. The semiconductor device of claim 9 wherein the semiconductor
device is an organic material substrate.
16. The semiconductor device of claim 9 wherein the semiconductor
device is a silicon carbide substrate.
17. The semiconductor device of claim 9 wherein the semiconductor
device has at least one bipolar transistor.
18. The semiconductor device of claim 9 wherein the semiconductor
device has at least one vertical bipolar transistor.
19. The semiconductor device of claim 9 wherein the semiconductor
device has at least one planar bipolar transistor with a conducting
surface layer.
20. The semiconductor device of claim 9 wherein the semiconductor
device has at least one MOS transistor.
21. The semiconductor device of claim 9 wherein the semiconductor
device has at least one IGBT.
22. A semiconductor device comprising: a substrate; a surface
layer; an active region including at least one emitter and one
collector disposed in the device; a single drift layer disposed
between said emitter and said collector, said drift layer having at
least one graded concentration of dopants, said drift layer further
having a first static unidirectional electric field to aid movement
of carriers from said emitter to said collector; and at least one
isolation region disposed in the semiconductor device, said
isolation region having a graded concentration of dopants and a
second static unidirectional electric field to aid movement of
carriers.
23. The semiconductor device of claim 22 wherein the semiconductor
device is a varactor.
24. The semiconductor device of claim 22 wherein the semiconductor
device is a varistor.
25. The semiconductor device of claim 22 wherein the semiconductor
device is an avalanche transistor.
26. The semiconductor device of claim 22 wherein the semiconductor
device is a Zener diode.
27. The semiconductor device of claim 22 wherein the semiconductor
device is a Schottky diode.
28. The semiconductor device of claim 22 wherein the semiconductor
device is a tunneling diode.
29. The semiconductor device of claim 22 wherein the semiconductor
device is an Esaki diode.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a Divisional of U.S. application Ser.
No. 10/934,915, filed on Sep. 3, 2004, which application is
incorporated herein by reference.
FIELD OF INVENTION
[0002] This present invention relates to all semiconductor devices
and systems. Particularly it applies to diffused diodes, avalanche
diodes, Schottky devices, power MOS transistors, JFET's, RF bipolar
transistors, IGBTs (Insulated Gate Bipolar Transistors), varactors,
digital VLSI, mixed signal circuits and sensor devices including
camera ICs employing CCD (Charge Coupled Device) as well as CMOS
technologies.
BACKGROUND OF INVENTION
[0003] Bipolar Junction transistors (BJT) are minority carrier
devices as the principle device conduction mechanism. However,
majority carriers also a small yet finite role in modulating the
conductivity in BJTs. Consequently, both carriers (electrons and
holes) play a role in the switching performance of BJTs. The
maximum frequency of operation in BJTs is limited by the base
transit time as well as the quick recombination of the majority
carriers when the device is switched off (prior to beginning the
next cycle). The dominant carrier mechanism in BJTs is carrier
diffusion. Carrier drift current component is fairly small,
especially in uniformly doped base BJTs. Efforts have been made in
graded base transistors to create an `aiding drift field`, to
enhance the diffusing minority carrier's speed from emitter to
collector. However, most semiconductor devices, including various
power MOSFETs (traditional, DMOS, lateral, vertical and a host of
other configurations), IGBT's (Insulated Gated Base Transistors),
still use a uniformly doped drift epitaxial region in the base.
FIG. 1 shows the relative doping concentration versus distance in a
BJT. FIG. 2 shows the `uniformly doped epi region` in a IGBT. In
contrast to BJTs, MOS devices are majority carrier devices for
conduction. The conduction is channel dominated. The channel can be
a surface in one plane in planar devices. The surface can also be
on the sidewalls in a vertical device. Other device architectures
to combine planar and vertical conductions are also possible. The
maximum frequency of operation is dictated primarily by
source-drain separation distance. Most MOS devices use a uniformly
doped substrate (or a well region). When a MOSFET is optimally
integrated with a BJT in a monolithic fashion, an IGBT results. The
IGBT inherits the advantages of both MOSFET and BJT. It also brings
new challenges because the required characteristics (electron
transit and hole recombination as fast as possible in the case of
an n-channel IGBT) require different dopant gradients either in the
same layer at different positions, or at the interfaces of similar
or dissimilar layers.
[0004] `Retrograde` wells have been attempted, with little success,
to help improve soft error immunity in SRAM's and visual quality in
imaging circuits. FIG. 3(a) shows a typical CMOS VLSI device
employing a twin well substrate, on which active devices are
subsequently fabricated. FIGS. 3(b), 3(c), and 3(d) illustrate
device cross sections, as practiced today. `Retrograde` and `halo`
wells have also been attempted to improve refresh time in DRAM's
(dynamic random access memories), as well as, reducing dark current
(background noise) and enhance RGB (Red, Green, Blue) color
resolution in digital camera Ics. Most of these techniques either
divert the minority carriers away form the active regions of
critical charge storage nodes at the surface, or, increase minority
carrier density locally as the particular application requires.
BRIEF DESCRIPTION OF DRAWINGS
[0005] For a more complete understanding of the present invention,
and the advantages thereof, reference is now made to the following
descriptions taken in conjunction with the accompanying drawings,
in which:
[0006] FIG. 1 illustrates the relative doping profiles of emitter,
base, and collector, for the two most popular bipolar junction
transistors: namely, A--uniform base, and B--graded base;
[0007] FIG. 2 illustrates the cross section of a commercial IGBT
with a uniform epitaxial drift region (base);
[0008] FIGS. 3(a), 3(b), 3(c), 3(d) illustrate cross sections
commonly used CMOS silicon substrate with two wells (one n-well in
which p-channel transistors are subsequently fabricated, and, one
p-well in which n-channel transistors are subsequently
fabricated)--typical IC, EEPROM using tunnel insulator, DRAM and
NAND flash;
[0009] FIG. 4 illustrates the cross section of a IGBT, using one
embodiment of the invention described here, where the dopant is
optimally graded in the eptaxial drift region; and
[0010] FIGS. 5(a), 5(b), 5(c) illustrate the cross sections of a
MOS silicon substrate with two wells, and, an underlying layer
using embodiments of the invention to improve performance in each
application--VLSI logic, DRAM/image IC, nonvolatile memory IC.
DETAILED DESCRIPTION OF THE INVENTION
[0011] The relative doping concentrations of emitter and collector
regions varies from 10.sup.18 to 10.sup.20/cm.sup.3, where as the
base region is 10.sup.14 to 10.sup.16/cm.sup.3 depending on the
desired characteristics of the BJT. In graded base p-n-p
transistors, the donor dopant concentration may be 10 to 100.times.
at the emitter-base junction, relative to the base-collector
junction (1.times.). The gradient can be linear, quasi linear,
exponential or complimentary error function. The relative slope of
the donor concentration throughout the base, creates a suitable
aiding drift electric field, to help the holes (p-n-p transistor)
transverse from emitter to collector. Since the aiding drift field
helps hole conduction, the current gain at a given frequency is
enhanced, relative to a uniformly-doped-(base) BJT. The improvement
in cut-off frequency (or, frequency at unity gain, f.sub.T) can be
as large as 2.times.-5.times.. Similar performance improvements are
also applicable to n-p-n transistors.
[0012] As illustrated in FIG. 4, in one embodiment according to the
invention, a donor gradient is established from the emitter-drift
epitaxial base region junction of the punch-through IGBT, to the
drift epitaxial base region--n.sup.t buffer layer boundary
(electrons in this case are accelerated in their transit from
emitter to collector). The `average` base resistance is optimized,
so that conductivity modulation and lifetime (for minority
carriers) in base region are not compromised. By sweeping the
carriers towards the n' buffer region two advantages are
obtained--the frequency of operation (combination of t.sub.on and
t.sub.off as is known in the IGBT commercial nomenclature) can be
enhanced. More importantly, during t.sub.off, holes can be
recombined much quicker at the n.sup.t buffer layer, compared to a
uniformly doped n.sup.- epitaxial drift region by establishing a
different dopant gradient near the n+ buffer layer. It should be
noted that the drift region can also be a non-epitaxial silicon
substrate. Epitaxy enhances lifetime, but, epitaxy is not
mandatory. Different layers of dopan regions can be transferred
through wafer to wafer bonding (or other similar transfer
mechanisms) for eventual device fabrication. The "reverse recovery
time" for an IGBT is significantly improved due to the optimized
graded dopant in the so called "drift region" as well as at the
interfaces of the drift region. Graded dopants can also be
implemented in the n+ buffer layer as well as other regions
adjacent to the respective layers. Two important performance
enhancements are the result of dopant gradients. For example, in an
n-channel IGBT, electrons can be swept from source to drain
rapidly, while at the same time holes can be recombined closer to
the n+buffer layer. This can improve t(on) and t(off) in the same
device.
[0013] The following paragraph, beginning on page 5, line 6, and
ending on page 11, line 28, is amended as indicated in the marked
up version below:
[0014] As illustrated in FIGS. 5(a), 5(b), 5(c), donor gradient is
also of benefit to very large scale integrated circuits
(VLSI)--VLSI logic, DRAM, nonvolatile memory like NAND flash.
Spurious minority carriers can be generated by clock switching in
digital VLSI logic and memory IC'S. These unwanted carriers can
discharge dynamically-held `actively held high` nodes. Statically
held nodes (with V.sub.cc) can not be affected, in most cases.
Degradation of refresh time in DRAM's is one of the results,
because the capacitor holds charge dynamically Similarly,
degradation of CMOS digital images, in digital imaging IC's is
another result of the havoc caused by minority carriers. Pixel and
color resolution can be significantly enhanced in imaging IC's with
the embodiments described here. Creating `Sub Terrain`
recombination centers underneath the wells (gold doping, platinum
doping) as is done in some high-voltage diodes is not practical for
VLSI circuits. Hence, a novel technique has been described here by
creating a drift field to sweep these unwanted minority carriers
into the substrate as quickly as possible, from the active
circuitry at the surface. In a preferred embodiment, the subterrain
n-layer has a graded donor concentration to sweep the minority
carriers deep into the substrate. One or more of such layers can
also be implemented through wafer to wafer bonding or similar
"transfer" mechanisms. This n-layer can be a deeply-implanted
layer. It can also be an epitaxial layer. The n-well and p-well
also can be graded or retrograded in dopants, as desired, to sweep
those carriers away from the surface as well. The graded dopant can
also be implemented in surface channel MOS devices to accelerate
majority carriers towards the drain. In nonvolatile memory devices,
to decrease programming time, carriers should be accelerated
towards the surface when programming of memory cells is executed.
The graded dopant can also be used to fabricate superior Junction
field-effect transistors where the "channel pinchoff" is controlled
by a graded channel instead of a uniformly doped channel (as
practiced in prior art).
[0015] One of ordinary skill and familiarity in the art will
recognize that the concepts taught herein can be customized and
tailored to a particular application in many advantageous ways. For
instance, minority carriers can be channeled to the surface, to aid
programming in nonvolatile memory devices (NOR, NAND,
multivalued-cell). Moreover, single well, as well triple-well CMOS
fabrication techniques can also be optimized to incorporate these
embodiments, individually and collectively. Any modifications of
such embodiments (described here) fall within the spirit and scope
of the invention. Hence, they fall within the scope of the claims
described below
[0016] Although the invention has been described with reference to
specific embodiments, these descriptions are not meant to be
construed in a limiting sense. Various modifications of the
disclosed embodiments, as well as alternative embodiments of the
invention will become apparent to persons skilled in the art upon
reference to the description of the invention. It should be
appreciated by those skilled in the art that the conception and the
specific embodiment disclosed may be readily utilized as a basis
for modifying or designing other structures for carrying out the
same purposes of the present invention. It should also be realized
by those skilled in the art that such equivalent constructions do
not depart from the spirit and scope of the invention as set forth
in the appended claims.
[0017] It is therefore, contemplated that the claims will cover any
such modifications or embodiments that fall within the true scope
of the invention.
* * * * *