U.S. patent application number 13/614812 was filed with the patent office on 2013-07-25 for method to form silicide contact in trenches.
This patent application is currently assigned to GLOBALFOUNDRIES Inc.. The applicant listed for this patent is Michael A. GUILLORN, Christian LAVOIE, Ghavam G. SHAHIDI, Bin YANG, Zhen ZHANG. Invention is credited to Michael A. GUILLORN, Christian LAVOIE, Ghavam G. SHAHIDI, Bin YANG, Zhen ZHANG.
Application Number | 20130189839 13/614812 |
Document ID | / |
Family ID | 48796518 |
Filed Date | 2013-07-25 |
United States Patent
Application |
20130189839 |
Kind Code |
A1 |
GUILLORN; Michael A. ; et
al. |
July 25, 2013 |
METHOD TO FORM SILICIDE CONTACT IN TRENCHES
Abstract
A method for forming silicide contacts includes forming a
dielectric layer on a gate spacer, a gate stack, and a first
semiconductor layer. The first semiconductor layer comprises
source/drain regions. Contact trenches are formed in the dielectric
layer so as to expose at least a portion of the source/drain
regions. A second semiconductor layer is formed within the contact
trenches. A metallic layer is formed on the second semiconductor
layer. An anneal is performed to form a silicide region between the
second semiconductor layer and the metallic layer. A conductive
contact layer is formed on the metallic layer or the silicide
region.
Inventors: |
GUILLORN; Michael A.;
(Yorktown Heights, NY) ; LAVOIE; Christian;
(Pleasantville, NY) ; SHAHIDI; Ghavam G.; (Pound
Ridge, NY) ; YANG; Bin; (San Carlos, CA) ;
ZHANG; Zhen; (Ossining, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
GUILLORN; Michael A.
LAVOIE; Christian
SHAHIDI; Ghavam G.
YANG; Bin
ZHANG; Zhen |
Yorktown Heights
Pleasantville
Pound Ridge
San Carlos
Ossining |
NY
NY
NY
CA
NY |
US
US
US
US
US |
|
|
Assignee: |
GLOBALFOUNDRIES Inc.
Grand Cayman
NY
INTERNATIONAL BUSINESS MACHINES CORPORATION
Armonk
|
Family ID: |
48796518 |
Appl. No.: |
13/614812 |
Filed: |
September 13, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13356090 |
Jan 23, 2012 |
|
|
|
13614812 |
|
|
|
|
Current U.S.
Class: |
438/675 ;
257/E21.586 |
Current CPC
Class: |
H01L 29/41775 20130101;
H01L 21/76846 20130101; H01L 21/823871 20130101; H01L 2924/0002
20130101; H01L 29/458 20130101; H01L 29/78621 20130101; H01L 23/485
20130101; H01L 29/41733 20130101; H01L 2924/0002 20130101; H01L
29/6659 20130101; H01L 21/823814 20130101; H01L 21/28518 20130101;
H01L 21/76855 20130101; H01L 29/41725 20130101; H01L 29/66772
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
438/675 ;
257/E21.586 |
International
Class: |
H01L 21/768 20060101
H01L021/768 |
Claims
1. A method for forming silicide contacts, the method comprising:
forming a dielectric layer on a gate spacer, a gate stack, and a
first semiconductor layer comprising source/drain regions; forming
contact trenches in the dielectric layer, wherein the contact
trenches expose at least a portion of the source/drain regions;
forming a second semiconductor layer within the contact trenches,
wherein a bottom portion of the second semiconductor layer is
formed on exposed portions of the source/drain regions, and wherein
the second semiconductor layer comprises vertical sidewalls formed
on inner sidewalls of the contact trenches; forming a metallic
layer on the second semiconductor layer; and forming a conductive
contact layer on the metallic layer.
2. The method of claim 1, further comprising: after forming the
metallic layer and prior to forming the conductive contact layer,
performing an anneal, wherein the anneal forms a silicide region
between the second semiconductor layer and the metallic layer.
3. The method of claim 1, further comprising: after forming the
conductive contact layer, performing an anneal, wherein the anneal
forms a silicide region between second semiconductor layer and the
metallic layer.
4. The method of claim 1, further comprising: forming, prior to
forming the conductive contact layer, a conductive contact liner on
the metallic layer.
5. The method of claim 1, further comprising: prior to forming the
second semiconductor layer, forming an interlayer on the exposed
portion of the source/drain regions.
6. The method of claim 5, wherein the interlayer comprises at least
one of impurities, dopants, and band edge materials.
7. The method of claim 1, further comprising: removing the second
semiconductor layer, the metallic layer, and the conductive contact
layer from the dielectric layer, wherein the dielectric layer acts
as a stop layer.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is continuation of and claims priority from
U.S. patent application Ser. No. 13/356,090 filed on Jan. 23, 2012,
now ______, the disclosure of which is hereby incorporated by
reference in its entirety.
FIELD OF THE INVENTION
[0002] The present invention generally relates to the field of
semiconductors, and more particularly relates to forming silicide
contacts for a semiconductor device.
BACKGROUND OF THE INVENTION
[0003] Silicide contacts are of specific importance to integrated
circuits, including those having complementary metal oxide
semiconductor (CMOS) devices, because of the need to reduce the
electrical resistance of the contacts (particularly at the
source/drain and gate regions) in order to increase chip
performance. Silicides are metal compounds that are thermally
stable and provide for low electrical resistivity at the
silicon/metal interface. Reducing contact resistance improves
device speed, therefore increasing device performance.
SUMMARY OF THE INVENTION
[0004] In one embodiment, a method for forming silicide contacts is
disclosed. The method comprises forming a dielectric layer on a
gate spacer, a gate stack, and a first semiconductor layer. The
semiconductor layer comprises source/drain regions. Contact
trenches are formed in the dielectric layer so as to expose at
least a portion of the source/drain regions. A second semiconductor
layer is deposited/formed within the contact trenches. A metallic
layer is deposited/formed on the second semiconductor layer for
formation of a silicide layer/region. A conductive contact layer is
formed/formed on the metallic or silicide layer/region to fill the
contact trenches. These layers outside the contact trenches are
mechanically removed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] The accompanying figures where like reference numerals refer
to identical or functionally similar elements throughout the
separate views, and which together with the detailed description
below are incorporated in and form part of the specification, serve
to further illustrate various embodiments and to explain various
principles and advantages all in accordance with the present
invention, in which:
[0006] FIG. 1 is a cross-sectional view of a semiconductor
structure after a dielectric layer has been formed on a
semiconductor substrate according to one embodiment of the present
invention;
[0007] FIG. 2 is a cross-sectional view of the semiconductor
structure after contact regions have been formed in the dielectric
layer according to one embodiment of the present invention;
[0008] FIG. 3 is a cross-sectional view of the semiconductor
structure after a semiconductor layer and a metallic layer have
been formed in the contact regions according to one embodiment of
the present invention;
[0009] FIG. 4 is a cross-sectional view of the semiconductor
structure after a conductive contact layer and conductive fill
material layer and a metallic layer have been formed in the contact
regions according to one embodiment of the present invention;
[0010] FIG. 5 is a cross-sectional view of the semiconductor
structure after a planarization process has been performed on the
structure shown in FIG. 4 according to one embodiment of the
present invention;
[0011] FIG. 6 is an operational flow diagram illustrating one
process for forming silicide contacts according to one embodiment
of the present invention.
DETAILED DESCRIPTION
[0012] As required, detailed embodiments of the present invention
are disclosed herein; however, it is to be understood that the
disclosed embodiments are merely exemplary of the invention, which
can be embodied in various forms. Therefore, specific structural
and functional details disclosed herein are not to be interpreted
as limiting, but merely as a basis for the claims and as a
representative basis for teaching one skilled in the art to
variously employ the present invention in virtually any
appropriately detailed structure. Further, the terms and phrases
used herein are not intended to be limiting; but rather, to provide
an understandable description of the invention.
[0013] The terms "a" or "an", as used herein, are defined as one as
or more than one. The term plurality, as used herein, is defined as
two as or more than two. Plural and singular terms are the same
unless expressly stated otherwise. The term another, as used
herein, is defined as at least a second or more. The terms
including and/or having, as used herein, are defined as comprising
(i.e., open language). The term coupled, as used herein, is defined
as connected, although not necessarily directly, and not
necessarily mechanically. The terms program, software application,
and the like as used herein, are defined as a sequence of
instructions designed for execution on a computer system. A
program, computer program, or software application may include a
subroutine, a function, a procedure, an object method, an object
implementation, an executable application, an applet, a servlet, a
source code, an object code, a shared library/dynamic load library
and/or other sequence of instructions designed for execution on a
computer system.
[0014] As discussed above, silicide contacts are of specific
importance to integrated circuits. However, most conventional
processes for forming silicide contacts experience a certain amount
of consumption of the substrate during silicide formation. In
conventional transistors, nickel and its alloys are commonly used
for silicides, where nickel to silicon consumption ratio is, for
example, approximately 1.8. Such consumption can be a serious issue
when the substrate material is limited. One example is the thin
silicon-on-insulator (SOI) device. Another drawback of conventional
processes is that selectively etching excessive silicide can be
challenging for various metals. Therefore, one or more embodiments
of the present invention forms contact regions that comprises a
semiconductor layer formed within the contact regions. This
semiconductor layer is formed on source/drain regions within the
underlying semiconductor layer (active region). A metallic layer is
formed on the second semiconductor layer. A conductive contact
layer is formed on the metallic or silicide layer. By forming a
semiconductor layer on the source/drain regions silicon from the
underlying semiconductor layer is not consumed when
silicide/germanide regions are formed. Another advantage is that
band edge silicide/germanide is obtainable. A further advantage is
that the silicide/contact integration process of various
embodiments allows for silicide integration using rare earth
materials.
[0015] FIGS. 1-5 illustrate an example of a process for forming
silicide contacts for a semiconductor device according to one
embodiment of the present invention. It should be noted that the
following process discussed below is applicable to both nFET and
pFET devices. It should also be noted that one or more embodiments
of the present invention are applicable to both bulk substrate
devices and SOI devices. As shown in FIG. 1, there is provided a
handle substrate 102, a buried insulator layer (e.g., buried oxide
(BOX)) 104, and a top semiconductor layer 106. The handle substrate
102 can be a semiconductor substrate comprising a single
crystalline semiconductor material such as single crystalline
silicon, a polycrystalline semiconductor material, an amorphous
semiconductor material, or a stack thereof. The thickness of the
handle substrate 102 can be, for example, from 50 microns to 1,000
microns, although lesser and greater thicknesses can also be
employed. A buried insulator layer 104 includes a dielectric
material such as silicon oxide, silicon nitride, silicon
oxynitride, or any combination thereof.
[0016] The thickness of the buried insulator layer 104 can be, for
example, form 50 nm to 500 nm, although lesser and greater
thicknesses can also be employed. The thickness of the top
semiconductor layer 106 can be, for example, from 3 nm to 80 nm,
and typically from 5 nm to 10 nm, although lesser and greater
thicknesses can also be employed. The top semiconductor layer 106
can comprise any semiconducting material, including but not limited
to Si (silicon), strained Si, SiC (silicon carbide), Ge (geranium),
SiGe (silicon germanium), SiGeC (silicon-germanium-carbon), Si
alloys, Ge alloys, GaAs (gallium arsenide), InAs (indium arsenide),
InP (indium phosphide), GaSb (gallium antimonide), or any
combination thereof, as well as other III/V or II/VI compound
semiconductors and alloys thereof.
[0017] FIG. 1 shows that the top semiconductor layer 106 includes
various single crystalline semiconductor portions, which can
comprise, for example, a body/channel region 108, a source
extension region 110, a drain extension region 112, a planar source
region 114, and a planar drain region 116. Shallow trench isolation
structures 118 can be formed in the top semiconductor layer 106
employing conventional fabrication methods. For example, the
shallow trench isolation structures 118 can be formed by trenches
extending from the top surface of the top semiconductor layer 106
at least to the top surface of the buried insulator layer 104,
filling the trenches with a dielectric material, and removing
excess dielectric material from above the top surface of the top
semiconductor layer 106.
[0018] The various single crystalline semiconductor portions (108,
110, 112, 114, 116) in the top semiconductor layer 106 can be
formed by introducing electrical dopants such as B, Ga, In, P, As,
and/or Sb by ion implantation, plasma doping, and/or gas phase
doping employing various masking structures as known in the art.
Before implanting electrical dopants into various portions of the
top semiconductor layer 106, a gate stack structure 120 and gate
spacer 122 are formed. The gate stack 120 is formed on the
semiconductor layer 106 over the body region 108. In one
embodiment, the gate stack 120 comprises a gate dielectric 124 and
a gate conductor 126. In the illustrated embodiment, a gate
polysilicon cap 128 is deposited on the gate conductor layer 126,
such as through LPCVD or silicon sputtering. It should be noted
that instead of first forming the gate stack 120, a replacement
(dummy) gate structure can be formed to act as a place holder for
the gate stack, which is formed during a subsequent processing
step.
[0019] The gate stack 120 can be formed by depositing a stack of a
gate dielectric material and a gate conductor material on the top
semiconductor layer 106. This stack is then patterned and etched to
form the gate dielectric 124 and the overlying gate conductor 126
on a portion of the top semiconductor layer 106. The gate
dielectric 124 of this embodiment is a conventional dielectric
material (such as silicon oxide, silicon nitride, silicon
oxynitride, or a stack thereof) that is formed by thermal
conversion of a top portion of the active region and/or by chemical
vapor deposition (CVD). In an alternative embodiment, the gate
dielectric 124 is a high-k dielectric material (such as hafnium
oxide, zirconium oxide, lanthanum oxide, aluminum oxide, titanium
dioxide, strontium titanate, lanthanum aluminate, yttrium oxide, an
alloy thereof, or a silicate thereof) that is formed by CVD, atomic
layer deposition (ALD), molecular beam epitaxy (MBE), pulsed laser
deposition (PLD), liquid source misted chemical deposition (LSMCD),
or physical vapor deposition (PVD). Alternatively, the gate
dielectric may comprise any suitable combination of those
dielectric materials.
[0020] The gate conductor 126 is a semiconductor (e.g.,
polysilicon) gate layer and/or a metal gate layer. For example, the
gate dielectric 124 can be a conventional dielectric material and
the gate conductor 126 can be a semiconductor gate layer.
Alternatively, the gate dielectric 124 can be a high-k dielectric
material and the gate conductor 126 can be a metal gate layer of a
conductive refractory metal nitride (such as tantalum nitride,
titanium nitride, tungsten nitride, titanium aluminum nitride,
triazacyclononane, or an alloy thereof). In a further embodiment,
the gate conductor 126 comprises a stack of a metal gate layer and
a semiconductor gate layer. The gate stack 120 can also include a
work function metallic layer as well. In yet a further embodiment,
the gate stack 120 can be formed atop an optional chemical oxide
layer (not shown) (also referred to herein as an "interfacial
layer"), which is formed on an exposed semiconductor surface of the
body portion 108 of the top semiconductor layer 106.
[0021] The gate spacer 122 comprises a dielectric material (such as
silicon oxide, silicon nitride, silicon oxynitride or any
combination of these). The gate spacer 122 is formed on gate stack
120 and on a portion of the top semiconductor layer 106. In one
embodiment, a reactive-ion etch process is used to remove the
dielectric material on horizontal surfaces such as the top of the
gate stack 120, the STI regions 118, and portions of the top
semiconductor layer 106 to form a gate spacer only on the sidewall
of the gate structure 106. However, the gate spacer material can be
etched such that the gate spacer 122 also resides on top of the
gate structure 106 as well.
[0022] A dielectric layer 130 (e.g., an oxide layer, nitride layer,
low-k material or any suitable combination of those materials) is
then formed over the entire structure, as shown in FIG. 1. Next,
portions of the dielectric layer 130 over the source/drain regions
114, 116 are removed (e.g., through a dry etch such as RIE and/or a
wet etch using HF) so as to create contact regions such as
trenches/openings 232 and 234 exposing a portion of the
source/drain regions 114, 116, as shown in FIG. 2. A semiconductor
material is deposited and a contact trench semiconductor layer 336
is formed on the exposed portion of the source/drain regions 114,
116, inner sidewalls of the contact trenches 232, 234, and a top
surface of the dielectric layer 130, as shown in FIG. 3. The
contact trench semiconductor layer 336 can be formed by chemical
vapor deposition (CVD), molecular beam epitaxy (MBE), physical
vapor deposition (PVD), atomic layer deposition (ALD), or any
combination thereof. The contact trench semiconductor layer 336
comprises any semiconducting material, including but not limited to
Si, strained Si, SiC, Ge, SiGe, SiGeC, Si alloys, Ge alloys, GaAs,
InAs, InP, GaSb, or any combination thereof, as well as other III/V
or II/VI compound semiconductors and alloys thereof. The contact
trench semiconductor layer 336 can be formed with a thickness
ranging from, for example, 1-10 nm.
[0023] A metal/metallic material is deposited and a contact trench
metallic layer 338 is formed on the contact trench semiconductor
layer 336. For example, the contact trench metallic layer 338 is
formed on the inner sidewalls of the contact trench semiconductor
layer 336, a bottom (horizontal) portion of the contact trench
semiconductor layer 336 (which is formed on the source/drain
regions 114, 116), and a top surface of the contact trench
semiconductor layer 336, as shown in FIG. 3. The contact trench
metallic layer 338 can be formed by chemical vapor deposition
(CVD), physical vapor deposition (PVD), atomic layer deposition
(ALD), or any combination thereof. The contact trench metallic
layer 338 comprises a metallic material, including but not limited
to nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt), rare
earth metals (e.g., Erbium (Er), Ytterbium (Yt), etc.), silicides
(or germanides) of these materials, or an alloy or any combination
thereof. The contact trench metallic layer 338 can be formed with a
thickness ranging from, for example, 1-10 nm. It should be noted
that, in one embodiment, the thickness of the metallic layer 338
can be adjusted such that the semiconductor layer 336 is consumed
during the silicide reaction process provided subsequent thermal
treatment.
[0024] It should be noted that in one embodiment, an optional thin
layer (interlayer) of impurities (e.g., Sulfur (S), Selenium (Se),
etc.), dopants (e.g., Boron (B), Arsenic (As), Phosphorous (P),
Antimony (Sb), Gallium (Ga), Aluminum (Al), etc.), band edge
materials (e.g., Pt, Er, Yb, Al, etc.) can be formed on the
source/drain region 114, 116 of the top semiconductor layer 106
prior to forming the contact trench semiconductor layer 336. This
optional thin layer modifies the Schottky barrier height (SBH) of
the contact trench semiconductor layer 336 for reducing contact
resistance.
[0025] After the contact trench metallic layer 338 has been formed,
an optional conductive contact liner 440 (e.g., a titanium nitride
liner, tantalum nitride liner, etc.) is formed on the contact
trench metallic layer 338. For example, the optional conductive
contact liner 440 is formed on the inner sidewalls of the contact
trench metallic layer 338, a bottom (horizontal) portion of the
contact trench metallic layer 338 (which is formed on the bottom
portion of the contact trench semiconductor layer 336), and a top
surface of the contact trench metallic layer 338, as shown in FIG.
4. Then, a conductive fill material layer 442 (e.g., a metal, such
as tungsten, copper, aluminum, or any other conventional contact
material) is deposited in the remaining portion of the contact
trenches 232, 234 until the contact trenches 232, 234 are filled,
as shown in FIG. 4. The conductive fill material layer 442 is
formed on the inner sidewalls of the conductive contact liner 440,
a bottom (horizontal) portion of the conductive contact liner 440
(which is formed on the bottom portion of the contact trench
metallic layer 338), and a top surface of the conductive contact
liner 440, as shown in FIG. 4.
[0026] An anneal is then optionally performed to form silicide
(germanide) resulting from the reaction of the contact trench
metallic layer 338 with the contact trench semiconductor layer 336.
It should be noted that this anneal can also be performed after the
contact trench metallic layer 338 has been formed and prior to
forming the conductive contact liner 440.
[0027] It should be noted that, in one embodiment, optional
impurities (e.g., Sulfur (S), Selenium (Se), etc.), dopants (e.g.,
Boron (B), Arsenic (As), Phosphorous (P), Antimony (Sb), Gallium
(Ga), Aluminum (Al), etc.), band edge materials (e.g., Pt, Er, Yb,
Al, etc.) are supplied on the metallic layer 338 or the formed
silicide (germanide), e.g. by ion implantation or other deposition
methods. The impurities can be thermally diffused to the silicide
(germanide) substrate interface to reduce contact resistance.
[0028] The contact trench semiconductor layer 336, contact trench
metallic layer 338, conductive contact liner 440, and conductive
fill material layer 442 are then planarized utilizing any
conventional process such as, but not limited to, chemical
mechanical polishing (CMP) or RIE, where the dielectric layer 130
is used as a stop layer. The resulting structure is shown in FIG.
5. Conventional processes are the performed to complete the
fabrication process.
[0029] FIG. 6 is an operational flow diagram illustrating one
process for forming silicide contacts according to one embodiment
of the present invention. In FIG. 6, the operational flow diagram
begins at step 602 and flows directly to step 604. It should be
noted that each of the steps shown in FIG. 6 has been discussed in
greater detail above with respect to FIGS. 1-5. After a gate
structure 120, gate spacer 122, and source/drain regions 114, 116
are formed, a dielectric layer 130, at step 604, is formed over a
top semiconductor layer 106, the gate spacer 122, and the gate
structure 120. Contact trenches 232, 234, at step 606, are formed
in the dielectric layer 130 so as to expose at least a portion of
the source/drain regions 114, 116.
[0030] A contact trench semiconductor layer 336, at step 608, is
formed within the contact trenches 232, 234. A contact trench
metallic layer 338, at step 610, is formed on the contact trench
semiconductor layer 336. An optional conductive contact liner 440,
at step 612 is formed on the contact trench metallic layer 338. A
conductive fill material layer 442, at step 614, is formed in the
remaining portion of the contact trenches 232, 234. Conventional
fabrication processes, at step 616, are performed to complete the
device. The control flow then exits at step 618.
[0031] It should be noted that some features of the present
invention may be used in an embodiment thereof without use of other
features of the present invention. As such, the foregoing
description should be considered as merely illustrative of the
principles, teachings, examples, and exemplary embodiments of the
present invention, and not a limitation thereof.
[0032] It should be understood that these embodiments are only
examples of the many advantageous uses of the innovative teachings
herein. In general, statements made in the specification of the
present application do not necessarily limit any of the various
claimed inventions. Moreover, some statements may apply to some
inventive features but not to others.
[0033] The circuit as described above is part of the design for an
integrated circuit chip. The chip design is created in a graphical
computer programming language, and stored in a computer storage
medium (such as a disk, tape, physical hard drive, or virtual hard
drive such as in a storage access network). If the designer does
not fabricate chips or the photolithographic masks used to
fabricate chips, the designer transmits the resulting design by
physical means (e.g., by providing a copy of the storage medium
storing the design) or electronically (e.g., through the Internet)
to such entities, directly or indirectly. The stored design is then
converted into the appropriate format (e.g., GDSII) for the
fabrication of photolithographic masks, which typically include
multiple copies of the chip design in question that are to be
formed on a wafer. The photolithographic masks are utilized to
define areas of the wafer (and/or the layers thereon) to be etched
or otherwise processed.
[0034] The methods as discussed above are used in the fabrication
of integrated circuit chips.
[0035] The resulting integrated circuit chips can be distributed by
the fabricator in raw wafer form (that is, as a single wafer that
has multiple unpackaged chips), as a bare chip, or in a packaged
form. In the latter case, the chip is mounted in a single chip
package (such as a plastic carrier, with leads that are affixed to
a motherboard or other higher level carrier) or in a multichip
package (such as a ceramic carrier that has either or both surface
interconnections or buried interconnections). In any case, the chip
is then integrated with other chips, discrete circuit elements,
and/or other signal processing devices as part of either (a) an
intermediate product, such as a motherboard, or (b) an end product.
The end product can be any product or electronic device that
includes integrated circuit chips, ranging from toys and other
low-end applications to advanced computer products having a
display, a keyboard, or other input device, and a central
processor.
[0036] Although specific embodiments of the invention have been
disclosed, those having ordinary skill in the art will understand
that changes can be made to the specific embodiments without
departing from the spirit and scope of the invention. The scope of
the invention is not to be restricted, therefore, to the specific
embodiments, and it is intended that the appended claims cover any
and all such applications, modifications, and embodiments within
the scope of the present invention.
* * * * *