U.S. patent application number 13/599834 was filed with the patent office on 2013-06-13 for test pattern of semiconductor device, method of manufacturing test pattern and method of testing semiconductor device by using test pattern.
The applicant listed for this patent is Chang Kil KIM. Invention is credited to Chang Kil KIM.
Application Number | 20130147509 13/599834 |
Document ID | / |
Family ID | 48571404 |
Filed Date | 2013-06-13 |
United States Patent
Application |
20130147509 |
Kind Code |
A1 |
KIM; Chang Kil |
June 13, 2013 |
TEST PATTERN OF SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING TEST
PATTERN AND METHOD OF TESTING SEMICONDUCTOR DEVICE BY USING TEST
PATTERN
Abstract
A test pattern of a semiconductor device includes a plurality of
active regions defined in a semiconductor substrate and arranged in
parallel with each other, a plurality of gate patterns formed over
the plurality of active regions, a plurality of gate contacts
formed over the plurality of gate patterns, first junction contacts
formed over respective end portions of odd-numbered active regions
among the plurality of active regions, second junction contacts
formed over respective end portions of even-numbered active regions
among the plurality of active regions, and a contact pad configured
to couple the first junction contacts and the plurality of gate
contacts.
Inventors: |
KIM; Chang Kil; (Seoul,
KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
KIM; Chang Kil |
Seoul |
|
KR |
|
|
Family ID: |
48571404 |
Appl. No.: |
13/599834 |
Filed: |
August 30, 2012 |
Current U.S.
Class: |
324/762.01 ;
257/48; 257/E21.576; 257/E23.002; 438/586 |
Current CPC
Class: |
H01L 22/34 20130101 |
Class at
Publication: |
324/762.01 ;
257/48; 438/586; 257/E23.002; 257/E21.576 |
International
Class: |
H01L 23/58 20060101
H01L023/58; G01R 31/26 20060101 G01R031/26; H01L 21/768 20060101
H01L021/768 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 13, 2011 |
KR |
10-2011-0133731 |
Claims
1. A test pattern of a semiconductor device, the test pattern
comprising: a plurality of active regions defined in a
semiconductor substrate and arranged in parallel with each other; a
plurality of gate patterns formed over the plurality of active
regions; a plurality of gate contacts formed over the plurality of
gate patterns; first junction contacts formed over respective end
portions of odd-numbered active regions among the plurality of
active regions; second junction contacts formed over respective end
portions of even-numbered active regions among the plurality of
active regions; and a contact pad configured to couple the first
junction contacts and the plurality of gate contacts.
2. The test pattern of claim 1, wherein the plurality of gate
patterns and the plurality of gate contacts are formed in a scribe
region of the semiconductor substrate with substantially the same
structures as gate patterns and gate contacts of an X decoder.
3. The test pattern of claim 1, wherein a first terminal (+) is
coupled to the contact pad, and a second terminal (-) is coupled to
the second junction contacts.
4. The test pattern of claim 1, wherein the end portions of the
odd-numbered active regions are disposed opposite the end portions
of the even-numbered active regions.
5. A semiconductor device, comprising: an X decoder including first
gate patterns and first gate contacts and configure to select word
lines of a memory cell block; a plurality of active regions defined
in a scribe region of a semiconductor substrate and arranged in
parallel with each other; a plurality of second gate patterns
formed over the plurality of active regions; a plurality of second
gate contacts formed over the plurality of gate patterns, wherein
the second gate patterns and gate contacts have the same structures
as the first gate patterns and gate contacts of the X decoder;
first and second junction contacts formed over respective end
portions of the plurality of active regions; and a first contact
pad configured to couple the first junction contacts and the
plurality of second gate contacts.
6. The test pattern of claim 5, further comprising: a second
contact pad configured to couple the second junction contacts.
7. A test pattern of a semiconductor device, the test pattern
comprising: first active regions and second active regions defined
in a scribe region of a semiconductor substrate and alternating
with each other; a plurality of gate patterns formed over the first
active regions and the second active regions, respectively; a
plurality of gate contacts formed over the plurality of gate
patterns; at least one first contact formed over the first active
regions; and at least one second contact formed over the second
active regions.
8. The test pattern of claim 7, wherein the first contact is
coupled to a first terminal (+), and the second contact is coupled
to the second terminal (-).
9. A method of forming a test pattern of a semiconductor device,
the method comprising: defining a plurality of active regions by
performing an isolation process on a semiconductor substrate;
forming a plurality of gate patterns over the plurality of active
regions; forming a plurality of gate contacts coupled to top
portions of the plurality of gate patterns; forming first and
second junction contacts coupled to respective end portions of the
plurality of active regions; and forming a first contact pad
coupled to the first junction contacts and the plurality of gate
contacts.
10. The method of claim 9, wherein the forming of the plurality of
gate patterns and the plurality of gate contacts is performed in a
process of forming gates patterns and gate contacts for transistors
of an X decoder of the semiconductor device.
11. The method of claim 10, wherein the plurality of gate patterns
and the plurality of gate contacts have the same structures as the
gates patterns and the gate contacts of the X decoder,
respectively.
12. The method of claim 9, wherein the forming of the first and
second junction contacts coupled to the respective end portions of
the plurality of active regions comprises: forming the first
junction contacts coupled to respective end portions of
odd-numbered active regions among the plurality of active regions;
and forming the second junction contacts coupled to respective end
portions of even-numbered active regions among the plurality of
active regions.
13. The method of claim 12, wherein the end portions of the
odd-numbered active regions are disposed opposite the end portions
of the even-numbered active regions.
14. The method of claim 9, further comprising: forming a second
contact pad coupled to the second junction contacts.
15. The method of claim 14, wherein a first terminal (+) is coupled
to the first contact pad, and a second terminal (-) is coupled to
the second contact pad.
16. A method of testing a semiconductor device which includes a
plurality of second gate patterns and a plurality of second gate
contacts over first and second active regions the same structure as
first gate patterns and first gate contacts of an X decoder, the
method comprising: coupling a first terminal (+) to at least one
first contact coupled to the first active regions; coupling a
second terminal (-) to at least one second contact coupled to the
second active regions; and testing whether or not current flows
between the first terminal and the second terminal.
17. The method of claim 16, wherein the first gate patterns and the
first gate contacts of the X decoder are determined to be aligned
with each other in the testing of whether or not the current flows
between the first terminal and the second terminal.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] Priority is claimed to Korean patent application number
10-2011-0133731 filed on Dec. 13, 2011, the entire disclosure of
which is incorporated herein by reference in its entirety.
BACKGROUND
[0002] 1. Field of Invention
[0003] An embodiment of the present invention relates to a test
pattern of a semiconductor device, a method of manufacturing the
test pattern and a method of testing the semiconductor device by
using the test pattern and, more particularly, to a test pattern of
a semiconductor device for testing gate pads thereof for alignment,
a method of manufacturing the test pattern and a method of testing
the semiconductor device by using the test pattern.
[0004] 2. Description of Related Art
[0005] With increasing integration degree of semiconductor devices,
it is important to reduce the sizes of components that constitute
the semiconductor devices, contacts that electrically couple the
components and relevant regions.
[0006] As the sizes of the contacts and the components of the
semiconductor devices are reduced, overlap margin therebetween may
also be reduced. As a result, misalignment may occur between the
contacts and the components. In order to test the contacts and
components for alignment, a test pattern may be formed in a scribe
region of a semiconductor device.
BRIEF SUMMARY
[0007] An embodiment relates to a test pattern of a semiconductor
device for detecting a misalignment between gates and contacts of
an X decoder of a semiconductor device, a method of manufacturing
the test pattern and a method of testing the semiconductor device
by using the test pattern.
[0008] A test pattern of a semiconductor device according to an
embodiment of the present invention includes a plurality of active
regions defined in a semiconductor substrate and arranged in
parallel with each other, a plurality of gate patterns formed over
the plurality of active regions, a plurality of gate contacts
formed over the plurality of gate patterns, first junction contacts
formed over respective end portions of odd-numbered active regions
among the plurality of active regions, second junction contacts
formed over respective end portions of even-numbered active regions
among the plurality of active regions, and a contact pad configured
to couple the first junction contacts and the plurality of gate
contacts.
[0009] A semiconductor device according to an embodiment of the
present invention includes an X decoder including first gate
patterns and first gate contacts and configure to select word lines
of a memory cell block, a plurality of active regions defined in a
scribe region of a semiconductor substrate and arranged in parallel
with each other, a plurality of second gate patterns formed over
the plurality of active regions, a plurality of second gate
contacts formed over the plurality of gate patterns, wherein the
second gate patterns and gate contacts have the same structures as
the first gate patterns and gate contacts of the X decoder, first
and second junction contacts formed over respective end portions of
the plurality of active regions, and a first contact pad configured
to couple the first junction contacts and the plurality of second
gate contacts.
[0010] A test pattern of a semiconductor device according to an
embodiment of the present invention includes first active regions
and second active regions defined in a scribe region of a
semiconductor substrate and alternating with each other, a
plurality of gate patterns formed over the first active regions and
the second active regions, respectively, a plurality of gate
contacts formed over the plurality of gate patterns, at least one
first contact formed over the first active regions, at least one
second contact formed over the second active regions, and a contact
pad configured to couple one of the first and second contacts and
the plurality of gate contacts.
[0011] A method of forming a test pattern of a semiconductor device
according to an embodiment of the present invention includes
defining a plurality of active regions by performing an isolation
process on a semiconductor substrate, forming a plurality of gate
patterns over the plurality of active regions, forming a plurality
of gate contacts coupled to top portions of the plurality of gate
patterns, forming first and second junction contacts coupled to
respective end portions of the plurality of active regions, and
forming a first contact pad coupled to the first junction contacts
and the plurality of gate contacts.
[0012] A method of testing a semiconductor device, which includes a
plurality of second gate patterns and a plurality of second gate
contacts over first and second active regions the same structure as
first gate patterns and first gate contacts of an X decoder,
according to an embodiment of the present invention includes
coupling a first terminal (+) to at least one first contact coupled
to the first active regions, coupling a second terminal (-) to at
least one second contact coupled to the second active regions, and
testing whether or not current flows between the first terminal and
the second terminal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIGS. 1 to 4 are three-dimensional views of a semiconductor
device according to an embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
[0014] Hereinafter, various embodiments of the present disclosure
will be described in detail with reference to the accompanying
drawings. The figures are provided to enable those of ordinary
skill in the art to make and use the present invention according to
the exemplary embodiments of the present invention.
[0015] A test pattern and a method of forming the test pattern to
detect misalignment between gates of a plurality of transistors and
contacts coupled to the gates of the transistors. The transistors
may be included in an X decoder configured to selectively couple
global word lines and word lines of a memory cell block of a
semiconductor device according to an embodiment of the present
invention.
[0016] FIGS. 1 to 4 are three-dimensional views of a semiconductor
device according to an embodiment of the present invention.
[0017] Referring to FIG. 1, an etch process may be performed on a
scribe region of a semiconductor substrate 100, thus to form a
plurality of trenches 102. Subsequently, the plurality of trenches
102 may be filled with insulating layers to thus form a plurality
of isolation layers 104. The plurality of isolation layers 104 may
be arranged in parallel with each other. The scribe region of the
semiconductor substrate 100 may be divided into active regions and
isolation regions by the plurality of isolation layers 104.
[0018] The above-described isolation process may be also performed
on an X decoder region of the semiconductor substrate 100 where an
X decoder, that is configured to selectively couple global word
lines and word lines of a memory cell block of the semiconductor
device, is to be formed, so that the scribe region and the X
decoder region may have substantially the same structure as each
other.
[0019] Referring to FIG. 2, gate patterns 106 may be formed over
the active regions of the scribe region of the semiconductor
substrate 100. Each of the gate patterns 106 may be formed over
each of the active regions. The gate patterns 106 formed over the
active regions may be spaced apart by a given distance such that
the gate patterns 106 may be electrically insulated from each
other. Each of the gate patterns 106 may be formed of a polysilicon
layer.
[0020] The above-described processes of forming the gate patterns
106 may be performed at the same time as processes of forming gates
for transistors of the X decoder are performed, so that the scribe
region and the X decoder region may have substantially the same
structure as each other.
[0021] Referring to FIG. 3, gate contacts 108A and 108B may be
formed over the gate patterns 106, respectively, so that the gate
contacts 108A and 108B may be coupled to the gate patterns 106,
respectively. At this time, in order for the gate contact 108A to
be electrically coupled to the gate pattern 106 without causing
misalignment therebetween, the gate contact 108A is to be formed at
the upper center of the gate pattern 106. However, when
misalignment occurs, the gate contact 108B may extend from a
corresponding active region to neighboring active regions of the
semiconductor substrate 100.
[0022] First and second junction contacts 110A and 110B may be
formed over end portions of the plurality of active regions
arranged in parallel in the semiconductor substrate 100. For
example, the first junction contacts 11OA may be formed over end
portions of even-numbered active regions, while the second junction
contacts 110B may be formed over end portions of odd-numbered
active regions. Here, the first junction contacts 110A and the
second junction contacts 110B are formed over the end portions,
opposite to each other, of the even-numbered and odd-numbered
active regions, respectively.
[0023] Referring to FIG. 4, a first contact pad 112A is formed such
that the first contact pad 112A may be coupled to top portions of
the first junction contacts 110A and the gate contacts 108A and
108B. In addition, a second contact pad 112B is formed such that
the second contact pad 112B may be coupled to top portions of the
second junction contacts 110B.
[0024] A first terminal (+) may be coupled to the first contact pad
112A during a test operation, and a second terminal (-) may be
coupled to the second contact pad 112B during a test operation.
[0025] When the first terminal and the second terminal are coupled
to the first contact pad 112A and the second contact pad 112B,
respectively, during the test operation, misalignment of the gate
contacts 108A and 108B may be detected by testing whether or not
current flows between the first terminal and the second
terminal.
[0026] In an embodiment of the present invention, two gate patterns
and two contacts corresponding to each of the two gate patterns are
depicted for illustration purposes. However, the number of test
patterns may be equal to the number of transistors included in the
X decoder of the semiconductor device, and a test operation may be
performing using these test patterns.
[0027] As described above, according to an embodiment of the
present invention, a test pattern having the same structure as an X
decoder may be formed in a scribe region of a semiconductor
substrate, and the test pattern may be used to detect misalignment
between gate patterns and contacts of the X decoder by performing a
test operation of coupling test terminals to contacts coupled to
active regions and gate patterns of the test pattern.
[0028] According to an embodiment of the present invention,
misalignment margin during processing may be checked by forming a
test pattern used to detect misalignment between gates and contacts
of an X decoder of a semiconductor device, thus to determine the
optimal size of a gate pad and the optimal size of a contact.
* * * * *