U.S. patent application number 13/751434 was filed with the patent office on 2013-06-06 for junction barrier schottky rectifiers having epitaxially grown p+-n junctions and methods of making.
This patent application is currently assigned to Power Integrations, Inc.. The applicant listed for this patent is Power Integrations, Inc.. Invention is credited to Lin Cheng, Michael S. Mazzola.
Application Number | 20130140585 13/751434 |
Document ID | / |
Family ID | 38370926 |
Filed Date | 2013-06-06 |
United States Patent
Application |
20130140585 |
Kind Code |
A1 |
Mazzola; Michael S. ; et
al. |
June 6, 2013 |
JUNCTION BARRIER SCHOTTKY RECTIFIERS HAVING EPITAXIALLY GROWN P+-N
JUNCTIONS AND METHODS OF MAKING
Abstract
A junction barrier Schottky (JBS) rectifier device and a method
of making the device are described. The device comprises an
epitaxially grown first n-type drift layer and p-type regions
forming p.sup.+-n junctions and self-planarizing epitaxially
over-grown second n-type drift regions between and, optionally, on
top of the p-type regions. The device may include an edge
termination structure such as an exposed or buried P.sup.+ guard
ring, a regrown or implanted junction termination extension (JTE)
region, or a "deep" mesa etched down to the substrate. The Schottky
contact to the second n-type drift region and the ohmic contact to
the p-type region together serve as an anode. The cathode can be
formed by ohmic contact to the n-type region on the backside of the
wafer. The devices can be used in monolithic digital, analog, and
microwave integrated circuits.
Inventors: |
Mazzola; Michael S.;
(Starkville, MS) ; Cheng; Lin; (Durham,
NC) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Power Integrations, Inc.; |
San Jose |
CA |
US |
|
|
Assignee: |
Power Integrations, Inc.
San Jose
CA
|
Family ID: |
38370926 |
Appl. No.: |
13/751434 |
Filed: |
January 28, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12146580 |
Jun 26, 2008 |
8384182 |
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13751434 |
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11396615 |
Apr 4, 2006 |
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12146580 |
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Current U.S.
Class: |
257/77 ;
257/475 |
Current CPC
Class: |
H01L 29/0661 20130101;
H01L 29/8611 20130101; H01L 29/0619 20130101; H01L 29/0615
20130101; H01L 29/0623 20130101; H01L 29/872 20130101; H01L 29/1608
20130101 |
Class at
Publication: |
257/77 ;
257/475 |
International
Class: |
H01L 29/872 20060101
H01L029/872 |
Goverment Interests
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH
[0002] This invention was made with U.S. Government support under
Air Force Research Laboratory Agreement No. F33615-01-D-2103. The
U.S. Government may have certain rights in this invention.
Claims
1-50. (canceled)
51. A semiconductor device comprising: a semiconductor substrate of
a first conductivity type; a semiconductor drift layer above the
substrate; a plurality of highly doped epitaxial layer regions of
semiconductor material of a second conductivity type different than
the first conductivity type, each of the highly doped epitaxial
layer regions separated from one another on the drift layer to form
a plurality of junction barriers therewith, the highly doped
epitaxial layer regions each having an upper surface and sidewalls;
and a plurality of epitaxial drift layer regions of semiconductor
material of the first conductivity type, at least some of the
epitaxial drift layer regions being disposed between sidewalls of
adjacent of the highly doped epitaxial layer regions to
electrically couple with the drift layer; at least one ohmic
contact with at least some of the plurality of highly doped
epitaxial layer regions; and at least one Schottky contact with at
least some of the drift layer regions of semiconductor
material.
52. The semiconductor device of claim 51, wherein each of the
highly doped epitaxial layer regions is an elongate finger.
53. The semiconductor device of claim 51, wherein the plurality of
epitaxial drift layer regions of the first conductivity type extend
above and over the upper surfaces of the plurality of highly doped
epitaxial layer regions of the second conductivity type to contact
one another.
54. The semiconductor device of claim 51, wherein the device
comprises a semiconductor buffer layer of the first semiconductor
type on the substrate, wherein the semiconductor drift layer is on
the semiconductor buffer layer.
55. The semiconductor device of claim 51, wherein the semiconductor
substrate, the semiconductor drift layer, the highly doped
epitaxial layer regions, and the epitaxial drift layer regions are
silicon carbide.
56. The semiconductor device of claim 51, wherein the at least one
ohmic contact and the at least one Schottky contact are both formed
by a single metal layer.
57. The semiconductor device of claim 51, wherein the drift layer
and the epitaxial drift layer regions each have a dopant
concentration of 1.times.10.sup.14/cm.sup.3 to
1.times.10.sup.17/cm.sup.3.
58. The semiconductor device of claim 51, wherein the epitaxial
drift layer regions have a different dopant concentration than the
semiconductor drift layer.
59. The semiconductor device of claim 51, further comprising an
ohmic contact on the semiconductor substrate opposite the highly
doped epitaxial layer regions and the epitaxial drift layer
regions.
60. The semiconductor device of claim 51, further comprising a
highly doped epitaxial bus-bar of the second conductivity type
connecting the highly doped epitaxial layer regions.
61. The semiconductor device of claim 60, wherein: the bus-bar has
a first width; each of the highly doped epitaxial layer regions is
an elongate finger having a second width; and the second width is
less than the first width.
62. The semiconductor device of claim 51, wherein the at least one
ohmic contact has a different composition than the at least one
Schottky contact.
63. The semiconductor device of claim 51, further comprising an
edge termination structure in a peripheral portion of the
device.
64. A pinch diode made of a high bandgap semiconductor, the diode
comprising: a substrate of the high bandgap semiconductor of a
first conductivity type; a plurality of highly doped epitaxial
layer regions of the high bandgap semiconductor of a second
conductivity type different than the first conductivity type, each
of the highly doped epitaxial layer regions separated from one
another to form a plurality of junction barriers with underlying of
the high bandgap semiconductor material; and a plurality of
epitaxial drift layer regions of the high bandgap semiconductor of
the first conductivity type, at least some of the epitaxial drift
layer regions being disposed between adjacent of the highly doped
epitaxial layer regions to form a junction barriers with the highly
doped epitaxial layer regions; at least one ohmic contact with at
least some of the plurality of highly doped epitaxial layer
regions; and at least one Schottky contact with at least some of
the drift layer regions of semiconductor material.
65. The pinch diode of claim 64, wherein the high bandgap
semiconductor is silicon carbide.
66. The pinch diode of claim 64, wherein the plurality of epitaxial
drift layer regions of the first conductivity type extend above and
over the upper surfaces of the plurality of highly doped epitaxial
layer regions of the second conductivity type to contact one
another.
67. The pinch diode of claim 64, wherein the at least one ohmic
contact and the at least one Schottky contact are both formed by a
single metal layer.
Description
[0001] This application is a continuation of U.S. patent
application Ser. No. 12/146,580, filed on Jun. 26, 2008, allowed,
which is a divisional application of U.S. patent application Ser.
No. 11/396,615, filed on Apr. 4, 2006, abandoned. Each of the
above-referenced applications is incorporated by reference herein
in its entirety.
BACKGROUND
[0003] 1. Technical Field
[0004] The present invention relates, in general, to junction
barrier Schottky rectifiers or diodes with a vertical p.sup.+-n
junction and, in particular, to such devices having an epitaxially
grown drift layer and epitaxially overgrown drift regions forming a
p.sup.+-n junction which may or may not be buried and
self-planarized Schottky contact regions. The devices can be formed
in a wide band-gap semiconductor material such as silicon
carbide.
[0005] 2. Background of the Technology
[0006] Silicon Carbide (SiC), a wide band-gap semiconductor
material, is very attractive for use in high-power,
high-temperature, and/or radiation resistant electronics. SiC power
switches are logical candidates for these applications due to their
excellent material physical properties such as wide energy
band-gap, high breakdown field strength, high saturated electron
drift velocity and high thermal conductivity compared to the
conventional silicon counter part. In addition to the above
advantages, SiC power devices can operate with lower specific
on-resistance than conventional silicon power devices [1]. SiC
unipolar devices are expected to replace Si bipolar switches and
rectifiers in the 600-3000 V range in the very near feature.
[0007] Generally speaking, there are three types of rectifiers [2]:
(1) Schottky diodes, which offer a low effective turn-on voltage
hence low on-state losses and extremely high switching speed due to
primarily majority carrier conduction resulting in no diffusion
capacitance [3] and thereby no real reverse recovery on turning off
as well as no forward voltage overshoot on turning on, but suffer
from high leakage current; (2) P-i-N diodes, which offer low
leakage current but show reverse recovery charge during switching;
and (3) Junction Barrier Schottky (JBS) diodes which offers
Schottky-like on-state and switching characteristics, and PiN-like
off-state characteristics by screening the Schottky surface from
the high electric field [4]. In conventional high voltage (>600
V) circuits using Si PiN diodes, the primary source of power loss
is the dissipation of reverse recovery charge during the turn-off
of the rectifier. A fast recovery from SiC JBS diodes allows the
design of packages with much lower thermal requirements for both
the rectifier and the switch, and is expected to increase in the
power density of circuits by >3.times..
[0008] Because of the fundamental differences in material
properties and processing technologies, traditional Si or GaAs
microelectronics technologies in power rectifiers (or diodes) can
not be easily transferred to SiC. A number of reports of SiC
rectifiers have appeared in the last several decades (e.g.,
[2-6]).
[0009] U.S. Pat. No. 4,982,260 describes defining p-type emitter
regions by etching through a heavily doped p-type well created by
diffusion. However, since diffusion of dopants into SiC occurs very
slowly at even extremely high temperatures, as a practical matter,
a p-type well can only be formed in n-type SiC by ion implantation
which can result in low minority carrier lifetime due to damage
caused by implantation.
[0010] An example of a SiC Junction Barrier Schottky (JBS)/Merged
P-I-N Schottky (MPS) grid can be found in U.S. Pat. No. 6,524,900
B2. This device has Schottky metal deposited on implanted p-type
islands defined by plasma etching through an epitaxially grown
layer. However, this structure is unable to effectively protect
itself from a surge current in case of absence of p-type ohmic
contacts on p-type regions and insufficient conductivity modulation
caused by low doping of p-type regions.
[0011] An example of a junction barrier rectifier employing an
implanted P.sup.+ region to form p-n junction can be found in U.S.
Pat. No. 6,104,043. In this case, although Ohmic contacts are
formed on heavily doped implanted p-type regions, the conductivity
modulation in the drift region of such a structure suffers from low
minority carrier lifetime caused by residual implantation damages
even after high-temperature thermal anneal.
[0012] To date, most of the obstacles to low-cost volume
manufacturing can be traced back to the p.sup.+-n junction level
process steps. Also, the heavily doped p-type region for
[0013] Ohmic contact can be difficult to fabricate in SiC because
of the large band-gap of SiC. To obtain an abrupt p.sup.+-n
junction for both conductivity modulation and Ohmic contact in SiC
junction barrier Schottky diodes, ion implantation is often used to
form the P.sup.+ region. Damage induced during ion implantation and
post implantation anneal at very high temperatures (e.g.,
temperatures >=1500.degree. C.) can cause the reverse leakage
current of p-n junction to increase and tend to degrade the surface
of SiC on which the Schottky contact is to be made. Damage
resulting from these processing steps can greatly affect device
performance including forward conduction and blocking capability.
It is also difficult to have a precise control of p.sup.+-n
junction depth by ion implantation because of a combination of
uncertainties on actual depth profile of implantation tail, defect
density, redistribution of implanted ions after annealing, and
ionization percentage of dopant atoms and point defects under
different bias and/or temperature stress.
[0014] To eliminate these drawbacks, alternative methods of forming
a p.sup.+-n junction can be used. One method is to selectively grow
P.sup.+ gate regions epitaxially as disclosed in U.S. Pat. No.
6,767,783. Another method of forming a p.sup.+-n junction is to
epitaxially regrow a P.sup.+ layer on top of an trench-etched
N.sup.- drift layer, followed by a plasma etch-back or
chemical-mechanical polishing or other planarization method to
expose the N.sup.- drift region for Schottky metal contact. A
similar method is disclosed in U.S. Pat. No. 6,897,133 B2. In the
device described in this reference, however, lightly doped P
regions are used to form the p-n junction. Also in this device, the
epitaxially grown p-type regions do not form JFET regions that may
significantly limit current conduction under both normal and surge
current operating conditions.
[0015] Accordingly, there still exists a need for improved methods
of manufacturing semiconductor devices.
SUMMARY According to a first embodiment, a semiconductor device is
provided which comprises:
[0016] a substrate layer comprising a semiconductor material of a
first conductivity type;
[0017] an optional buffer layer comprising a semiconductor material
of the first conductivity type on the substrate layer,
[0018] a drift layer on the substrate layer or buffer layer, the
drift layer comprising a semiconductor material of the first
conductivity type;
[0019] a central region comprising a plurality of regions of
semiconductor material of a second conductivity type different than
the first conductivity type on a central portion of the drift
layer, the regions of semiconductor material of the second
conductivity type having upper surfaces and sidewalls; and
[0020] an epitaxially over-grown drift region of semiconductor
material of the first conductivity on the drift layer adjacent the
plurality of regions of semiconductor material of the second
conductivity type and, optionally, on upper surfaces of the
plurality of regions of semiconductor material of the second
conductivity type.
[0021] According to a second embodiment, an integrated circuit is
provided which comprises:
[0022] a semiconductor device as set forth above; and
[0023] at least one additional electronic power component formed on
the substrate layer.
[0024] According to a third embodiment, a method of making a
semiconductor device is provided which comprises:
[0025] selectively etching through a layer of semiconductor
material of a second conductivity type on a drift layer of
semiconductor material of a first conductivity type different than
the second conductivity type to expose material of the drift layer
thereby forming a central region comprising a plurality of regions
of semiconductor material of the second conductivity type on the
drift layer, the regions of semiconductor material of the second
conductivity type having upper surfaces and sidewalls;
[0026] epitaxially over-growing a drift region of semiconductor
material of the first conductivity type on exposed surfaces of the
drift layer adjacent to the regions of semiconductor material of
the second conductivity type and on upper surfaces of the regions
of semiconductor material of the second conductivity type; and
[0027] etching the drift region to expose at least a portion of the
upper surfaces of the regions of semiconductor material of the
second conductivity type;
[0028] wherein the drift layer is on a semiconductor substrate or
wherein the drift layer is on a buffer layer comprising a
semiconductor material of the first conductivity type and wherein
the buffer layer is on the semiconductor substrate. A device made
by the above described method is also provided.
BRIEF DESCRIPTION OF THE DRAWINGS
[0029] FIG. 1A is an schematic two-dimensional illustration of a
JBS rectifier according to one embodiment having exposed P.sup.+
finger, bus-bar, and guard ring regions.
[0030] FIG. 1B is an schematic two-dimensional illustration of a
JBS rectifier according to one embodiment having only the P.sup.+
bus-bar regions exposed and having buried p.sup.+-n junctions and
guard rings.
[0031] FIG. 1C is an schematic two-dimensional illustration of a
JBS rectifier according to one embodiment having exposed P.sup.+
finger and bus-bar regions and showing junction termination
extension (JTE) and mesa edge termination.
[0032] FIG. 1D is an schematic two-dimensional illustration of a
JBS rectifier according to one embodiment having only the P.sup.+
bus-bar regions exposed and buried p.sup.+-n junctions and showing
JTE and mesa edge termination.
[0033] FIG. 2 is a schematic diagram of a starting N.sup.+
substrate layer having an epitaxially grown N.sup.+ buffer layer,
an N-type drift layer, and a P.sup.+ layer on the drift layer.
[0034] FIG. 3A is a schematic diagram of a device having trenched
P.sup.+ fingers, bus-bars, and guard rings (as an edge termination
structure) which are formed on top of an N-type drift layer.
[0035] FIGS. 3B and 3C are schematic top views of two embodiments
of the device showing two different p-type bus bar
arrangements.
[0036] FIG. 4 is a schematic diagram of the P.sup.+ finger,
bus-bar, and guard ring as an exemplary edge termination being
trench-filled and planarized with the 2.sup.nd N-type drift
layer.
[0037] FIG. 5A is a schematic diagram of the 2.sup.nd N-type drift
layer being etched back or patterned then etched back to expose all
P.sup.+ finger, bus-bar, and guard ring (as an exemplar of edge
termination method).
[0038] FIG. 5B is a schematic diagram of the 2.sup.nd N-type drift
layer being etched back or patterned then etched back to expose
only the P.sup.+ bus-bar regions.
[0039] FIG. 5C is a schematic diagram of the 2.sup.nd N-type drift
layers being etched back or patterned then etched back to expose
all P.sup.+ finger and bus-bar with JTE or mesa edge
termination.
[0040] FIG. 5D is a schematic diagram of the 2.sup.nd N-type drift
layers being etched back or patterned then etched back to expose
only the P.sup.+ bus-bar regions with JTE or mesa edge
termination.
[0041] FIG. 6A is a schematic diagram of the dielectric layer(s)
being deposited and patterned to form either electrical isolation
or passivation on the JBS diodes having exposed P.sup.+ finger,
bus-bar, and guard ring regions.
[0042] FIG. 6B is a schematic diagram of the dielectric layer(s)
being deposited and patterned to form either electrical isolation
or passivation on the JBS diodes having exposed only the P.sup.+
bus-bar regions and buried p.sup.+-n junctions and guard ring.
[0043] FIG. 6C is a schematic diagram of the dielectric layer(s)
being deposited and patterned to form either electrical isolation
or passivation on the JBS diodes having exposed P.sup.+ finger and
bus-bar regions with JTE or mesa edge termination.
[0044] FIG. 6D is a schematic diagram of the dielectric layer(s)
being deposited and patterned to form either electrical isolation
or passivation on the JBS diodes having exposed only the P.sup.+
bus-bar regions and buried p.sup.+-n junctions with JTE or mesa
edge termination, and to open windows for Schottky and Ohmic metal
contacts.
[0045] FIG. 7A is a schematic diagram of the metals being deposited
to form electrically conducting contacts to the 2.sup.nd N.sup.-
drift regions, all exposed P.sup.+ regions, and backside of the
substrate on the JBS diodes having exposed P.sup.+ finger, bus-bar,
and guard ring regions.
[0046] FIG. 7B is a schematic diagram of the metals being deposited
to form electrically conducting contacts to the 2.sup.nd N.sup.-
drift regions, all exposed P.sup.+ regions, and backside of the
substrate on the JBS diodes having exposed only the P.sup.+ bus-bar
regions and buried p.sup.+-n junctions and guard ring.
[0047] FIG. 7C is a schematic diagram of the metals being deposited
to form electrically conducting contacts to the 2.sup.nd N.sup.-
drift regions, all exposed P.sup.+ regions, and backside of the
substrate on the JBS diodes having exposed P.sup.+ finger and
bus-bar regions with JTE or mesa edge termination.
[0048] FIG. 7D is a schematic diagram of the metals being deposited
to form electrically conducting contacts to the 2.sup.nd N.sup.-
drift regions, all exposed P.sup.+ regions, and backside of the
substrate on the JBS diodes having exposed only the P.sup.+ bus-bar
regions and buried p.sup.+-n junctions with JTE or mesa edge
termination.
REFERENCE NUMERALS
[0049] 1. Substrate [0050] 2. N.sup.+ buffer layer [0051] 3. N-type
drift layer [0052] 4. P-type regions (e.g., fingers) [0053] 5.
P-type bus-bar for metal contacts [0054] 6. (a) P-type passivated
guard rings; (b) P-type buried guard rings; (c) P-type epitaxially
re-grown or implanted JTE region; (d) mesa edge termination etched
through all epitaxial layers down to the substrate [0055] 7. P-type
trenches [0056] 8. N-type self-planarized drift region [0057] 9.
Isolation dielectric and Passivation dielectric [0058] 10. Anode
metal contacts on the exposed P.sup.+ regions and N-type drift
region [0059] 11. Backside Cathode metal contact
DETAILED DESCRIPTION
[0060] An object of the present invention is to provide a Junction
Barrier Schottky (JBS) rectifier with all epitaxially grown single
or dual drift regions including a self-planarized 2.sup.nd drift
region and buried or exposed p.sup.+-n junction with P.sup.+ guard
rings or JTE with or without a N.sup.+ field stop region or "deep"
mesa edge termination in SiC, that can be made electrically
isolated from the other devices fabricated on the same die, and
that can be implemented in such a way that the devices fabricated
on the same die may be monolithically integrated with other
electronic power components, for example junction field-effect
transistors (JFETs) or bipolar junction transistors (BJTs).
[0061] A further object of the invention is to provide the concept
and an example of planarization of trenched P.sup.+ region by
homo-epitaxial over-growth of the 2.sup.nd lightly doped N.sup.-
drift regions on a patterned silicon carbide substrate.
[0062] A further object of the invention is to provide the concept
and an example of planarization of trenched P.sup.+ region by
homo-epitaxial over-growth of only the 2.sup.nd lightly doped
N.sup.- drift regions on a silicon carbide patterned substrate.
[0063] A further object of the invention is to provide a method of
the fabrication of the above devices.
[0064] Methods of forming a p.sup.+-n junction and devices made by
these methods are described herein. According to one embodiment,
the method comprises epitaxially growing a P.sup.+ layer on top of
a flat first N.sup.- drift layer, followed by an etch-back of the
P.sup.+ layer down to the drift region to form a patterned P+ layer
comprising elongate P.sup.+ regions (i.e., fingers) and,
optionally, one or more bus-bars. According to one embodiment, the
bus-bars can connect all of the P.sup.+ fingers together around the
periphery of the device to permit external metal contact to the
Schottky contact metal thus permitting forward biasing of the
buried p.sup.+-n junction structure which will provide conductivity
modulated current for surge protections.
[0065] The devices may comprise an edge termination structure. Edge
termination methods include, but are not limited to, P.sup.+ guard
rings, P-type junction termination extension (JTE) by either
epitaxial growth or ion implantation, or "deep" mesa edge
termination (i.e.: mesa etched down through all epitaxial N.sup.-
drift and P.sup.+ layers into the N.sup.+ substrate).
[0066] A second n-type drift region is then over-grown on the
patterned P.sup.+ region and the exposed first N.sup.- drift layer.
The doping concentration of the re-grown second N.sup.- drift
region can be different from that of the first N.sup.- drift layer.
For example, there is a trade-off between lower leakage current but
higher on-resistance (R.sub.on) or higher on-state voltage drop
(V.sub.F) from lower N.sup.- drift doping concentration. The
trade-off of this design may be partially cancelled by re-growing
the second N.sup.- drift region with higher doping concentration
than that of the first N.sup.- drift layer. Alternatively, the
second N.sup.- drift region may be more lightly doped than the
first N.sup.- drift layer.
[0067] The following advantages can be realized by using an
epitaxially grown P-type region instead of an implanted P-type
region: [0068] Precisely and readily controlled vertical p.sup.+-n
junction dimensions, including a greater depth of the p region than
is physically possible with implantation (usually <0.5 .mu.m for
high KeV implantation versus >1 .mu.m for an epitaxial process)
which permits considerably better optimization of the design trade
between the reverse blocking performance and the forward conduction
performance (on-resistance) of the JBS rectifier; [0069] Flexible
and convenient to add an optional p-type external "bus bar" when
creating the P.sup.+ trenches. The p-type external "bus bar" can
connect to all the p-type fingers, which can be either buried into
the over-grown N.sup.- drift region or exposed to metal contact, in
order to reduce the gate resistance hence improve switching
performance of the JBS rectifier; [0070] Heavily doped p-type
material for efficient conductivity modulation can be achieved
without a high-temperature post anneal, which would eliminate
surface degradation of the SiC Schottky contact area by the
high-temperature anneal (>1500.degree. C.) thus improving the
ideality and performance of the Schottky diode while simultaneously
improving the conductivity modulation of the p.sup.+-n diode.
[0071] Freedom to form abrupt and/or graded p-n junction for
reliably grading the electrical field in the vicinity of the p-n
junction without degrading the efficiency of conductivity
modulation. [0072] The p-n junction regions are free of
implantation damage and implantation straggle. This results in (1)
easy fabrication of abrupt and/or graded p-n junctions for easy
depletion and improved minority carrier life time hence improved
conductivity modulation, (2) avoidance of problems due to
unexpected variation of the structure (meaning doping and geometry)
of the p-n junction by implantation, and (3) reliable grading of
the electric field in the vicinity of the p-n junction. [0073] A
more robust and reliable p.sup.+-n junction reduces the reverse
leakage current, and the shift of the threshold voltage with
temperature. [0074] The elimination of concern for incomplete
activation of the implanted P-type dopant and about the creation of
unintended implantation-induced defects, resulting in a
significantly higher yield and hence a reduced manufacturing
cost.
[0075] The following advantages of re-growing an N.sup.- drift
layer on top of structured P.sup.+ regions to form a p.sup.+-n
junction, as described herein, can be realized with respect to
re-growing a P.sup.+ layer on top of structured N.sup.- drift
regions followed by etch back to expose the N.sup.- drift region:
[0076] Freedom to dope the 2.sup.nd drift layer different from the
1.sup.st drift layer, in order to have both on-resistance (or
V.sub.F) and leakage current (or blocking capability) optimized to
improve the device performance. [0077] Flexibility with the
follow-on processing of the 2.sup.nd re-grown N.sup.- layer to
either expose the P.sup.+ regions by etching back the 2.sup.nd
N.sup.- layer to the P.sup.+ region for an enhanced
"surge-current-protected" JBS diode or to leave the P.sup.+
semiconductor buried but use an external P.sup.+ bus-bar for Ohmic
contact formation to lower the cost of fabrication while still
maintaining a degree of surge-current capability in a high-voltage
rated JBS diode. [0078] Since the relative area of the
Schottky-contacted N.sup.- region versus the P.sup.+ region is one
of the factors that determine the R.sub.on or V.sub.F, a narrower
P.sup.+ structure results in more Schottky area hence lower
R.sub.on and V.sub.F. In addition, wider spacing or more Schottky
area between the two adjacent P.sup.+ regions can also help to
reduce the peak current density, providing better surge-current
protection. When filling the structured N.sup.- drift layer with
the P.sup.+ region to form the p-n junction, the width of the
trench through the N.sup.- area needs to be large enough to allow a
reasonable aspect ratio for the re-grown P.sup.+ to planarize and
be free of key-holes (i.e., voids that form in the semiconductor
during re-growth due to an excessive aspect ratio). In contrast,
this disclosure teaches re-growing the N.sup.- drift layer on the
structured P.sup.+ regions, so that the latter can be made smaller
or narrower using conventional photo-lithography or any other
available techniques than that made by re-growing P.sup.+ on the
structured N.sup.- drift regions. [0079] Self-planarized re-growth
of the second N.sup.- drift region on the structured P.sup.+
regions can be easily achieved by optimizing the P.sup.+ trench
crystallographic orientation as described in U.S. patent
application Ser. No. 11/198,298, filed on Aug. 8, 2005, which is
incorporated by reference herein. In this embodiment, the second
re-grown N.sup.- layer is etched back to expose the P.sup.+ regions
for ohmic contact formation, because the self-planarization effect
provided by the epitaxial re-growth process specified in the '298
application permits the trenches made in the P.sup.+ layer to be
filled in by the second N.sup.- drift region with reduced residual
undulation, they can be wider (i.e., they have lower aspect ratio)
than those in which trenches in the N.sup.- drift layer are filled
in with the P.sup.+ layer. In this manner, the post-epi
planarization and patterning required to achieve continuous
coverage of the follow-on metallization processes can be
simplified.
[0080] Once the second N.sup.- drift region fills in the P.sup.+
trenches and over-grows on top of the structured epitaxial P.sup.+
regions, it can be patterned and etched back to expose either all
the P.sup.+ regions or only the bus-bars which connect to all the
buried P.sup.+ fingers for external metal contacts. An edge
termination structure can then be formed. Edge termination
structures can be formed by a selectively re-grown or implanted
p-type JTE region with or without N.sup.+ field-stop region, "deep"
mesa etched through all epitaxial layers down to the N.sup.+
substrate, or P.sup.+ guard rings. Metal layers are then applied on
top of the second N.sup.- drift region to form a Schottky contact
and on top of the exposed P.sup.+ region to form an Ohmic contact,
and backside of the substrate to form an Ohmic contact. Finally,
thick metal layers can be applied on top of both Schottky and Ohmic
contacts to form the anode of the diode and on the backside Ohmic
contact to form the cathode of the diode. The schedule of the Ohmic
contact formation in the sequence just described, which may require
a high-temperature anneal, is such that the electrical properties
of the Schottky contact are not compromised.
[0081] The P.sup.+ trench depth or finger height, the P.sup.+
finger width, the distance between two adjacent P.sup.+ fingers for
the second N.sup.- region to fill in, and the doping concentration
of the first drift layer and the second drift region can be
selected according to formulae known to those schooled in the art
to have low R.sub.on and V.sub.F while still making the depletion
of the drift layer continuous among all the P.sup.+ regions in the
off-state to screen the high electrical field in the depletion
region from the Schottky barrier existing at the surface-interface
of the Schottky metal and the second N.sup.- drift region.
[0082] Considering the effect of surface topology on the
photolithography and metal contact steps remaining after
over-growth of the second N.sup.- drift region, it is preferable to
have the second drift region reasonably planar on top of the
structured P.sup.+ regions. However, the alternating trenches and
P.sup.+ fingers normally work against the planar growth of a
regrown epitaxial layer. A method for self-planarized epitaxial
re-growth which can be used to form the second N.sup.- drift region
is described in U.S. patent application Ser. No. 11/198,298, which
is incorporated by reference herein. Furthermore, by optimizing the
P.sup.+ trench depth or finger height, the P.sup.+ finger width,
the separation between two adjacent P.sup.+ fingers for the second
N.sup.- drift region to fill in, the self-planarized second n-type
drift regions can be homoepitaxially over-grown free of key-holes
(i.e., free of voids or inclusions in the single-crystal epitaxial
material) on the trenched P.sup.+ regions.
[0083] According to further embodiments, the disclosed JBS
rectifiers can be monolithically integrated with other electronic
power components, such as JFETs or BJTs (Bipolar Junction
Transistors) or MOSFETs or gate turn-off thyristors (GTOs) in SiC.
These monolithic devices can be made by selective or blanket
re-growth of one or more n-type and/or p-type layers, for example a
third N.sup.+ layer grown on top of the second drift region to form
a junction field-effect transistor on the same die with the JBS
rectifiers, where the source and channel regions can be defined by
a selective plasma etch-back of the N.sup.+ and the second N.sup.-
drift regions.
[0084] The device can be built on a silicon carbide substrate,
which can be electrically either p-type or n-type with or without
an epitaxially grown buffer layer of the same conductivity type.
For n-type substrates, the device comprises an epitaxially grown
first n-type drift and then a p-type trenched region, followed by
an epitaxially re-grown n-type planarized second drift region which
may have the same or different doping concentration from the first
drift layer. The device structure is defined using conventional
photolithography and plasma dry-etch. The Schottky contact to the
n-type drift region and Ohmic contact to the p-type region are
formed on top of the wafer, while the Ohmic contact to the heavily
doped substrate is formed on the backside of the wafer. Depending
on the lateral distance between the two adjacent p-type regions,
the proposed JBS diode may have different on- and off-state
characteristics, and can be implemented for both punch-through and
non-punch-through modes of off-state operation for the same n-type
doping of the second drift region. In addition, the devices
described above, can be used in monolithic microwave integrated
circuits (MMICs). Moreover, the devices described above can be
fabricated monolithically with other power electronic components on
the same wafer or die for use in power switching or converter or
booster circuits.
[0085] Silicon carbide crystallizes in more than 200 different
poly-types. The most important are: 3C--SiC (cubic unit cell, zinc
blende); 2H--SiC; 4H--SiC; 6H--SiC (hexagonal unit cell, wurtzile);
and 15R--SiC (rhombohedral unit cell). However, the 4H-polytype is
more attractive for power devices thanks to its larger bandgap and
higher electron mobility. Although the 4H--SiC is preferred, it is
to be understood that the present invention is applicable to
devices and integrated circuits described herein made of other
poly-types of silicon carbide.
[0086] The semiconductor device and method will be described in
greater detail hereafter with reference to the accompanying
drawings, in which embodiments of the invention are described using
silicon carbide (SiC) as a semiconductor material.
[0087] FIGS. 1A-1D are schematic two-dimensional views of a
semiconductor device referred to as a Junction Barrier Schottky
(JBS) rectifier illustrating different edge termination structures.
As shown in FIGS. 1A-1D, the device is built on a silicon carbide
substrate 1, which can be electrically either p-type or n-type,
with or without an epitaxially grown buffer layer 2 of the same
conductivity type. When an n-type substrate is used, the device
comprises an epitaxially grown first n-type drift layer 3 and then
a p-type trenched region 4, followed by an epitaxially re-grown
n-type self-planarized second drift region 8 which may have the
same or different doping concentration from the first drift layer.
As shown, the p-type region comprises bus bars 5. The device
structure can be defined using conventional photolithography and
plasma dry-etch. Metal forming the Schottky contact on the second
drift region is connected to the Ohmic contacts on the exposed
p-type regions to form a continuous anode 10 on top of the wafer
while a cathode 11 is formed by Ohmic contact to the n-type region
on the backside of the substrate. As shown in FIGS. 1A and 1B, the
P.sup.+ guard ring regions 6(a) and 6(b) can be either exposed to
the passivation dielectric layer 9 as shown in FIG. 1A or buried
into lightly n-type drift region 8 as shown in FIG. 1B.
[0088] FIG. 1C is a schematic two-dimensional illustration of a JBS
rectifier having exposed P.sup.+ finger and bus-bar regions. FIG.
1C also illustrates both junction termination extension (JTE) 6c
and mesa edge termination 6d structures.
[0089] FIG. 1D is a schematic two-dimensional illustration of a JBS
rectifier according to a further embodiment having buried p.sup.+-n
junctions and exposed P.sup.+ bus-bar regions. FIG. 1D also
illustrates both junction termination extension (JTE) 6c and mesa
edge termination 6d structures.
[0090] Referring now to FIG. 2, a schematic diagram shows the
starting N.sup.+ substrate with epitaxially grown N.sup.+ buffer,
first N-type drift, and P.sup.+ layers. A high-quality, heavily
doped, thin N.sup.+ buffer layer with minimum defect density serves
as a good stop of electrical field at the interface of N-type drift
and N.sup.+ buffer layers. The buffer layer shown in FIG. 2 is
optional. The lightly doped N-type drift region provides the
blocking capability, while the heavily doped P.sup.+ epi-layer
forms the p.sup.+-n junction that provides the junction barrier.
The junction barrier provides for the possibility of conductivity
modulation by hole injection to conduct surge currents. P.sup.-
epi-layer can also be used to provide edge termination in the form
of, for example, guard rings. FIG. 2 also shows representative
doping concentrations for each of these layers.
[0091] Referring now to FIG. 3A, the P.sup.+ epi-layer can be
patterned using a masking material. Exemplary masking materials
include, but are not limited to, photo-resists, lifted-off metals,
oxides, or any other known materials. As shown in FIG. 3, the
P.sup.+ layer can then be etched down to the first n-type drift
layer 3 to simultaneously form: P.sup.+ fingers 4 and trenches 7
for conductivity modulation; one or more P-type external bus-bars 5
that can connect to the P.sup.+ fingers 4 for Ohmic metal contact;
and P.sup.+ guard rings 6(a, b) for edge termination.
[0092] FIGS. 3B and 3C are schematic top views of devices showing
two alternative bus bar arrangements. FIG. 3B shows an embodiment
wherein the bus-bars 5 circumscribe the p-type regions 4. FIG. 3C
shows an alternative embodiment wherein the bus-bars 5 enclose the
p-type regions 4 on three sides. Other arrangements of p-type
regions 4 and bus-bars 5 are also possible.
[0093] Referring now to FIG. 4, the trenched P.sup.+ regions are
filled and planarized with homoepitaxial N-type semiconductor
material to form second n-type drift regions. The doping
concentration of these second n-type drift regions can be different
from the first n-type drift layer and/or graded for facilitating
the degree of depletion of the drift layer and to control the
magnitude of the electric field within the junction barrier region.
Generally, planarization occurs by optimizing the C/Si ratio and
the trench orientation with respect to the direction of the
off-cut. The same is true for 4H--SiC cut 8.degree. or 4.degree.
off of the basal plane ([0001]) towards the <112-0>
direction. The same is true for 6H--SiC cut 3.5.degree. off of
[0001] towards the <112-0> direction. The orthogonal
orientation of the major flat (i.e., off-cut towards the
<11-00> direction) works equally well.
[0094] In FIGS. 2-4, the SiC layers can be formed by doping the
layers with donor or acceptor materials using known techniques.
Exemplary donor materials include nitrogen and phosphorus. Nitrogen
is a preferred donor material. Exemplary acceptor materials for
doping SiC include boron and aluminum. Aluminum is a preferred
acceptor material. The above materials are merely exemplary,
however, and any acceptor and donor materials which can be doped
into silicon carbide can be used. The doping levels and thicknesses
of the various layers of the JBS rectifiers described herein can be
varied to produce a device having desired characteristics for a
particular application. Similarly, the dimensions of the various
features of the device can be varied to produce a device having
desired characteristics for a particular application.
[0095] FIGS. 5A-5D illustrate devices having either buried P.sup.+
fingers (FIGS. 5B and 5D) or exposed P.sup.+ fingers (FIGS. 5A and
5C) illustrating various edge termination structures. As shown in
FIGS. 5A and 5C, the second N-type drift regions can be patterned
and etched down to expose both the P.sup.+ fingers 4 and the
bus-bar regions 5 for metal contacts. As shown in FIGS. 5B and 5D,
the second N-type drift region can be patterned and etched down to
expose only the P.sup.+ bus-bar regions, resulting in buried
p.sup.+-n junctions beneath the second n-type drift region. As
shown in FIG. 5A, the device can have exposed P.sup.+ guard ring
regions as an edge termination structure. Alternatively, as shown
in FIG. 5B, the device can have buried P.sup.+ guard ring regions.
FIGS. 5C and 5D also illustrate both junction termination extension
(JTE) 6c and mesa edge termination 6d structures.
[0096] Referring now to FIGS. 6A-6D, a dielectric layer or stack 9
for electrical isolation can then be grown and/or deposited
anywhere on the upper surface of the device followed by a
patterning and etch through the dielectric layer or stack to open
Schottky and Ohmic metal contacts on top of the device. The
dielectric layer or stack 9 can be used between different devices
fabricated on the same wafer. The dielectric layer or stack 9 can
provide electrical field passivation outside the anode metal
contact and on top of the edge termination structure. The edge
termination structure can be an exposed guard ring as shown in FIG.
6A, buried guard ring regions as shown in FIG. 6B, JTE regions as
shown in FIGS. 6C and 6D, or mesa edge termination regions as also
shown in FIGS. 6C and 6D.
[0097] As shown in FIGS. 7A-7D, single or multiple metal layers can
be deposited on top of the second drift region and bus-bar regions
10 as well as on the backside of the wafer 11. As shown in FIGS. 7A
and 7C, metal layer 10 can also be deposited on the exposed P.sup.+
fingers 4. The metal layers 10, 11 may consist of one or two
different metals or metal alloys or metal mixtures. For example,
one metal or alloy or mixture can be used for the Schottky contact
to the second n-type drift region and another metal or alloy or
mixture can be used to form a good Ohmic contact to both the
P.sup.+ finger and the P.sup.+ bus-bar regions as shown in FIGS. 7A
and 7C. Alternatively, the anode can contact only the P.sup.+
bus-bar regions as shown in FIGS. 7B and 7D. When two different
metals are used, an Ohmic metal or metal alloy or metal mixture can
be deposited and selectively etched followed by a high-temperature
anneal (e.g., >900.degree. C.) to form Ohmic contact to the
P.sup.- regions prior to the Schottky metal/alloy/mixture
deposition. If one metal or metal alloy or metal mixture is
carefully selected for simultaneous Schottky and Ohmic contacts
formation, a low temperature (e.g., >500.degree. C.) anneal will
make Ohmic contact to the P.sup.+ region without damaging the
Schottky contact.
[0098] Multiple JBS devices as described herein can be fabricated
on the same die for different voltage and current ratings by
choosing proper widths of the P.sup.+ fingers and trenches. In
addition, the JBS devices described herein can be monolithically
fabricated with other power electronic components (e.g., JFETs or
BJTs) on the same die by selectively or blanket re-growing one or
more n-type and/or p-type layers, for example an N.sup.+ layer on
top of the second drift region, to form a junction field-effect
transistor (JFET) on the same die with the JBS rectifiers, wherein
the source and channel regions can be defined by a selectively
plasma etch-back of the N.sup.+ layer and the second N.sup.- drift
region in SiC.
[0099] By inverting the electrical polarity of the substrate and
the epitaxial layers, a JBS rectifier with an n.sup.+-p junction
can be fabricated using the methods described herein.
[0100] The SiC layers can be formed by epitaxial growth on a
suitable substrate. The layers can be doped during epitaxial
growth.
[0101] While the foregoing specifications teaches the principles of
the present invention, with examples provided for the purpose of
illustration, it will be appreciated by one skilled in the art from
reading this disclosure that various changes in form and detail can
be made without departing from the true core of the invention.
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