U.S. patent application number 13/746460 was filed with the patent office on 2013-05-30 for method for fabricating vertical channel type nonvolatile memory device.
This patent application is currently assigned to SK HYNIX INC.. The applicant listed for this patent is SK hynix Inc.. Invention is credited to Kwon HONG, Sun-Hwan HWANG, Moon-Sig JOO, Ki-Hong LEE.
Application Number | 20130137228 13/746460 |
Document ID | / |
Family ID | 43306779 |
Filed Date | 2013-05-30 |
United States Patent
Application |
20130137228 |
Kind Code |
A1 |
LEE; Ki-Hong ; et
al. |
May 30, 2013 |
METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY
DEVICE
Abstract
A method for fabricating a vertical channel type nonvolatile
memory device includes: stacking a plurality of interlayer
insulating layers and a plurality of gate electrode conductive
layers alternately over a substrate; etching the interlayer
insulating layers and the gate electrode conductive layers to form
a channel trench exposing the substrate; forming an undoped first
channel layer over the resulting structure including the channel
trench; doping the first channel layer with impurities through a
plasma doping process; and filling the channel trench with a second
channel layer.
Inventors: |
LEE; Ki-Hong; (Gyeonggi-do,
KR) ; JOO; Moon-Sig; (Gyeonggi-do, KR) ; HONG;
Kwon; (Gyeonggi-do, KR) ; HWANG; Sun-Hwan;
(Gyeonggi-do, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SK hynix Inc.; |
Gyeonggi-do |
|
KR |
|
|
Assignee: |
SK HYNIX INC.
Gyeonggi-do
KR
|
Family ID: |
43306779 |
Appl. No.: |
13/746460 |
Filed: |
January 22, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13244247 |
Sep 23, 2011 |
8399323 |
|
|
13746460 |
|
|
|
|
12493439 |
Jun 29, 2009 |
8048743 |
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13244247 |
|
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Current U.S.
Class: |
438/268 |
Current CPC
Class: |
H01L 21/2236 20130101;
H01L 27/11578 20130101; H01L 27/11582 20130101; H01L 29/66833
20130101 |
Class at
Publication: |
438/268 |
International
Class: |
H01L 29/66 20060101
H01L029/66 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 12, 2009 |
KR |
10-2009-0052159 |
Claims
1. A method for fabricating a vertical channel type nonvolatile
memory device, the method comprising; stacking a plurality of
interlayer insulating layers and a plurality of conductive layers
alternately over a substrate, etching the interlayer insulating
layers and the conductive layers to form a channel trench exposing
the substrate; and alternately forming first and second channel
layers with different doping concentrations in the channel
trench.
2. The method of claim 1, wherein the forming of the first and
second channel layers comprises: forming an undoped first channel
layer over a structure including the channel trench; and forming a
doped second channel layer over the undoped first channel
layer.
3. The method of claim 1, further comprising: performing a thermal
treatment process after forming the first and second channel
layers.
4. The method of claim 3, wherein the performing of a thermal
treatment process includes diffusing the doped impurities of the
second channel layer into the undoped first channel layer to form a
doped first channel layer.
5. The method of claim 1, further comprising: forming a charge
blocking layer, a charge trap layer, and a tunnel insulating layer
over a structure including the channel trench before the forming of
the first and second channel layers.
6. The method of claim 1, wherein the conductive layer is a gate
electrode.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a division of U.S. patent application
Ser. No. 13/244,247 filed on Sep. 23, 2011, which is a division of
U.S. patent application Ser. No. 12/493,439 filed on Jun. 29, 2009
and issued as U.S. Pat. No. 8,048,743 on Nov. 1, 2011, which claims
priority of Korean Patent Application No. 10-2009-0052159, filed on
Jun. 12, 2009. The disclosure of each of the foregoing applications
is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a method for fabricating a
nonvolatile memory device, and more particularly, to a method for
fabricating a three-dimensional (3D) nonvolatile memory device.
[0003] Nonvolatile memory devices retain stored data even when
power is interrupted. However, two-dimensional (2D) memory devices
fabricated in a single layer on a silicon substrate have
limitations in improving integration density. Therefore, 3D
nonvolatile memory devices with memory cells stacked vertically
from a silicon substrate are desirable.
[0004] Hereinafter, the structure and limitation of a conventional
3D nonvolatile memory device will be described in detail with
reference to FIG. 1.
[0005] FIG. 1 is a cross-sectional view of a conventional 3D
nonvolatile memory device. Specifically, FIG. 1 is a
cross-sectional view of a nonvolatile memory device in which
strings are vertically arranged over a substrate. For the sake of
convenience, a description about a process of forming a lower
selection transistor and an upper selection transistor is
omitted.
[0006] Referring to FIG. 1, a plurality of interlayer insulating
layers 11 and a plurality of gate electrode conductive layers 12
are alternately formed on a substrate 10 having required lower
structures such as source lines and lower select transistors that
are formed, for example, below the interlayer insulating layers 11
and the plurality of gate electrode conductive layers 12.
Thereafter, the interlayer insulating layers 11 and the gate
electrode conductive layers 12 are selectively etched to form a
channel trench exposing the surface of the substrate 10.
[0007] A charge blocking layer, a charge trapping layer, and a
tunnel insulating layer are sequentially formed over the resulting
structure including the channel trench. Thereafter, an etch-back
process is performed to expose the surface of the substrate 10. For
illustration purposes, the charge blocking layer, the charge
trapping layer, and the tunnel insulating layer are shown as one
layer denoted by a reference numeral 13.
[0008] The channel trench is filled with a channel layer to form a
channel 14 protruding vertically from the substrate 10. Herein, the
channel layer may be formed by growing a monocrystalline silicon
layer through an epitaxial growth process, or may be formed by
depositing a polysilicon layer through a chemical vapor deposition
(CVD) process.
[0009] Consequently, a plurality of stacked memory cells are formed
along the channel 14 protruding vertically from the substrate 10,
and the memory cells are connected in series between a lower select
transistor (not shown) and an upper select transistor (not shown)
to constitute one string.
[0010] However, the foregoing conventional method has limitations
in controlling the doping concentration of the channel 14.
[0011] In general, for fabrication of a nonvolatile memory device,
the doping concentration of the channel 14 is controlled to control
the threshold voltage of the memory cells. For example, the
threshold voltage is controlled by doping the channel layer with
n-type impurities at a low concentration. In the case of a
conventional planar nonvolatile memory device, a channel layer is
formed and the channel layer is doped with impurities through an
ion implantation process, thereby forming a channel with a low
doping concentration.
[0012] However, in the case of the vertical channel type
nonvolatile memory device, because the channel trench is filled
with the channel layer to form the channel 14, doping by ion
implantation is difficult to implement. Also, even when the channel
layer is formed through a doping process, it is not easy to
implement a doping concentration of less than 1E19 atoms/cm.sup.3.
That is, according to the conventional method, it is impossible to
form a vertical channel with a low doping concentration for
fabrication of a 3D nonvolatile memory device.
[0013] For illustration purposes, limitations that occur in forming
a channel of a memory cell have been explained. However, such
limitations may also occur in forming a lower select transistor or
an upper select transistor.
SUMMARY OF THE INVENTION
[0014] An embodiment of the present invention is directed to
provide a method for fabricating a 3D nonvolatile memory device,
which can easily control the doping concentration of a channel.
[0015] In accordance with an aspect of the present invention, there
is provided a method for fabricating a vertical channel type
nonvolatile memory device, the method including: stacking a
plurality of interlayer insulating layers and a plurality of gate
electrode conductive layers alternately over a substrate; etching
the interlayer insulating layers and the gate electrode conductive
layers to form a channel trench exposing the substrate; forming an
undoped first channel layer over the resulting structure including
the channel trench; doping the first channel layer with impurities
through a plasma doping process; and filling the channel trench
with a second channel layer.
[0016] In accordance with another aspect of the present invention,
there is provided a method for fabricating a vertical channel type
nonvolatile memory device, the method including: stacking a
plurality of interlayer insulating layers and a plurality of gate
electrode conductive layers alternately over a substrate; etching
the interlayer insulating layers and the gate electrode conductive
layers to form a channel trench exposing the substrate; and
alternately forming first and second channel layers with different
doping concentrations in the channel trench.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIG. 1 is a cross-sectional view of a conventional 3D
nonvolatile memory device.
[0018] FIGS. 2A to 2C are cross-sectional views illustrating a
process for fabricating a 3D nonvolatile memory device in
accordance with an embodiment of the present invention.
[0019] FIGS. 3A to 3D are cross-sectional views illustrating a
process for fabricating a 3D nonvolatile memory device in
accordance with another embodiment of the present invention.
[0020] FIGS. 4A to 4D are cross-sectional views illustrating a
process for fabricating a 3D nonvolatile memory device in
accordance with another embodiment of the present invention.
[0021] FIGS. 5A and 5B are cross-sectional views illustrating a
process for fabricating a 3D nonvolatile memory device in
accordance with another embodiment of the present invention.
DESCRIPTION OF SPECIFIC EMBODIMENTS
[0022] Other objects and advantages of the present invention can be
understood by the following description, and become apparent with
reference to the embodiments of the present invention.
[0023] Referring to the drawings, the illustrated thickness of
layers and regions are exemplary and may not be exact. When a first
layer is referred to as being "on" a second layer or on a
substrate, it could mean that the first layer is formed directly on
the second layer or the substrate, or it could also mean that a
third layer may exist between the first layer and the second layer
or the substrate. Furthermore, the same or like reference numerals
represent the same or like components, even if they appear in
different embodiments or drawings of the present invention.
[0024] FIGS. 2A to 2C are cross-sectional views illustrating a
process for fabricating a 3D nonvolatile memory device in
accordance with an embodiment of the present invention.
[0025] Referring to FIG. 2A, a plurality of interlayer insulating
layers 21 and a plurality of gate electrode conductive layers 22
are alternately formed on a substrate 20.
[0026] Herein, the interlayer insulating layers 21 serve to isolate
a plurality of memory cells from each other. The interlayer
insulating layer 21 may include an oxide layer. Also, the gate
electrode conductive layer 22 may include a polysilicon layer.
[0027] Also, the interlayer insulating layer 21 and the gate
electrode conductive layer 22 may be formed repeatedly according to
the number of memory cells to be stacked on the substrate 20. For
illustration purposes, the present embodiment illustrates the case
of stacking two memory cells.
[0028] The interlayer insulating layers 21 and the gate electrode
conductive layers 22 are etched to form a channel trench exposing
the surface of the substrate 20.
[0029] A charge blocking layer, a charge trapping layer, and a
tunnel insulating layer are sequentially formed over the resulting
structure including the channel trench, and an etch-back process is
performed to expose the surface of the substrate 20. For
illustration purposes, the charge blocking layer, the charge
trapping layer, and the tunnel insulating layer are illustrated as
one layer denoted by a reference numeral 23.
[0030] An undoped first channel layer 24 is formed over the
resulting structure including the charge blocking layer, the charge
trapping layer, and the tunnel insulating layer. Herein, the first
channel layer 24 is formed such that a center region of the channel
trench is hollow.
[0031] A plasma doping process is performed to dope the first
channel layer 24 with impurities. For example, a first channel
layer 24 may include an undoped polysilicon layer, and the first
channel layer 24 may be doped with n-type impurities.
[0032] Through the plasma doping process, the first channel layer
24 is doped with impurities to a certain thickness from the surface
of the first channel layer 24. Herein, the doping concentration is
highest at the surface of the first channel layer 24 and decreases
with an increase in depth from the surface of the first channel
layer 24.
[0033] Referring to FIG. 2B, a heavily-doped region of the first
channel layer 24 is etched to a predetermined thickness. That is,
the first channel layer 24 is etched to a predetermined thickness
from the surface of the first channel layer 24 to remove the
high-concentration impurities of the first channel layer 24,
thereby leaving only the low-concentration impurities of the first
channel layer 24A. The first channel layer 24 etched to the
predetermined thickness is denoted by a reference numeral 24A.
[0034] A first channel layer 25 is formed on the resulting
structure to fill the channel trench. The second channel layer 25
may include an undoped polysilicon layer.
[0035] Referring to FIG. 2C, a planarization process is performed
to expose the surface of the interlayer insulating layer 21,
thereby forming a channel CH including a first channel layer 24B
and a second channel layer 25A.
[0036] A thermal treatment process is performed to diffuse the
doped impurities of the first channel layer 24B into the second
channel layer 25A, thereby forming a channel CH with a low doping
concentration.
[0037] FIGS. 3A to 3D are cross-sectional views illustrating a
process for fabricating a 3D nonvolatile memory device in
accordance with another embodiment of the present invention. A
description of an overlap with the embodiment of FIGS. 2A to 2C
will be omitted.
[0038] Referring to FIG. 3A, a plurality of interlayer insulating
layers 31 and a plurality of gate electrode conductive layers 32
are alternately formed on a substrate 30. The interlayer insulating
layers 31 and the gate electrode conductive layers 32 are etched to
form a channel trench exposing the surface of the substrate 30.
[0039] A charge blocking layer, a charge trapping layer, and a
tunnel insulating layer are sequentially formed over the resulting
structure including the channel trench, and an etch-back process is
performed to expose the surface of the substrate 30. For
illustration purposes, the charge blocking layer, the charge
trapping layer, and the tunnel insulating layer are illustrated as
one layer denoted by a reference numeral 33.
[0040] A first channel layer 34 is formed over the resulting
structure including the charge blocking layer, the charge trapping
layer, and the tunnel insulating layer 33. For example, the first
channel layer 34 may include an undoped polysilicon layer.
[0041] Referring to FIG. 3B, a buffer layer 35 is formed on the
first channel layer 34. Herein, the buffer layer 35 serves to
prevent the first channel layer 34 from being directly doped with
impurities in the subsequent process. The buffer layer 35 may
include an oxide layer or a nitride layer. For example, if the
buffer layer 35 is an oxide layer, an oxide layer may be deposited
on the first channel layer 34 or the surface of the first channel
layer 34 may be oxidized to a predetermined thickness through an
oxidation process to form the buffer layer 35.
[0042] A plasma doping process is performed to dope the first
channel layer 34 with impurities. The buffer layer 35 on the first
channel layer 34 is doped with impurities, and then the first
channel layer 34 is doped with impurities, The buffer layer 35 can
prevent the first channel layer 34 from being directly doped with
impurities. Thus, the buffer layer 35 is doped at a relatively high
doping concentration, and the first channel layer 34 is doped at a
relatively low doping concentration.
[0043] The thickness of the buffer layer 35 may be controlled to
control the doping concentration of the first channel layer 34. For
example, the doping concentration of the first channel layer 34 may
be reduced by increasing the thickness of the buffer layer 35.
[0044] Referring to FIG. 3C, the buffer layer 35 is removed to
remove the heavily-doped region. The buffer layer 35 may be removed
through a wet etching process.
[0045] A second channel layer 36 is formed over the resulting
structure without the buffer layer 35. The second channel layer 36
may include an undoped polysilicon layer.
[0046] Referring to FIG. 3D, a planarization process is performed
to expose the surface of the interlayer insulating layer 31,
thereby forming a channel CH including a first channel layer 34A
and a second channel layer 36A.
[0047] A thermal treatment process is performed to diffuse the
doped impurities of the first channel layer 34A into the second
channel layer 36A, thereby forming a channel CH with a low doping
concentration.
[0048] FIGS. 4A to 4D are cross-sectional views illustrating a
process for fabricating a 3D nonvolatile memory device in
accordance with another embodiment of the present invention. A
detailed description of the process that overlaps with the
description of the foregoing embodiments will be omitted.
[0049] Referring to FIG. 4A, a plurality of interlayer insulating
layers 41 and a plurality of gate electrode conductive layers 42
are alternately formed on a substrate 40. The interlayer insulating
layers 41 and the gate electrode conductive layers 42 are etched to
form a channel trench exposing the surface of the substrate 40.
[0050] A charge blocking layer, a charge trapping layer, and a
tunnel insulating layer are sequentially formed over the resulting
structure including the channel trench, and an etch-back process is
performed to expose the surface of the substrate 40. For
illustration purposes, the charge blocking layer, the charge
trapping layer, and the tunnel insulating layer are illustrated as
one layer denoted by a reference numeral 43.
[0051] A first channel layer 44 is formed over the resulting
structure including the charge blocking layer, the charge trapping
layer, and the tunnel insulating layer. The first channel layer 44
may include an undoped polysilicon layer.
[0052] A plasma doping process is performed to dope the first
channel layer 44 with impurities. A first channel layer 44 may
include an undoped polysilicon layer, and the first channel layer
44 may be doped with n-type impurities. The doping concentration is
highest at the surface of the first channel layer 44, and decreases
with an increase in depth from the surface of the first channel
layer 44.
[0053] Referring to FIG. 4B, a buffer layer 45 is formed on the
first channel layer 44. The buffer layer 45 serves to remove the
heavily-doped region of the first channel layer 44. The buffer
layer 45 may include an oxide layer or a nitride layer.
[0054] For example, if the buffer layer 45 is an oxide layer, the
surface of the first channel layer 44 may be oxidized to a
predetermined thickness through an oxidation process to form an
oxide layer. At this point, the surface of the first channel layer
44 with a high doping concentration is oxidized to form the oxide
layer, i.e., the buffer layer 45.
[0055] The buffer layer 45 formed through the oxidation process is
removed in the subsequent process, thereby removing the
heavily-doped region. Thus, the remaining doping concentration of
the first channel layer 44 may be controlled by controlling the
oxidation level of the first channel layer 44, i.e., the thickness
of the buffer layer 45. For example, the remaining doping
concentration of the first channel layer 44 may be reduced by
increasing the oxidation thickness of the first channel layer 44,
i.e., by increasing the thickness of the buffer layer 45.
[0056] Referring to FIG. 4C, the buffer layer 45 is removed. The
buffer layer 45 may be removed through a wet etching process.
[0057] In this way, the impurities of the surface of the first
channel layer 44 heavily doped through the plasma doping process
can be removed by removing the buffer layer 45 formed by oxidizing
the surface of the first channel layer 44. Accordingly, the
heavily-doped region is removed and only the lightly-doped region
remains in a first channel layer 44A.
[0058] A second channel layer 46 is formed over the resulting
structure without the buffer layer 45. The second channel layer 46
may include an undoped polysilicon layer.
[0059] Referring to FIG. 4D, a planarization process is performed
to expose the surface of the interlayer insulating layer 41,
thereby forming a channel CH including a first channel layer 44A
and a second channel layer 46A.
[0060] A thermal treatment process is performed to diffuse the
doped impurities of the first channel layer 44B into the second
channel layer 46A, thereby forming a channel CH with a low doping
concentration.
[0061] FIGS. 5A and 5B are cross-sectional views illustrating a
process for fabricating a 3D nonvolatile memory device in
accordance with another embodiment of the present invention. A
detailed description that overlaps with the description of the
foregoing embodiments of the present invention will be omitted.
[0062] Referring to FIG. 5A, a plurality of interlayer insulating
layers 51 and a plurality of gate electrode conductive layers 52
are alternately formed on a substrate 50. The interlayer insulating
layers 51 and the gate electrode conductive layers 52 are etched to
form a channel trench exposing the surface of the substrate 50.
[0063] A charge blocking layer, a charge trapping layer, and a
tunnel insulating layer 53 are sequentially formed over the
resulting structure including the channel trench, and an etch-back
process is performed to expose the surface of the substrate 50. For
illustration purposes, the charge blocking layer, the charge
trapping layer, and the tunnel insulating layer are illustrated as
one layer denoted by a reference numeral 53.
[0064] A first channel layer and a second channel layer are
alternately formed in the channel trench. The first channel layer
and the second channel layer have different doping concentrations.
The first channel layer has a relative low doping concentration and
the second channel layer has a relatively high doping
concentration. Hereinafter, a description is provided for an
exemplary case where the first channel layer 54 is undoped and the
second channel layer 55 is doped.
[0065] A first channel layer 54 is formed over the resulting
structure including the charge blocking layer, the charge trapping
layer, and the tunnel insulating layer.
[0066] A doped second channel layer 55 is formed on the resulting
structure including the first channel layer 54. The second channel
layer 55 may be formed through a doping process. More specifically,
the second channel layer 55 may include a polysilicon layer doped
with n-type impurities.
[0067] Referring to FIG. 5B, a thermal treatment process is
performed to diffuse the doped impurities of the second channel
layer 55 into the first channel layer 54.
[0068] A planarization process is performed to expose the surface
of the interlayer insulating layer 51, thereby forming a
lightly-doped channel CH including a first channel layer 54A and a
second channel layer 55A.
[0069] Even if the present embodiment has been described an
exemplary case of forming the channel including the first channel
layer 54 and the second channel layer 55, a plurality of channel
layers may also be repeatedly formed to form a multi-stack
channel.
[0070] As described above, a first channel layer may be doped with
impurities through a plasma doping process, and the heavily-doped
region may be etched to a predetermined thickness, thereby making
it possible to form a lightly-doped channel. In particular, a
buffer layer is formed on the first channel layer and removed in
the subsequent process, thereby making it possible to easily remove
the heavily-doped region.
[0071] Also, the first and second channel layers are alternately
formed with different doping concentrations, and a thermal
treatment process is performed on the resulting structure, thereby
making it possible to easily form a lightly-doped channel.
[0072] While the present invention has been described with respect
to the specific embodiments, it will be apparent to those skilled
in the art that various changes and modifications may be made
without departing from the spirit and scope of the invention as
defined in the following claims.
* * * * *