U.S. patent application number 13/616158 was filed with the patent office on 2013-05-23 for power semiconductor device driving circuit.
This patent application is currently assigned to DENSO CORPORATION. The applicant listed for this patent is Atsushi Kobayashi, Hisashi Takasu. Invention is credited to Atsushi Kobayashi, Hisashi Takasu.
Application Number | 20130127500 13/616158 |
Document ID | / |
Family ID | 48222213 |
Filed Date | 2013-05-23 |
United States Patent
Application |
20130127500 |
Kind Code |
A1 |
Kobayashi; Atsushi ; et
al. |
May 23, 2013 |
POWER SEMICONDUCTOR DEVICE DRIVING CIRCUIT
Abstract
A power semiconductor device driving circuit includes a gate
control terminal, which is provided at a position separated from a
drain terminal of a power semiconductor device by a predetermined
distance so that electric discharge is generated between the drain
terminal and the gate control terminal at the time of generation of
surge. A surge voltage is applied to the gate control terminal due
to this discharge, the gate of the power semiconductor device is
charged to turn on and absorb the surge energy. Thus it becomes
possible to suppress the surge voltage applied to the drain
terminal and prevent breakdown of the power semiconductor
device.
Inventors: |
Kobayashi; Atsushi;
(Kariya-city, JP) ; Takasu; Hisashi; (Nishio-city,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Kobayashi; Atsushi
Takasu; Hisashi |
Kariya-city
Nishio-city |
|
JP
JP |
|
|
Assignee: |
DENSO CORPORATION
Kariya-city
JP
|
Family ID: |
48222213 |
Appl. No.: |
13/616158 |
Filed: |
September 14, 2012 |
Current U.S.
Class: |
327/109 |
Current CPC
Class: |
H03K 2217/0045 20130101;
H03K 17/0822 20130101; H03K 17/08 20130101; H03K 2217/0027
20130101 |
Class at
Publication: |
327/109 |
International
Class: |
H03K 3/011 20060101
H03K003/011 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 18, 2011 |
JP |
2011-252884 |
Claims
1. A power semiconductor device driving circuit comprising: a power
semiconductor device formed of a semiconductor switching device,
which controls a current supplied to a first terminal and a second
terminal based on a gate voltage applied to a gate terminal, the
first terminal and the second terminal being a high-side terminal
and a low-side terminal; a gate driving circuit for controlling the
gate voltage applied to the gate terminal of the power
semiconductor device; a discharge terminal provided at a position
separated from the first terminal by a predetermined distance to
cause a discharge between the first terminal when the voltage at
the first terminal rises by generation of surge and reaches a
dielectric breakdown voltage; and a gate charge circuit, which
turns on the power semiconductor device by charging a gate of the
power semiconductor device based on the discharge between the first
terminal and the discharge terminal and lowers the voltage of the
first terminal by a current flowing between the first terminal and
the second terminal.
2. The power semiconductor device driving circuit according to
claim 1, wherein: the discharge terminal includes a gate control
terminal; the gate charge circuit includes a resistor provided
between the gate control terminal and the gate terminal of the
power semiconductor device; and the gate of the power semiconductor
device is charged by the surge voltage, which is generated by the
surge, applied to the gate control terminal and applied to the gate
terminal through the resistor.
3. The power semiconductor device driving circuit according to
claim 1, wherein: the discharge terminal includes a gate control
terminal provided in the gate driving circuit; and the gate
charging circuit includes a voltage holding circuit, which is
provided in the gate driving circuit and turns on the power
semiconductor device by holding the gate terminal in a state that a
predetermined voltage is applied to the gate terminal for a
predetermined period when the surge voltage is applied to the gate
control terminal.
4. The power semiconductor device driving circuit according to
claim 3, wherein: the discharge terminal further includes another
gate control terminal provided outside the gate driving circuit;
the gate charge circuit includes a resistor provided between the
another gate control terminal and the gate terminal of the power
semiconductor device; and the gate of the power semiconductor
device is charged by the surge voltage, which is generated by the
surge, applied to the another gate control terminal and applied to
the gate terminal through the resistor.
5. The power semiconductor device driving circuit according to
claim 1, wherein: the discharge terminal is a connection terminal
connected to the second terminal; voltage dividing resistors are
provided between the second terminal and the connection terminal to
input a voltage divided by the voltage dividing resistors to the
gate control terminal provided in the gate driving circuit; and the
gate charging circuit includes a voltage holding circuit, which
turns on the power semiconductor device by holding the gate
terminal in a state that a predetermined voltage is applied to the
gate terminal for a predetermined period when the voltage divided
by the voltage dividing resistors is applied to the gate control
terminal.
6. The power semiconductor device driving circuit according to
claim 3, further comprising: an auxiliary power source for
supplying a voltage, which is smaller than a voltage required to
fully turn on the power device, wherein the gate charging circuit
includes a switch, which is turned on during the predetermined
period by the voltage holding circuit, and the gate charging
circuit applies an auxiliary power voltage supplied by the
auxiliary power source to the gate terminal as the predetermined
voltage when the switch is turned on.
7. An electric system comprising: a full-bridge circuit including
two circuits, each of which includes a pair of power semiconductor
devices, each of which is connected to the power semiconductor
device driving circuit according to claim 1, the full-bridge
circuit generating an AC voltage; and a load connected between a
junction of one pair of the power semiconductor devices connected
in series in one of the two circuits and a junction of another pair
of the power semiconductor devices connected in series in another
of the two circuits, the load being driven by the AC voltage of the
full-bridge circuit.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is based on and incorporates herein by
reference Japanese patent application No, 2011-252884 filed on Nov.
18, 2011.
TECHNICAL FIELD
[0002] The present disclosure relates to a power semiconductor
device driving circuit for driving a power semiconductor device
(semiconductor switching device), which switches over supply of
current to a load.
BACKGROUND
[0003] In a power semiconductor device, a surge voltage
(overvoltage) greater than a withstand voltage is generated between
a drain and a source, that is, in a drain-source path, of the power
semiconductor device due to an inductive (L) load and noise, when
it is turned off in the switching operation. This surge voltage
sometimes causes breakdown of the power semiconductor device. A
conventional power semiconductor device is generally made of
silicon (Si) and a withstand voltage of such a power semiconductor
device is limited by a limited characteristic or performance of Si
material itself. As an alternative, a wide gap semiconductor device
exemplified by gallium nitride (GaN) is considered. The GaN
semiconductor device is promising as a power semiconductor device,
which has a low on-resistance and a high withstand voltage.
[0004] Although the conventional Si semiconductor device (for
example, MOSFET and IGBT) is configured to withstand surge
voltages, the GaN semiconductor device itself is not configured so
and hence has no surge voltage withstand property. It is therefore
necessary to provide an external circuit to ensure the surge
voltage withstand property, which is required to be used for
vehicles.
[0005] JP 2000-077537A (patent document), which corresponds to U.S.
Pat. No. 6,385,028, discloses a power semiconductor device, which
improves surge voltage withstand property. FIG. 11 shows an
exemplary power semiconductor device driving circuit. As shown in
the figure, Zener diodes 102 are arranged for voltage clamping
between a drain and a gate of a power semiconductor device 100 in
addition to Zener diodes 101 arranged for gate protection between
the gate and a source of the power semiconductor device 100. When a
surge voltage is applied to the drain, the Zener diodes 102 beak
down and absorb the surge.
[0006] According to the driving circuit disclosed in the patent
document, when the surge voltage in a drain-source path exceeds the
Zener voltage at the time of turn-off of the power semiconductor
device 100, its drain-gate path conducts and a gate voltage is
raised. Thus the surge voltage is controlled to a sum of the Zener
voltage and a threshold voltage of the power semiconductor
device.
[0007] However, since a rated voltage of the Zener diode increases
in a high power system, the driving circuit becomes large and costs
high.
[0008] The GaN semiconductor device described above has a small
capacitance and hence is more susceptible to parasitic capacitance
than the conventional semiconductor device. For this reason, if a
parasitic capacitance is added to the gate, it will lower high
speed switching performance characteristic.
SUMMARY
[0009] It is therefore an object to provide a power semiconductor
device driving circuit, which can increase a surge withstand
voltage of a power semiconductor device and protect the power
semiconductor device from overvoltage.
[0010] According to one aspect, a power semiconductor device
driving circuit is provided with a power semiconductor device, a
gate driving circuit, a discharge terminal and a gate charge
circuit. The power semiconductor device is formed of a
semiconductor switching device, which controls a current supplied
to a first terminal and a second terminal based on a gate voltage
applied to a gate terminal. The first terminal and the second
terminal are a high-side terminal and a low-side terminal. The gate
driving circuit controls the gate voltage applied to the gate
terminal of the power semiconductor device. The discharge terminal
is provided at a position separated from the first terminal by a
predetermined distance to cause a discharge between the first
terminal when the voltage at the first terminal rises by generation
of surge and reaches a dielectric breakdown voltage. The gate
charge circuit turns on the power semiconductor device by charging
a gate of the power semiconductor device based on the discharge
between the first terminal and the discharge terminal and lowers
the voltage of the first terminal by a current flowing between the
first terminal and the second terminal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The above and other objects, features and advantages will
become more apparent from the following detailed description made
with reference to the accompanying drawings. In the drawings:
[0012] FIG. 1 is a circuit diagram showing a first embodiment of a
power semiconductor device driving circuit;
[0013] FIG. 2 is a time chart showing a basic operation of the
first embodiment when a power semiconductor device is turned
off;
[0014] FIG. 3 is a circuit diagram showing a second embodiment of a
power semiconductor device driving circuit;
[0015] FIG. 4 is a time chart showing a basic operation of the
second embodiment when a power semiconductor device is turned
off;
[0016] FIG. 5 is a circuit diagram showing a third embodiment of a
power semiconductor device driving circuit;
[0017] FIG. 6 is a time chart showing a basic operation of the
third embodiment when a power semiconductor device is turned
off;
[0018] FIG. 7 is a circuit diagram showing an electric system
including a full-bridge circuit, which uses a fourth embodiment of
a power semiconductor device driving circuit;
[0019] FIG. 8 is a time chart showing a basic operation of the
fourth embodiment when a power semiconductor device is turned
off;
[0020] FIG. 9 is a circuit diagram showing a fifth embodiment of a
power semiconductor device driving circuit;
[0021] FIG. 10 is a time chart showing a basic operation of the
fifth embodiment when a power semiconductor device is turned off;
and
[0022] FIG. 11 is a circuit diagram showing a conventional power
semiconductor device driving circuit.
EMBODIMENT
[0023] A power semiconductor device driving circuit will be
described in detail below with reference to various embodiments
shown in the drawings, in which same or similar parts are
designated by same reference numerals.
First Embodiment
[0024] A first embodiment of a power semiconductor device driving
circuit is configured as shown in FIG. 1. A voltage at a control
terminal 1a of a power semiconductor device 1 formed of a
semiconductor switching device is controlled to control a current,
which flows between a first terminal 1b and a second terminal 1c.
The first terminal 1b and the second terminal 1c are a high-side
terminal and a low-side terminal of the power semiconductor device
1, respectively. Thus a current supplied to a load 2 connected to
the first terminal 1b of the power semiconductor device 1 is
controlled. Although the load 2 is exemplified as being connected
to the first terminal 1b of the power semiconductor device 1, that
is, a high potential side, it may be connected to the second
terminal 1c, that is, a low potential side. Although the power
semiconductor device 1 is exemplified as a MOSFET. In case that the
power semiconductor device 1 is the MOSFET, the control terminal
1a, the first terminal 1b and the second terminal 1c are a gate
terminal, a drain terminal and a source terminal, respectively. The
control terminal 1a, the first terminal 1b and the second terminal
1c are referred to as a gate terminal, a drain terminal and a
source terminal, respectively.
[0025] A voltage (gate terminal voltage) of the gate terminal 1a of
the power semiconductor device 1 is controlled by a gate driving
circuit 4 through a gate resistor 3. By controlling the gate
terminal voltage, the power semiconductor device 1 is turned on and
off. The gate driving circuit 4 is configured to control the gate
terminal voltage based on a gate signal applied from, for example,
an external control unit.
[0026] A gate control terminal 5 is provided separately from the
gate terminal 1a as a discharge terminal at a position spaced apart
from the drain terminal 1b by a predetermined distance. The drain
terminal 1b and the gate control terminal 5 are configured to face
each other and are electrically insulated by providing, for
example, a vacuumed condition or an air/gas-filled condition. In a
case that the space between the drain terminal 1b and the gate
control terminal 5 is vacuumed or filled with predetermined gas,
entirety of the power semiconductor device driving circuit 1 or at
lease a space between the drain terminal 1b and the gate control
terminal 5 is sealed gas-tightly by a case, and the inside of the
case is vacuumed or filled with the predetermined gas.
[0027] The gate control terminal 5 is connected electrically only
to a resistor 6. The resistor 6 is provided to form a gate charging
circuit between the gate control terminal 5 and a connection wire
between the gate resistor 3 and the gate terminal 1a, that is,
between the gate control terminal 5 and the gate terminal 1a.
Further, a Zener diode 7 is provided between the gate terminal 1a
and a reference potential point, that is, a GND potential point
which is the same potential as the source terminal 1c. The Zener
diode 7 limits a gate-source voltage not t exceed the Zener
voltage.
[0028] In the power semiconductor device driving circuit 1, the
resistor 6 and the Zener diode 7 may be connected externally, and
the gate resistor 3 and the gate driving circuit 4 may be provided
in one integrated circuit (IC). Alternatively, all the parts may be
provided in one integrated circuit or provided externally as the
case may be.
[0029] An operation of the first embodiment will be described next
with reference to FIG. 2, which is a time chart showing a basic
operation of the driving circuit at the time of turn-off of the
semiconductor power device 1. Since an operation at the time of
turn-on of the semiconductor power device 1 is the same as in the
conventional circuit, only the basic operation at the time of
turn-off is described.
[0030] At time T0, the gate terminal voltage Vg is maintained to be
equal to or higher than a threshold voltage Vth by the gate driving
circuit 4 and the power semiconductor device 1 is maintained in an
on-state. When the gate terminal voltage is then changed to 0 at
time T1 the power semiconductor device 1 is turned off.
[0031] At this turn-off time, a surge voltage is applied to a
drain-source path of the power semiconductor device 1 due to an
inductive load and noise. If no countermeasure is taken, the drain
terminal voltage Vd becomes higher than a power source voltage Vcc
and the surge voltage further rises above a dielectric breakdown
voltage Vdb as indicated by a dotted line in FIG. 2 as a
comparative example. When the surge voltage rises above a withstand
voltage Vw of the power semiconductor device 1, the power
semiconductor device 1 beaks down.
[0032] According to the first embodiment, as described above, the
gate control terminal 5 is arranged at the position spaced apart
from the drain terminal 1b by the predetermined distance. Further
the drain terminal lb and the gate control terminal 5 are
electrically insulated. If the voltage between the drain terminal
1b and the gate control terminal 5 reaches the dielectric breakdown
voltage, electric discharge occurs and a surge voltage is applied
to the gate control terminal 5. This surge voltage is applied to
the gate of the power semiconductor device 1 through the resistor 6
to charge the gate. The power semiconductor device 1 thus
temporarily turns on at time T2 and the drain terminal voltage
decreases. At this time, energy of the surge voltage (surge energy)
is consumed by the on-resistance of the power semiconductor device
1.
[0033] When the gate voltage of the power semiconductor device 1
falls below the threshold voltage due to absorption of the surge
energy, the drain terminal voltage rises again. When the voltage
between the drain terminal 1b and the gate control terminal 5
reaches the dielectric breakdown voltage at time T3, the discharge
arises again so that the voltage is developed at the gate control
terminal 5. This voltage charges the gate of the power
semiconductor device 1 through the resistor 6. The above-described
operation is repeated until the surge energy disappear. The surge
voltage applied to the drain terminal 1b is thus suppressed.
[0034] The dielectric breakdown voltage Vdb [kV] is defined by the
following equation according to Paschen's law. In the following
equation, 3 is a constant [kV] corresponding to atmospheric air.
This constant varies when the space between the drain terminal 1b
and the gate control terminal 5 is vacuumed or filled with
predetermined gas. The inter-terminal distance indicates a distance
[mm] of a discharge path between the drain terminal 1b and the gate
control terminal 5.
Vdb=3.times.inter-terminal distance. (Eq. 1)
[0035] By adjusting the distance between the drain terminal 1b and
the gate control terminal 5 in this equation, the dielectric
breakdown voltage Vdb is made smaller than the withstand voltage of
the power semiconductor device 1. Thus, the surge voltage developed
in the drain-source path of the power semiconductor device 1 is
limited to the dielectric breakdown voltage and becomes lower than
the withstand voltage of the power semiconductor device 1. As a
result, it is possible to suppress the power semiconductor device 1
from breaking down by the surge voltage.
[0036] As described above, the gate control terminal 5 is provided
at a position distanced from the drain terminal 1b by the
predetermined distance in the power semiconductor device driving
circuit 1, so that the discharge is generated between the drain
terminal 1b and the gate control terminal 5 at the time of
generation of surge. As a result of the discharge, the surge
voltage is applied to the gate control terminal 5 and the gate of
the power semiconductor device 1 is charged so that the power
semiconductor device 1 is turned on to absorb the surge energy. It
thus becomes possible to suppress the surge voltage applied to the
drain terminal 1b. The power semiconductor device 1 can thus be
protected from breaking down. As a result, the surge withstand
voltage of the power semiconductor device 1 can be increased, the
overvoltage applied to the drain terminal 1b can be suppressed and
the protection from the overvoltage can be improved.
[0037] In addition, since this configuration adds only a small
parasitic capacitor to the gate of the power semiconductor device
1, high speed switching performance is not lowered. It is thus
possible to provide the power semiconductor device driving circuit
1, which can increase the withstand voltage of the power
semiconductor device and protect the power semiconductor device
from overvoltage without lowering the high speed switching
performance.
[0038] According to the first embodiment, discharge occurs between
the drain terminal 1b and the gate control terminal 5. It is
therefore preferred that only the drain terminal 1b and the gate
control terminal 5 are exposed at a position distanced from other
devices thereby to eliminate influence on the other devices.
Second Embodiment
[0039] A second embodiment of a power semiconductor device driving
circuit is configured as shown in FIG. 3. The second embodiment is
different from the first embodiment in that the position
arrangement of the gate control terminal 5 and the configuration of
the gate driving circuit 4 are changed. The second embodiment is
the same as the first embodiment in respect to other parts and
hence only the different parts will be described.
[0040] As shown in FIG. 3, the gate control terminal 5 is provided
in the gate driving circuit 4, and a voltage holding circuit 10, a
logic circuit 11 and three switches (SW) 12 to 14 are provided
within the gate driving circuit 4. Further, an auxiliary power
source 15 is connected to the gate driving circuit 4. The voltage
holding circuit 10, the switch 13, the auxiliary power source 15
and the like form a gate charging circuit. The resistor 6 and the
Zener diode 7 provided in the first embodiment are eliminated.
[0041] The voltage holding circuit 10 is configured to receive the
voltage of the gate control terminal 5. When the discharge occurs
between the drain terminal 1b and the gate control terminal 5 at
the time of generation of surge, the surge voltage is applied. When
the surge voltage is applied, the voltage holding circuit 10
outputs a high-level signal indicating the application of surge
voltage for a predetermined period set longer than a period
required to consume the surge energy. The circuit controls the gate
terminal voltage of the power semiconductor device 1 to a voltage
required to consume the surge energy as describe below. That is,
the voltage holding circuit 10 uses the surge voltage applied to
the gate control terminal 5 as a signal source, and controls the
gate terminal voltage of the power semiconductor device 1 when the
surge voltage is applied.
[0042] The logic circuit 11 is configured to turn on either one of
the switches 12 to 14 at a desired timing based on the gate signal
and the output of the voltage holding circuit 10. Specifically, the
logic circuit 11 is configured to have a NOT circuit 11a, a NOR
circuit 11b and a NAND circuit 11c. The NOT circuit 11a is for
inputting an inverted gate signal to the second switch 13. The gate
signal is inputted to the first switch 12 and the inverted gate
signal, which is inverted by the NOT circuit 11a, is inputted to
the NOR circuit 11b. The NOR circuit 11b is configured to turn on
the second switch 13 by not only the gate signal (specifically the
signal which is generated by inversion of the gate signal) but also
the output of the voltage holding circuit 10. The NOR circuit 11b
inputs the output of the NOT circuit 11a and the output of the
voltage holding circuit 10 to control the second switch 13. The
NAND circuit 11c controls the third switch 14 based on the gate
signal and the output of the voltage holding circuit 10.
[0043] The first to the third switches 12 to 14 are switches, which
control the gate terminal voltage of the power semiconductor device
1. The first and the second switches 12 and 13 are used as
switches, which basically on/off-controls the power semiconductor
device 1. Specifically, the gate terminal voltage is set to the
power source voltage Vcc, when the first switch 12 is turned on and
the second switch 13 is turned off. The gate terminal voltage is
set to a GND potential, when the first switch 12 is turned off and
the second switch 13 is turned on. The third switch 14 is used as a
switch for controlling the gate terminal voltage of the power
semiconductor device 1 to a surge energy absorbing voltage, which
is close to the threshold voltage of the power semiconductor device
1. Specifically, this voltage is higher than the threshold voltage
and lower than a voltage, by which the power semiconductor device 1
is fully turned on.
[0044] The auxiliary power source 15 generates an auxiliary power
voltage Va, which corresponds to the surge energy absorbing
voltage. The auxiliary power voltage Va is applied to the gate
terminal 1a of the power semiconductor device 1 when the third
switch 14 is turned on.
[0045] The operation of the second embodiment will be described
below with reference to FIG. 4, which shows a basic operation of
the second embodiment at the time of turn-off of the power
semiconductor device 1. Since an operation of the second embodiment
at the time of turn-on is the same as in the conventional circuit,
only the basic operation at the time of turn-off is described.
[0046] At time T0, the first switch 12 and the second switch 13 are
maintained in the on-state and the off-state based on the gate
signal, respectively. As a result, the gate terminal voltage of the
power semiconductor device 1 is the same as the power voltage. Vcc
and the power semiconductor device 1 is in the on-state. At this
time, since no voltage is applied to the gate control terminal 5,
the output level of the voltage holding circuit 10 is low, the
output level of the NAND circuit 11c is also low, and the third
switch 14 is in the off-state.
[0047] When the gate signal is changed from the low level to the
high level at the time of turn-off as indicated at time T1, the
first switch 12 is turned off, the second switch 13 is turned on.
Since the gate terminal voltage becomes 0, the power semiconductor
device 1 is turned off. At this turn-off time, the surge voltage is
generated between the drain-source path of the power semiconductor
device 1. When the voltage between the drain terminal 1b and the
gate control terminal 5 reaches the dielectric breakdown voltage at
time T2, the surge voltage is generated by the discharge and
applied to the gate control terminal 5. This surge voltage is
applied to the voltage holding circuit 10 and the output level of
the voltage holding circuit is changed to and maintained at the
high level during a predetermined period.
[0048] The output level of the NAND circuit 11 also changes to the
high level. At time T30, which is after an elapse of a delay time
of the logic circuit 11, the third switch 14 is turned on. The
output level of the NOR circuit 11b becomes high and the second
switch 13 is turned off. The auxiliary power voltage Va supplied by
the auxiliary power source 15 is applied to the gate terminal 1a of
the power semiconductor device 1 through the third switch 14, and
the gate of the power transistor 1 is charged. As a result, the
power semiconductor device 1 is turned on. The drain terminal
voltage is decreased and during this period the surge energy is
consumed by the on-resistance of the power semiconductor device
1.
[0049] At this time, the voltage applied to the terminal 1a of the
power semiconductor device 1 is controlled to the auxiliary power
voltage Va, which is close to the threshold voltage and lower than
the voltage with which the power semiconductor device 1 is fully
turned on. Thus, the power semiconductor device 1 has a smaller
channel than in the full-on state. The narrowed channel has a
larger resistance component and is in a limited-on state (for
example, half-on state), in which the current flowing in the
drain-source path is limited. It is therefore possible to more
easily consume the surge energy than in a case that the power
semiconductor device 1 is fully turned on. The surge energy can
thus be consumed in a shorter period.
[0050] At time T40, which is after an elapse of a predetermined
period required to consume the surge energy, the output level of
the voltage holding circuit 10 returns to the low level, the output
level of the NAND circuit 11c becomes low and the third switch 14
returns to the off state. Further the output level of the NOR
circuit 11b becomes low, the second switch 14 is turned on and the
voltage of the gate terminal 1a of the power semiconductor device 1
becomes 0. Thus the power semiconductor device 1 is turned off. It
is thus possible to suppress the surge voltage applied to the drain
terminal 1b when the power semiconductor device 1 is turned
off.
[0051] As described above, according to the second embodiment, the
gate driving circuit 4 is provided with the gate control terminal 5
and the voltage holding circuit 10 provided therein. Further, the
power semiconductor device 1 is maintained in the on-state until
the consumption of surge energy is finished. The second embodiment
provides the similar advantage as the first embodiment.
[0052] Since the surge energy is absorbed by repetition of
generation of discharge in the first embodiment, noise is likely to
generate. According to the second embodiment, however, the
repetition of generation of discharge is reduced and hence the
noise can be suppressed.
[0053] Further, according to the second embodiment, the auxiliary
power voltage Va is applied to the gate terminal 1a of the power
semiconductor device 1 by the voltage holding circuit 10 during the
period of consumption of the surge energy. That is, the power
semiconductor device 1 is not fully turned on, but is in the
limited turn-on state, in which the current flowing in the
drain-source path is limited. It is thus possible to consume the
surge energy in a shorter period in comparison to a case, in which
the power semiconductor device 1 is fully turned on.
[0054] In a case that the first to the third switches 12 to 14 are
controlled by the logic circuit 11, switching of the second switch
13 and the third switch 14 is delayed by a delay time generated in
the logic circuit 11 from the change of the output level of the
voltage holding circuit 10 to the high level. The surge voltage of
the drain terminal 1b becomes higher than the dielectric breakdown
voltage in correspondence to the delay period. However, the delay
period is short and the surge voltage does not exceed the withstand
voltage of the power semiconductor device 1. The power
semiconductor device 1 is not therefore subjected to breakdown.
Third Embodiment
[0055] A third embodiment of a power semiconductor device driving
circuit is configured as shown in FIG. 5. The third embodiment is a
combination of the first embodiment (FIG. 1) and the second
embodiment (FIG. 3). Since the basic configuration is the same as
the first and the second embodiments, only differences from the
first and the second embodiments will be described.
[0056] As shown in FIG. 5, the gate control terminal 5 and the
Zener diode 7 are provided in the same way as in the first
embodiment. Further the gate control terminal 5 is provided also
for the gate driving circuit 4. In addition, the voltage holding
circuit 10, the logic circuit 11, the first to the third switches
12 to 14 and the auxiliary power source 15 are provided in the same
way as in the second embodiment. Although the gate control terminal
5 connected to the resistor 6 and the gate control terminal 5
connected to the gate driving circuit 4 are shown as provided
separately and connected by an electric conductor, these terminals
5 may be provided as a single terminal.
[0057] In the second embodiment, the gate terminal 1a of the power
semiconductor device 1 can be controlled to the auxiliary power
voltage Va, that is, closely to the threshold voltage, and the
surge energy can be consumed in a short period. However, when the
surge voltage is generated, the delay of the logic circuit 11
occurs.
[0058] However, by combining the first embodiment and the second
embodiment, it becomes possible to charge the gate of the power
semiconductor device 1 at high speeds according to the
configuration of the first embodiment and to consume the surge
energy at earlier time according to the configuration of the second
embodiment.
[0059] A basic operation of the third embodiment at the time of
turn-off will be described below.
[0060] At time T0, the first switch 12 and the second switch 13 are
maintained in the on-state and the off state based on the gate
signal, respectively. As a result, the gate terminal voltage of the
power semiconductor device 1 is the same as the power voltage Vcc
and the power semiconductor device 1 is in the on-state. At this
time, since no voltage is applied to the gate control terminal 5,
the output level of the voltage holding circuit 10 is low, the
output level of the NAND circuit 11c is also low, and the third
switch 14 is in the off-state.
[0061] When the gate signal is changed from the low level to the
high level at the time of turn-off as indicated at time T1, the
first switch 12 is turned off, the second switch 13 is turned on.
Since the gate terminal voltage becomes 0, the power semiconductor
device 1 is turned off. At this turn-off time, the surge voltage is
generated in the drain-source path of the power semiconductor
device 1. When the voltage between the drain terminal 1b and the
gate control terminal 5 reaches the dielectric breakdown voltage at
time T2, the discharge is generated and the surge voltage is
applied to the gate control terminal 5. As a result, the power
semiconductor device 1 is temporarily turned on and the drain
terminal voltage is decreased. During this period, the surge energy
is consumed by the on-resistance of the power semiconductor device
1.
[0062] When the surge voltage is applied to the gate control
terminal 5, this voltage is also inputted to the voltage holding
circuit 10 and the output level of the voltage holding circuit 10
is changed to the high level during this period.
[0063] For this reason, even when the drain terminal voltage rises
because of the fall of the gate voltage to be lower than the
threshold voltage, the delay time of the logic circuit 11 elapses
during that period. The third switch 14 and the second switch 13
are turned on and off, respectively. The auxiliary power voltage Va
generated by the auxiliary power source 15 is applied to the gate
terminal 1a of the power semiconductor device 1, and the gate
terminal voltage of the power transistor 1 is charged. As a result,
the power semiconductor device 1 is turned on. The drain terminal
voltage is decreased and the surge energy is consumed by the
on-resistance of the power semiconductor device 1 in a short
period. Then the third embodiment operates in the same manner as
the second embodiment.
[0064] By combining the first embodiment and the second embodiment
as described above, it becomes possible to charge the gate at high
speeds according to the configuration of the first embodiment and
to consume the surge energy at earlier time according to the
configuration of the second embodiment. Although the noise problem
arises in the first embodiment because the surge energy generated
by the repetition of discharges is absorbed, such a noise problem
can be minimized in the third embodiment because the number of
times of discharging is reduced. Further it becomes possible to
attain the surge voltage suppression before the elapse of the delay
time of the logic circuit.
Fourth Embodiment
[0065] A fourth embodiment of a power semiconductor device driving
circuit is configured in the same way as the first embodiment and
used for a full-bridge circuit of four arms as shown in FIG. 7.
However, the second and the third embodiments may also be used
similarly for the full-bridge circuit. This full-bridge circuit may
be applied to an electric system, for example, a DC-DC converter, a
PWM converter or the like.
[0066] In FIG. 7, four driving circuits, each of which forms an
arm, are arranged in a full-bridge shape. That is, two circuits,
each of which has two power semiconductor devices 1 connected in
series between a positive side and a negative side of a DC power
source 30, are provided. In this configuration, the load 2 is
formed of an inductive component 2a and a resistive component 2b,
and connected between junctions (neutral points) of the two power
semiconductor devices 1 of each circuit. Thus the power
semiconductor device driving circuit 1 can be exemplarily applied
to the full-bridge circuit.
[0067] A basic operation of the full-bridge circuit at the turnoff
time is shown in FIG. 7. Since the operation of the fourth
embodiment at the turn-on time is the same as the conventional
circuit, only the basic operation at the turnoff time will be
described. As shown in FIG. 7, in one of the two circuits each
having two series-connected power semiconductor devices 1, a
high-side power semiconductor device 1, its drain-source path
voltage, a low-side power semiconductor device 1 and its
drain-source path voltage are designated as SW1, VDS1, SW2 and
VDS2, respectively. Further, in the other of the two circuits each
having two series-connected power semiconductor devices 1, a
high-side power semiconductor device 1, its drain-source path
voltage, a low-side power semiconductor device 1 and its
drain-source path voltage are designated as SW3, VDS3, SW4 and
VDS4, respectively. The gate terminals 1a of the power
semiconductor devices SW1 to SW4 are designated as G1 to G4,
respectively. Similarly, the gate control terminals 5 of the same
are designated as G10 to G40.
[0068] In the bridge circuit, the power semiconductor devices SW1
and SW4 operate synchronously so that a current flows through the
power semiconductor devices SW1 and SW4 through the load 2 at the
same time and the power semiconductor devices SW2 and SW3 operate
synchronously so that a current flows through the power
semiconductor devices SW2 and SW3 through the load 2 at the same
time. The pair of the power semiconductor devices SW1, SW4 and the
pair of the power semiconductor devices SW2, SW3 turn on and off
alternately to generate an AC voltage for the load 2. A dead time
is provided so that both of the pairs turn off at the same time to
prevent power supply short-circuit.
[0069] After the power semiconductor devices SW1 and SW4 are turned
off, the drain terminal voltages Vd (VDS1 and VDS4) of the power
semiconductor devices SW1 and SW4 reach the dielectric breakdown
voltage relative to the gate control terminals G10 and G40. As a
result, voltages are generated at the gate control terminals G10
and G40 by the discharge. The generated voltages are applied to the
gates of the power semiconductor devices SW1 and SW4 through
respective resistors 6 to charge the gates. The power semiconductor
devices SW1 and SW4 turn on and the drain terminal voltages of the
power semiconductor devices SW1 and SW4 are lowered. During this
period, the surge energy is consumed by the power semiconductor
devices SW1 and SW4. This operation is repeated until the surge
energy disappears. The surge voltages developed at the drain
terminal voltages Vd (VDS1, VDS4) of the power semiconductor
devices SW1 and SW4 are suppressed.
[0070] Since it is during the dead time period that the power
devices SW1 and SW4 turn on repeatedly, the pair of power
semiconductor devices SW1, SW4 and the pair of power semiconductor
devices SW2, SW3 do not turn on at the same and hence the power
supply short-circuit is not caused. When the power semiconductor
devices SW2 and SW3 turn off, the power semiconductor devices SW2
and SW3 operate in the same way as the power semiconductor devices
SW1 and SW4. As a result, the surge energy can be consumed and the
surge voltages generated at the drain terminal voltages (VDS2,
VDS4) of the power semiconductor devices SW2 and SW3 can be
suppressed.
Fifth Embodiment
[0071] A fifth embodiment of a power semiconductor device driving
circuit is configured as shown in FIG. 9. The fifth embodiment is
different from the second embodiment in respect of a section, at
which the discharge is generated, but is the same as the second
embodiment in other respects. Therefore, only the difference from
the second embodiment will be described.
[0072] As shown in FIG. 9, the gate control terminal 5 is provided
in the gate driving circuit 4. Further, the voltage holding circuit
10, the logic circuit 11, three switches 12 to 14 and the auxiliary
power source 15 are provided in the gate driving circuit 4. The
resistor 6 and the Zener diode 7 provided in the first embodiment
are not provided.
[0073] According to the fifth embodiment, a source connection
terminal 40, which is connected as a connection terminal to the
source terminal 1c is used as a discharge terminal so that the
discharge is generated between the drain terminal 1b and the source
connection terminal 40. Voltage dividing resistors 41 and 42 are
provided between the source terminal 1c and the source connection
terminal 40. A junction between the voltage dividing resistors 41
and 42 is connected to the gate control terminal 5 provided in the
gate driving circuit 4.
[0074] A basic operation of the fifth embodiment at the turn-off
time is shown in FIG. 10. Since the operation of at the turn-on
time is the same as the conventional circuit, only the basic
operation at the turn-off time will be described.
[0075] At time T0, the same condition is maintained as in the case
of the second embodiment shown at time T0 in FIG. 4. When the gate
signal is changed from the low level to the high level at the
turn-off time at time T1 from the above-described condition, the
first switch 12 and the second switch 13 are turned off and on,
respectively. Since the gate terminal voltage is reduced to 0, the
power semiconductor device 1 is turned off. At this turn-off time,
the surge voltage is generated in the drain-source path of the
power semiconductor device 1. When the voltage reaches the
dielectric breakdown voltage between the drain terminal 1b and the
source connection terminal 40 at time T2, the discharge occurs and
applies the surge voltage to the source connection terminal 40.
This voltage is divided by the voltage dividing resistors 41 and 42
and applied to the voltage holding circuit 10 through the gate
control terminal 5. The output of the voltage holding circuit 10 is
switched over to the high level during a predetermined period.
[0076] Thus, the same operation is performed as shown after time T1
in FIG. 4 so that the power semiconductor device 1 is turned on and
the drain terminal voltage is lowered. During this period, the
surge energy is consumed by the on-resistance of the power
semiconductor device 1. Since the auxiliary power voltage Va is
used as the voltage, which is applied to the gate terminal 1a of
the power semiconductor device 1, it becomes possible to more
easily consume the surge energy than in a case of fully turning on
the power semiconductor device 1.
[0077] The same advantage is provided as in the second embodiment
by thus suppressing the surge voltage of the drain terminal 1b and
absorbing the surge energy based on the discharge between the drain
terminal 1b and the source connection terminal 40.
Other Embodiments
[0078] In each of the first to the fifth embodiments, the power
semiconductor device 1 is formed of a MOSFET. However, the power
semiconductor device 1 may be formed of other semiconductor
switching devices such as an IGBT, thyristor or GTO (gate turn-off
thyristor). In case of the IGBT, however, sections representing the
first terminal 1b and the second terminal 1c are changed so that
the first terminal 1b and the second terminal 1c are set to a
collector terminal and an emitter terminal.
[0079] Although the full-bridge circuit is exemplified as an
example of application of the driving circuit in the fourth
embodiment, the driving circuit may be applied to a half-bridge
circuit or a three-phase bridge circuit.
* * * * *