U.S. patent application number 13/284730 was filed with the patent office on 2013-05-02 for systems and methods for dual process data decoding.
This patent application is currently assigned to LSI Corporation. The applicant listed for this patent is Wu Chang, Lei Chen, Yang Han, Zongwang Li, Shaohua Yang, Fan Zhang. Invention is credited to Wu Chang, Lei Chen, Yang Han, Zongwang Li, Shaohua Yang, Fan Zhang.
Application Number | 20130111289 13/284730 |
Document ID | / |
Family ID | 48173722 |
Filed Date | 2013-05-02 |
United States Patent
Application |
20130111289 |
Kind Code |
A1 |
Zhang; Fan ; et al. |
May 2, 2013 |
SYSTEMS AND METHODS FOR DUAL PROCESS DATA DECODING
Abstract
Various embodiments of the present invention provide systems and
methods for data processing. For example, data processing systems
are disclosed that include a data decoding system. The data
decoding system includes a data decoder circuit and a simplified
maximum likelihood value modification circuit. The data decoder
circuit is operable to apply a data decode algorithm to a decoder
input to yield a first decoded output and an indication of at least
one point of failure of the first decoded output. The simplified
maximum likelihood value modification circuit is operable to
identify a symbol of the first decoded output associated with the
point of failure, and to modify a subset of values associated with
the identified symbol to yield a modified decoded output.
Inventors: |
Zhang; Fan; (Milpitas,
CA) ; Chen; Lei; (Santa Clara, CA) ; Li;
Zongwang; (San Jose, CA) ; Yang; Shaohua; (San
Jose, CA) ; Han; Yang; (Sunnyvale, CA) ;
Chang; Wu; (Santa Clara, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Zhang; Fan
Chen; Lei
Li; Zongwang
Yang; Shaohua
Han; Yang
Chang; Wu |
Milpitas
Santa Clara
San Jose
San Jose
Sunnyvale
Santa Clara |
CA
CA
CA
CA
CA
CA |
US
US
US
US
US
US |
|
|
Assignee: |
LSI Corporation
|
Family ID: |
48173722 |
Appl. No.: |
13/284730 |
Filed: |
October 28, 2011 |
Current U.S.
Class: |
714/752 ;
714/E11.032 |
Current CPC
Class: |
H03M 13/1108 20130101;
H03M 13/1128 20130101; G11B 20/1833 20130101; H03M 13/1171
20130101; H03M 13/3707 20130101; G11B 2020/185 20130101; H03M
13/451 20130101; H03M 13/1142 20130101; H03M 13/1111 20130101 |
Class at
Publication: |
714/752 ;
714/E11.032 |
International
Class: |
H03M 13/05 20060101
H03M013/05; G06F 11/10 20060101 G06F011/10 |
Claims
1. A data processing system, the data processing system comprising:
a data decoding system including: a data decoder circuit operable
to apply a data decode algorithm to a decoder input to yield a
first decoded output and an indication of at least one point of
failure of the first decoded output; a simplified maximum
likelihood value modification circuit operable to identify a symbol
of the first decoded output associated with the point of failure,
and to modify a subset of values associated with the identified
symbol to yield a modified decoded output; and wherein the data
decoder circuit is further operable to apply the data decode
algorithm to the decoder input guided by the modified decoded
output to yield a second decoded output.
2. The data processing system of claim 1, wherein the simplified
maximum likelihood value modification circuit comprises: a syndrome
calculation circuit operable to calculate a syndrome based upon a
number of symbols associated with the point of failure; an array
calculator circuit operable to calculate an array of possible hard
decision values across the contributors to the point of failure;
and an index identifier circuit operable to determine a candidate
from the array as the identified symbol.
3. The data processing system of claim 2, wherein the simplified
maximum likelihood value modification circuit further comprises: a
likely symbol value selector circuit operable to determine whether
the subset of values associated with the identified symbol includes
one log likelihood ratio value or two log likelihood ratio
values.
4. The data processing circuit of claim 1, wherein the data
processing system is implemented as part of a device selected from
a group consisting of: a storage device, and a receiving
device.
5. The data processing system of claim 1, wherein the data
processing system is implemented as part of an integrated
circuit.
6. The data processing system of claim 1, wherein the data decode
algorithm is a low density parity check algorithm, and wherein the
point of failure of the decoded output is a failure of a parity
check equation implemented as part of the low density parity check
algorithm.
7. The data processing system of claim 6, wherein the low density
parity check algorithm is selected from a group consisting of: a
non-binary low density parity check algorithm, and a binary low
density parity check algorithm.
8. The data processing system of claim 6, wherein the low density
parity check algorithm is implemented as a belief propagation data
decode algorithm.
9. The data processing system of claim 1, wherein the data
processing system further comprises: a data detector circuit
operable to apply a data detection algorithm to a data set to yield
a detected output, wherein the decoder input is derived from the
detected output.
10. The data processing system of claim 9, wherein the data
detection algorithm is selected from a group consisting of: a
maximum a posteriori data detection algorithm and a Viterbi
detection algorithm.
11. The data processing system of claim 1, wherein the data decoder
circuit further comprises: a controller circuit operable to
selectively control generation of the modified decoded output.
12. The data processing system of claim 11, wherein the controller
circuit enables generation of the modified decoded output when: a
number of iterations of the data decoder circuit applying the data
decode algorithm to the decoder input is greater than a first
threshold value; a number of points of failure corresponding to the
first decoded output is less than a second threshold value; and the
number of points of failure corresponding to the first decoded
output is the same as the number of points of failure corresponding
to a previous decoded output.
13. The data processing system of claim 12, wherein the first
threshold value is three, and the second threshold value is
ten.
14. A method for data processing, the method comprising: applying a
data decode algorithm by a data decoder circuit to a decoder input
to yield a first decoded output and an indication of at least one
point of failure of the first decoded output; identifying at least
a first symbol and a second symbol associated with the point of
failure of the first decoded output; calculating a syndrome
including the first symbol and the second symbol; calculating an
array of possible hard decision values across the contributors to
the point of failure; determining an index corresponding to a
candidate from the array as an identified symbol; determining a
subset values associated with the identified symbol to be modified;
modifying the subset of values to yield a modified decoded output;
and applying the data decode algorithm by the data decoder circuit
to the decoder input guided by the modified decoded output to yield
a second decoded output.
15. The method of claim 14, wherein calculating the syndrome is
done in accordance with the following equation: s = i = 0 M v i
.times. e i , ##EQU00008## wherein v.sub.i corresponds to hard
decision values of variable nodes corresponding to the point of
failure of a check node, M is the number of variable nodes
corresponding to the check node, and e.sub.i corresponds to edge
values connecting the variable nodes to the check node.
16. The method of claim 15, wherein calculating the array of
possible hard decision values across the contributors to the point
of failure is done in accordance with the following equation:
Array.sub.i,j=(j.times.e.sub.i.sup.-1)-HD.sub.i, for i .di-elect
cons. {1, 2, . . . M}, j .di-elect cons. {1, 2, 3}, wherein j
represents the contribution from the calculated syndrome, HD.sub.i
represents the most likely symbol for a particular instance i, and
e.sub.i.sup.-1 corresponds to an inverse edge value for the
particular instance i.
17. The method of claim 16, wherein determining the index is done
in accordance with the following equation: index.sub.j=arg
min.sub.i(LLR.sub.HD.sub.i .sub.XOR Array.sub.i,j), wherein j
.di-elect cons. {1, 2, 3}, and wherein LLR is a log likelihood
ratio of the most likely symbol.
18. A storage device, the storage device comprising: a storage
medium; a head assembly disposed in relation to the storage medium
and operable to provide a sensed signal corresponding to
information on the storage medium; a read channel circuit
including: an analog to digital converter circuit operable to
sample an analog signal derived from the sensed signal to yield a
series of digital samples; an equalizer circuit operable to
equalize the digital samples to yield a data set; a data detector
circuit operable to apply a data detection algorithm to the data
set to yield a detected output; and a data decoding system
including: a data decoder circuit operable to apply a data decode
algorithm to a decoder input to yield a first decoded output and an
indication of at least one point of failure of the first decoded
output; a simplified maximum likelihood value modification circuit
operable to identify a symbol of the first decoded output
associated with the point of failure, and to modify a subset of
values associated with the identified symbol to yield a modified
decoded output; and wherein the data decoder circuit is further
operable to apply the data decode algorithm to the decoder input
guided by the modified decoded output to yield a second decoded
output.
19. The storage device of claim 18, wherein the simplified maximum
likelihood value modification circuit comprises: a syndrome
calculation circuit operable to calculate a syndrome based upon a
number of symbols associated with the point of failure; an array
calculator circuit operable to calculate an array of possible hard
decision values across the contributors to the point of failure; an
index identifier circuit operable to determine a candidate from the
array as the identified symbol; and a likely symbol value selector
circuit operable to determine whether the subset of values
associated with the identified symbol includes one log likelihood
ratio value or two log likelihood ratio values.
20. The storage device of claim 18, wherein the simplified maximum
likelihood value modification circuit further comprises: a
controller circuit operable to selectively control generation of
the modified decoded output, wherein the controller circuit enables
generation of the modified decoded output when: a number of
iterations of the data decoder circuit applying the data decode
algorithm to the decoder input is greater than a first threshold
value; a number of points of failure corresponding to the first
decoded output is less than a second threshold value; and the
number of points of failure corresponding to the first decoded
output is the same as the number of points of failure corresponding
to a previous decoded output.
Description
BACKGROUND OF THE INVENTION
[0001] The present inventions are related to systems and methods
for data processing, and more particularly to systems and methods
for data decoding.
[0002] Various storage systems include data processing circuitry
implemented with a data decoding circuit. In some cases, a belief
propagation based decoder circuit is used. In such cases where high
rate low density parity check codes are used, an error floor is
more severe because short cycles are unavoidable. Such short cycles
make the messages in the belief propagation decoder correlate
quickly and degrade the performance. In contrast, a maximum
likelihood decoder may be used as it does not exhibit the same
limitations. However, such maximum likelihood decoders are
typically too complex for practical implementation.
[0003] Hence, for at least the aforementioned reasons, there exists
a need in the art for advanced systems and methods for data
processing.
BRIEF SUMMARY OF THE INVENTION
[0004] The present inventions are related to systems and methods
for data processing, and more particularly to systems and methods
for data decoding.
[0005] Various embodiments of the present invention provide data
processing systems. Such data processing systems include a data
decoding system. The data decoding system includes a data decoder
circuit and a simplified maximum likelihood value modification
circuit. The data decoder circuit is operable to apply a data
decode algorithm to a decoder input to yield a first decoded output
and an indication of at least one point of failure of the first
decoded output. The simplified maximum likelihood value
modification circuit is operable to identify a symbol of the first
decoded output associated with the point of failure, and to modify
a subset of values associated with the identified symbol to yield a
modified decoded output. In such embodiments, the data decoder
circuit is further operable to apply the data decode algorithm to
the decoder input guided by the modified decoded output to yield a
second decoded output.
[0006] In some instances of the aforementioned embodiments, the
simplified maximum likelihood value modification circuit includes a
syndrome calculation circuit, an array calculator circuit, and an
index calculator circuit. The syndrome calculation circuit is
operable to calculate a syndrome based upon a number of symbols
associated with the point of failure. The array calculator circuit
is operable to calculate an array of possible hard decision values
across the contributors to the point of failure. The index
identifier circuit is operable to determine a candidate from the
array as the identified symbol. In some cases, the simplified
maximum likelihood value modification circuit further includes a
likely symbol value selector circuit that is operable to determine
whether the subset of values associated with the identified symbol
includes one log likelihood ratio value or two log likelihood ratio
values.
[0007] In some instances of the aforementioned embodiments, the
data processing system is implemented as part of a storage device.
In other instances of the aforementioned embodiments, the data
processing system is implemented as part of a receiving device. In
some cases, the data processing system is implemented as part of an
integrated circuit. In some instances of the aforementioned
embodiments, the data decode algorithm is a low density parity
check algorithm, and the point of failure of the decoded output is
a failure of a parity check equation implemented as part of the low
density parity check algorithm. In some such cases, the low density
parity check algorithm is a non-binary low density parity check
algorithm. In other such cases, the low density parity check
algorithm is a binary low density parity check algorithm. In
various cases, the low density parity check algorithm is
implemented as a belief propagation data decode algorithm.
[0008] In some instances of the aforementioned embodiments, the
data processing system further includes a data detector circuit
operable to apply a data detection algorithm to a data set to yield
a detected output, wherein the decoder input is derived from the
detected output. In some such instances, the data detection
algorithm may be, but is not limited to, a maximum a posteriori
data detection algorithm or a Viterbi detection algorithm.
[0009] In various instances of the aforementioned embodiments, the
data decoder circuit further includes a controller circuit operable
to selectively control generation of the modified decoded output.
The controller circuit may enable generation of the modified
decoded output when: a number of iterations of the data decoder
circuit applying the data decode algorithm to the decoder input is
greater than a first threshold value; a number of points of failure
corresponding to the first decoded output is less than a second
threshold value; and the number of points of failure corresponding
to the first decoded output is the same as the number of points of
failure corresponding to a previous decoded output. In some cases,
the first threshold value is three, and the second threshold value
is ten.
[0010] Other embodiments of the present invention provide methods
for data processing that include: applying a data decode algorithm
by a data decoder circuit to a decoder input to yield a first
decoded output and an indication of at least one point of failure
of the first decoded output; identifying at least a first symbol
and a second symbol associated with the point of failure of the
first decoded output; calculating a syndrome including the first
symbol and the second symbol; calculating an array of possible hard
decision values across the contributors to the point of failure;
determining an index corresponding to a candidate from the array as
an identified symbol; determining a subset values associated with
the identified symbol to be modified; modifying the subset of
values to yield a modified decoded output; and applying the data
decode algorithm by the data decoder circuit to the decoder input
guided by the modified decoded output to yield a second decoded
output.
[0011] In some cases, calculating the syndrome is done in
accordance with the following equation:
s = i = 0 M v i .times. e i , ##EQU00001##
where v.sub.i corresponds to hard decision values of the variable
nodes feeding a check node associated with the unsatisfied check, M
is the number of variable nodes corresponding to the check node,
and e.sub.i corresponds to the edge values connecting the variable
nodes to the check node. In various cases, calculating the array of
possible hard decision values across the contributors to the point
of failure is done in accordance with the following equation:
HD'.sub.i,j=(j.times.e.sub.i.sup.-1)-HD.sub.i, for i .di-elect
cons. {1, 2, . . . M , j .di-elect cons. {1, 2, 3}.
where j represents the contribution from the calculated syndrome,
HDi represents the most likely symbol for a particular instance i,
and e.sub.i.sup.-1 corresponds to an inverse edge value for the
particular instance i. In one or more cases, determining the index
is done in accordance with the following equation:
i*.sub.j=arg min.sub.i(LLR.sub.HD.sub.i .sub.XOR HD'.sub.i,j)
where j .di-elect cons. {1, 2, 3}, and LLR is a log likelihood
ratio of the most likely symbol.
[0012] This summary provides only a general outline of some
embodiments of the invention. Many other objects, features,
advantages and other embodiments of the invention will become more
fully apparent from the following detailed description, the
appended claims and the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] A further understanding of the various embodiments of the
present invention may be realized by reference to the figures which
are described in remaining portions of the specification. In the
figures, like reference numerals are used throughout several
figures to refer to similar components. In some instances, a
sub-label consisting of a lower case letter is associated with a
reference numeral to denote one of multiple similar components.
When reference is made to a reference numeral without specification
to an existing sub-label, it is intended to refer to all such
multiple similar components.
[0014] FIG. 1a shows a data processing circuit including a
combination data decoder system including a combination of a low
density parity check decoder circuit and a simplified maximum
likelihood decode value modification circuit in accordance with one
or more embodiments of the present invention;
[0015] FIG. 1b shows a portion of a decoder algorithm graph having
M variable nodes (v.sub.i) connected to a check node where the
checksum is unsatisfied via a M edges 134 that each have an edge
value;
[0016] FIG. 1c depicts a controller circuit that may be used in
relation to the decoder system of FIG. 1 in accordance with various
embodiments of the present invention;
[0017] FIG. 1d depicts a simplified maximum likelihood decode value
modification circuit that may be used in relation to the decoder
system of FIG. 1 in accordance with various embodiments of the
present invention;
[0018] FIG. 2a is a flow diagram showing method for simplified
maximum likelihood value modification data decoding in accordance
with various embodiments of the present invention;
[0019] FIG. 2b is a flow diagram showing a method for utilizing the
method of FIG. 2a in relation to a non-binary data decode process
in accordance with some embodiments of the present invention;
[0020] FIG. 3 shows a storage device including simplified maximum
likelihood decode value modification circuitry in accordance with
one or more embodiments of the present invention; and
[0021] FIG. 4 shows a data transmission system including simplified
maximum likelihood decode value modification circuitry in
accordance with various embodiments of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0022] The present inventions are related to systems and methods
for data processing, and more particularly to systems and methods
for data decoding.
[0023] Various embodiments of the present invention provide data
processing systems that include a data decoder circuit having a low
density parity check decoder circuit and a simplified maximum
likelihood decode value modification circuit that is selectively
used to modify an output of the low density parity check decoder
circuit when a possible trapping set is detected. As just one of
many advantages, the aforementioned approach allows for using data
decoder circuits that exhibit relatively low complexity such as,
for example, a belief propagation decoder circuit, while using
another decoder algorithm to correct errors that are not
correctable by the low complexity decoder algorithm. As the errors
to be corrected are localized by the belief propagation decoder
circuit, the complexity of the other decoder circuit may be very
low.
[0024] In some cases, selective modification of an output of the
low density parity check decoder circuit is done based upon some
conclusions about a subset of uncorrectable errors. In particular,
it has been determined that: every unsatisfied checks is connected
by one error symbol, the error symbol has the most significant
ambiguity among all variable nodes associated with an unsatisfied
checks, and the second most likely symbol associated with the error
symbol is almost always the correct symbol. Based upon this, some
embodiments of the present invention identify uncorrectable errors
that seem to correspond to the above criteria, and modify the error
symbol to use the second most likely value. In some cases, the
uncorrectable error condition is referred to as a potential
trapping set condition.
[0025] Turning to FIG. 1a, a data processing circuit 100 is shown
that includes a data decoding circuit 170 including a combination
of a low complexity decoder circuit 166 and a simplified maximum
likelihood decode value modification circuit 168 in accordance with
one or more embodiments of the present invention. Data processing
circuit 100 includes an analog front end circuit 110 that receives
an analog signal 105. Analog front end circuit 110 processes analog
signal 105 and provides a processed analog signal 112 to an analog
to digital converter circuit 114. Analog front end circuit 110 may
include, but is not limited to, an analog filter and an amplifier
circuit as are known in the art. Based upon the disclosure provided
herein, one of ordinary skill in the art will recognize a variety
of circuitry that may be included as part of analog front end
circuit 110. In some cases, analog signal 105 is derived from a
read/write head assembly (not shown) that is disposed in relation
to a storage medium (not shown). In other cases, analog signal 105
is derived from a receiver circuit (not shown) that is operable to
receive a signal from a transmission medium (not shown). The
transmission medium may be wired or wireless. Based upon the
disclosure provided herein, one of ordinary skill in the art will
recognize a variety of source from which analog input 105 may be
derived.
[0026] Analog to digital converter circuit 114 converts processed
analog signal 112 into a corresponding series of digital samples
116. Analog to digital converter circuit 114 may be any circuit
known in the art that is capable of producing digital samples
corresponding to an analog input signal. Based upon the disclosure
provided herein, one of ordinary skill in the art will recognize a
variety of analog to digital converter circuits that may be used in
relation to different embodiments of the present invention. Digital
samples 116 are provided to an equalizer circuit 120. Equalizer
circuit 120 applies an equalization algorithm to digital samples
116 to yield an equalized output 125. In some embodiments of the
present invention, equalizer circuit 120 is a digital finite
impulse response filter circuit as are known in the art. In some
cases, equalizer 120 includes sufficient memory to maintain one or
more codewords until a data detector circuit 130 is available for
processing, and for multiple processes through data detector
circuit 130.
[0027] Data detector circuit 130 is operable to apply a data
detection algorithm to a received codeword or data set, and in some
cases data detector circuit 130 can process two or more codewords
in parallel. In some embodiments of the present invention, data
detector circuit 130 is a Viterbi algorithm data detector circuit
as are known in the art. In other embodiments of the present
invention, data detector circuit 130 is a maximum a posteriori data
detector circuit as are known in the art. Of note, the general
phrases "Viterbi data detection algorithm" or "Viterbi algorithm
data detector circuit" are used in their broadest sense to mean any
Viterbi detection algorithm or Viterbi algorithm detector circuit
or variations thereof including, but not limited to, bi-direction
Viterbi detection algorithm or bi-direction Viterbi algorithm
detector circuit. Also, the general phrases "maximum a posteriori
data detection algorithm" or "maximum a posteriori data detector
circuit" are used in their broadest sense to mean any maximum a
posteriori detection algorithm or detector circuit or variations
thereof including, but not limited to, simplified maximum a
posteriori data detection algorithm and a max-log maximum a
posteriori data detection algorithm, or corresponding detector
circuits. Based upon the disclosure provided herein, one of
ordinary skill in the art will recognize a variety of data detector
circuits that may be used in relation to different embodiments of
the present invention. Data detector circuit 130 is started based
upon availability of a data set from equalizer circuit 120 or from
a central memory circuit 150.
[0028] Upon completion, data detector circuit 130 provides a
detector output 196. Detector output 196 includes soft data. As
used herein, the phrase "soft data" is used in its broadest sense
to mean reliability data with each instance of the reliability data
indicating a likelihood that a corresponding bit position or group
of bit positions has been correctly detected. In some embodiments
of the present invention, the soft data or reliability data is log
likelihood ratio data as is known in the art. Detected output 196
is provided to a local interleaver circuit 142. Local interleaver
circuit 142 is operable to shuffle sub-portions (i.e., local
chunks) of the data set included as detected output and provides an
interleaved codeword 146 that is stored to central memory circuit
150. Interleaver circuit 142 may be any circuit known in the art
that is capable of shuffling data sets to yield a re-arranged data
set. Interleaved codeword 146 is stored to central memory circuit
150. Interleaved codeword 146 is comprised of a number of encoded
sub-codewords designed to reduce the complexity of a downstream
data decoder circuit while maintaining reasonable processing
ability.
[0029] Once a data decoding circuit 170 is available, a previously
stored interleaved codeword 146 is accessed from central memory
circuit 150 as a stored codeword 186 and globally interleaved by a
global interleaver/de-interleaver circuit 184. Global
interleaver/De-interleaver circuit 184 may be any circuit known in
the art that is capable of globally rearranging codewords. Global
interleaver/De-interleaver circuit 184 provides a decoder input 152
input to low data decoding circuit 170.
[0030] Data decoding circuit 170 includes low density parity check
decoder circuit 166, simplified maximum likelihood decode value
modification circuit 168, and a controller circuit 175. Low density
parity check decoder circuit 166 may be any decoder circuit known
in the art that is less complex to implement than a maximum
likelihood decoder circuit. In some embodiments of the present
invention, low density parity check decoder circuit 166 is a belief
propagation data decoder circuit as are known in the art. Such a
belief propagation data decoder circuit may be implemented similar
to that discussed in Pearl, Judea, "REVEREND BAYES ON INFERENCE
ENGINES: A DISTRIBUTED HIERARCHAL APPROACH", AAAI-82 Proceedings,
1982. The entirety of the aforementioned reference is incorporated
herein by reference for all purposes. Low density parity check
decoder circuit 166 receives decoder input 152 and applies a
decoder algorithm thereto to yield a decoder output 167. In
addition, checksum indices 169 (i.e., an identification of a
particular parity check equation) of any unsatisfied parity checks
are generated. Decoder output 167 and checksum indices 169 are
provided to controller circuit 175. In addition, decoder output 167
is fed back to low complexity decoder circuit 166 where it can be
used to guide subsequent application of the decoder algorithm to
decoder input 152.
[0031] Controller circuit 175 utilizes decoder output 167 and
checksum indices 169 to determine if a potential trapping set
condition has occurred. Where a potential trapping set condition
has occurred, a log likelihood ratio (LLR) subset output 177 (a
portion of decoder output 167) and corresponding index outputs 176
(i.e., a portion of checksum indices 169 corresponding to LLR
subset output 177) are provided by controller circuit 175 to
simplified maximum likelihood decode value modification circuit
168. Simplified maximum likelihood decode value modification
circuit 168 determines which symbols are associated with an
unsatisfied check. Each unsatisfied check is indicated by index
outputs 176. A total syndrome (s) is calculated for each of the
unsatisfied checks in accordance with the following equation:
s = i = 0 M v i .times. e i , ##EQU00002##
where v.sub.i corresponds to hard decision values of the variable
nodes feeding a check node associated with the unsatisfied check, M
is the number of variable nodes corresponding to the check node,
and e.sub.i corresponds to the edge values connecting the variable
nodes to the check node. FIG. 1b shows a portion of a decoder
algorithm graph 131 showing M variable nodes (v.sub.i) 132
connected to a check node 133 where the checksum is unsatisfied via
a M edges 134 that each have an edge value.
[0032] Simplified maximum likelihood decode value modification
circuit 168 calculates an array of possible hard decision values
across the contributors to the unsatisfied check in accordance with
the following equation:
HD'.sub.i,j=(j.times.e.sub.i.sup.-1)-HD.sub.i, for i .di-elect
cons. {1, 2, . . . M}, j .di-elect cons. {1, 2, 3},
where j represents the contribution from the previously calculated
total syndrome, HD.sub.i represents the most likely hard decision
for the particular instance i, and e.sub.i.sup.-1 corresponds to
the inverse edge value for the particular instance i. In this case,
j is a value of 1 to 3 as the decoder is a non-binary decoder using
two bit symbols with three non-zero LLR values for each symbol.
Where a binary decoder is being used, j .di-elect cons. {1}. Where
three bit symbols are used, j .di-elect cons. {1, 2, 3, 4, 5, 6,
7}. Thus, while the rest of this embodiment is discussed in
relation to a two-bit symbol situation, one of ordinary skill in
the art will recognize a variety of other binary and non-binary
decoders to which the inventions may be applied.
[0033] Using the aforementioned array, simplified maximum
likelihood decode value modification circuit 168 determines the
most likely candidate from the array for modification. The most
likely candidate is selected as the instance i in each row of the
array (i.e., j .di-elect cons. {1, 2, 3}) that has the lowest LLR
value. This determination may be done in accordance with the
following equation:
i*.sub.j=arg min.sub.i(LLR.sub.HD.sub.i .sub.XOR HD'.sub.i,j), for
j .di-elect cons. {1, 2, 3}.
This determination results in three index values i.sub.1, i.sub.2,
i.sub.3 where j .di-elect cons. {1, 2, 3}. Again, where a different
number of bits per symbol are being used, the number of index
values will be correspondingly different.
[0034] The LLR values associated with the index value i*.sub.j are
used by simplified maximum likelihood decode value modification
circuit 168 whether one or two LLR values are to be modified. In
particular, simplified maximum likelihood decode value modification
circuit 168 determines whether modifying one LLR value associated
with the symbol indicated by index value i*.sub.j results in a
greater change than modifying two LLR values associated with the
symbol indicated by index value i*.sub.j. The determination may be
made based upon the following comparison:
LLR HD i XORHD i , s ' .gtoreq. j = 1 3 LLR HD i XORHD i , j ' -
LLR HD i XORHD i , s ' ##EQU00003##
Where the comparison indicates that modifying a single LLR value
yields a greater change than modifying two LLR values of the symbol
indicated by index value i*.sub.j, the following symbol
modification is performed:
HD.sub.i*.sub.s=HD.sub.i*.sub.j.
Otherwise, where the comparison indicates that modifying a single
LLR value does not yield a greater change than modifying two LLR
values of the symbol indicated by index value i*.sub.j, the
following symbol modifications are:
HD.sub.i*.sub.j=HD.sub.i*.sub.j, for j.noteq.s.
The modified symbol (with one or two values modified) are provided
as a replacement symbol output 179 to LDPC decoder circuit 166 that
inserts the modified symbol into decoder output 167 prior to a
subsequent application of the data decoder algorithm to decoder
input 152.
[0035] In one particular embodiment of the present invention, a
potential trapping set condition is considered to have occurred
where the number of remaining unsatisfied checks after application
of the decoder algorithm to decoder input 152 is less than ten, and
the indexes corresponding to the remaining unsatisfied checks have
not changed for at least two local iterations (i.e., passes through
low complexity decoder circuit 166). In addition, in some cases,
controller circuit 175 is not enabled to indicate a potential
trapping set condition until at least four local iterations of
decoder algorithm to decoder input 152 have completed. Based upon
the disclosure provided herein, one of ordinary skill in the art
will recognize other indicia that may be used to define the
occurrence of a potential trapping set condition and/or to trigger
operation of partial maximum likelihood decoder circuit 168.
[0036] In addition, controller circuit 175 determines whether the
data decoding algorithm converged. Where the data decoding
algorithm failed to converge and no more local iterations
(iterations through low density parity check decoder circuit 166),
controller circuit 175 provides a decoder output 154 (i.e., decoder
output 167) back to central memory circuit 150 via global
interleaver/de-interleaver circuit 184. Prior to storage of decoded
output 154 to central memory circuit 150, decoded output 154 is
globally de-interleaved to yield a globally de-interleaved output
188 that is stored to central memory circuit 150. The global
de-interleaving reverses the global interleaving earlier applied to
stored codeword 186 to yield decoder input 152. Once data detector
circuit 130 is available, a previously stored de-interleaved output
188 is accessed from central memory circuit 150 and locally
de-interleaved by a de-interleaver circuit 144. De-interleaver
circuit 144 re-arranges decoder output 148 to reverse the shuffling
originally performed by interleaver circuit 142. A resulting
de-interleaved output 197 is provided to data detector circuit 130
where it is used to guide subsequent detection of a corresponding
data set receive as equalized output 125.
[0037] Alternatively, where the data decoding algorithm converged,
controller circuit 175 provides an output codeword 172 to a
de-interleaver circuit 180. De-interleaver circuit 180 rearranges
the data to reverse both the global and local interleaving applied
to the data to yield a de-interleaved output 182. De-interleaved
output 182 is provided to a hard decision output circuit 190. Hard
decision output circuit 190 is operable to re-order data sets that
may complete out of order back into their original order. The
originally ordered data sets are then provided as a hard decision
output 192.
[0038] An example of operation of controller circuit 175 is
provided in the following pseudo-code:
TABLE-US-00001 If (number of unsatisfied checks == 0) { provide
decoder output 167 as output codeword 172 } Else if (number of
unsatisfied checks > 0 && number of local iterations ==
maximum) { provide decoder output 167 as decoded output 154 } Else
if (number of unsatisfied checks > 0 && [number of
unsatisfied checks >= M OR number of local iterations is < N
OR indexes 169 change from one local iteration to the next]) {
provide decoder output 167 as an input to low complexity decoder
circuit 166 } Else if (number of unsatisfied checks > 0
&& [number of unsatisfied checks < M AND number of local
iterations is >= N OR indexes 169 do not change from one local
iteration to the next]) { provide LLR subset output 177 to partial
maximum likelihood decoder circuit 168 }
[0039] Turning to FIG. 1c, a controller circuit 101 that may be
used in place of controller circuit 175 of FIG. 1 in accordance
with various embodiments of the present invention. Controller
circuit 101 includes an LLR subset register 102 that stores each
element of decoder output 167 that corresponds to a non-zero value
of a checksum identified as one of checksum indices 169. An LLR
subset register output 103 is provided by LLR subset register 102.
In addition, controller circuit 101 includes an unsatisfied check
index register 106 that stores each index for which one or more
instances of decoder output 167 stored to LLR subset register 102.
Controller circuit 101 also includes a codeword completion circuit
113 that counts decoder outputs 167 to determine whether all
instances of a codeword have been received. Where a completed
codeword is received, a codeword complete output 117 is asserted
high.
[0040] An unsatisfied check counter circuit 127 counts the number
of non-zero parity check equation results (i.e., unsatisfied
checks) indicated by checksum indices to yield an unsatisfied check
count value 128. Unsatisfied check counter circuit 127 is reset
whenever codeword complete output 117 is asserted such that a
completed codeword is indicated. Hence, unsatisfied check count
value 128 indicates the number of unsatisfied checks that occur for
a given codeword. A count output equals zero circuit 131 indicates
whether unsatisfied check count value 128 is equal to zero. Where
unsatisfied check count value 128 is determined to be equal to
zero, count output equals zero circuit 131 asserts a zero count
output 133. Where zero count output 133 is asserted indicating that
unsatisfied check count value 128 is zero, an output codeword
generator circuit 134 provides decoder output 167 as output
codeword 172.
[0041] In addition, a count output less than M circuit 129
determines whether unsatisfied check count value 128 is greater
than zero and less than a value M. In some cases, M is ten. Based
upon the disclosure provided herein, one of ordinary skill in the
art will recognize other values of M that may be used in relation
to different embodiments of the present invention. Where count
output less than M circuit 129 determines that the value of
unsatisfied check count value 128 is greater than zero and less
than M, count output less than M circuit 129 asserts an M count
output 132.
[0042] A local iteration counter circuit 118 receives codeword
complete output 117 and counts the number of local iterations that
have been applied to the particular codeword (received as decoder
output 167). The number of local iterations is provided as a local
iteration count value 119. A count output greater than N circuit
receives local iteration count value 119 and asserts a count value
greater than N output 126 whenever local iteration count value 119
is greater than N. In some cases, N is three. Based upon the
disclosure provided herein, one of ordinary skill in the art will
recognize other values of N that may be used in relation to
different embodiments of the present invention. A count output
equals maximum local iterations circuit 121 receives local
iteration count value 119 and asserts a count value equals maximum
local iterations output 122 whenever local iteration count value
119 equals the defined maximum number of local iterations. is
greater than N. In some cases, N is three. Based upon the
disclosure provided herein, one of ordinary skill in the art will
recognize other values of N that may be used in relation to
different embodiments of the present invention. Where M count
output 132 indicates that the number of unsatisfied checks is not
zero and count value equals maximum local iterations output 122
indicates the maximum number of local iterations have been
performed, a decoded output generator circuit 123 provides a
derivative of decoder output 167 as decoded output 154.
[0043] An index buffer 108 receives index values 107 from
unsatisfied check index register 106 and stores them upon
completion of a codeword (e.g., codeword complete output 117 is
asserted). Index values 109 from index buffer 108 are compared with
index values 107 by a same indexes circuit 111 to determine whether
there has been a change over the last two local iterations to
determine if the same parity check equations remain unsatisfied.
Where the same parity check equations remain unsatisfied, same
indexes circuit 111 asserts an unchanged output 112. In addition,
index values 107 are provided as an index output 176. LLR subset
output generator circuit 104 provides LLR subset register output
103 as LLR subset output 177 whenever same indexes output 112 is
asserted, count value greater than N output 126 is asserted, and M
count output 132 are all asserted.
[0044] Turning to FIG. 1d, a simplified maximum likelihood decode
value modification circuit 800 is shown that may be used in
relation to the decoder system of FIG. 1 in accordance with various
embodiments of the present invention. Simplified maximum likelihood
decode value modification circuit 800 includes a syndrome
calculation circuit 810 that receives log likelihood ratio output
177 and index output 176, and based thereon determines which
symbols are associated with a given unsatisfied check, and
calculates a total syndrome for each of the unsatisfied checks in
accordance with the following equation:
s = i = 0 M v i .times. e i , ##EQU00004##
where v.sub.i corresponds to hard decision values of the variable
nodes feeding a check node associated with the unsatisfied check, M
is the number of variable nodes corresponding to the check node,
and e.sub.i corresponds to the edge values connecting the variable
nodes to the check node. Referring to FIG. 1b, a portion of a
decoder algorithm graph 131 showing M variable nodes (v.sub.i) 132
connected to a check node 133 where the checksum is unsatisfied via
a M edges 134 that each have an edge value. Syndrome calculation
circuit 810 provides a syndrome output 812.
[0045] In addition, simplified maximum likelihood decode value
modification circuit 800 includes an unsatisfied check array
calculator circuit 820 that receives log likelihood ratio output
177 and index output 176, and based thereon determines which
symbols are associated with a given unsatisfied check and
calculates an calculates an array of possible hard decision values
across the contributors to the unsatisfied check in accordance with
the following equation:
HD'.sub.i,j=(j.times.e.sub.i.sup..times.1)-HD.sub.i, for i
.di-elect cons. {1, 2, . . . M}, j .di-elect cons. {1, 2, 3},
where j represents the contribution from the previously calculated
total syndrome, HD.sub.i represents the most likely hard decision
for the particular instance i, and e.sub.i.sup.-1 corresponds to
the inverse edge value for the particular instance i. In this case,
j is a value of 1 to 3 as the decoder is a non-binary decoder using
two bit symbols with three non-zero LLR values for each symbol.
Where a binary decoder is being used, j .di-elect cons. {1}. Where
three bit symbols are used, j .di-elect cons. {1, 2, 3,4, 5, 6, 7}.
Thus, while the rest of this embodiment is discussed in relation to
a two-bit symbol situation, one of ordinary skill in the art will
recognize a variety of other binary and non-binary decoders to
which the inventions may be applied. Unsatisfied check array
calculator circuit 820 provides the calculated array as a vector
output 822 to an index identifier circuit 832.
[0046] Index identifier circuit 830 uses vector output 822
representing the array of possible hard decision values to
determine the most likely candidate from the array for
modification. The most likely candidate is selected as the instance
i in each row of the array (i.e., j .di-elect cons. {1, 2, 3}) that
has the lowest LLR value. This determination may be done in
accordance with the following equation:
i*.sub.j=arg min.sub.i(LLR.sub.HD.sub.i .sub.XOR HD'.sub.i,j), for
j .di-elect cons. {1, 2, 3}.
This determination results in three index values i.sub.1, i.sub.2,
i.sub.3 where j .di-elect cons. {1, 2, 3}. Again, where a different
number of bits per symbol are being used, the number of index
values will be correspondingly different. This identified set of
index values is provided as an index output 832 to a likely symbol
value selector and modification circuit 830.
[0047] Likely symbol value selector and modification circuit 830
uses the LLR values indicated by index output to determine whether
one or two LLR values are to be modified. In particular, likely
symbol value selector and modification circuit 830 determines
whether modifying one LLR value associated with the symbol
indicated by index value i*.sub.j results in a greater change than
modifying two LLR values associated with the symbol indicated by
index value i*.sub.j. The determination may be made based upon the
following comparison:
LLR HD i XORHD i , s ' .gtoreq. j = 1 3 LLR HD i XORHD i , j ' -
LLR HD i XORHD i , s ' ##EQU00005##
Where the comparison indicates that modifying a single LLR value
yields a greater change than modifying two LLR values of the symbol
indicated by index value i*.sub.j, the following symbol
modification is performed:
HD.sub.i*.sub.s=HD.sub.i*.sub.j,
Otherwise, where the comparison indicates that modifying a single
LLR value does not yield a greater change than modifying two LLR
values of the symbol indicated by index value i*.sub.j, the
following symbol modifications are:
HD.sub.i*.sub.j=HD.sub.i*.sub.j.sub.,j, for j.noteq.s.
The modified symbol (with one or two values modified) are provided
as a replacement symbol output 179.
[0048] Turning to FIG. 2a, a flow diagram 200 shows a method for
selectively combined data decoding in accordance with various
embodiments of the present invention. Following flow diagram 200,
an analog input is received (block 205). The analog input may be
derived from, for example, a storage medium or a data transmission
channel. Based upon the disclosure provided herein, one of ordinary
skill in the art will recognize a variety of sources of the analog
input. The analog input is converted to a series of digital samples
(block 210). This conversion may be done using an analog to digital
converter circuit or system as are known in the art. Of note, any
circuit known in the art that is capable of converting an analog
signal into a series of digital values representing the received
analog signal may be used. The resulting digital samples are
equalized to yield an equalized output (block 215). In some
embodiments of the present invention, the equalization is done
using a digital finite impulse response circuit as are known in the
art. Based upon the disclosure provided herein, one of ordinary
skill in the art will recognize a variety of equalizer circuits
that may be used in place of such a digital finite impulse response
circuit to perform equalization in accordance with different
embodiments of the present invention.
[0049] It is determined whether a data detector circuit is
available (block 220). Where a data detector circuit is available
(block 220), a data detection algorithm is applied to the equalized
output guided by a data set derived from a decoded output where
available (e.g., the second and later iterations through the data
detector circuit and the data decoder circuit) from a central
memory circuit to yield a detected output (block 225). In some
embodiments of the present invention, data detection algorithm is a
Viterbi algorithm as are known in the art. In other embodiments of
the present invention, the data detection algorithm is a maximum a
posteriori data detector circuit as are known in the art. The data
set derived from the decoded output maybe a de-interleaved version
of the decoded data set. A signal derived from the detected output
(e.g., a locally interleaved version of the detected output) is
stored to the central memory to await processing by a data decoder
circuit (block 230).
[0050] In parallel to the previously discussed data detection
processing, it is determined whether a data decoder circuit is
available (block 240). Where the data decoder circuit is available
(block 240), a previously stored derivative of a detected output is
accessed from the central memory (block 245). A low density parity
check decode algorithm is applied to the derivative of the detected
output to yield a decoded output (block 250). In some embodiments
of the present invention, low density parity check decoder circuit
166 is a belief propagation data decoder circuit as are known in
the art. Such a belief propagation data decoder circuit may be
implemented similar to that discussed in Pearl, Judea, "REVEREND
BAYES ON INFERENCE ENGINES: A DISTRIBUTED HIERARCHAL APPROACH",
AAAI-82 Proceedings, 1982. It should be noted that other
embodiments of the present may use different decode algorithms.
[0051] It is determined whether the decoded output converged (i.e.,
the original data set is recovered) (block 255). In some cases,
such convergence is found where all of the checksum equations
utilized as part of the low complexity decode algorithm are correct
(i.e., there are no unsatisfied checks). Where the decode algorithm
converged (block 255), the decoded output is provided as a hard
decision output (block 260). Otherwise, where the decode algorithm
failed to converge (block 255), it is determined whether the number
of local iterations of the data decode algorithm on the current
data set exceeded a threshold value N (block 265). In some cases, N
is four. Based upon the disclosure provided herein, one of ordinary
skill in the art will recognize other values of N that may be used
in relation to different embodiments of the present invention.
Where the number of local iterations has not exceeded the threshold
value N (block 265), the processes of blocks 250-265 are repeated
for the same data set using the previous decoded output as a
guide.
[0052] Otherwise, where the number of local iterations has exceeded
the threshold value N (block 265), it is determined whether another
local iteration is to be performed (block 270). In some cases, this
is determined by comparing the number of local iterations that have
been completed to a defined threshold number. Where another local
iteration is not called for (e.g., the number of local iterations
equals a maximum number of local iterations) (block 270), the
decoded output is stored to the central memory circuit where it
awaits processing by the data detector circuit (i.e., another
global iteration) (block 275). Otherwise, where it is determined
that another local iteration is called for (e.g., the number of
local iterations is not equal to a maximum number of local
iterations) (block 270), it is determined whether the number of
remaining unsatisfied checks is less than a threshold value M
(block 280). In some cases, M is ten. Based upon the disclosure
provided herein, one of ordinary skill in the art will recognize
other values of M that may be used in relation to different
embodiments of the present invention. Where the number of
unsatisfied checks is not less than the threshold value M (block
280), the processes of blocks 250-280 are repeated for the same
data set using the previous decoded output as a guide.
[0053] Otherwise, where the number of unsatisfied checks is less
than the threshold value M (block 280), a symbol modification is
performed (block 292). Symbol modification (block 292) includes
identifying the most likely symbol corresponding to each
unsatisfied check for modification (block 285). It is the
determined whether one or two LLR values associated with each of
the identified symbols are to be modified (block 290). The
determine LLR values are then modified (block 295). The modified
decoded output is then used to guide re-application of the low
density parity check decoding algorithm to the derivative of the
detected output (block 250), and the processes of blocks 255-292
are repeated.
[0054] Turning to FIG. 2b, a flow diagram 299 shows a method for
performing the function of block 292 of FIG. 2a in relation to a
non-binary data decode process in accordance with some embodiments
of the present invention. In this example, each symbol is two bits
representing four potential symbol values (i.e., `00`, `01`, `10`,
`11). Following flow diagram 299, a first unsatisfied check is
selected (block 272). In some cases, such an unsatisfied check is a
parity check equation that did not yield a zero output after
application of the data decode algorithm. Each unsatisfied check
has a number of symbol values from which the unsatisfied check is
calculated. A syndrome for all of the values associated with the
selected unsatisfied check is calculated (block 274). In some
cases, the syndrome is calculated in accordance with the following
equation:
s = i = 0 M v i .times. e i , ##EQU00006##
where v.sub.i corresponds to hard decision values of the variable
nodes feeding a check node associated with the unsatisfied check, M
is the number of variable nodes corresponding to the check node,
and e.sub.i corresponds to the edge values connecting the variable
nodes to the check node. Referring to FIG. 1b, a portion of a
decoder algorithm graph 131 showing M variable nodes (v.sub.i) 132
connected to a check node 133 where the checksum is unsatisfied via
a M edges 134 that each have an edge value. Syndrome calculation
circuit 810 provides a syndrome output 812.
[0055] An array of possible hard decision values are calculated
across the contributors to the unsatisfied check in accordance with
the following equation:
HD'.sub.i,j=(j.times.e.sub.i.sup.-1)-HD.sub.i, for i .di-elect
cons. {1, 2, . . . M}, j .di-elect cons. {1, 2, 3},
where j represents the contribution from the previously calculated
total syndrome, HD, represents the most likely hard decision for
the particular instance i, and e.sub.i.sup.-1 corresponds to the
inverse edge value for the particular instance i. In this case, j
is a value of 1 to 3 as the decoder is a non-binary decoder using
two bit symbols with three non-zero LLR values for each symbol.
Where a binary decoder is being used, j .di-elect cons. {1}. Where
three bit symbols are used, j .di-elect cons. {1, 2, 3,4, 5, 6, 7}.
Thus, while the rest of this embodiment is discussed in relation to
a two-bit symbol situation, one of ordinary skill in the art will
recognize a variety of other binary and non-binary decoders to
which the inventions may be applied.
[0056] An index identifying the most likely candidate from the
aforementioned array is selected (block 278). The most likely
candidate is selected as the instance i in each row of the array
(i.e., j .di-elect cons. {1, 2, 3}) that has the lowest LLR value.
The index may be calculated in accordance with the following
equation:
i*.sub.j=arg min.sub.i (LLR.sub.HD.sub.i .sub.XOR HD'.sub.i,j), for
j .di-elect cons. {1, 2, 3}.
This determination results in three index values i.sub.1, i.sub.2,
i.sub.3 where j .di-elect cons. {1, 2, 3}. Again, where a different
number of bits per symbol are being used, the number of index
values will be correspondingly different.
[0057] It is then determined whether one or two LLR values of the
symbol identified by the aforementioned index are to be modified
(block 282). In particular, it is determined whether modifying one
LLR value associated with the symbol indicated by index value
i*.sub.j results in a greater change than modifying two LLR values
associated with the symbol indicated by index value i*.sub.j. The
determination may be made based upon the following comparison:
LLR HD i XORHD i , s ' .gtoreq. j = 1 3 LLR HD i XORHD i , j ' -
LLR HD i XORHD i , s ' ##EQU00007##
[0058] Where the comparison indicates that modifying a single LLR
value yields a greater change than modifying two LLR values of the
symbol indicated by index value i*.sub.j (block 282), then one LLR
value of the symbol identified by the index is modified (block
284). The modification may be made in accordance with the following
equation:
HD.sub.i*.sub.s=HD.sub.i*.sub.j.
Otherwise, where the comparison indicates that modifying a single
LLR value does not yield a greater change than modifying two LLR
values of the symbol indicated by index value i*.sub.j (block 282),
then two LLR values of the symbol identified by the index are
modified (block 286). The modification may be made in accordance
with the following equation:
HD.sub.i*.sub.j=HD.sub.i*.sub.j.sub.,j, for j.noteq.s.
[0059] It is then determined whether another unsatisfied check
remains (block 288). Where another unsatisfied check remains (block
288), the next unsatisfied check is selected (block 2294), and the
processes of blocks 272-288 are repeated to further modify the
decoded output. Alternatively, where no additional unsatisfied
checks remain (block 288), the process is returned to that
discussed in relation to FIG. 2a where the modified decoded output
is used to guide re-application of the low density parity check
decoding algorithm to the derivative of the detected output (block
250).
[0060] Turning to FIG. 3, a storage device 300 is shown including
simplified maximum likelihood value modification circuitry in
accordance with one or more embodiments of the present invention.
Storage device 300 may be, for example, a hard disk drive. Storage
device 300 also includes a preamplifier 370, an interface
controller 320, a hard disk controller 366, a motor controller 368,
a spindle motor 372, a disk platter 378, and a read/write head
assembly 376. Interface controller 320 controls addressing and
timing of data to/from disk platter 378. The data on disk platter
378 consists of groups of magnetic signals that may be detected by
read/write head assembly 376 when the assembly is properly
positioned over disk platter 378. In one embodiment, disk platter
378 includes magnetic signals recorded in accordance with either a
longitudinal or a perpendicular recording scheme.
[0061] In a typical read operation, read/write head assembly 376 is
accurately positioned by motor controller 368 over a desired data
track on disk platter 378. Motor controller 368 both positions
read/write head assembly 376 in relation to disk platter 378 and
drives spindle motor 372 by moving read/write head assembly to the
proper data track on disk platter 378 under the direction of hard
disk controller 366. Spindle motor 372 spins disk platter 378 at a
determined spin rate (RPMs). Once read/write head assembly 378 is
positioned adjacent the proper data track, magnetic signals
representing data on disk platter 378 are sensed by read/write head
assembly 376 as disk platter 378 is rotated by spindle motor 372.
The sensed magnetic signals are provided as a continuous, minute
analog signal representative of the magnetic data on disk platter
378. This minute analog signal is transferred from read/write head
assembly 376 to read channel circuit 310 via preamplifier 370.
Preamplifier 370 is operable to amplify the minute analog signals
accessed from disk platter 378. In turn, read channel circuit 310
decodes and digitizes the received analog signal to recreate the
information originally written to disk platter 378. This data is
provided as read data 303 to a receiving circuit. A write operation
is substantially the opposite of the preceding read operation with
write data 301 being provided to read channel circuit 310. This
data is then encoded and written to disk platter 378.
[0062] During operation, data decoding applied to the information
received from disk platter 378 may not converge. Where it is
determined that there is a possible trapping set or other
impediment to convergence, a simplified maximum likelihood value
modification circuit identifies a symbol associated with an
unsatisfied check that exhibits the most significant ambiguity.
This symbol is then modified and used to replace a corresponding
symbol in a previously generated decoded output prior to a
subsequent application of a data decode algorithm to a decoder
input. Such symbol modification circuitry may be implemented
similar to that discussed above in relation to FIGS. 1a-1d, and/or
may be done using a process similar to that discussed above in
relation to FIGS. 2a-2b.
[0063] It should be noted that storage system may utilize SATA, SAS
or other storage technologies known in the art. Also, it should be
noted that storage system 300 may be integrated into a larger
storage system such as, for example, a RAID (redundant array of
inexpensive disks or redundant array of independent disks) based
storage system. It should also be noted that various functions or
blocks of storage system 300 may be implemented in either software
or firmware, while other functions or blocks are implemented in
hardware.
[0064] Turning to FIG. 4, a data transmission system 400 including
simplified maximum likelihood value modification circuitry in
accordance with various embodiments of the present invention. Data
transmission system 400 includes a transmitter 410 that is operable
to transmit encoded information via a transfer medium 430 as is
known in the art. The encoded data is received from transfer medium
430 by receiver 420. Transceiver 420 incorporates data decoder
circuitry. While processing received data, received data is
converted from an analog signal to a series of corresponding
digital samples, and the digital samples are equalized to yield an
equalized output. The equalized output is then provided to a data
processing circuit including both a data detector circuit and a
data decoder circuit. Data is passed between the data decoder and
data detector circuit via a central memory allowing for variation
between the number of processing iterations that are applied to
different data sets. It should be noted that transfer medium 430
may be any transfer medium known in the art including, but not
limited to, a wireless medium, an optical medium, or a wired
medium. Based upon the disclosure provided herein, one of ordinary
skill in the art will recognize a variety of transfer mediums that
may be used in relation to different embodiments of the present
invention.
[0065] During operation, data decoding applied to the information
received via transfer medium 430 may not converge. Where it is
determined that there is a possible trapping set or other
impediment to convergence, a simplified maximum likelihood value
modification circuit identifies a symbol associated with an
unsatisfied check that exhibits the most significant ambiguity.
This symbol is then modified and used to replace a corresponding
symbol in a previously generated decoded output prior to a
subsequent application of a data decode algorithm to a decoder
input. Such symbol modification circuitry may be implemented
similar to that discussed above in relation to FIGS. 1a-1d, and/or
may be done using a process similar to that discussed above in
relation to FIGS. 2a-2b.
[0066] It should be noted that the various blocks discussed in the
above application may be implemented in integrated circuits along
with other functionality. Such integrated circuits may include all
of the functions of a given block, system or circuit, or only a
subset of the block, system or circuit. Further, elements of the
blocks, systems or circuits may be implemented across multiple
integrated circuits. Such integrated circuits may be any type of
integrated circuit known in the art including, but are not limited
to, a monolithic integrated circuit, a flip chip integrated
circuit, a multichip module integrated circuit, and/or a mixed
signal integrated circuit. It should also be noted that various
functions of the blocks, systems or circuits discussed herein may
be implemented in either software or firmware. In some such cases,
the entire system, block or circuit may be implemented using its
software or firmware equivalent. In other cases, the one part of a
given system, block or circuit may be implemented in software or
firmware, while other parts are implemented in hardware.
[0067] In conclusion, the invention provides novel systems,
devices, methods and arrangements for data processing. While
detailed descriptions of one or more embodiments of the invention
have been given above, various alternatives, modifications, and
equivalents will be apparent to those skilled in the art without
varying from the spirit of the invention. Therefore, the above
description should not be taken as limiting the scope of the
invention, which is defined by the appended claims.
* * * * *