U.S. patent application number 13/633429 was filed with the patent office on 2013-04-11 for measuring capacitance of a capacitive sensor with a microcontroller having an analog output for driving a guard ring.
This patent application is currently assigned to MICROCHIP TECHNOLOGY INCORPORATED. The applicant listed for this patent is MICROCHIP TECHNOLOGY INCORPORATED. Invention is credited to Keith Curtis, Burke Davison, Yann LeFaou, Zeke Lundstrum, Sean Steedman.
Application Number | 20130090873 13/633429 |
Document ID | / |
Family ID | 48042613 |
Filed Date | 2013-04-11 |
United States Patent
Application |
20130090873 |
Kind Code |
A1 |
Lundstrum; Zeke ; et
al. |
April 11, 2013 |
Measuring Capacitance of a Capacitive Sensor with a Microcontroller
Having an Analog Output for Driving a Guard Ring
Abstract
A microcontroller measures capacitance of capacitive sensors
having guard rings associated therewith. A guard ring is provided
around each capacitive sensor plate and is charged to substantially
the same voltage as a voltage on the associated capacitive sensor
plate. The guard ring reduces parasitic capacitances of the
capacitive sensor plate caused by differences in voltage potentials
between the capacitive sensor plate, and adjacent circuit
conductors, ground planes and power planes. An analog output is
buffered and coupled to an analog input coupled to the capacitive
sensor plate, and is used to drive the guard ring voltage to
substantially the same voltage as the voltage on the capacitive
sensor plate.
Inventors: |
Lundstrum; Zeke; (Chandler,
AZ) ; Curtis; Keith; (Gilbert, AZ) ; Davison;
Burke; (Chandler, AZ) ; Steedman; Sean;
(Phoenix, AZ) ; LeFaou; Yann; (Tempe, AZ) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
MICROCHIP TECHNOLOGY INCORPORATED; |
Chaandler |
AZ |
US |
|
|
Assignee: |
MICROCHIP TECHNOLOGY
INCORPORATED
Chandler
AZ
|
Family ID: |
48042613 |
Appl. No.: |
13/633429 |
Filed: |
October 2, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61544363 |
Oct 7, 2011 |
|
|
|
Current U.S.
Class: |
702/64 ; 341/155;
700/286 |
Current CPC
Class: |
H03K 2217/960765
20130101; H03K 2217/960705 20130101; H03K 17/9622 20130101; H03K
17/962 20130101 |
Class at
Publication: |
702/64 ; 700/286;
341/155 |
International
Class: |
G06F 19/00 20110101
G06F019/00; H03M 1/12 20060101 H03M001/12; G06F 1/26 20060101
G06F001/26 |
Claims
1. A microcontroller comprising: a digital processor with memory; a
plurality of external input/output nodes that can be programmed to
function as analog nodes, a multiplexer controlled by the digital
processor for selecting one of said analog nodes and coupling the
analog node to an analog bus; an analog-to-digital converter (ADC)
coupled with the analog bus for converting an analog voltage on the
analog bus to a digital representation thereof and having a digital
output coupled to the digital processor for conveying the digital
representation, and a further external node which can be connected
by means of a programmable switch controlled by the digital
processor to the analog bus independent from said multiplexer.
2. A microcontroller according to claim 1, further comprising: at
least one analog output driver; a sample and hold capacitor
associated with the ADC; a first analog node coupled to a first
analog bus in the microcontroller; a second analog node coupled to
a second analog bus in the microcontroller, the second analog bus
is also coupled to an input of the at least one analog output
driver; the first analog bus is switchably coupled to a power
supply common, a power supply voltage, the sample and hold
capacitor, or the second analog bus; the second analog bus is
switchably coupled to the power supply common, the power supply
voltage, or the first analog bus; the sample and hold capacitor is
switchably coupled to either the first analog bus or an input of
the ADC; and at least one third analog output node of the
microcontroller is coupled to a respective one of the at least one
analog output driver.
3. The microcontroller according to claim 2, wherein the second
analog node is adapted for coupling to a capacitive sensor.
4. The microcontroller according to claim 2, wherein the at least
one third analog output node is adapted for coupling to a guard
ring associated with the capacitive sensor, wherein a voltage on
the guard ring is substantially the same voltage as on the
capacitive sensor.
5. The microcontroller according to claim 2, wherein the first
analog node is adapted for coupling to an external capacitor.
6. The microcontroller according to claim 1, further comprising at
least one internal capacitor switchably coupled to the first analog
bus.
7. The microcontroller according to claim 2, further comprising a
plurality of switches, wherein: a first one of the plurality of
switches couples the first and second analog buses together when
closed, a second one of the plurality of switches couples the first
analog bus to a power supply common when closed, a third one of the
plurality of switches couples the second analog bus to a power
supply voltage when closed, a fourth one of the plurality of
switches couples the first analog bus to the power supply voltage
when closed, and a fifth one of the plurality of switches couples
the second analog bus to the power supply common when closed.
8. The microcontroller according to claim 7, wherein the digital
processor controls the plurality of switches.
9. The microcontroller according to claim 7, wherein the plurality
of switches are a plurality of field effect transistor (FET)
switches.
10. The microcontroller according to claim 1, further comprising: a
precision timer coupled to the digital processor; a plurality of
switches; a first node coupled to the plurality of switches, the
first node is also adapted for coupling to an external capacitive
sensor; a sample and hold circuit having a control input coupled to
the precision timer, an analog input coupled to the first node and
an analog output coupled to an input of the ADC; a constant current
source coupled to the plurality of switches; wherein the plurality
of switches are controlled by the precision timer for coupling the
first node to either a power supply common or the constant current
source; a second node; and an analog driver having an analog input
coupled to the first node and an analog output coupled to the
second node, whereby a voltage on the second node is substantially
the same as a voltage on the first node; wherein the second node is
adapted for coupling to an external guard ring associated with the
external capacitive sensor; wherein the first node is coupled to
the power supply common through the plurality of switches until a
start of a precision time period determined by the precision timer
then the first node is coupled to the constant current source,
whereby the external capacitive sensor is charged by the constant
current source until a stop of the precision time period determined
by the precision timer; after the stop of the precision timer
occurs a sample of a voltage charge on the external capacitive
sensor is taken by and stored in the sample and hold circuit; the
sampled and stored voltage charge is converted by the ADC to a
digital representation thereof; and the digital processor reads the
digital representation from the ADC and determines a capacitance
value of the external capacitive sensor from the precision time
period and the digital representation of the voltage charge.
11. The microcontroller according to claim 10, further comprising:
a constant current sink coupled to the plurality of switches;
wherein the first node is coupled to a power supply voltage through
the plurality of switches until a start of another precision time
period determined by the precision timer then the first node is
coupled to the constant current sink, whereby the external
capacitive sensor is discharged by the constant current sink until
another stop of the precision time period determined by the
precision timer; after the another stop of the precision timer
occurs a sample of another voltage charge on the external
capacitive sensor is taken by and stored in the sample and hold
circuit; the sampled and stored another voltage charge is converted
by the ADC to another digital representation thereof; and the
digital processor reads the another digital representation from the
ADC and determines a capacitance value of the external capacitive
sensor from the another precision time period and the another
digital representation of the another voltage charge.
12. The microcontroller according to claim 1, further comprising: a
variable frequency oscillator; a frequency measurement circuit
having an output coupled to the digital processor and an input
coupled to the variable frequency oscillator; a first node coupled
to the variable frequency oscillator, the first node is also
adapted for coupling to an external capacitive sensor; a second
node adapted for coupling to an external guard ring associated with
the external capacitive sensor; and an analog driver having an
analog input coupled to the first node and an analog output coupled
to the second node, whereby a voltage on the second node is
substantially the same as a voltage on the first node; wherein the
external capacitive sensor is part of a frequency determining
circuit of the variable frequency oscillator, whereby a frequency
of the variable frequency oscillator changes when a capacitance
value of the external capacitive sensor changes; wherein the
frequency measurement circuit measures and converts the frequency
of the variable frequency oscillator into a digital representation
thereof; and wherein the digital processor reads the digital
representation of the frequency and determines a capacitance value
of the external capacitive sensor.
13. A capacitive sensor system, said system comprising: a
capacitive sensor; a guard ring associated with the capacitive
sensor; a microcontroller, comprising: a digital processor with
memory; a plurality of external input/output nodes that can be
programmed to function as analog nodes, a multiplexer controlled by
the digital processor for selecting one of said analog nodes and
coupling the analog node to an analog bus; an analog-to-digital
converter (ADC) coupled with the analog bus for converting an
analog voltage on the analog bus to a digital representation
thereof and having a digital output coupled to the digital
processor for conveying the digital representation; a further
external node which can be connected by means of a programmable
switch controlled by the digital processor to the analog bus
independent from said multiplexer; a sample and hold capacitor
coupled to a plurality of switches; a first node coupled to the
plurality of switches; wherein a first one of the plurality of
switches couples the sample and hold capacitor to either an input
of the ADC or the first node; a second node coupled to the
plurality of switches and the capacitive sensor; a third node
coupled to the guard ring associated with the capacitive sensor;
and an analog driver having an analog input coupled to the second
node and an analog output coupled to the third node, whereby a
voltage on the third node is substantially the same as a voltage on
the second node; wherein a first one of the plurality of switches
couples the first and second nodes together when closed, a second
one of the plurality of switches couples the first node to a power
supply common when closed, a third one of the plurality of switches
couples the second node to a power supply voltage when closed, a
fourth one of the plurality of switches couples the first node to
the power supply voltage when closed, and a fifth one of the
plurality of switches couples the second node to the power supply
common when closed.
14. The capacitive sensor system according to claim 13, further
comprising a padding capacitor coupled to the first node, wherein a
combined capacitive value of the padding capacitor and the sample
and hold capacitor are approximately equal to the capacitive value
of the capacitive sensor.
15. The capacitive sensor system according to claim 13, wherein the
digital processor controls the plurality of switches.
16. A capacitive sensor system, said system comprising: a
capacitive sensor; a guard ring associated with the capacitive
sensor; a microcontroller, comprising: a digital processor with
memory; a precision timer coupled to the digital processor; an
analog-to-digital converter (ADC) having an output coupled to the
digital processor; a first node coupled to a plurality of switches
and the capacitive sensor; a sample and hold circuit having a
control input coupled to the precision timer, an analog input
coupled to the first node and an analog output coupled to an input
of the ADC; a constant current source coupled to the plurality of
switches; wherein the plurality of switches are controlled by the
precision timer for coupling the first node to either a power
supply common or the constant current source; a second node coupled
to the guard ring; and an analog driver having an analog input
coupled to the first node and an analog output coupled to the
second node, whereby a voltage on the second node is substantially
the same as a voltage on the first node; wherein the first node is
coupled to the power supply common through the plurality of
switches until a start of a precision time period determined by the
precision timer then the first node is coupled to the constant
current source, whereby the external capacitive sensor is charged
by the constant current source until a stop of the precision time
period determined by the precision timer; after the stop of the
precision timer occurs a sample of a voltage charge on the external
capacitive sensor is taken by and stored in the sample and hold
circuit; the sampled and stored voltage charge is converted by the
ADC to a digital representation thereof; and the digital processor
reads the digital representation from the ADC and determines a
capacitance value of the capacitive sensor from the precision time
period and the digital representation of the voltage charge.
17. A capacitive sensor system, said system comprising: a
capacitive sensor; a guard ring associated with the capacitive
sensor; a microcontroller, comprising: a digital processor with
memory; a variable frequency oscillator; a frequency measurement
circuit having an output coupled to the digital processor and an
input coupled to the variable frequency oscillator; a first node
coupled to the variable frequency oscillator and the external
capacitive sensor; a second node coupling to the guard ring; and an
analog driver having an analog input coupled to the first node and
an analog output coupled to the second node, whereby a voltage on
the second node is substantially the same as a voltage on the first
node; wherein the external capacitive sensor is part of a frequency
determining circuit of the variable frequency oscillator, whereby a
frequency of the variable frequency oscillator changes when a
capacitance value of the external capacitive sensor changes;
wherein the frequency measurement circuit measures and converts the
frequency of the variable frequency oscillator into a digital
representation thereof; and wherein the digital processor reads the
digital representation of the frequency and determines a
capacitance value of the external capacitive sensor.
18. A method for measuring capacitance of a capacitive sensor and
controlling a voltage on a guard ring associated with the
capacitive sensor, said method comprising the steps of: providing a
capacitive sensor; providing a guard ring associated with the
capacitive sensor; providing to the guard ring a voltage that is
substantially the same as a voltage on the capacitive sensor;
providing a microcontroller, comprising: a digital processor with
memory; an analog-to-digital converter (ADC) having an output
coupled to the digital processor; a sample and hold capacitor
coupled to a plurality of switches; a first node coupled to the
plurality of switches; wherein a first one of the plurality of
switches couples the sample and hold capacitor to either an input
of the ADC or the first node; a second node coupled to the
plurality of switches and the capacitive sensor; a third node
coupled to the guard ring associated with the capacitive sensor;
and an analog driver having an analog input coupled to the second
node and an analog output coupled to the third node, whereby a
voltage on the third node is substantially the same as a voltage on
the second node; coupling the sample and hold capacitor to the
first node; coupling the first node to a power supply voltage;
coupling the second node to a power supply common; coupling the
first and second nodes together long enough for a first charge to
settle therebetween; decoupling the sample and hold capacitor from
the first node; coupling the second node to the power supply
common; coupling the second node to the power supply voltage;
converting the settled first charge on the sample and hold
capacitor to a first digital representation thereof with the ADC;
reading the first digital representation from the ADC with the
digital processor; coupling the first node to the power supply
common; coupling the first and second nodes together long enough
for a second charge to settle therebetween; decoupling the sample
and hold capacitor from the first node; coupling the second node to
the power supply voltage; coupling the second node to the power
supply common; converting the settled second charge on the sample
and hold capacitor to a second digital representation thereof with
the ADC; and reading the second digital representation from the ADC
with the digital processor.
19. The method according to claim 18, further comprising the step
of processing the first and the second digital representations with
the digital processor to substantially reduce common mode
noise.
20. The method according to claim 18, further comprising the steps
of: storing the first and the second digital representations in a
memory associated with the digital processor; comparing the stored
first and second digital representations with subsequent first and
second digital representations, wherein if the stored first and
second digital representations are substantially the same as the
subsequent first and second digital representations then the
capacitive sensor is not actuated, and if the stored first and
second digital representations are not substantially the same as
the subsequent first and second digital representations then the
capacitive sensor is actuated.
21. A method for measuring capacitance of a capacitive sensor and
controlling a voltage on a guard ring associated with the
capacitive sensor, said method comprising the steps of: providing
to a guard ring associated with a capacitive sensor a voltage that
is substantially the same as a voltage on the capacitive sensor,
further comprising the steps of: a) charging a capacitive sensor to
a second voltage; b) charging a sample and hold capacitor to a
first voltage; c) coupling together the sample and hold capacitor
and the capacitive sensor long enough for a first charge to settle
therebetween; d) decoupling the sample and hold capacitor from the
capacitive sensor; e) converting the settled first charge on the
sample and hold capacitor to a first digital representation thereof
with an analog-to-digital converter (ADC); f) charging the
capacitive sensor to the second voltage; g) charging the capacitive
sensor to the first voltage; h) reading the first digital
representation of the first charge from the ADC with a digital
processor; i) coupling together the sample and hold capacitor and
the capacitive sensor long enough for a second charge to settle
therebetween; j) decoupling the sample and hold capacitor from the
capacitive sensor; k) converting the settled second charge on the
sample and hold capacitor to a second digital representation
thereof with the analog-to-digital converter (ADC); l) charging the
capacitive sensor to the first voltage; m) charging the capacitive
sensor to the second voltage; n) reading the second digital
representation of the second charge from the ADC with the digital
processor; and o) returning to step b).
22. The method according to claim 21, wherein the first voltage is
approximately a power supply voltage and the second voltage is
approximately a power supply common.
23. The method according to claim 21, wherein the first voltage is
approximately a power supply common and the second voltage is
approximately a power supply voltage.
24. The method according to claim 21, wherein a voltage on the
guard ring is substantially the same as a voltage on the capacitive
sensor.
25. A method for measuring capacitance of a capacitive sensor and
controlling a voltage on a guard ring associated with the
capacitive sensor, said method comprising the steps of: providing a
capacitive sensor; providing a guard ring associated with the
capacitive sensor; providing to the guard ring a voltage that is
substantially the same as a voltage on the capacitive sensor;
providing a mixed signal integrated circuit, comprising: a digital
processor with memory; a precision timer coupled to the digital
processor; an analog-to-digital converter (ADC) having an output
coupled to the digital processor; a first node coupled to a
plurality of switches and the capacitive sensor; a sample and hold
circuit having a control input coupled to the precision timer, an
analog input coupled to the first node and an analog output coupled
to an input of the ADC; a constant current source coupled to the
plurality of switches; wherein the plurality of switches are
controlled by the precision timer for coupling the first node to
either a power supply common or the constant current source; a
second node coupled to the guard ring; and an analog driver having
an analog input coupled to the first node and an analog output
coupled to the second node, whereby a voltage on the second node is
substantially the same as a voltage on the first node; coupling the
first node to the power supply common through the plurality of
switches until a start of a precision time period determined by the
precision timer; then coupling the first node to the constant
current source, whereby the external capacitive sensor is charged
by the constant current source until a stop of the precision time
period determined by the precision timer; sampling and storing
after the stop of the precision timer occurs a voltage charge on
the capacitive sensor with the sample and hold circuit; converting
the sampled and stored voltage charge to a digital representation
thereof; and reading the digital representation from the ADC with
the digital processor; and determining a capacitance value of the
capacitive sensor from the digital representation of the voltage
charge.
26. A method for measuring capacitance of a capacitive sensor and
controlling a voltage on a guard ring associated with the
capacitive sensor, said method comprising the steps of: providing a
capacitive sensor; providing a guard ring associated with the
capacitive sensor; and providing to the guard ring a voltage that
is substantially the same as a voltage on the capacitive sensor;
providing a microcontroller, comprising: a digital processor with
memory; a variable frequency oscillator; a frequency measurement
circuit having an output coupled to the digital processor and an
input coupled to the variable frequency oscillator; a first node
coupled to the variable frequency oscillator and the external
capacitive sensor; a second node coupling to the guard ring; and an
analog driver having an analog input coupled to the first node and
an analog output coupled to the second node, whereby a voltage on
the second node is substantially the same as a voltage on the first
node; measuring a frequency of the variable frequency oscillator
with the frequency determining circuit; providing a digital
representation of the measured frequency to the digital processor;
and determining a capacitance value of the capacitive sensor from
the digital representation of the frequency.
Description
RELATED PATENT APPLICATION
[0001] This application claims priority to commonly owned U.S.
Provisional Patent Application Ser. No. 61/544,363; filed Oct. 7,
2011; entitled "Microcontroller ADC with External Access to the
Analog Input Bus," by Zeke Lundstrum, Keith Curtis, Burke Davison,
Sean Steedman and Yann LeFaou; which is hereby incorporated by
reference herein for all purposes.
TECHNICAL FIELD
[0002] The present disclosure relates to analog-to-digital and
frequency converters in particular for use in a microcontroller
and, more particularly, for use by a microcontroller with
capacitive touch detection capabilities.
BACKGROUND
[0003] Touching of a capacitive sensor or approaching a capacitive
proximity sensor by an object, e.g., a piece of metal, a finger, a
hand, a foot, a leg, etc., changes certain parameters thereof, in
particular the capacitance value of a capacitor that is built into
the touch sensor used, for example, in human to machine interface
devices, e.g., keypad or keyboard. Microcontrollers now include
peripherals that enhance the detection and evaluation of such
capacitive sensors. One such application utilizes capacitive
voltage division (CVD) to evaluate whether a capacitive touch
element has been touched or not. Another application utilizes a
charge time measurement unit (CTMU) to charge a capacitive touch
element with a constant current source over a precise time, then
measuring a resulting voltage on the capacitive touch element at
the end of the precise time. Still another application is measuring
a change in frequency by a capacitive sensing module (CSM) that is
proportional to a change in the capacitance of the capacitive touch
element. However, when such sensors are operated in high noise
environments, the resolution or detection in conventional systems
may not suffice.
[0004] In particular parasitic capacitance may pose a problem in
many capacitive sensor applications. Parasitic capacitance is
generated whenever a conductor adjacent to the sensor (or its
connection to the microcontroller) is at a different voltage
potential then the sensor. Therefore it is preferable to reduce the
parasitic capacitance associated with capacitive sensors, assuming
that parasitic capacitance may decrease the sensitivity of a
capacitive sensor and thereby decrease the resolution of the
resulting capacitive conversion process, e.g., CVD, CTMU or
CSM.
SUMMARY
[0005] Therefore what is needed is an effective way to reduce
parasitic capacitance associated with a capacitive sensor, thereby
increasing its capacitive measurement change sensitivity during
operation thereof.
[0006] According to an embodiment, a microcontroller may comprise:
a digital processor with memory; a plurality of external
input/output nodes that can be programmed to function as analog
nodes, a multiplexer controlled by the digital processor for
selecting one of said analog nodes and coupling the analog node to
an analog bus; an analog-to-digital converter (ADC) coupled with
the analog bus for converting an analog voltage on the analog bus
to a digital representation thereof and having a digital output
coupled to the digital processor for conveying the digital
representation, and a further external node which can be connected
by means of a programmable switch controlled by the digital
processor to the analog bus independent from said multiplexer.
[0007] According to a further embodiment, the microcontroller may
comprise: at least one analog output driver; a sample and hold
capacitor associated with the ADC; a first analog node coupled to a
first analog bus in the microcontroller; a second analog node
coupled to a second analog bus in the microcontroller, the second
analog bus may also be coupled to an input of the at least one
analog output driver; the first analog bus may be switchably
coupled to a power supply common, a power supply voltage, the
sample and hold capacitor, or the second analog bus; the second
analog bus may be switchably coupled to the power supply common,
the power supply voltage, or the first analog bus; the sample and
hold capacitor may be switchably coupled to either the first analog
bus or an input of the ADC; and at least one third analog output
node of the microcontroller may be coupled to a respective one of
the at least one analog output driver.
[0008] According to a further embodiment, the second analog node
may be adapted for coupling to a capacitive sensor. According to a
further embodiment, the at least one third analog output node may
be adapted for coupling to a guard ring associated with the
capacitive sensor, wherein a voltage on the guard ring may be
substantially the same voltage as on the capacitive sensor.
According to a further embodiment, the first analog node may be
adapted for coupling to an external capacitor. According to a
further embodiment, at least one internal capacitor switchably may
be coupled to the first analog bus.
[0009] According to a further embodiment, the microcontroller may
comprise a plurality of switches, wherein: a first one of the
plurality of switches couples the first and second analog buses
together when closed, a second one of the plurality of switches
couples the first analog bus to a power supply common when closed,
a third one of the plurality of switches couples the second analog
bus to a power supply voltage when closed, a fourth one of the
plurality of switches couples the first analog bus to the power
supply voltage when closed, and a fifth one of the plurality of
switches couples the second analog bus to the power supply common
when closed.
[0010] According to a further embodiment, the digital processor
controls the plurality of switches. According to a further
embodiment, the plurality of switches may be a plurality of field
effect transistor (FET) switches.
[0011] According to a further embodiment, the microcontroller may
comprise: a precision timer coupled to the digital processor; a
plurality of switches; a first node coupled to the plurality of
switches, the first node may also be adapted for coupling to an
external capacitive sensor; a sample and hold circuit having a
control input coupled to the precision timer, an analog input
coupled to the first node and an analog output coupled to an input
of the ADC; a constant current source coupled to the plurality of
switches; wherein the plurality of switches may be controlled by
the precision timer for coupling the first node to either a power
supply common or the constant current source; a second node; and an
analog driver having an analog input coupled to the first node and
an analog output coupled to the second node, whereby a voltage on
the second node may be substantially the same as a voltage on the
first node; wherein the second node may be adapted for coupling to
an external guard ring associated with the external capacitive
sensor; wherein the first node may be coupled to the power supply
common through the plurality of switches until a start of a
precision time period determined by the precision timer then the
first node may be coupled to the constant current source, whereby
the external capacitive sensor may be charged by the constant
current source until a stop of the precision time period determined
by the precision timer; after the stop of the precision timer
occurs a sample of a voltage charge on the external capacitive
sensor may be taken by and stored in the sample and hold circuit;
the sampled and stored voltage charge may be converted by the ADC
to a digital representation thereof; and the digital processor
reads the digital representation from the ADC and determines a
capacitance value of the external capacitive sensor from the
precision time period and the digital representation of the voltage
charge.
[0012] According to a further embodiment, the microcontroller may
comprise: a constant current sink coupled to the plurality of
switches; wherein the first node may be coupled to a power supply
voltage through the plurality of switches until a start of another
precision time period determined by the precision timer then the
first node may be coupled to the constant current sink, whereby the
external capacitive sensor may be discharged by the constant
current sink until another stop of the precision time period
determined by the precision timer; after the another stop of the
precision timer occurs a sample of another voltage charge on the
external capacitive sensor may be taken by and stored in the sample
and hold circuit; the sampled and stored another voltage charge may
be converted by the ADC to another digital representation thereof;
and the digital processor reads the another digital representation
from the ADC and determines a capacitance value of the external
capacitive sensor from the another precision time period and the
another digital representation of the another voltage charge.
[0013] According to a further embodiment, the microcontroller may
comprise: a variable frequency oscillator; a frequency measurement
circuit having an output coupled to the digital processor and an
input coupled to the variable frequency oscillator; a first node
coupled to the variable frequency oscillator, the first node may be
also adapted for coupling to an external capacitive sensor; a
second node adapted for coupling to an external guard ring
associated with the external capacitive sensor; and an analog
driver having an analog input coupled to the first node and an
analog output coupled to the second node, whereby a voltage on the
second node may be substantially the same as a voltage on the first
node; wherein the external capacitive sensor may be part of a
frequency determining circuit of the variable frequency oscillator,
whereby a frequency of the variable frequency oscillator changes
when a capacitance value of the external capacitive sensor changes;
wherein the frequency measurement circuit measures and converts the
frequency of the variable frequency oscillator into a digital
representation thereof; and wherein the digital processor reads the
digital representation of the frequency and determines a
capacitance value of the external capacitive sensor.
[0014] According to another embodiment, a capacitive sensor system
may comprise: a capacitive sensor; a guard ring associated with the
capacitive sensor; a microcontroller, comprising: a digital
processor with memory; a plurality of external input/output nodes
that can be programmed to function as analog nodes, a multiplexer
controlled by the digital processor for selecting one of said
analog nodes and coupling the analog node to an analog bus; an
analog-to-digital converter (ADC) coupled with the analog bus for
converting an analog voltage on the analog bus to a digital
representation thereof and having a digital output coupled to the
digital processor for conveying the digital representation; a
further external node which can be connected by means of a
programmable switch controlled by the digital processor to the
analog bus independent from said multiplexer; a sample and hold
capacitor coupled to a plurality of switches; a first node coupled
to the plurality of switches; wherein a first one of the plurality
of switches couples the sample and hold capacitor to either an
input of the ADC or the first node; a second node coupled to the
plurality of switches and the capacitive sensor; a third node
coupled to the guard ring associated with the capacitive sensor;
and an analog driver having an analog input coupled to the second
node and an analog output coupled to the third node, whereby a
voltage on the third node may be substantially the same as a
voltage on the second node; wherein a first one of the plurality of
switches couples the first and second nodes together when closed, a
second one of the plurality of switches couples the first node to a
power supply common when closed, a third one of the plurality of
switches couples the second node to a power supply voltage when
closed, a fourth one of the plurality of switches couples the first
node to the power supply voltage when closed, and a fifth one of
the plurality of switches couples the second node to the power
supply common when closed.
[0015] According to a further embodiment, the capacitive sensor
system may comprise a padding capacitor coupled to the first node,
wherein a combined capacitive value of the padding capacitor and
the sample and hold capacitor may be approximately equal to the
capacitive value of the capacitive sensor. According to a further
embodiment, the digital processor controls the plurality of
switches.
[0016] According to yet another embodiment, a capacitive sensor
system may comprise: a capacitive sensor; a guard ring associated
with the capacitive sensor; a microcontroller may comprise: a
digital processor with memory; a precision timer coupled to the
digital processor; an analog-to-digital converter (ADC) having an
output coupled to the digital processor; a first node coupled to a
plurality of switches and the capacitive sensor; a sample and hold
circuit having a control input coupled to the precision timer, an
analog input coupled to the first node and an analog output coupled
to an input of the ADC; a constant current source coupled to the
plurality of switches; wherein the plurality of switches may be
controlled by the precision timer for coupling the first node to
either a power supply common or the constant current source; a
second node coupled to the guard ring; and an analog driver having
an analog input coupled to the first node and an analog output
coupled to the second node, whereby a voltage on the second node
may be substantially the same as a voltage on the first node;
wherein the first node may be coupled to the power supply common
through the plurality of switches until a start of a precision time
period determined by the precision timer then the first node may be
coupled to the constant current source, whereby the external
capacitive sensor may be charged by the constant current source
until a stop of the precision time period determined by the
precision timer; after the stop of the precision timer occurs a
sample of a voltage charge on the external capacitive sensor may be
taken by and stored in the sample and hold circuit; the sampled and
stored voltage charge may be converted by the ADC to a digital
representation thereof; and the digital processor reads the digital
representation from the ADC and determines a capacitance value of
the capacitive sensor from the precision time period and the
digital representation of the voltage charge.
[0017] According to still another embodiment, a capacitive sensor
system may comprise: a capacitive sensor; a guard ring associated
with the capacitive sensor; a microcontroller may comprise: a
digital processor with memory; a variable frequency oscillator; a
frequency measurement circuit having an output coupled to the
digital processor and an input coupled to the variable frequency
oscillator; a first node coupled to the variable frequency
oscillator and the external capacitive sensor; a second node
coupling to the guard ring; and an analog driver having an analog
input coupled to the first node and an analog output coupled to the
second node, whereby a voltage on the second node may be
substantially the same as a voltage on the first node; wherein the
external capacitive sensor may be part of a frequency determining
circuit of the variable frequency oscillator, whereby a frequency
of the variable frequency oscillator changes when a capacitance
value of the external capacitive sensor changes; wherein the
frequency measurement circuit measures and converts the frequency
of the variable frequency oscillator into a digital representation
thereof; and wherein the digital processor reads the digital
representation of the frequency and determines a capacitance value
of the external capacitive sensor.
[0018] According to another embodiment, a method for measuring
capacitance of a capacitive sensor and controlling a voltage on a
guard ring associated with the capacitive sensor may comprise the
steps of: providing a capacitive sensor; providing a guard ring
associated with the capacitive sensor; providing to the guard ring
a voltage that may be substantially the same as a voltage on the
capacitive sensor; providing a microcontroller may comprise: a
digital processor with memory; an analog-to-digital converter (ADC)
having an output coupled to the digital processor; a sample and
hold capacitor coupled to a plurality of switches; a first node
coupled to the plurality of switches; wherein a first one of the
plurality of switches couples the sample and hold capacitor to
either an input of the ADC or the first node; a second node coupled
to the plurality of switches and the capacitive sensor; a third
node coupled to the guard ring associated with the capacitive
sensor; and an analog driver having an analog input coupled to the
second node and an analog output coupled to the third node, whereby
a voltage on the third node may be substantially the same as a
voltage on the second node; coupling the sample and hold capacitor
to the first node; coupling the first node to a power supply
voltage; coupling the second node to a power supply common;
coupling the first and second nodes together long enough for a
first charge to settle therebetween; decoupling the sample and hold
capacitor from the first node; coupling the second node to the
power supply common; coupling the second node to the power supply
voltage; converting the settled first charge on the sample and hold
capacitor to a first digital representation thereof with the ADC;
reading the first digital representation from the ADC with the
digital processor; coupling the first node to the power supply
common; coupling the first and second nodes together long enough
for a second charge to settle therebetween; decoupling the sample
and hold capacitor from the first node; coupling the second node to
the power supply voltage; coupling the second node to the power
supply common; converting the settled second charge on the sample
and hold capacitor to a second digital representation thereof with
the ADC; and reading the second digital representation from the ADC
with the digital processor.
[0019] According to a further embodiment of the method, the step of
processing the first and the second digital representations with
the digital processor may substantially reduce common mode
noise.
[0020] According to a further embodiment of the method, the method
may comprise the steps of: storing the first and the second digital
representations in a memory associated with the digital processor;
comparing the stored first and second digital representations with
subsequent first and second digital representations, wherein if the
stored first and second digital representations may be
substantially the same as the subsequent first and second digital
representations then the capacitive sensor may be not actuated, and
if the stored first and second digital representations may not
substantially be the same as the subsequent first and second
digital representations then the capacitive sensor may be
actuated.
[0021] According to yet another embodiment, a method for measuring
capacitance of a capacitive sensor and controlling a voltage on a
guard ring associated with the capacitive sensor may comprise the
steps of: providing to a guard ring associated with a capacitive
sensor a voltage that may be substantially the same as a voltage on
the capacitive sensor, further comprising the steps of: a) charging
a capacitive sensor to a second voltage; b) charging a sample and
hold capacitor to a first voltage; c) coupling together the sample
and hold capacitor and the capacitive sensor long enough for a
first charge to settle therebetween; d) decoupling the sample and
hold capacitor from the capacitive sensor; e) converting the
settled first charge on the sample and hold capacitor to a first
digital representation thereof with an analog-to-digital converter
(ADC); f) charging the capacitive sensor to the second voltage; g)
charging the capacitive sensor to the first voltage; h) reading the
first digital representation of the first charge from the ADC with
a digital processor; i) coupling together the sample and hold
capacitor and the capacitive sensor long enough for a second charge
to settle therebetween; j) decoupling the sample and hold capacitor
from the capacitive sensor; k) converting the settled second charge
on the sample and hold capacitor to a second digital representation
thereof with the analog-to-digital converter (ADC); 1) charging the
capacitive sensor to the first voltage; m) charging the capacitive
sensor to the second voltage; n) reading the second digital
representation of the second charge from the ADC with the digital
processor; and o) returning to step b).
[0022] According to a further embodiment of the method, the first
voltage may be approximately a power supply voltage and the second
voltage may be approximately a power supply common. According to a
further embodiment of the method, the first voltage may be
approximately a power supply common and the second voltage may be
approximately a power supply voltage. According to a further
embodiment of the method, a voltage on the guard ring may be
substantially the same as a voltage on the capacitive sensor.
[0023] According to another embodiment, a method for measuring
capacitance of a capacitive sensor and controlling a voltage on a
guard ring associated with the capacitive sensor may comprise the
steps of: providing a capacitive sensor; providing a guard ring
associated with the capacitive sensor; providing to the guard ring
a voltage that may be substantially the same as a voltage on the
capacitive sensor; providing a mixed signal integrated circuit,
comprising: a digital processor with memory; a precision timer
coupled to the digital processor; an analog-to-digital converter
(ADC) having an output coupled to the digital processor; a first
node coupled to a plurality of switches and the capacitive sensor;
a sample and hold circuit having a control input coupled to the
precision timer, an analog input coupled to the first node and an
analog output coupled to an input of the ADC; a constant current
source coupled to the plurality of switches; wherein the plurality
of switches may be controlled by the precision timer for coupling
the first node to either a power supply common or the constant
current source; a second node coupled to the guard ring; and an
analog driver having an analog input coupled to the first node and
an analog output coupled to the second node, whereby a voltage on
the second node may be substantially the same as a voltage on the
first node; coupling the first node to the power supply common
through the plurality of switches until a start of a precision time
period determined by the precision timer; then coupling the first
node to the constant current source, whereby the external
capacitive sensor may be charged by the constant current source
until a stop of the precision time period determined by the
precision timer; sampling and storing after the stop of the
precision timer occurs a voltage charge on the capacitive sensor
with the sample and hold circuit; converting the sampled and stored
voltage charge to a digital representation thereof; and reading the
digital representation from the ADC with the digital processor; and
determining a capacitance value of the capacitive sensor from the
digital representation of the voltage charge.
[0024] According to yet another embodiment, a method for measuring
capacitance of a capacitive sensor and controlling a voltage on a
guard ring associated with the capacitive sensor may comprise the
steps of: providing a capacitive sensor; providing a guard ring
associated with the capacitive sensor; and providing to the guard
ring a voltage that may be substantially the same as a voltage on
the capacitive sensor; providing a microcontroller, comprising: a
digital processor with memory; a variable frequency oscillator; a
frequency measurement circuit having an output coupled to the
digital processor and an input coupled to the variable frequency
oscillator; a first node coupled to the variable frequency
oscillator and the external capacitive sensor; a second node
coupling to the guard ring; and an analog driver having an analog
input coupled to the first node and an analog output coupled to the
second node, whereby a voltage on the second node may be
substantially the same as a voltage on the first node; measuring a
frequency of the variable frequency oscillator with the frequency
determining circuit; providing a digital representation of the
measured frequency to the digital processor; and determining a
capacitance value of the capacitive sensor from the digital
representation of the frequency.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] A more complete understanding of the present disclosure may
be acquired by referring to the following description taken in
conjunction with the accompanying drawings wherein:
[0026] FIG. 1 illustrates a schematic block diagram of an
electronic system having a capacitive touch keypad, a capacitive
touch analog front end and a digital processor, according to the
teachings of this disclosure;
[0027] FIG. 2 illustrates a schematic elevational view of
capacitive sensor keys shown in FIG. 1;
[0028] FIG. 3 illustrates a schematic elevational view of
capacitive sensor keys shown in FIG. 1 and having capacitive guard
rings around each of the capacitive sensors, according to a
specific example embodiment of this disclosure;
[0029] FIG. 4 illustrates a schematic plan view of capacitive
sensor keys shown in FIG. 1 and having guard rings around each of
the capacitive sensors, according to another specific example
embodiment of this disclosure;
[0030] FIG. 5 illustrates a schematic elevational view of
electrostatic field lines surrounding a capacitive sensor and
grounded shield;
[0031] FIG. 6 illustrates a schematic elevational view of
electrostatic field lines surrounding a capacitive sensor, guard
ring and grounded shield, according to the teachings of this
disclosure;
[0032] FIG. 7 illustrates a schematic diagram of a mixed signal
integrated circuit device having CVD processing capabilities for a
capacitive sensor and associated guard ring, according to a
specific example embodiment of this disclosure;
[0033] FIG. 7A illustrates a schematic diagram of a mixed signal
integrated circuit device having CVD processing capabilities for
plurality of capacitive sensors and a guard ring, according to
another specific example embodiment of this disclosure;
[0034] FIG. 8 illustrates a schematic voltage-time diagram of
capacitance conversions, according to the teachings of this
disclosure;
[0035] FIG. 9 illustrates a schematic voltage-time diagram of
capacitance conversions and guard ring voltage control during these
conversions, according to a specific example embodiment of this
disclosure;
[0036] FIG. 10 illustrates a schematic timing diagram of the
capacitive conversion system shown in FIGS. 7 and 7A;
[0037] FIGS. 11 and 12 illustrate schematic process flow diagrams
of capacitive conversions, according to a specific example
embodiment of this disclosure;
[0038] FIG. 13 illustrates a time-voltage graph of a capacitor
being charged from a constant current source;
[0039] FIG. 14 illustrates a schematic diagram of a mixed signal
integrated circuit device having CTMU processing capabilities for a
plurality of capacitive sensors and a guard ring, according to
still another specific example embodiment of this disclosure;
[0040] FIG. 15 illustrates a schematic diagram of a mixed signal
integrated circuit device having two stage CTMU processing
capabilities for a capacitive sensor and associated guard ring,
according to yet another specific example embodiment of this
disclosure;
[0041] FIG. 16 illustrates a schematic diagram of a mixed signal
integrated circuit device having CSM processing capabilities for a
plurality of capacitive sensors and a guard ring, according to
another specific example embodiment of this disclosure ;
[0042] FIG. 17 illustrates a schematic block diagram of
multi-function port logic that supports a digital I/O and an analog
function via an analog pass gate switch, according to the teachings
of this disclosure;
[0043] FIG. 18 illustrates a schematic block diagram of
multi-function port logic that supports a digital I/O and an analog
function via an analog pass gate switch wherein the analog function
can be overridden to precharge and discharge a capacitive touch
sensor connected to the port with ADC controller logic, according
to the teachings of this disclosure; and
[0044] FIG. 19 illustrates a schematic block diagram of analog and
digital connection configurations, according to specific example
embodiments of this disclosure.
[0045] While the present disclosure is susceptible to various
modifications and alternative forms, specific example embodiments
thereof have been shown in the drawings and are herein described in
detail. It should be understood, however, that the description
herein of specific example embodiments is not intended to limit the
disclosure to the particular forms disclosed herein, but on the
contrary, this disclosure is to cover all modifications and
equivalents as defined by the appended claims.
DETAILED DESCRIPTION
[0046] Microcontrollers now include peripherals that enhance the
detection and evaluation of capacitive sensors. According to one
embodiment, capacitive voltage division (CVD) may be used to
evaluate whether a capacitive touch element has been touched or
not. According to another embodiment, a charge time measurement
unit (CTMU) may be used to evaluate whether a capacitive touch
element has been touched or not. According to still another
embodiment, a capacitive sensing module (CSM) may be used to
evaluate whether a capacitive touch element has been touched or
not. However, when capacitive sensors associated therewith are
operated in high noise environments, the resolution or capacitive
change detection in these capacitive measurement systems may not
suffice.
[0047] In particular parasitic capacitance may pose a problem in
many capacitive sensor application. Parasitic capacitance is
generated whenever a conductor adjacent to the sensor (or its
connection to the microcontroller) is at a different voltage
potential then the sensor. Thus there is a need to reduce the
parasitic capacitance of capacitive sensors, in order to increase
the resolution of the resulting capacitance change conversion
process. According to various embodiments disclosed herein a
voltage can be created approximating the sensor capacitance and
driving conductive traces placed between the sensor (and its
connection) and other conductors and/or ground plane in close
proximity thereto.
[0048] Referring now to the drawings, the details of specific
example embodiments are schematically illustrated. Like elements in
the drawings will be represented by like numbers, and similar
elements will be represented by like numbers with a different lower
case letter suffix.
[0049] Referring to FIG. 1, depicted is a schematic block diagram
of an electronic system having a capacitive touch keypad, a
capacitive touch analog front end and a digital processor,
according to the teachings of this disclosure. A microcontroller
integrated circuit device 101 may comprise a digital processor 106,
memory, one or more of input-output (I/O) ports (nodes), an
analog-to-digital converter (ADC), precision timers, multifunction
input and output nodes, charge time measurement unit (CTMU),
multiplexers, digital-to-analog converter (DAC), or combinations
thereof. A capacitive touch analog front end (AFE) 104 may be
implemented with some of the aforementioned functions of the
microprocessor 101. The capacitive touch AFE 104 may be coupled to
a matrix of capacitive sensor keys 102, e.g., pushbuttons, levers,
toggles, targets, handles, knobs, etc., through an analog
multiplexer (not shown).
[0050] The capacitive touch AFE 104 facilitates, with a single
low-cost integrated circuit microcontroller, all active functions
used in determining when there is actuation of capacitive sensors
by, for example but is not limited to, pressing and deflecting a
target key that changes the capacitance value of an associated
capacitive sensor. The capacitive touch AFE 104 measures the
capacitance value of each sensor of the matrix of capacitive sensor
keys 102 and converts the capacitance values into respective analog
direct current (DC) voltages or frequencies that are read and
converted into digital values with an analog-to-digital converter
(ADC) (not shown) or frequency measurement device (not shown), and
sent to the digital processor 106.
[0051] The digital processor 106 supplies clock and control
functions to the capacitive touch AFE 104, reads the analog voltage
detector output of the capacitive touch AFE 104, and selects each
key of the matrix of capacitive sensor keys 102. When actuation of
a key of the matrix of capacitive sensor keys 102 is determined,
the digital processor 106 will take an appropriate action. More
detailed descriptions of various capacitive touch systems are more
fully disclosed in Microchip Technology Incorporated application
notes AN1298, AN1325 and AN1334, available at www.microchip.com,
and are hereby incorporated by reference herein for all
purposes.
[0052] Referring to FIG. 2, depicted is a schematic elevational
view of capacitive sensor keys shown in FIG. 1. A substrate 204,
e.g., printed circuit board (PCB), may have a ground plane 206
(optional) that may be used for electromagnetic interference (EMI)
shielding. Capacitive sensor plates 208 may be transposed on a face
of the substrate 204 and in proximity to the ground plane 206
(optional). Other circuit conductors 210 (e.g., PCB traces) may
also be in close proximity to the capacitive sensor plates 208.
Touch targets 212 may lay over respective ones of the capacitive
sensor plates 208 and may have an air gap 214 therebetween. It is
contemplated and within the scope of this disclosure that a touch
target 212, as shown in FIG. 2, may be replaced by any object that
changes the capacitance of the capacitive sensor plate 208, e.g., a
piece of metal, a finger, a hand, a foot, a leg, etc. Coverings 216
may be placed over the capacitive sensor plates 208 and/or be part
of the touch targets 212 (optional) and have alpha-numerical
information engraved thereon. Each of the capacitive touch keys 108
comprises a sensor plate 208 and covering 216. Dielectric spacers
218 are located between each of the capacitive touch keys 108.
Optionally, a touch target 212 may be added over each respective
sensor plate 208.
[0053] The ground plane 206 (optional) and/or circuit conductors
210 may be at different voltage potentials then the capacitive
sensor plates 208. This creates parasitic capacitance between the
capacitive sensor plate 208 and portions of the ground plane 206
(optional) and/or circuit conductors 210 in close proximity to the
capacitive sensor plate 208. See FIG. 5 for a schematic
representation of electrostatic fields between the capacitive
sensor plate 208 and surrounding conductors at different voltage
potential. Note the strong electrostatic field lines between the
capacitive sensor plate 208 and the surrounding conductors. This
parasitic capacitance limits detection resolution of a change in
the capacitance value of the capacitive sensor plate 208 occurring
during a touch thereto. Parasitic capacitance similarly affects the
connections between the capacitive sensor plates 208 and the AFE
104. It also limits the amount of noise shielding that may be
employed in capacitive touch systems.
[0054] Referring to FIG. 3, depicted is a schematic elevational
view of capacitive sensor keys shown in FIG. 1 and having
capacitive guard rings around each of the capacitive sensors,
according to a specific example embodiment of this disclosure. A
guard ring 320 around each of the capacitive sensor plates 208 is
added to the capacitive sensor keys 102a. Otherwise all other
elements are substantially the same as the capacitive sensor keys
102 shown in FIG. 2. By maintaining a voltage on the guard ring 320
that is substantially the same as the voltage on the respective
capacitive sensor plate 208, parasitic capacitances are
significantly reduced. Thereby increasing detection resolution of a
change in the capacitance value of the capacitor sensor plate 208
occurring during a touch thereto. In addition, providing for
enhanced noise shielding does not affect the detection resolution
as it would in the configuration shown in FIG. 2. See FIG. 6 for a
schematic representation of electrostatic fields between the
capacitive sensor plate 208, guard ring 320, surrounding ground
plane 206 (optional) and conductors 210 (not shown), wherein the
capacitive sensor plate 208 and the guard ring 320 are at
substantially the same voltage potential. Note the much weaker
electrostatic field lines (longer lines) between the capacitive
sensor plate 208 and the surrounding conductors and the ground
plane 206 (optional). There is substantially no parasitic
capacitance between the capacitive sensor plate 208 and the guard
ring 320 because both are at substantially the same voltage
potential.
[0055] Referring to FIG. 4, depicted is a schematic plan view of
capacitive sensor keys shown in FIG. 1 and having guard rings
around each of the capacitive sensors, according to another
specific example embodiment of this disclosure. Each of the
capacitive sensor plates 208 of the touch keys 108 are surrounded
by guard rings 420 that are electrically coupled together and have
the same voltage potential thereon. In this configuration only one
capacitive sensor plate 208 capacitance value is determined at a
time so the entire matrix of guard rings 420 assumes the voltage
potential of the capacitive sensor plate 208 having its capacitance
value determined by the AFE 104 and digital processor 106, as more
fully described hereinafter.
[0056] Each of the guard rings 320 shown in FIG. 3 may be
independent of one another and have different voltages thereon, but
would require more connections to the digital processor 106. So
unless simultaneous capacitance readings of more than one
capacitive sensor plate 208 needs to be determined at the same
time, the single voltage potential guard rings 420 (FIG. 4) would
suffice and require fewer circuit connections to the digital
processor 106.
[0057] Referring to FIG. 7, depicted is a schematic diagram of a
mixed signal integrated circuit device having CVD processing
capabilities for a capacitive sensor and associated guard ring,
according to a specific example embodiment of this disclosure. The
mixed signal integrated circuit device 101a shown in FIG. 7, e.g.,
a microcontroller, is applicable when using the capacitive voltage
divider (CVD) method of determining the capacitance value of the
capacitive sensor plate 208. By first determining the capacitance
value of an untouched capacitive sensor plate 208 and then
determining a subsequent capacitance value of a touched capacitive
sensor plate 208, a touch to that capacitive sensor plate 208 may
be determined based upon the change in capacitance thereof. In CVD
two capacitors are charged/discharged to opposite voltage values.
Then the two oppositely charged capacitors are coupled together and
a resulting voltage is measured on the connected two capacitors. A
more detailed explanation of CVD is presented in commonly owned
United States Patent Application Publication No. US 2010/0181180,
incorporated by reference herein for all purposes. The switches
shown in FIG. 7 may be, for example but are not limited to, field
effect transistor (FET) switches. The nodes 728 and 730 are analog
nodes coupled to respective internal single line (conductor) analog
buses 732 and 734, respectively.
[0058] The capacitance of the capacitive sensor plate 208 is
represented by variable capacitor 704 (first CVD capacitor), and
the second CVD capacitor may be the sample and hold capacitor 716
if these two capacitors have fairly close capacitive values e.g.,
1:1 to about 3:1. The reason for this in CVD is that part of the
charge from one capacitor is transferred to the other capacitor
having no charge or an opposite charge. For example, when the two
CVD capacitors are equal in value, half of the charge on one will
be transferred to the other capacitor. A two to one capacitance
ratio will result in 1/3 of the charge being transferred to or
taken from the smaller (1/2C) capacitor depending upon which of one
the capacitors was initially charged. When the sample and hold
capacitor 716 is substantially smaller than the capacitive sensor
capacitor 704, additional capacitance 706a may be added externally
to node 728, and/or internal capacitance 706b may be added
independently of node 728 so that the combined capacitance of the
capacitors 716, 706a and/or 706b have sufficient capacitance in
relation to the capacitance value of the capacitive sensor
capacitance 704 to meet the criteria above. This results in the
best resolution in determining a capacitance value using CVD.
Capacitor 716 is also the sample and hold capacitor used to sample
and hold the analog voltage resulting after charge is transferred
between the two CVD capacitors. Once the charge transfer is
complete, an analog-to-digital converter (ADC) 718 converts the
resulting charge voltage to a digital value that is read by the
digital processor 106 for further processing and determination of
the capacitance value of the touch sensor capacitor 704.
[0059] In the example hereinafter presented, the capacitance values
for the capacitor 704 (first CVD capacitor), and capacitor 706a (an
externally connected capacitor) and capacitor 706b are selected in
combination with the sample and hold capacitor 716 to result in a
combined voltage of 1/3 or 2/3 of the Vdd voltage depending on
whether the first CVD capacitor 704 is discharged to Vss or charged
to Vdd, and the combination of capacitors 706 and 716 are charged
to Vdd or discharged to Vss, respectively. In this example, the
capacitor 704 is about twice the capacitance as the capacitance of
the parallel connected combination of capacitors 706 and 716. The
resulting quiescent voltage after coupling the two opposite
polarity charged CVD capacitors together will be about 1/3*Vdd when
the capacitor 704 was initially discharged to Vss, and about
2/3*Vdd when the capacitor 704 was initially charged to Vdd.
[0060] Optionally, an analog buffer driver 714 having a high input
impedance may be coupled to node 730 which is also coupled to the
capacitor 704. The analog buffer driver 714 has a low impedance
output that may be switchably coupled through switch J to the node
726 that is also coupled to the guard ring capacitance 702. The
output voltage of the analog buffer driver 714 faithfully follows
the voltage at the input thereto. Therefore, the voltage on the
guard ring 320 or 420 substantially follows the voltage on the
respective sensor plate 208 being evaluated for a capacitance value
by the digital processor 106.
[0061] Referring to FIG. 7A, depicted is a schematic diagram of a
mixed signal integrated circuit device having CVD processing
capabilities for a plurality of capacitive sensors and a guard
ring, according to another specific example embodiment of this
disclosure. The mixed signal integrated circuit device 101b shown
in FIG. 7A, e.g., a microcontroller, performs substantially the
same as the device 101a shown in FIG. 7 except that there is only
one single wire analog bus 732a; wherein internal capacitors 706b
and 706c are coupled/decoupled from the bus 732a with switches H,
the external node 728 is coupled/decoupled from the bus 732a with
switch G, and node 726 is coupled/decoupled from the bus 732a with
switch J. Only one set of Vdd/Vss switches D and C are used wherein
the first CVD capacitor 704 is charged/discharged during a
different time period then the second CVD capacitor 716 (and 706)
is discharged/charged. This saves a set of switches and a second
internal analog bus (see FIG. 7 bus 734).
[0062] In addition, a plurality of switches I (multiplexer) are
used to multiplex each of the capacitive sensors 704 used in the
capacitive touch keys 108 shown in FIG. 1. These circuit features
may also be incorporated into the circuit of FIG. 7. The analog
multiplexer switches I select respective ones of the plurality of
sensor capacitors 704 as the capacitive touch analog front end 104
scans the capacitive touch keys 108. The plurality of nodes 730 are
typically multi-purpose programmable analog or digital inputs
and/or outputs. For explanatory clarity in this disclosure only
analog input/output (two way) configured nodes are shown.
[0063] Optionally, an analog buffer driver 714 having a high input
impedance may be coupled between the node 726 and the single wire
analog bus 732a through switch J when the selected one of the
plurality of capacitors 704 is being charged/discharged. The analog
buffer driver 714 has a low impedance output coupled to the node
726 which is coupled to the guard ring capacitance 702. The output
voltage of the analog buffer driver 714 faithfully follows the
voltage on the selected one of the plurality of capacitors 704.
[0064] With respect to FIGS. 7 and 7A, it is contemplated and
within the scope of this disclosure that various embodiments of a
microcontroller may include external node 728 to allow for
connection of an external capacitor 706a as explained hereinabove.
An additional adjustable capacitor(s) 706b (and 706c) may be
present internally and may be switchably coupled to the analog bus
732a. However, other embodiments may not provide for such an
external node 728. Instead, either capacitance 716 may have the
appropriate value or an additional internal capacitance 706b, for
example a variable capacitance, is or can be connected to bus 732.
Furthermore, as each external node 726, 728, and 730 may be
programmable to support multiple functions, additional switches
(not shown in FIG. 7) may be used to allow to use nodes 726, 728,
and 730 for other functions as will be explained in more detail
hereinafter with respect to FIGS. 17 and 18.
[0065] Referring to FIGS. 8 and 9, depicted are schematic
voltage-time diagrams of capacitance conversions (FIG. 8), and
guard ring voltage control (FIG. 9) during these conversions,
according to a specific example embodiment of this disclosure. In
segment I the capacitors 706 and 716 (sample and hold capacitor)
are charged to Vdd, the capacitive sensor capacitor 704 and the
guard ring capacitance 702 are discharged to Vss. In segment II the
capacitors 706, 716 and 704 are coupled together and a quiescent
voltage of about 1/3*Vdd will result when the capacitive touch key
108 is not depressed, and a little less than 1/3*Vdd when
depressed. The guard ring capacitance 702 follows the voltage on
the capacitor 704 (capacitive sensor) so as to minimize any
parasitic capacitances therebetween. Toward the end of segment II
the sample and hold capacitor 716 decouples from the capacitors 706
and 704 and retains the quiescent voltage obtained during segment
II. In segment III any voltage charge on the capacitor 704
(capacitive sensor) is discharged to substantially Vss, then at the
beginning of segment IV the capacitor 704 (capacitive sensor) and
the guard ring capacitance 702 are charged to substantially Vdd.
Meantime also in segment IV the quiescent voltage stored on the
sample and hold capacitor 716 is converted by the ADC 718 to a
digital value representing the quiescent voltage and read by the
digital processor 106. The digital value from the ADC 718 is used
in determining whether the capacitive sensor was being actuated
(touched), e.g., quiescent voltage lower then what is expected from
a non-actuated touch sensor or not. When the capacitive value of
the touch sensor capacitor 704 is actuated (touched) its
capacitance increases and the subsequent quiescent voltage will
thereby be less then when not actuated. This is true when the
capacitor 704 is initialized to Vss. When the capacitor 704 is
initialized to Vdd, the subsequent quiescent voltage is about
2/3*Vdd when the capacitive sensor is not actuated.
[0066] In segment V the capacitors 706 and 716 (sample and hold
capacitor) are discharged to Vss, the capacitive sensor capacitor
704 and guard ring capacitance 702 have already been charged to
Vdd. In segment VI the capacitors 706, 716 and 704 are coupled
together and a quiescent voltage of about 2/3*Vdd will result when
the capacitive touch key 108 is not depressed, and a little more
than 2/3*Vdd when depressed. The guard ring capacitance 702 follows
the voltage on the capacitor 704 (capacitive sensor) so as to
minimize any parasitic capacitances therebetween. Toward the end of
segment VI the sample and hold capacitor 716 decouples from the
capacitors 706 and 704 and retains the quiescent voltage obtained
during segment VI. In segment VII the capacitor 704 (capacitive
sensor) is charged to substantially Vdd, then at the beginning of
segment VIII the capacitor 704 (capacitive sensor) and the guard
ring capacitance 702 are discharged to substantially Vss. Meantime
also in segment VIII the quiescent voltage stored on the sample and
hold capacitor 716 is converted by the ADC 718 to a digital value
representing the quiescent voltage and read by the digital
processor 106. The digital value from the ADC 718 is used in
determining whether the capacitive sensor was being actuated
(touched), e.g., quiescent voltage lower then what is expected from
a non-actuated touch sensor or not. When the capacitive value of
the touch sensor capacitor 704 is actuated (touched) its
capacitance increases and the subsequent quiescent voltage will
thereby be greater than when not actuated. This is true when the
capacitor 704 is initialized to Vdd. When the capacitor 704 is
initialized to Vss, the subsequent quiescent voltage is about
1/3*Vdd when the capacitive sensor is not actuated, as described
hereinabove. These sequences repeat for each one of the touch keys
108. Also by inverting the voltage charge polarities every other
capacitive measurement cycle and averaging the capacitive
measurement values, a type of differential operation is achieved
that minimizes common mode noise and interference, e.g., 60 Hz
power line interference.
[0067] Referring to FIG. 10, depicted is a schematic timing diagram
of the capacitive conversion system shown in FIG. 7. This schematic
timing diagram clearly represents a specific example operational
embodiment of the circuit shown in FIG. 7. Voltages on nodes 724,
726, 728 and 730 are shown in relation to the operational open and
close combinations of switches A-F. FIG. 10 basically represents
the same voltage and timing waveforms as shown in FIG. 9. It is
contemplated and within the scope of this disclosure that other and
further circuit designs and timing diagrams could be used with
equal effect, and one having ordinary skill in electronic circuit
design and having the benefit of this disclosure could replicate
the results described herein.
[0068] Referring to FIGS. 11 and 12, depicted are schematic process
flow diagrams of capacitive conversions, according to a specific
example embodiment of this disclosure. In step 1102 a capacitance
value conversion is started. In step 1104 the sample and hold
capacitor combination of the capacitors 706 and 716 are charged to
a first voltage. In step 1106 the capacitive sensor and capacitive
sensor guard ring are charged to a second voltage. The first
voltage may be Vdd and the second voltage may be Vss or visa versa.
The capacitive sensor guard ring is charged to the second voltage
so as to minimize parasitic capacitance that would otherwise
develop at the capacitive sensor due to electrostatic charge caused
by a difference of voltage potential between the capacitive sensor
and adjacent conductors.
[0069] In step 1112 the sample and hold capacitor combination,
previously charged to the first voltage, is coupled to the
capacitive sensor, previously charged to the second voltage. In
step 1114 the sample and hold capacitor and the capacitive sensor
are coupled together long enough in time for a complete settling to
a common quiescent first charge. Then in step 1116 the sample and
hold capacitor is decoupled from the capacitive sensor and the
sample and hold capacitor thereafter retains the settled first
charge. In step 1118 conversion to a digital representation of the
first charge stored in the sample and hold capacitor begins.
[0070] In step 1120 the capacitive sensor and guard ring are
briefly discharged to the second voltage. In step 1122 the
capacitive sensor and guard ring are charged to the first voltage.
The capacitive sensor guard ring is charged to the first voltage so
as to minimize parasitic capacitance that would otherwise develop
at the capacitive sensor due to electrostatic charge caused by a
difference of voltage potential between the capacitive sensor and
adjacent conductors. In step 1126 the conversion of the first
charge to a digital representation thereof terminates and is then
read by the digital processor 106 for determining the capacitance
value of the capacitive sensor 108.
[0071] In step 1128 the sample and hold capacitor combination of
the capacitors 706 and 716 are charged to the second voltage. In
step 1130 the capacitive sensor and capacitive sensor guard ring
are charged to the first voltage. The capacitive sensor guard ring
is charged to the first voltage so as to minimize parasitic
capacitance that would otherwise develop at the capacitive sensor
due to electrostatic charge caused by a difference of voltage
potential between the capacitive sensor and adjacent
conductors.
[0072] In step 1136 the sample and hold capacitor combination,
previously charged to the second voltage level, is coupled to the
capacitive sensor, previously charged to the first voltage. In step
1138 the sample and hold capacitor combination and the capacitive
sensor are coupled together long enough in time for a complete
settling to a quiescent second charge. Then in step 1140 the sample
and hold capacitor is decoupled from the capacitive sensor and the
sample and hold capacitor thereafter retains the settled second
charge). In step 1142 a conversion to a digital representation of
the second charge stored in the sample and hold capacitor
begins.
[0073] In step 1144 the capacitive sensor and guard ring are
briefly discharged to the first voltage. In step 1146 the
capacitive sensor and guard ring are charged to the second voltage.
The capacitive sensor guard ring is charged to the second voltage
so as to minimize parasitic capacitance that would otherwise
develop at the capacitive sensor due to electrostatic charge caused
by a difference of voltage potential between the capacitive sensor
and adjacent conductors. In step 1150 the conversion of the second
charge to a digital representation thereof terminates and is then
read by the digital processor 106 for determining the capacitance
value of the capacitive sensor 108. The digital representations of
the first and second charges may thereafter be processed to reduce
common mode noise and interference, e.g., 60 Hz power line
interference.
[0074] Referring to FIG. 14, depicted is a schematic diagram of a
mixed signal integrated circuit device having CTMU processing
capabilities for a plurality of capacitive sensors and a guard
ring, according to still another specific example embodiment of
this disclosure. The mixed signal integrated circuit device 101c
shown in FIG. 14, e.g., a microcontroller, may comprise a charge
time measurement unit (CTMU) comprising a precision timer 1420, a
sample and hold circuit 1416, a constant current source 1422, and
current steering switches 1424; an analog-to-digital converter
(ADC) 1418, and a digital processor with memory 1406. The voltage
at node 726 will follow the voltage on the signal wire analog bus
1432, as more fully described hereinabove. Optionally, an analog
buffer driver 714 having a high input impedance may be coupled
between the node 726 and the single wire analog bus 1432. The
analog buffer driver 714 has a low impedance output coupled to the
node 726 which is coupled to the guard ring capacitance 702. The
output voltage of the analog buffer driver 714 faithfully follows
the voltage on the selected one of the plurality of capacitors
704.
[0075] A plurality of switches I (multiplexer) are used to
multiplex each of the capacitive sensors 704 used in the capacitive
touch keys 108 shown in FIG. 1. The analog multiplexer switches I
select respective ones of the plurality of sensor capacitors 704 as
the capacitive touch analog front end 104 scans the capacitive
touch keys 108. The plurality of nodes 730 are typically
multi-purpose programmable analog or digital inputs and/or outputs.
Node 726 and the plurality of nodes 730 may be programmed to
support a plurality of functions as will be explained in more
detail hereinafter for the circuits shown in Figures. 17 and 18.
For explanatory clarity in this disclosure only analog input/output
(two way) configured nodes are shown.
[0076] The function of the CTMU may better be understood by
referring to FIG. 13, wherein a time-voltage graph of a capacitor
being charged from a constant current source is depicted. When a
capacitor 704 is charged through a constant current source 1422,
the voltage, V, across the capacitor 704 increases linearly with
time, according to equation (1):
I=C*dV/dT Eq. (1)
where C is the capacitance value of the capacitor 704, I is the
current from the constant current source 1422 and V is the voltage
on the capacitor 704 at time T. When any two values of the current,
I; time, T; and voltage, V are known, the other unknown value may
be calculated from the two known values. For example, if the
charging current from the constant current source 1422, and the
time interval between T.sub.1 at voltage V.sub.1 and T.sub.2 at
voltage V.sub.2 are known, then the capacitance of the capacitor
704 may be determined using equation (1) above.
[0077] The digital processor 1406 enables the precision timer 1420
of the CTMU to begin precise timing of the constant current source
1422 charging of the capacitor 730. At a first time the precision
timer 1420 closes switch 1424a and opens switches 1424b and 1424c,
thereby starting the constant current charging of the capacitor
704. The constant current source 1422 charges the capacitor 704
with a resulting linearly increasing voltage thereon (see
voltage-time graph of FIG. 13 until a second time). At the second
time the sample and hold circuit 1416 takes a voltage sample of the
voltage charge on the capacitor 730. Thereafter, the precision
timer 1420 opens switch 1424a and closes switches 1424b and 1424c.
The voltage charge on the capacitor 704 starts at zero voltage and
returns back to zero voltage due to switch 1424c being closed. The
elapse time from the precision timer 1420 is sent to the digital
processor 1406. The ADC 1418 converts the sampled voltage from the
sample and hold circuit 1416 into a digital representation thereof
and sends that digital representation to the digital processor
1406. The digital processor 1406 uses the elapse time from the
precision timer 1420 and the digital representation of the sampled
voltage from the ADC 1418 to determine a capacitance value for the
capacitor 704, according to equation (1) above. This process
continues repetitiously for each one of the capacitive touch keys
108.
[0078] The CTMU is more fully described in Microchip application
notes AN1250 and AN1375, available at www.microchip.com, and
commonly owned U.S. Pat. No. 7,460,441 B2, entitled "Measuring a
long time period;" and U.S. Pat. No. 7,764,213 B2, entitled
"Current-time digital-to-analog converter," both by James E.
Bartling; wherein all are hereby incorporated by reference herein
for all purposes.
[0079] The mixed signal integrated circuit device 101c may further
comprise a plurality of input/output nodes 742, programmable
receivers/drivers 740 coupled to the plurality of input/output
nodes 742, and an analog multiplexer 738 coupled to the
programmable receivers/drivers 740. The digital processor 106
controls the programmable receivers/drivers 740 and may thereby
configure any one or more of the plurality of input/output nodes
742 as analog inputs, digital inputs, analog outputs (DAC not
shown) and/or digital outputs. The multiplexer 738 is controlled by
the digital processor 106 and may be used to couple the input of
the ADC 718, to any one of the plurality of input/output nodes 742
configured as an analog input. The multiplexer 738 may also be used
to couple an analog module (not shown), e.g., ADC,
digital-to-analog converter (DAC), comparator, operational
amplifier, etc., to any one of or more of the plurality of
input/output nodes 742 configured appropriately as an analog input
or output.
[0080] Referring to FIG. 15, depicted is a schematic diagram of a
mixed signal integrated circuit device having two stage CTMU
processing capabilities for a capacitive sensor and associated
guard ring, according to yet another specific example embodiment of
this disclosure. The mixed signal integrated circuit device 101d
shown in FIG. 15, e.g., a microcontroller, may comprise a charge
time measurement unit (CTMU) comprising a precision timer 1420, a
sample and hold circuit 1416, a first constant current source 1422,
first current steering switches 1424, a second constant current
source 1536, second current steering switches 1534; inversion
switch 1532, an analog-to-digital converter (ADC) 1418, and a
digital processor with memory 1406. The voltage at node 726 will
follow the voltage at node 730, as more fully described
hereinabove. The circuit features shown in FIG. 14 may also be
incorporated into the circuit of FIG. 15.
[0081] The digital processor 1406 does a first capacitive
measurement sequence as described for the circuit shown in FIG. 14.
Then the digital processor 1406 changes the capacitive measurement
inversion switch 1532 from position a (operation the same as the
circuit shown in FIG. 14) to position b. Now switches 1534b and
1534c are closed, charging the capacitor 704 to Vdd. The digital
processor 1406 then enables the precision timer 1420 of the CTMU to
begin precise timing of the constant current source 1536
discharging of the capacitor 730.
[0082] At a first time the precision timer 1420 closes switch 1534a
and opens switches 1534b and 1534c, thereby starting the constant
current discharging of the capacitor 704. The constant current
source 1536 discharges the capacitor 704 with a resulting linearly
decreasing voltage thereon. At the second time the sample and hold
circuit 1416 takes a voltage sample of the voltage charge on the
capacitor 730. Thereafter, the precision timer 1420 opens switch
1534a and closes switches 1534b and 1534c. The voltage charge on
the capacitor 704 starts at Vdd volts and returns back to Vdd volts
due to switch 1534b being closed. The elapse time from the
precision timer 1420 is sent to the digital processor 1406. The ADC
1418 converts the sampled voltage from the sample and hold circuit
1416 into a digital representation thereof and sends that (second
conversion) digital representation to the digital processor 1406.
The digital processor 1406 uses the elapse time from the precision
timer 1420 and the digital representation of the sampled voltage
from the ADC 1418 to determine a second capacitance value for the
capacitor 704, according to equation (1) above. The digital
representations from the first and second conversions (first
charging, second discharging) may thereafter be processed to reduce
common mode noise and interference, e.g., 60 Hz power line
interference. This process continues repetitiously for each one of
the capacitive touch keys 108.
[0083] Referring to FIG. 16, depicted is a schematic diagram of a
mixed signal integrated circuit device having CSM processing
capabilities for a plurality of capacitive sensors and a guard
ring, according to another specific example embodiment of this
disclosure. The mixed signal integrated circuit device 101e shown
in FIG. 16, e.g., a microcontroller, may comprise a variable
frequency oscillator 1618, a frequency measurement circuit 1620 and
a digital processor 1620. The optional analog buffer driver 714
functions as more fully described hereinabove. A selected one of
the plurality of capacitors 704 is part of the frequency
determining circuit of the variable frequency oscillator 1618, and
as the capacitance value thereof changes so does the resulting
frequency. The frequency measurement circuit 1620 measures the
frequencies from the variable frequency oscillator 1618 and
provides the measured frequencies in a digital format be read by
the digital processor 1620, which then determines the amount of
frequency change. A large enough change in frequency will indicate
that the capacitance value of the selected capacitor 704 has
changed which indicates that the associated capacitive touch key
108 is actuated. A capacitive measurement system using frequency is
more fully described in commonly owned U.S. Patent Application
Publication No. US 2011/0267309, entitled "Mutual Capacitance
Measurement in a Multi-Touch Input Device;" by Jerry Hanauer and
Todd O'Connor; is hereby incorporated by reference herein for all
purposes.
[0084] A plurality of switches I (multiplexer) are used to
multiplex each of capacitive sensors 704 used in the capacitive
touch keys 108 shown in FIG. 1. The analog multiplexer switches I
select respective ones of the plurality of sensor capacitors 704 as
the capacitive touch analog front end 104 scans the capacitive
touch keys 108. The plurality of nodes 730 are typically
multi-purpose programmable analog or digital inputs and/or outputs.
For explanatory clarity in this disclosure only analog input/output
(two way) configured nodes are shown.
[0085] Referring to FIG. 17, depicted is a schematic block diagram
of multi-function port logic that supports a digital I/O and an
analog function via an analog pass gate switch, according to the
teachings of this disclosure. A digital driver 1754 having a
tri-state output is coupled to the external node 728 and is
controlled by a tri-state control signal from, for example but is
not limited to, the digital processor 106. A digital output signal
from, for example but is not limited to, the digital processor 106
is coupled to an input of the digital driver 1754.
[0086] An analog pass gate switch 1750, which for example may
implement switch G in FIG. 7A, is controlled by analog switch logic
1752 that may be controlled by an analog bus control signal,
independent form the ADC channel selection, from, for example but
is not limited to, the digital processor 106. Generally an analog
multiplexer for the internal ADC is configured to allow only one of
the multiple switches to close so that only one of the external
pins at a time is connected to the internal ADC. However, according
to another embodiment, an analog multiplexer for the ADC may be
configured to allow that more than one switch can be controlled to
connect an external pin to the analog bus. Hence, the control logic
1752 and analog pass gate switches 1750 may either be controlled
independently from the analog multiplexer or may be part of the
analog multiplexer. The analog pass gate switch 1750 when closed
enables direct coupling of the node 728 to an analog bus 1732, as
more fully described hereinabove. When the analog pass gate switch
1750 is closed, the output of the digital driver 1754 is put into a
high impedance state by the tri-state control, thereby minimally
affecting the node 728 when being used as an analog port. It is
contemplated and within the scope of this disclosure that other
functions may be included according to other embodiments described
herein.
[0087] Referring to FIG. 18, depicted is a schematic block diagram
of multi-function port logic that supports a digital I/O and an
analog function via an analog pass gate switch wherein in addition
the analog function can be overridden to precharge and discharge a
capacitive touch sensor connected to the port with ADC controller
logic, according to the teachings of this disclosure. Such a port
logic may be used for any of the external pins 730 and when the
analog multiplexer is configured to allow more than one switch to
be closed then also for pin 728. Switching between digital and
analog functions at the node 730 can be processor intensive and may
require a complex program to properly handle all related digital
and analog functions required of the node 730, as more fully
described hereinabove. In order to take the load, e.g., program
steps and/or control functions, off of the processor 106 during
setup and determination, e.g., FIGS. 8-12, of the capacitance value
of each capacitive sensor, an ADC override feature may be
incorporated into the capacitive touch determination circuits
described herein. Use of a dedicated ADC controller incorporating
the circuit functions shown in FIG. 18 will save digital processor
program steps and allow for the processor to perform other
functions during determination of the capacitive sensor
capacitance. However, according to other embodiments, the override
function can also be omitted. Also, according to yet other
embodiments, the port logic as shown in FIGS. 17 and 18 may be
combined to create a universal port logic for each external pin, as
for example, shown in FIG. 7A. Thus, a universal port logic for all
external pins may have two pass gates which can be controlled
independently to connect to the analog bus or may have a single
pass gate which is part of the analog multiplexer that allows to be
controlled by an independent enable signal.
[0088] A digital driver 1854 having a tri-state output is coupled
to the external node 730 and is controlled by a tri-state control
signal from a multiplexer 1858. A digital output signal from a
multiplexer 1860 is coupled to an input of the digital driver 1854.
An analog pass gate switch 1850, which may implement the switch I
in FIG. 7A, is controlled by analog switch logic 1852. When the ADC
override enable signal is at a logic low the multiplexer 1858
couples the tri-state control signal to control the tri-state
output of the digital driver 1854, and the multiplexer 1860 couples
the digital output signal to the input of the digital driver 1854.
The ADC channel select (analog bus control) controls the analog
pass gate switch 1850 to directly couple the node 730 to the analog
bus 732, as more fully described hereinabove. In this
configuration, the circuit shown in FIG. 18 functions in
substantially the same fashion as the circuit shown in FIG. 17.
[0089] However, when the ADC override enable signal is at a logic
high the multiplexer 1858 couples the ADC override data enable
signal to control the tri-state output of the digital driver 1854,
and the multiplexer 1860 couples the ADC override data signal to
the input of the digital driver 1854. The analog pass gate switch
1850 is forced to decouple the analog bus 732 from the node 730. In
this configuration the ADC override data enable and ADC override
data signals may be provided by an ADC logic controller (not
shown), and may be used to charge or discharge a capacitive touch
sensor coupled to the node 730 without requiring program intensive
actions from the digital processor 106.
[0090] Port logic for nodes 726 and 728 may be implemented as shown
in FIG. 17 or FIG. 18 as explained above. The plurality of Nodes
730 can be implemented as shown in FIG. 18. As mentioned above, a
universal port may be used for all external pins. Additional
functions, such as the additional drivers 714 or other logic or
circuitry can be implemented to support other functionalities
according to a respective external pin.
[0091] Referring to FIG. 19, depicted is a schematic block diagram
of analog and digital connection configurations, according to
specific example embodiments of this disclosure. A plurality of
analog pass gate switches 1938 may implement an analog multiplexer
and couple and decouple a plurality of nodes 730x to and from an
analog bus 732, e.g., selection of each of a plurality of
capacitive touch sensors. Either a direct connection couples
together the node 728 and the analog bus 732 (e.g., see FIG. 7), or
an optional analog pass gate switch 1936 may couple and decouple
the node 728 to and from the analog bus 732 (e.g., see FIG. 7A). As
explained above, the additional pass gate switch 1936 can be part
of the analog multiplexer if the multiplexer is designed to allow
more than one switch to be closed. A plurality of switches 1934 may
couple and decouple additional sample and hold capacitors 1944 to
and from the analog bus 732. Switch 1940 may be used to charge the
analog bus 732 to Vdd, and switch 1942 may be used to discharge the
analog bus 732 to Vss.
[0092] While embodiments of this disclosure have been depicted,
described, and are defined by reference to example embodiments of
the disclosure, such references do not imply a limitation on the
disclosure, and no such limitation is to be inferred. The subject
matter disclosed is capable of considerable modification,
alteration, and equivalents in form and function, as will occur to
those ordinarily skilled in the pertinent art and having the
benefit of this disclosure. The depicted and described embodiments
of this disclosure are examples only, and are not exhaustive of the
scope of the disclosure.
* * * * *
References