U.S. patent application number 13/473991 was filed with the patent office on 2013-04-04 for semiconductor device and method of manufacture thereof.
This patent application is currently assigned to Mitsubishi Electric Corporation. The applicant listed for this patent is Akira GOTO, Taichi OBARA, Takami OTSUKI. Invention is credited to Akira GOTO, Taichi OBARA, Takami OTSUKI.
Application Number | 20130082283 13/473991 |
Document ID | / |
Family ID | 47991739 |
Filed Date | 2013-04-04 |
United States Patent
Application |
20130082283 |
Kind Code |
A1 |
OTSUKI; Takami ; et
al. |
April 4, 2013 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF
Abstract
A semiconductor device includes an insulating substrate, a
wiring pattern formed on the insulating substrate, a semiconductor
chip secured to the wiring pattern, a junction terminal formed of
the same material as the wiring pattern and electrically connected
to the semiconductor chip, one end of the junction terminal being
secured to the insulating substrate, the other end of the junction
terminal extending upward away from the insulating substrate, and a
control circuit for transmitting a control signal for the
semiconductor chip, the control circuit being electrically
connected to the junction terminal.
Inventors: |
OTSUKI; Takami; (Tokyo,
JP) ; OBARA; Taichi; (Tokyo, JP) ; GOTO;
Akira; (Fukuoka, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
OTSUKI; Takami
OBARA; Taichi
GOTO; Akira |
Tokyo
Tokyo
Fukuoka |
|
JP
JP
JP |
|
|
Assignee: |
Mitsubishi Electric
Corporation
Chiyoda-ku
JP
|
Family ID: |
47991739 |
Appl. No.: |
13/473991 |
Filed: |
May 17, 2012 |
Current U.S.
Class: |
257/77 ; 257/76;
257/773; 257/E21.586; 257/E23.01; 257/E29.002; 257/E29.082;
438/675 |
Current CPC
Class: |
H01L 2924/181 20130101;
H01L 25/162 20130101; H01L 2924/00014 20130101; H01L 2924/13055
20130101; H01L 2224/73265 20130101; H01L 25/50 20130101; H01L
21/4821 20130101; H01L 2224/48091 20130101; H01L 2224/48247
20130101; H01L 23/24 20130101; H01L 2224/48091 20130101; H01L
2924/00 20130101; H01L 2224/45099 20130101; H01L 2924/00014
20130101; H01L 2924/00 20130101; H01L 23/3735 20130101; H01L 24/48
20130101; H01L 2924/181 20130101; H01L 2924/19107 20130101; H01L
23/3121 20130101; H01L 2924/00014 20130101; B22D 19/00 20130101;
B22D 21/04 20130101; H01L 23/49811 20130101; H01L 24/32 20130101;
H01L 24/49 20130101; H01L 2224/49 20130101; H01L 2924/13055
20130101; H01L 2224/32225 20130101; H01L 2224/48137 20130101 |
Class at
Publication: |
257/77 ; 257/773;
257/76; 438/675; 257/E23.01; 257/E29.002; 257/E29.082;
257/E21.586 |
International
Class: |
H01L 29/16 20060101
H01L029/16; H01L 29/02 20060101 H01L029/02; H01L 21/768 20060101
H01L021/768; H01L 23/48 20060101 H01L023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 29, 2011 |
JP |
2011-214412 |
Claims
1. A semiconductor device comprising: an insulating substrate; a
wiring pattern formed on said insulating substrate; a semiconductor
chip secured to said wiring pattern; a junction terminal formed of
the same material as said wiring pattern and electrically connected
to said semiconductor chip, one end of said junction terminal being
secured to said insulating substrate, the other end of said
junction terminal extending upward away from said insulating
substrate; and a control circuit for transmitting a control signal
for said semiconductor chip, said control circuit being
electrically connected to said junction terminal.
2. The semiconductor device according to claim 1, further
comprising: a power terminal formed of the same material as said
wiring pattern and electrically connected to said semiconductor
chip, one end of said power terminal being secured to said
insulating substrate, the other end of said power terminal
extending upward away from said insulating substrate.
3. A semiconductor device comprising: an insulating substrate; a
wiring pattern formed on said insulating substrate and including a
first wiring pattern, a second wiring pattern, and a third wiring
pattern; a semiconductor chip secured to said first wiring pattern;
a junction terminal electrically connected to said semiconductor
chip, one end of said junction terminal being embedded in said
second wiring pattern, the other end of said junction terminal
extending upward away from said insulating substrate; a control
circuit for transmitting a control signal for said semiconductor
chip, said control circuit being electrically connected to said
junction terminal; and a power terminal electrically connected to
said semiconductor chip, one end of said power terminal being
embedded in said third wiring pattern, the other end of said power
terminal extending upward away from said insulating substrate.
4. The semiconductor device according to claim 1, further
comprising a control circuit wiring pattern formed of the same
material as said wiring pattern and provided on said insulating
substrate, wherein said control circuit is secured to said control
circuit wiring pattern.
5. The semiconductor device according to claim 2, further
comprising: a bottom surface pattern formed on a bottom surface of
said insulating substrate; and a molded resin covering said
insulating substrate, said wiring pattern, said semiconductor chip,
said junction terminal, said control circuit, and said power
terminal, and outwardly exposing said other end of said junction
terminal, said other end of said power terminal, and the surface of
said bottom surface pattern opposite that in contact with said
insulating substrate.
6. The semiconductor device according to claim 2, further
comprising: a bottom surface pattern formed on a bottom surface of
said insulating substrate; an adhesive primer formed on a surface
of said wiring pattern and a surface of said insulating substrate;
and a molded resin covering said insulating substrate, said wiring
pattern, said primer, said semiconductor chip, said junction
terminal, said control circuit, and said power terminal, and
outwardly exposing said other end of said junction terminal, said
other end of said power terminal, and the surface of said bottom
surface pattern opposite that in contact with said insulating
substrate.
7. The semiconductor device according to claim 5, wherein the
coefficient of linear expansion of said molded resin is equal to
that of said wiring pattern.
8. The semiconductor device according to claim 1, wherein said
semiconductor chip is formed of a wide bandgap semiconductor.
9. The semiconductor device according to claim 8, wherein said wide
bandgap semiconductor is silicon carbide, gallium nitride-based
material, or diamond.
10. A method of manufacturing a semiconductor device, comprising: a
step of placing an insulating substrate in a mold having a wiring
pattern-forming cavity for forming a wiring pattern on said
insulating substrate and also having a junction terminal-forming
cavity for forming a junction terminal extending upward from said
insulating substrate; an aluminum pouring step of pouring aluminum
into said wiring pattern-forming cavity and said junction
terminal-forming cavity; and a step of cooling said aluminum.
11. The method according to claim 10, wherein: said mold has a
power terminal-forming cavity for forming a power terminal
extending upward from said insulating substrate; and said aluminum
pouring step includes pouring aluminum into said power
terminal-forming cavity.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device
used, e.g., for high power switching, etc., and a method of
manufacture thereof.
[0003] 2. Background Art
[0004] Japanese Laid-Open Patent Publication No. 2002-315357
discloses a semiconductor device in which metal plates serving as
wiring patterns are formed on an insulating substrate. Connection
terminals are secured to the wiring patterns and extend upward away
from the insulating substrate. The connection terminals are used to
connect the semiconductor device and external components.
[0005] The manufacturing process for the semiconductor device
disclosed in the above publication is complicated, since the
connection terminals are secured onto the wiring patterns. As a
result, the semiconductor device disclosed in the publication is
costly to produce.
SUMMARY OF THE INVENTION
[0006] The present invention has been made to solve the foregoing
problem. It is, therefore, an object of the present invention to
provide a semiconductor device suitable for being manufactured at a
reduced cost, and a method of manufacture thereof. The features and
advantages of the present invention may be summarized as
follows.
[0007] According to one aspect of the present invention, a
semiconductor device includes an insulating substrate, a wiring
pattern formed on the insulating substrate, a semiconductor chip
secured to the wiring pattern, a junction terminal formed of the
same material as the wiring pattern and electrically connected to
the semiconductor chip, one end of the junction terminal being
secured to the insulating substrate, the other end of the junction
terminal extending upward away from the insulating substrate, and a
control circuit for transmitting a control signal for the
semiconductor chip, the control circuit being electrically
connected to the junction terminal.
[0008] According to another aspect of the present invention, a
semiconductor device includes an insulating substrate, a wiring
pattern formed on the insulating substrate and including a first
wiring pattern, a second wiring pattern, and a third wiring
pattern, a semiconductor chip secured to the first wiring pattern,
a junction terminal electrically connected to the semiconductor
chip, one end of the junction terminal being embedded in the second
wiring pattern, the other end of the junction terminal extending
upward away from the insulating substrate, a control circuit for
transmitting a control signal for the semiconductor chip, the
control circuit being electrically connected to the junction
terminal, and a power terminal electrically connected to the
semiconductor chip, one end of the power terminal being embedded in
the third wiring pattern, the other end of the power terminal
extending upward away from the insulating substrate.
[0009] According to another aspect of the present invention, a
method of manufacturing a semiconductor device, includes a step of
placing an insulating substrate in a mold having a wiring
pattern-forming cavity for forming a wiring pattern on the
insulating substrate and also having a junction terminal-forming
cavity for forming a junction terminal extending upward from the
insulating substrate, an aluminum pouring step of pouring aluminum
into the wiring pattern-forming cavity and the junction
terminal-forming cavity, and a step of cooling the aluminum.
[0010] Other and further objects, features and advantages of the
invention will appear more fully from the following
description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a cross-sectional view of a semiconductor device
in accordance with a first embodiment of the present invention;
[0012] FIG. 2 is a diagram showing the molds, etc. used by the
semiconductor device manufacturing method of the first
embodiment;
[0013] FIG. 3 is a cross-sectional view of the semiconductor device
of the second embodiment;
[0014] FIG. 4 is a diagram showing the molds, etc. used by the
semiconductor device manufacturing method of the second
embodiment;
[0015] FIG. 5 is a cross-sectional view of the semiconductor device
of the third embodiment;
[0016] FIG. 6 is a cross-sectional view of the semiconductor device
of the fourth embodiment;
[0017] FIG. 7 is a cross-sectional view of the semiconductor device
of the fifth embodiment;
[0018] FIG. 8 is a cross-sectional view of the semiconductor device
of the sixth embodiment;
[0019] FIG. 9 is a diagram showing the molds, etc. used by the
semiconductor device manufacturing method of the sixth
embodiment;
[0020] FIG. 10 is a cross-sectional view showing a semiconductor
device in which a control circuit is secured onto a wiring
pattern;
[0021] FIG. 11 is a cross-sectional view showing a semiconductor
device provided with a molded resin; and
[0022] FIG. 12 is a cross-sectional view showing a semiconductor
device provided with an adhesive primer.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Embodiment
[0023] FIG. 1 is a cross-sectional view of a semiconductor device
in accordance with a first embodiment of the present invention. The
semiconductor device 10 includes an insulating substrate 12. The
insulating substrate 12 is formed, e.g., of AlN, Al.sub.2O.sub.3,
SiN, etc. Wiring patterns 14a and 14b are formed on the insulating
substrate 12. A junction terminal 14c is also formed on the
insulating substrate 12. One end of the junction terminal 14c is
secured to the insulating substrate 12, and the other end of the
junction terminal 14c extends upward away from the insulating
substrate 12. The junction terminal 14c is formed of the same
material as the wiring patterns 14a and 14b.
[0024] A bottom surface pattern 16 is formed on the bottom surface
of the insulating substrate 12. The bottom surface pattern 16 and
the wiring patterns 14a and 14b are formed of aluminum 1-5 mm
thick. A semiconductor chip 20 is secured to the wiring pattern 14b
by solder 18. The semiconductor chip 20 is configured, e.g., from
an IGBT and a diode formed of silicon. The semiconductor chip 20 is
electrically connected to the junction terminal 14c and the wiring
pattern 14a by wires 22.
[0025] A case 26 is secured to the insulating substrate 12 by
adhesives 24a and 24b. The case 26 is formed so as to outwardly
expose the bottom pattern 16. A power terminal 28 is formed along
an inner wall of the case 26. The power terminal 28 is electrically
connected to the semiconductor chip 20 by wires 22.
[0026] Silicon gel 30 is disposed within the case 26. The silicon
gel 30 seals the semiconductor chip 20. The junction terminal 14c
and the power terminal 28 extend through and outwardly from the
silicon gel 30. Outside the silicon gel 30, a control substrate 32
is connected to the junction terminal 14c. A control circuit 34 is
secured to the control substrate 32. The control circuit 34 is
electrically connected to the junction terminal 14c and transmits a
control signal for the semiconductor chip 20. A cover 38 for the
case 26 is mounted above the control substrate 32. A control
terminal 40 is secured to the control substrate 32. The control
terminal 40 extends through and outwardly from the cover 38.
[0027] A method of manufacturing a semiconductor device in
accordance with the first embodiment will now be described. FIG. 2
is a diagram showing the molds, etc. used by the semiconductor
device manufacturing method of the first embodiment. The wiring
patterns 14a and 14b, the junction terminal 14c, the bottom pattern
16 described above are formed by casting. Specifically, they are
formed by use of molds 42 and 44. The mold 42 has formed therein
wiring pattern-forming cavities 14a' and 14b' for forming the
wiring patterns 14a and 14b, respectively, on the insulating
substrate 12. The mold 42 also has formed therein a junction
terminal-forming cavity 14c' for forming the junction terminal 14c
which extends upward from the insulating substrate. The mold 44 has
formed therein a bottom surface pattern-forming cavity 16' for
forming the bottom surface pattern 16. The following steps are
performed using the molds 42 and 44.
[0028] First, the insulating substrate 12 is placed in a cavity
formed by the molds 42 and 44. Molten aluminum is then poured into
the wiring pattern-forming cavities 14a' and 14b', the junction
terminal-forming cavity 14c', and the bottom surface
pattern-forming cavity 16'. This step is referred to as the
aluminum pouring step. Next, the poured aluminum is cooled. The
molds 42 and 44 are then removed from the casting, i.e., the
insulating substrate 12 having the wiring patterns 14a and 14b, the
junction terminal 14c, and the bottom pattern 16 formed thereon.
The semiconductor chip 20 is then soldered to the wiring pattern
14b, and then other steps are performed to form the semiconductor
device 10 shown in FIG. 1.
[0029] The semiconductor device of the first embodiment is
configured such that the junction terminal 14c can be formed at the
same time as the wiring patterns 14a and 14b, etc. by casting.
Therefore, the semiconductor device can be manufactured without the
step of securing the junction terminal to a wiring pattern, making
it possible to manufacture the semiconductor device at a reduced
cost.
Second Embodiment
[0030] A semiconductor device and a method of manufacture thereof
in accordance with a second embodiment of the present invention
have many features common to the first embodiment. Therefore, the
following description of the semiconductor device and the method of
the second embodiment will be primarily limited to the differences
from the first embodiment. FIG. 3 is a cross-sectional view of the
semiconductor device of the second embodiment. The semiconductor
device 50 includes a power terminal 14d. One end of the power
terminal 14d is secured to the insulating substrate 12, and the
other end extends upward away from the insulating substrate 12. The
power terminal 14d is formed of the same material (aluminum) as the
wiring pattern 14b. That is, the power terminal 14d, the wiring
pattern 14b, the junction terminal 14c, and the bottom pattern 16
are all formed of aluminum. It should be noted that the power
terminal 14d is electrically connected to the semiconductor chip 20
by wires 22.
[0031] The method of manufacturing a semiconductor device in
accordance with the second embodiment will now be described. The
semiconductor device manufacturing method of the second embodiment
is basically similar to that of the first embodiment, but uses a
mold of a different configuration. FIG. 4 is a diagram showing the
molds, etc. used by the semiconductor device manufacturing method
of the second embodiment. Specifically, a mold 46 has formed
therein a power terminal-forming cavity 14d' for forming the power
terminal 14d which extends upward from the insulating substrate 12.
In the aluminum pouring step, molten aluminum is poured into the
wiring pattern-forming cavity 14b', the junction terminal-forming
cavity 14c', the power terminal-forming cavity 14d', and the bottom
surface pattern-forming cavity 16'. It should be noted that the
power terminal 14d which has been produced in the power
terminal-forming cavity 14d' is not yet in its final shape. After
the mold 46 is removed from the casting, the portion of the power
terminal 14d extending straight upward from the insulating
substrate 12 is bent into the desired shape, thereby completing the
formation of the power terminal 14d. Thus, in the semiconductor
device manufacturing method of the second embodiment, the wiring
pattern 14b, the junction terminal 14c, the power terminal 14d, and
the bottom surface pattern 16 are formed by casting in the molds 44
and 46.
[0032] The semiconductor device and the method of manufacture
thereof in accordance with the second embodiment are configured
such that the wiring pattern 14b, the junction terminal 14c, the
power terminal 14d, and the bottom surface pattern 16 are cast at
once. This simplifies the manufacturing process, making it possible
to manufacture the semiconductor device at a reduced cost.
Third Embodiment
[0033] A semiconductor device and a method of manufacture thereof
in accordance with a third embodiment of the present invention have
many features common to the first embodiment. Therefore, the
following description of the semiconductor device and the method of
the third embodiment will be primarily limited to the differences
from the first embodiment. FIG. 5 is a cross-sectional view of the
semiconductor device of the third embodiment. The semiconductor
device 60 includes a control circuit wiring pattern 14e formed on
the insulating substrate 12. The control circuit wiring pattern 14e
is formed of the same material (aluminum) as the wiring pattern
14b. That is, the control circuit wiring pattern 14e, the power
terminal 14d, the wiring pattern 14b, the junction terminal 14c,
and the bottom surface pattern 16 are all formed of aluminum. A
control circuit 34 is secured to the control circuit wiring pattern
14e. The control circuit 34 is connected to the semiconductor chip
20 and the junction terminal 14c by wires 22. Further, the control
circuit 34 is sealed by silicon gel 30.
[0034] In the semiconductor device of the third embodiment, the
control circuit 34 is secured to the control circuit wiring pattern
14e, thereby eliminating the need for a control substrate. Further,
in order to allow the semiconductor chip to be connected to an
external device, the semiconductor device of the third embodiment
includes the junction terminal 14c which performs the function of
both the junction terminal and the power terminal of the
semiconductor device shown in FIG. 1. Therefore, the semiconductor
device of the third embodiment can be manufactured at a reduced
cost.
Fourth Embodiment
[0035] A semiconductor device and a method of manufacture thereof
in accordance with a fourth embodiment of the present invention
have many features common to the third embodiment. Therefore, the
following description of the semiconductor device and the method of
the fourth embodiment will be primarily limited to the differences
from the third embodiment. FIG. 6 is a cross-sectional view of the
semiconductor device of the fourth embodiment. The semiconductor
device 70 is provided with a molded resin 72. The molded resin 72
covers the insulating substrate 12, the wiring pattern 14b, the
control circuit wiring pattern 14e, the semiconductor chip 20, the
junction terminal 14c, the control circuit 34, and the power
terminal 14d, and outwardly exposes the surface of the bottom
surface pattern 16 opposite that in contact with the insulating
substrate 12, the distal end of the junction terminal 14c, and the
distal end of the power terminal 14d. The coefficient of linear
expansion of the molded resin 72 is equal to that of the wiring
pattern 14b (i.e., the coefficient of linear expansion of
aluminum).
[0036] The semiconductor device 70 of the fourth embodiment is
provided with the molded resin 72, which eliminates the need for a
case, a cover, and silicon gel, such as those provided in the
semiconductor device of the third embodiment, making it possible to
manufacture the semiconductor device at a. reduced cost. It should
be noted that semiconductor devices of the type described herein
are configured such that the bottom surface pattern on the bottom
surface of the insulating substrate has a much larger surface area
than the wiring patterns on the top surface of the insulating
substrate. This means that the amount of aluminum on the bottom
surface of the insulating substrate is much greater than that on
the top surface of the insulating substrate. As a result it has
been found in some cases that the insulating substrate warps convex
upward due to the shrinkage of the bottom surface pattern caused by
the cooling of the pattern after heating. In the case of the
semiconductor device of the fourth embodiment, however, all the
materials surrounding the insulating substrate have equal
coefficients of linear expansion, since the coefficient of linear
expansion of the molded resin 72 is equal to that of the wiring
pattern 14b, making it possible to prevent warpage of the
insulating substrate 12.
[0037] Although the constituent materials of the molded resin 72
have not been specified, it is to be understood that the molded
resin 72 may be epoxy resin containing a filler such as glass or
silica. The use of such a filler makes it easy to adjust the
coefficient of linear expansion of the molded resin 72 to be equal
to that of aluminum. Alternatively, the molded resin 72 may be an
optimum type of resin for that purpose and does not contain filler.
For example, the molded resin 72 may be phenol resin. It should be
noted that the only requirement for the coefficient of linear
expansion of the molded resin 72 is that it be sufficiently close
to the coefficient of linear expansion of aluminum to prevent
warpage of the insulating substrate 12. Therefore, the coefficient
of linear expansion of the molded resin 72 need not be equal to
that of aluminum if it is possible to prevent warpage of the
insulating substrate 12.
Fifth Embodiment
[0038] A semiconductor device and a method of manufacture thereof
in accordance with a fifth embodiment of the present invention have
many features common to the fourth embodiment. Therefore, the
following description of the semiconductor device and the method of
the fifth embodiment will be primarily limited to the differences
from the fourth embodiment. FIG. 7 is a cross-sectional view of the
semiconductor device of the fifth embodiment. The semiconductor
device 74 includes an adhesive primer 76 formed on the surface of
the wiring patterns (of aluminum) and on the surface of the
insulating substrate 12. The adhesive primer 76 serves to increase
the adhesion between the molded resin 72 and the insulating
substrate 12. Thus in the semiconductor device of the fifth
embodiment, substantial adhesion between the molded resin 72 and
the insulating substrate 12 is ensured by use of the adhesive
primer 76.
Sixth Embodiment
[0039] A semiconductor device and a method of manufacture thereof
in accordance with a sixth embodiment of the present invention have
many features common to the first embodiment. Therefore, the
following description of the semiconductor device and the method of
the sixth embodiment will be primarily limited to the differences
from the first embodiment. FIG. 8 is a cross-sectional view of the
semiconductor device of the sixth embodiment. The semiconductor
device 80 is characterized in that one end of a junction terminal
82 and one end of a power terminal 84 are embedded in their
respective wiring patterns.
[0040] The insulating substrate 12 has a first wiring pattern 14f,
a second wiring pattern 14g, and a third wiring pattern 14h formed
thereon. The first wiring pattern 14f, the second wiring pattern
14g, and the third wiring pattern 14h are sometimes hereinafter
referred to collectively as the "wiring patterns." The
semiconductor chip 20 is secured onto the first wiring pattern
14f.
[0041] The semiconductor device 80 is provided with the junction
terminal 82. One end of the junction terminal 82 is embedded in the
second wiring pattern 14g, and the other end of the junction
terminal 82 extends upward away from the insulating substrate 12
and is connected to the control substrate 32. The junction terminal
82 is electrically connected to the semiconductor chip 20 by way of
the second wiring pattern 14g and a wire 22. The control circuit
34, which transmits a control signal for the semiconductor chip 20,
is electrically connected to the other end (i.e., the distal end)
of the junction terminal 82.
[0042] The semiconductor device 80 is also provided with the power
terminal 84. One end of the power terminal 84 is embedded in the
third wiring pattern 14h, and the other end of the power terminal
84 extends upward away from the insulating substrate 12. The power
terminal 84 is electrically connected to the semiconductor chip
20.
[0043] FIG. 9 is a diagram showing the molds, etc. used by the
semiconductor device manufacturing method of the sixth embodiment.
Specifically, the method uses the mold 44 (described above in
connection with the first embodiment) and a mold 86. The mold 86
has formed therein a first wiring pattern-forming cavity 14f' for
forming the first wiring pattern 14f, a second wiring
pattern-forming cavity 14g' for forming the second wiring pattern
14g, and a third wiring pattern-forming cavity 14h' for forming the
third wiring pattern 14h. The first wiring pattern 14f, the second
wiring pattern 14g, the third wiring pattern 14h, and the bottom
surface pattern 16 are formed on the insulating substrate 12 using
the molds 44 and 86. More specifically, molten aluminum is poured
into the molds 44 and 86 with the junction terminal 82 and the
power terminal 84 inserted into the mold 86 so that one end of the
junction terminal 82 is embedded into the second wiring pattern 14g
and one end of the power terminal 84 is embedded into the third
wiring pattern 14h. It should be noted that when the mold 86 has
been removed from the casting, the power terminal 14d is not yet in
its final shape and extends straight upward from the insulating
substrate 12. Therefore, after the removal of the mold 86, the
power terminal 14d is bent into its final shape.
[0044] The semiconductor device and the method of manufacture
thereof in accordance with the sixth embodiment are configured such
that the junction terminal 82 and the power terminal 84 are secured
to wiring patterns at the same time as when the wiring patterns are
formed, making it possible to simplify the manufacturing process.
It should be noted that it has been found difficult to form, at a
reasonable cost, a mold for forming a junction terminal and a power
terminal if these terminals have a complicated shape. In the
semiconductor device and the method of manufacture thereof in
accordance with the sixth embodiment, however, the junction
terminal and the power terminal are embedded in wiring patterns,
thereby eliminating the need to match the shape of the molds to
that of the junction terminal and the power terminal. This makes it
possible to manufacture semiconductor devices having a junction
terminal and a power terminal of a complicated configuration by a
simple process.
[0045] The semiconductor device and the method of manufacture
thereof in accordance with the sixth embodiment may be combined
with the above-described various techniques to further reduce cost.
FIG. 10 is a cross-sectional view showing a semiconductor device in
which a control circuit is secured onto a wiring pattern. This
configuration does not require a control substrate, resulting in a
reduced cost. FIG. 11 is a cross-sectional view showing a
semiconductor device provided with a molded resin. The use of the
molded resin 72 eliminates the need for a case, a cover, and
silicon gel, such as those provided in the semiconductor device of
the first embodiment, resulting in a reduced cost. FIG. 12 is a
cross-sectional view showing a semiconductor device provided with
an adhesive primer. This configuration results in improved
reliability, as compared to the configuration shown in FIG. 11.
[0046] Although in the first to sixth embodiments described above
the semiconductor chip 20 is formed of silicon, it is to be
understood that it may be formed of a wide bandgap semiconductor
having a wider bandgap than silicon. Examples of wide bandgap
semiconductors include silicon carbide, gallium nitride-based
materials, and diamond. IGBTs and diodes formed of wide bandgap
semiconductor have a high maximum allowable current density, making
it possible to reduce their size.
[0047] In accordance with the present invention, there are provided
semiconductor devices suitable for being manufactured at a reduced
cost, and a method of manufacture thereof.
[0048] Obviously many modifications and variations of the present
invention are possible in the light of the above teachings. It is
therefore to be understood that within the scope of the appended
claims the invention may be practiced otherwise than as
specifically described.
[0049] The entire disclosure of a Japanese Patent Application No.
2011-214412, filed on Sep. 29, 2011 including specification,
claims, drawings and summary, on which the Convention priority of
the present application is based, are incorporated herein by
reference in its entirety.
* * * * *