U.S. patent application number 13/618247 was filed with the patent office on 2013-03-28 for dual pci-x/pci-e card.
This patent application is currently assigned to Broadcom Coporation. The applicant listed for this patent is Charles J. PURWIN. Invention is credited to Charles J. PURWIN.
Application Number | 20130080675 13/618247 |
Document ID | / |
Family ID | 35636735 |
Filed Date | 2013-03-28 |
United States Patent
Application |
20130080675 |
Kind Code |
A1 |
PURWIN; Charles J. |
March 28, 2013 |
Dual PCI-X/PCI-E Card
Abstract
A dual bus interface PCB includes a main chipset component, a
first type bus interface connector, and a second type bus interface
connector. The PCB can be configured at fabrication time to enable
a variety of configurations for operation. Optionally, the PCB can
also be provided at least one memory chip and a NIC (Network
Interface Card) chip. By virtue of having a dual interface, the PCB
can be used with either the first type or the second type bus.
Furthermore, the dual interface PCB eliminates the need by chipset
manufacturers to carry multiple PCB variations of the same product
in order to support various bus interfaces. In one embodiment, the
PCB is a dual PCI-X/PCI-E interface PCB.
Inventors: |
PURWIN; Charles J.;
(Litchfield, NH) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
PURWIN; Charles J. |
Litchfield |
NH |
US |
|
|
Assignee: |
Broadcom Coporation
Irvine
CA
|
Family ID: |
35636735 |
Appl. No.: |
13/618247 |
Filed: |
September 14, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11037177 |
Jan 19, 2005 |
|
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13618247 |
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Current U.S.
Class: |
710/301 |
Current CPC
Class: |
H05K 1/117 20130101;
H05K 2201/09954 20130101; H05K 1/181 20130101; H05K 1/0295
20130101 |
Class at
Publication: |
710/301 |
International
Class: |
G06F 13/00 20060101
G06F013/00 |
Claims
1. A circuit board assembly, comprising: a circuit board; a first
bus interface connector mounted to the circuit board, the first bus
interface connector configured for a first interface protocol; a
second bus interface connector mounted to the circuit board, the
second bus interface configured for a second interface protocol; an
integrated circuit chip mounted to the circuit board and configured
to interface with at least one of the first and second bus
interface connectors; a first connector port selectively coupled to
the integrated circuit chip when the first bus interface connector
is enabled; and a second connector port selectively coupled to the
integrated circuit chip when the second bus interface connector is
enabled.
2. The circuit board assembly of claim 1, wherein the circuit board
is insertable into a motherboard by selectively inserting either
the first or the second interface connector into a corresponding
slot of the motherboard.
3. The circuit board assembly of claim 1, wherein the integrated
circuit chip is mounted to a first surface of the circuit board,
and wherein the first and second connector ports are mounted onto a
second surface of the circuit board.
4. The circuit hoard assembly of claim 3, wherein the first and
second connector ports are mounted in a central region of the
second surface of the circuit board.
5. The circuit board assembly of claim 1, further comprising: a
first set of signal traces routed from the integrated circuit chip
to the first bus interface connector; and a second set of signal
traces routed from the integrated circuit chip to the second bus
interface connector.
6. The circuit board assembly of claim 1, wherein the first bus
interface connector comprises a Peripheral Component
Interconnect-Extended (PCI-X) bus interface connector, and the
second bus interface connector comprises a Peripheral Component
Interconnect-Express (PCI-X) bus interface connector.
7. The circuit board assembly of claim 1, wherein the first and
second connector ports comprise SATA/SAS connector ports.
8. The circuit board assembly of claim 1, further comprising: a
memory chip mounted to the circuit board and coupled to the
integrated circuit chip.
9. The circuit board assembly of claim 1, wherein the integrated
circuit chip comprises a RAID controller.
10. The circuit board assembly of claim 9, wherein the first and
second connector ports connect the RAID controller to an array of
disk drives.
11. The circuit board assembly of claim 1, wherein the first bus
interface connector and the second bus interface connector are
mounted on opposite edges of the circuit board.
12. The circuit board assembly of claim 1, further comprising: a
Network Interface Card (NIC) chip mounted to the circuit board and
coupled to the integrated circuit; and an Ethernet connected
mounted to the circuit board and coupled to the NIC chip.
13. The circuit board assembly of claim 1, wherein the first bus
interface connector and the second bus interface connector are both
enabled.
14. A circuit board assembly, comprising: a circuit board; a first
bus interface connector mounted to the circuit board, the first bus
interface connector configured for a first interface protocol; a
second bus interface connector mounted to the circuit board, the
second bus interface configured for a second interface protocol; a
first connector port mounted to the circuit board, the first
connector port enabled when the first interface protocol is used by
the circuit board assembly; and a second connector port mounted to
the circuit board, the second connector port enabled when the
second interface protocol is used by the circuit board
assembly.
15. The circuit board assembly of claim 14, further comprising: an
integrated circuit chip mounted to the circuit board and configured
to interface with at least one of the first and second bus
interface connectors.
16. The circuit board assembly of claim 15, wherein the first
connector port is coupled to the integrated circuit chip when the
first interface protocol is used by the circuit board assembly, and
wherein the second connector port is coupled to the integrated
circuit when the second interface protocol is used by the circuit
board assembly.
17. The circuit board assembly of claim 14, wherein the first bus
interface connector comprises a Peripheral Component
Interconnect-Extended (PCI-X) bus interface connector, and the
second bus interface connector comprises a Peripheral Component
Interconnect-Express (PCI-E) bus interface connector.
18. A method of making a dual bus interface circuit board,
comprising: mounting a first bus interface connector and a second
bus interface connector onto opposite edges of a circuit board;
mounting an integrated circuit chip on the circuit board; routing a
first set of signal traces and a second set of signal traces from
the integrated circuit chip to the first and second bus interface
connectors, respectively; coupling a first connector port to the
integrated circuit chip when the first bus interface connector is
enabled; and coupling a second connector port to the integrated
circuit chip when the second bus interface connector is
enabled.
19. The method of claim 18, further comprising: selectively
mounting resistors at first ends of at least one of the first and
the second sets of signal traces to selectively enable at least one
of the first and second bus interface connectors.
20. The method of claim 18, wherein the first bus interface
connector comprises a Peripheral Component Interconnect-Extended
(PCI-X) bus interface connector, and the second bus interface
connector comprises a Peripheral Component Interconnect-Express
(PCI-E) bus interface connector.
Description
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] This application is a continuation of U.S. application Ser.
No. 11/037,177, filed Jan. 19, 2005, which is incorporated herein
by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention herein relates in general to a dual bus
interface printed circuit board (PCB) and more particularly to a
PCB provided with both a PCI-X (Peripheral Component
Interconnect--Extended) bus interface and a PCI-E (Peripheral
Component Interconnect--Express) bus interface.
[0004] 2. Background Art
[0005] In the field of I/O Interconnect, PCI (Peripheral Component
Interconnect) is a widely adopted I/O bus standard in a wide
variety of computer platforms. To meet the growing demand for
bandwidth by new applications, PCI has gone through several changes
in the last decade leading to extension standards such as PCI-2.2
and PCI-X (PCI--Extended). These extension standards however are
all built on the same architecture, protocols, signals, and
connector as the conventional PCI, the reuse having been mainly
supported by the combination of backward compatibility and the ease
of migration from the conventional PCI to the newer standards.
[0006] The conventional PCI architecture is based on a multi-drop,
parallel bus implementation, with one local bus being shared by
multiple peripheral devices to communicate with the central
processing unit (CPU). When first developed, the PCI architecture
solved some of the limitations of the previous bus standards such
as ISA (Industry Standard Architecture) and EISA (Extended ISA), by
allowing direct access of peripheral devices to the CPU. However,
with the exponential growth of CPU power, bus technology based on
the conventional PCI architecture is becoming more and more a
bottleneck to enhanced system performance. The main reason for that
being that a shared bus technology suffers from a scalability
problem, limiting the number of peripherals that can be efficiently
supported by a system.
[0007] At its current state, the conventional PCI bus technology is
theoretically very close to its practical limits, with only minor
performance gains possible at large costs in form factor. It is for
this reason therefore that the conventional PCI architecture is
slowly giving way to a new standard known as the PCI-E
(PCI--Express) standard.
[0008] The PCI-E architecture is based on a series of
point-to-point connections, with each connection employing a
packet-based transfer scheme and supporting bidirectional
communication. To meet the varying bandwidth needs of different
system components, PCI-E can be easily scaled from one to 32 lanes,
with a single lane providing 250 MB/sec of dedicated bandwidth in
each direction. In addition to providing ample bandwidth, PCI-E
also supports advanced power management, hot plugging, and its
packet-based transfer protocol allows for time dependent data
delivery and quality of service arbitration for high priority data
streams.
[0009] Although PCI-E clearly provides major performance
improvements compared to the conventional PCI standard and its
extensions (parallel PCI), serial PCI-E is not backward compatible
with parallel PCI, and the shift from parallel PCI to PCI-E is
likely to be a slow one. It is expected that parallel PCI will
coexist in many platforms with PCI-E to support today's lower
bandwidth applications, until a compelling need, such as a new form
factor, causes a full migration to fully PCI-E systems.
[0010] Foreseeing the coexistence of PCI and PCI-E in future
platforms, chip makers have been designing dual PCI-X/PCI-E
chipsets that can be operated with either of the two bus standards.
Currently available PCBs, however, are designed for use with only a
single bus standard, providing a single bus connector per card. As
a result, dual bus chipsets have to be mounted on multiple PCB
variations to support the various bus interface types, denying the
user the interface duality of the chipset component, and running
higher fabrication costs to chipset manufacturers.
[0011] The likely coexistence of the PCI-X and the PCI-E bus
standards in future computer platforms necessitates efficient
solutions to ensure the interoperability of the two. As PCI-E is
not backward compatible with the conventional PCI standard, of
which PCI-X is an extension, chipset manufacturers currently resort
to carrying multiple PCB variations of the same product in order to
support various bus interfaces. This solution is clearly a costly
and inefficient one from a fabrication process point of view.
[0012] What is needed therefore is a dual interface PCB card that
provides both PCI-X and PCI-E functionality.
BRIEF SUMMARY OF THE INVENTION
[0013] The present invention is directed to a PCB having multiple
different bus interface connectors, and a chipset that supports the
multiple bus interfaces. In an embodiment, the present invention
includes a dual PCI-X/PCI-E interface PCB. As a result, the dual
interface functionality of a PCI-X/PCI-E chipset can be fully taken
advantage of by the user, operating the chipset on either a PCI-X
or a PCI-E bus. Furthermore, chipset fabrication costs can be
reduced as well as the fabrication process simplified, by the
production of a single dual bus interface PCB instead of multiple
board variations to support various bus interface types.
[0014] Further embodiments, features, and advantages of the present
invention, as well as the structure and operation of the various
embodiments of the present invention, are described in detail below
with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES
[0015] The accompanying drawings, which are incorporated herein and
form a part of the specification, illustrate the present invention
and, together with the description, further serve to explain the
principles of the invention and to enable a person skilled in the
pertinent art to make and use the invention.
[0016] FIG. 1A is a top view diagram of a dual-interface PCB
100.
[0017] FIG. 1B is another top view diagram of the dual-interface
PCB 100.
[0018] FIG. 2A is a top view diagram of the dual-interface PCB 100
in a PCI-X configuration.
[0019] FIG. 2B is another top view diagram of the dual-interface
PCB 100 in a PCI-X configuration.
[0020] FIG. 3A is a top view diagram of the dual-interface PCB 100
in a PCI-E configuration.
[0021] FIG. 3B is another top view diagram of the dual-interface
PCB 100 in a PCI-E configuration.
[0022] FIG. 3C is another top view diagram of the dual-interface
PCB 100 in a PCI-E configuration.
[0023] FIG. 3D is another top view diagram of the dual-interface
PCB 100 in a PCI-E configuration.
[0024] FIG. 4 is another top view diagram of the dual-interface PCB
100.
[0025] FIG. 5 is a side view diagram of the dual-interface PCB
100.
[0026] FIG. 6 is a 3D view diagram of the dual-interface PCB
100.
[0027] The present invention will be described with reference to
the accompanying drawings. The drawing in which an element first
appears is typically indicated by the leftmost digit(s) in the
corresponding reference number.
DETAILED DESCRIPTION OF THE INVENTION
Overview
[0028] FIG. 1A shows a top view of an example dual-interface PCB
100 according to the present invention. In the example, the PCB 100
includes a main chipset 110, a first interface connector 120A, a
second interface connector 120B, and two pairs of screw holes 130A
and 130B located on edges A and B of the PCB 100, respectively. The
main chipset 110 is an electronic chipset that supports two
different types of bus interfaces. The two pairs of screw holes
130A and 1308 allow the PCB 100 to be attached to a computer case
from either edge A or edge B. Other attachment mechanisms can also
be employed.
[0029] In the example of FIG. 1A, the interface connectors 120A and
120B are illustrated at opposite edges of the PCB 100. The
invention is not, however, limited to this example. Based on the
description herein, one skilled in the relevant art(s) will
understand that connectors 120A and 120B can be positioned on
adjacent edges or on the same edge of PCB 100.
[0030] In another example embodiment, shown in FIG. 1B, the main
chipset 110 is a RAID (Redundant Arrays of Inexpensive Disks)
controller chipset. The interface connector 120A is a PCI-E bus
interface connector. The interface connector 120B is a PCI-X bus
interface connector. Connector ports 150A and 150B are placed on
edge A and edge B of the PCB, respectively. The connector ports
150A and 150B are used to interface the RAID controller chipset 110
to an array of disk drives (not shown in the diagram). Signal
traces 140A and 160A are routed from the main chipset 110 toward
edge A of the PCB and interface connector 120A, respectively.
Similarly, signal traces 140B and 160B are routed from the main
chipset 110 toward edge B of the PCB and interface connector 120B,
respectively. Surface mount/through hole resistors can be mounted
at the main chipset's ends of signal traces 140A, 140B, 160A, and
160B to connect the main chipset 110 to connector ports 150A,
connector ports 150B, interface connector, 120A, and interface
connector 120B, respectively. In the exemplary embodiment shown,
the PCB 100 is configured such that the interface connector 120B
and connector ports 150A are enabled.
[0031] In the example of FIG. 1B, connector ports 150A and 150B are
illustrated on opposite edges of the PCB 100. The invention is not,
however, limited to this example. Based on the description herein,
one skilled in the relevant art(s) will understand that connector
ports 150A and 150B can be positioned on adjacent edges or on a
surface of PCB 100.
[0032] In an embodiment, connector ports 150A or 150B are
optionally attached to the PCB at the end of the fabrication
process. The PCB configuration would have been determined then,
and, connector ports 150A or 150B would be attached as necessary.
In another embodiment, each of connector ports 150A and 150B
include a set of 8 SATA/SAS (Serial Advanced Technology
Attachment/Serial Attached SCSI) connector ports.
[0033] FIG. 2A shows a top view of the dual-interface PCB 100 in a
PCI-X configuration. Surface mount/through hole resistors 210 are
mounted at the main chipset's ends of signal traces 140A to connect
the main chipset 110 to connector ports 150A. Similarly, surface
mount/through hole resistors 230 are mounted at the main chipset's
ends of signal traces 160B to connect the main chipset 110 to PCI-X
interface connector 120B.
[0034] A mounting bracket 220B is attached to edge B of the PCB.
The bracket 220B allows the PCB to be fixed from edge B to a
computer system's case, such that PCI-X connector 120B can be
inserted into a matching PCI-X slot on the computer system's
motherboard.
[0035] In this example of FIG. 2A, the PCI-E interface connector
120A is not enabled, and no connector ports 150B are placed on edge
B of the PCB. Signal traces 140B and 160A however are still laid
out on the PCB.
[0036] FIG. 2B shows another top view of the dual-interface PCB 100
in a PCI-X configuration. For ease of illustration, signal traces
140B are omitted from the drawing. A cache memory chip 240 is
optionally provided on board the PCB 100. Signal traces 260 connect
the main chipset 110 to the memory chip 240. The memory chip 240
serves to improve the performance of the main chipset 110, by
providing it quick access to a nearby memory cache. While a single
memory chip 240 is shown in the diagram, it should be obvious to
one skilled in the art that additional memory chips can also be
used in this and/or other embodiments of the PCB 100.
[0037] FIG. 3A shows a top view of the dual-interface PCB 100 in a
PCI-E configuration. In the embodiment, surface mount/through hole
resistors 310 are mounted at the main chipset's ends of signal
traces 140B to connect the main chipset 110 to connector ports
150B. Similarly, surface mount/through hole resistors 330 are
mounted at the main chipset's ends of signal traces 160A to connect
the main chipset 110 to PCI-X interface connector 120A. A mounting
bracket 220A is attached to edge A of the PCB 100. The bracket 220A
allows the PCB to be fixed from edge A to a computer system's case,
such that the PCI-E connector 120A can be inserted into a matching
PCI-E slot on the computer system's motherboard. In this exemplary
embodiment, the PCI-X interface connector 120B is not enabled, and
no connector ports 150A are placed on edge A of the PCB. Signal
traces 140A and 160B however are still laid out on the PCB.
[0038] FIG. 3B shows another top view of the dual-interface PCB 100
in a PCI-E configuration. For ease of illustration, signal traces
140A are omitted from the drawing. In this embodiment, a cache
memory chip 340 is optionally provided on board the PCB 100. Signal
traces 360 connect the main chipset 110 to the memory chip 340. The
memory chip 340 serves to improve the performance of the main
chipset 110, by providing it quick access to a nearby memory cache.
While a single memory chip 340 is shown in the diagram, it should
be obvious to one skilled in the art that additional memory chips
can also be used in this and/or other embodiments of the PCB
100.
[0039] FIG. 3C shows another top view of the dual-interface PCB 100
in a PCI-E configuration. In this embodiment, a NIC (Network
Interface Card) chip 360 is provided on the PCB 100. Signal traces
370 are routed from the main chipset 110 to the NIC chip 360. An
Ethernet connector 380 is attached onto edge B of the PCB 100. The
connector 380 can be, for example, an RJ45 connector. Signal traces
140A and 160B are omitted from the drawing for convenience.
[0040] FIG. 3D is another top view of the dual-interface PCB 100 in
a PCI-E configuration. In this embodiment, depending on the number
of I/O pins provided on the main chipset 110, the PCI-X interface
connector 120B and/or the NIC chip 360 can be enabled. Some of the
I/O pins of the main chipset 110 can be configured to be used by
either the interface connector 120B or the NIC chip 360. The
selection of a configuration is optionally made at fabrication time
through the use of surface mount/through hole resistors to enable
selected traces on the PCB 100. FIG. 3D shows a configuration
wherein signal traces 370 are enabled but signal traces 160B are
not, resulting in a connected NIC chip 360 but a disconnected PCI-X
bus interface 120B.
[0041] In FIG. 4, signal traces 140A, 140B, 160A, and 160B are all
enabled. As a result, in this configuration, both interface
connectors 120A and 120B, as well as connector ports 150A and 150B,
are operational. No mounting bracket is shown in FIG. 4, but one
can be attached to edge A and/or B of the PCB 100.
[0042] The PCB 100 can be used with either a PCI-X or a PCI-E bus
interface. The switching from using one interface to using the
other is achieved by transferring the mounting bracket from one
edge to the other, rotating the PCB 180.degree. degrees, and
plugging the desired bus interface connector into a matching bus
slot on the computer system's motherboard.
[0043] FIG. 5 shows a side view of the dual-interface PCB 100. In
this embodiment, connector ports 150A and 150B are attached
centrally onto a surface of the PCB 100, instead of being placed on
opposite edges A and B. The configuration frees area of the PCB
100, while still allowing an easy attachment of a matching cable at
connector ports 150A and/or 150B. In the exemplary embodiment shown
in FIG. 5, the PCB 100 is ready for use in a PCI-X configuration
with the mounting brackets 220B attached to edge B of the PCB.
Connector ports 150A would be used in this configuration.
[0044] FIG. 6 shows a 3D view of the dual-interface PCB 100 mounted
onto a motherboard 610 of a computer system. The motherboard 610 is
shown provided with both a PCI-X bus slot 620 and a PCI-E bus slot
630. The PCB 100 is shown used in the PCI-E configuration with the
PCI-E bus connector 120A connected to the PCI-E slot 630. Connector
ports 150B are shown connected to matching SATA/SAS cables, also
connected to the array of disk drives.
[0045] The present invention puts forward a novel solution in the
form of a dual interface PCB. The dual interface PCB of the current
invention is easily configurable at fabrication time, and can
support a number of different variations.
[0046] While the invention is described herein in view of a dual
PCI-X/PCI-E interface PCB, the scope of the invention should not be
limited by the type of interfaces supported by the PCB. It also
should be noted that the PCB layouts provided in the accompanying
drawings have been presented by way of example only, and not
limitation.
CONCLUSION
[0047] While specific configurations and arrangements are
discussed, it should be understood that this is done for
illustrative purposes only. A person skilled in the pertinent art
will recognize that other configurations and arrangements can be
used without departing from the spirit and scope of the present
invention. It will be apparent to a person skilled in the pertinent
art that this invention can also be employed in a variety of other
applications.
[0048] While various embodiments of the present invention have been
described above, it should be understood that they have been
presented by way of example only, and not limitation. It will be
apparent to persons skilled in the relevant art that various
changes in form and detail can be made therein without departing
from the spirit and scope of the invention. Thus, the breadth and
scope of the present invention should not be limited by any of the
above-described exemplary embodiments, but should be defined only
in accordance with the following claims and their equivalents.
* * * * *