U.S. patent application number 13/666980 was filed with the patent office on 2013-03-07 for method for fabricating a semiconductor structure.
This patent application is currently assigned to UNITED MICROELECTRONICS CORP.. The applicant listed for this patent is United Microelectronics Corp.. Invention is credited to Lung-En Kuo.
Application Number | 20130059441 13/666980 |
Document ID | / |
Family ID | 45556456 |
Filed Date | 2013-03-07 |
United States Patent
Application |
20130059441 |
Kind Code |
A1 |
Kuo; Lung-En |
March 7, 2013 |
METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE
Abstract
A method for fabricating a semiconductor structure is disclosed.
The method includes the steps of: providing a substrate; depositing
a material layer on the substrate; forming at least one dielectric
layer on the material layer; forming a patterned resist on the
dielectric layer; performing a first trimming process on at least
the patterned resist; and performing a second trimming process on
at least the dielectric layer, wherein the second trimming process
comprises trimming greater than 70% of a total trimming value.
Inventors: |
Kuo; Lung-En; (Tainan City,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
United Microelectronics Corp.; |
Hsin-Chu City |
|
TW |
|
|
Assignee: |
UNITED MICROELECTRONICS
CORP.
Hsin-Chu City
TW
|
Family ID: |
45556456 |
Appl. No.: |
13/666980 |
Filed: |
November 2, 2012 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
12851550 |
Aug 5, 2010 |
8329594 |
|
|
13666980 |
|
|
|
|
Current U.S.
Class: |
438/694 ;
257/E21.214 |
Current CPC
Class: |
H01L 21/32139 20130101;
H01L 21/28123 20130101 |
Class at
Publication: |
438/694 ;
257/E21.214 |
International
Class: |
H01L 21/302 20060101
H01L021/302 |
Claims
1. A method for fabricating a semiconductor structure, comprising
the steps of: providing a substrate; depositing a material layer on
the substrate; forming at least one dielectric layer on the
material layer; forming a patterned resist on the dielectric layer;
performing a first trimming process on at least the patterned
resist; and performing a second trimming process on at least the
dielectric layer, wherein the second trimming process comprises
trimming greater than 70% of a total trimming value.
2. The method of claim 1, wherein the material layer comprises
silicon, polysilicon layer or metal.
3. The method of claim 1, further comprising calculating a fixed
time of the second trimming process after trimming greater than 70%
of the total trimming value.
4. The method of claim 1, wherein the at least one dielectric layer
comprises a bottom anti-reflective coating (BARC) and a hard
mask.
5. The method of claim 4, further comprising: performing the first
trimming process on the patterned resist; using the patterned
resist for etching the BARC; performing the second trimming process
on the patterned resist and the BARC; using the patterned resist
and the BARC to etch the hard mask for exposing the material layer;
performing a third trimming process on the BARC and the hard mask;
and using the BARC and the hard mask for etching the material
layer.
6. The method of claim 4, further comprising: performing the first
trimming process on the patterned resist and the BARC; using the
patterned resist and the BARC to etch the hard mask for exposing
the material layer; performing the second trimming process on the
BARC and the hard mask; and using the BARC and the hard mask for
etching the material layer.
7. The method of claim 1, wherein the at least one dielectric layer
comprises a dielectric anti-reflective coating (DARC), an advanced
patterning film (APF), and a hard mask.
8. The method of claim 7, further comprising: performing the first
trimming process on the patterned resist and the DARC; using the
patterned resist and the DARC for etching the APF; performing the
second trimming process on the DARC and the APF; and using the DARC
and the APF to etch the hard mask for exposing the material layer;
and performing a third trimming process on the APF and the hard
mask; and using the APF and the hard mask for etching the material
layer.
9. The method of claim 7, further comprising: performing the first
trimming process on the patterned resist and the DARC; using the
patterned resist and the DARC for etching the APF and the hard mask
for exposing the material layer; performing the second trimming
process on the APF and the hard mask; and using the APF and the
hard mask for etching the material layer.
10. The method of claim 1, wherein the second trimming process is
conducted according to a fixed time for controlling the width
difference between the top of the material layer and the bottom of
the material layer no more than 10%.
11. The method of claim 1, wherein the second trimming process is
performed on at least the dielectric layer after exposing the
material layer.
12. A method for fabricating a semiconductor structure, comprising
the steps of: providing a substrate; depositing a material layer on
the substrate; forming at least one dielectric layer on the
material layer; forming a patterned resist on the dielectric layer;
performing a first trimming process on at least the patterned
resist; and performing a second trimming process on at least the
dielectric layer after exposing the material layer.
13. The method of claim 12, wherein the material layer comprises
silicon, polysilicon layer or metal.
14. The method of claim 12 further comprising calculating a fixed
time of the second trimming process after trimming greater than 70%
of the total trimming value.
15. The method of claim 12, wherein the at least one dielectric
layer comprises a bottom anti-reflective coating (BARC) and a hard
mask.
16. The method of claim 15, further comprising: performing the
first trimming process on the patterned resist; using the patterned
resist for etching the BARC; performing the second trimming process
on the patterned resist and the BARC; using the patterned resist
and the BARC to etch the hard mask for exposing the material layer;
performing a third trimming process on the BARC and the hard mask;
and using the BARC and the hard mask for etching the material
layer.
17. The method of claim 15, further comprising: performing the
first trimming process on the patterned resist and the BARC; using
the patterned resist and the BARC to etch the hard mask for
exposing the material layer; performing the second trimming process
on the BARC and the hard mask; and using the BARC and the hard mask
for etching the material layer.
18. The method of claim 12, wherein the at least one dielectric
layer comprises a dielectric anti-reflective coating (DARC), an
advanced patterning film (APF), and a hard mask.
19. The method of claim 18, further comprising: performing the
first trimming process on the patterned resist and the DARC; using
the patterned resist and the DARC for etching the APF; performing
the second trimming process on the DARC and the APF; and using the
DARC and the APF to etch the hard mask for exposing the material
layer; and performing a third trimming process on the APF and the
hard mask; and using the APF and the hard mask for etching the
material layer.
20. The method of claim 18, further comprising: performing the
first trimming process on the patterned resist and the DARC; using
the patterned resist and the DARC for etching the APF and the hard
mask for exposing the material layer; performing the second
trimming process on the APF and the hard mask; and using the APF
and the hard mask for etching the material layer.
21. The method of claim 12, wherein the second trimming process is
conducted according to a fixed time for controlling the width
difference between the top of the material layer and the bottom of
the material layer no more than 10%.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a continuation application of U.S. patent
application Ser. No. 12/851,550, filed on Aug. 5, 2010, and all
benefits of such earlier application are hereby claimed for this
new continuation application.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention relates to a method for fabricating a
semiconductor structure, and more particularly, to a method of
trimming hard mask for forming a gate electrode layer of a MOS
structure.
[0004] 2. Description of the Prior Art
[0005] During the process of manufacturing metal oxide
semiconductor transistors (MOS transistors), the formation of a
conductive gate plays an important role. In order to meet the
demand of miniaturization of the semiconductor industry, the
current channel length under the gate must meet the standard of
less than 35 nm. To meet the less than 35 nm channel length
requirement, it is crucial to control the critical dimension (CD)
during the process of exposure of the gate so as to control the
line width of the conductive layer (poly-Si layer for example)
after the etching process. Because the current lithographic tool
techniques are incapable of obtaining the ideal CD, trimming
methods are employed in some prior art methods to reduce the size
of gate line width. However, most photo resist layers useful in the
current gate exposure process are 193 nm photo resist layers which
are intrinsically less resistant to the etching condition than 365
nm photo resist layers are on account of acrylic and cycloalkenyl
polymer composition in contrast to 365 nm photo resist layers
composed of aryl moiety. Furthermore, the thickness of 193 nm photo
resist layers reduces as the exposure wavelength shortens. Under
the dual disadvantages of poor etching resistance and less and less
thickness, it is hard for 193 nm photo resist layers to meet the
minimum requirement of 30 nm owing to the available thickness being
10 nm or less during the trimming process on 193 nm photo resist
layers.
[0006] In order to overcome the problem, the current techniques
deals with the problems by transferring the pattern on the photo
resist layer to the hard mask beneath the photo resist layer. After
being patterned, the hard mask is ready for the trimming process to
reduce the gate line width. In addition, the hard mask must have
high etching selectivity to the conductive layer used in forming
gate layer. Accordingly, the trimmed hard mask is ready to be the
template for etching transfer process to define the line width of
gate layer.
[0007] However, as only one trimming process is typically employed
on the photo resist layer and the hard mask above the designated
gate layer, issues such as line twisting or line less often occur
on the hard mask beneath the photo resist layer and result in a
flawed gate structure. Moreover, the hard mask is also prone to
line collapse during the trimming procedure and the following
etching on conductive layer, which would destroy the entire process
or the results. Accordingly, it is important to develop a better
method for trimming hard masks to form the gate of MOS transistors
with ideal gate length.
SUMMARY OF THE INVENTION
[0008] It is an objective of the present invention to provide a
method of trimming hard masks for fabricating a gate layer of a MOS
device.
[0009] According to a preferred embodiment of the present
invention, a method for fabricating a semiconductor structure is
disclosed. The method includes the steps of: providing a substrate;
depositing a material layer on the substrate; forming at least one
dielectric layer on the material layer; forming a patterned resist
on the dielectric layer; performing a first trimming process on at
least the patterned resist; performing a second trimming process on
at least the dielectric layer; and using the dielectric layer as
mask for etching the material layer.
[0010] Another aspect of the present invention discloses a method
for fabricating a semiconductor structure, which includes the steps
of: providing a substrate; depositing a material layer on the
substrate; forming at least one dielectric layer on the material
layer; forming a patterned resist on the dielectric layer;
performing a first trimming process on at least the patterned
resist; and performing a second trimming process on at least the
dielectric layer, wherein the second trimming process comprises
trimming greater than 70% of a total trimming value.
[0011] Another aspect of the present invention discloses a method
for fabricating a semiconductor structure, which includes the steps
of: providing a substrate; depositing a material layer on the
substrate; forming a plurality of trimming layers on the material
layer; and performing at least a two-step trimming process on the
trimming layers such that the trimming layers are trimmed
twice.
[0012] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIGS. 1-4 illustrate a method for fabricating a
semiconductor structure according to a preferred embodiment of the
present invention.
[0014] FIGS. 5-8 illustrate a method for fabricating a
semiconductor structure according to an embodiment of the present
invention.
DETAILED DESCRIPTION
[0015] Referring to FIGS. 1-4, FIGS. 1-4 illustrate a method for
fabricating a semiconductor structure according to a preferred
embodiment of the present invention. As shown in FIG. 1, a
substrate 12, such as a silicon substrate is provided. Next, a gate
dielectric layer (not shown) preferably composed of oxide,
oxy-nitride, nitrogen-containing dielectric materials or a
combination thereof may be formed on the substrate by thermal
oxidation, chemical vapor deposition (CVD), or plasma enhanced
chemical vapor deposition (PECVD). A material layer, such as a
silicon layer or a polysilicon layer 14 is then deposited on the
gate dielectric layer and at least a dielectric layer 16 is formed
on the polysilicon layer 14 thereafter.
[0016] The at least one dielectric layer 16 may be composed of one
single dielectric layer or a plurality of dielectric layers. In
this embodiment, a plurality of dielectric layers are deposited on
the polysilicon layer 14, in which the dielectric layers include a
hard mask 18 and a bottom anti-reflective coating (BARC) 20. In
this embodiment, the hard mask 18 could be selected from a material
consisting of SiON, SiO.sub.2, TEOS, or a combination thereof, and
the BARC 20 may be formed from an organic polymer anti-reflective
coating material, such as a 365 nm (I-line) resist layer. A
patterned resist 22 is formed on the BARC 20 thereafter.
[0017] After the patterned resist 22 is formed, a trimming process
24 could be conducted to narrow the width of the patterned resist
22. The trimming process 24 may be accomplished by a plasma etch
using gases such as oxygen, ozone, CF.sub.4, CHF.sub.3 or
HBr/O.sub.2, and if the target layer to be trimmed were resist
material, ashing may be used.
[0018] As shown in FIG. 2, after trimming the patterned resist 22,
an etching process is carried out by using the patterned resist as
mask to remove a portion of the BARC 20 underneath. After the
pattern of the patterned resist 22 is transferred to the BARC 20,
another trimming process 26 is conducted to narrow the width of the
patterned resist 22 and the BARC 20. The etching gas used in this
trimming process 26 preferably trims only the target layers such as
the aforementioned patterned resist 22 and BARC 20 without
affecting any other layer underneath, and could be identical or
different from the etching gas used in the previous trimming step
24.
[0019] As shown in FIG. 3, after the patterned resist 22 and the
BARC 20 are trimmed, an etching is performed by using the patterned
resist 22 and the BARC 20 as mask to remove a portion of the hard
mask 18 underneath. As the etching is carried out on the hard mask
18, a portion of the polysilicon layer 14 surface is exposed and
the patterned resist 22 may be etched away as the pattern of the
BARC 20 is transferred to the hard mask 18. Next, another trimming
process 28 could be conducted to narrow the width of the BARC 20
and the hard mask 18. The etching gas used in this trimming process
28 could be identical or different from the etching gas used in the
previous trimming steps 24 or 26.
[0020] Preferably, as a substantial amount of polysilicon layer 14
is lost due to the etching gas used during the trimming procedure,
a fixed time were to be calculated for the trimming process 28
after exposing the polysilicon layer 14 to control the width
difference between the top of the polysilicon layer 14 and the
bottom of the polysilicon layer 14 no more than 10%. According to a
preferred embodiment of the present invention, the fixed time of
the trimming procedure is calculated after trimming greater than
70% of a total trimming value.
[0021] For instance, if a width of the BARC 20 and the hard mask 18
were to be reduced from 60 nm to 40 nm after the surface of the
polysilicon layer 14 is exposed, 6 nm from the total of 20 nm being
etched away in the trimming procedure would be reserved for the
polysilicon layer 14. As the trimming procedure starts, a fixed
time of 30 seconds is calculated to trim the 6 nm for the
polysilicon layer 14.
[0022] It should be noted that even though three trimming processes
24, 26, 28 are disclosed in this embodiment, operators could choose
to perform only two or all three of these trimming process 24, 26,
28 through the fabrication.
[0023] For instance, if only the trimming processes 26 and 28 were
selected to be performed throughout the fabrication, operators
could omit the trimming process 24 by using the un-trimmed
patterned resist 22 directly as mask to pattern the BARC 20 and
perform the subsequent trimming processes 26 and 28 as mentioned
previously.
[0024] Moreover, despite the aforementioned embodiment strips the
patterned resist 22 after the trimming process 26 by either a
separate etching process or along with the patterning of the hard
mask 18, the patterned resist 22 could also be remained on the BARC
20 and the hard mask 18 until exposing the surface of the
polysilicon layer 14. In other words, after trimming the patterned
resist 22, one ore more etching process could be carried by using
the patterned resist 22 as mask to pattern the BARC 20 and hard
mask 18 until exposing the surface of the polysilicon layer 14.
After the polysilicon layer 14 is exposed, another trimming process
is conducted to trim the patterned resist 22, the patterned BARC
20, and the patterned hard mask 18 before patterning the
polysilicon layer 14. This approach of performing at least two
trimming process that all involves the trimming of patterned resist
is also within the scope of the present invention.
[0025] As shown in FIG. 4, after the patterned BARC 20 and the hard
mask 18 are trimmed, an etching is performed by using the patterned
BARC 20 and the hard mask 18 as mask to remove a portion of the
polysilicon layer 14 underneath for forming a patterned polysilicon
layer 14. The patterned polysilicon layer 14 is preferably used as
a gate electrode of a metal-oxide semiconductor (MOS) device, and
after the patterned polysilicon 14 is formed, typical MOS
fabrication involving the formation of offset spacer, lightly doped
drain, main spacer, source/drain region, epitaxial layers, stress
layers, salicides, and contact plugs could be employed to form a
MOS structure. As the fabrication of these MOS structure elements
are commonly known to those skilled in the art in this field, the
details of which are omitted herein for the sake of brevity.
[0026] In another embodiment of the present invention, the material
layer can include other suitable materials, such as silicon,
silicon oxide or metal. Therefore, the patterned material layer
fabricated by above mentioned steps can be used as other
semiconductor structure, such as STI or contact plug.
[0027] Referring to FIGS. 5-8, FIGS. 5-8 illustrate a method for
fabricating a semiconductor structure according to an embodiment of
the present invention. As shown in FIG. 5, a substrate 42, such as
a silicon substrate is provided. Next, a gate dielectric layer (not
shown) preferably composed of oxide, oxy-nitride,
nitrogen-containing dielectric materials or a combination thereof
may be formed on the substrate by thermal oxidation, chemical vapor
deposition (CVD), or plasma enhanced chemical vapor deposition
(PECVD). A polysilicon layer 44 is then deposited on the gate
dielectric layer and at least a dielectric layer 46 is formed on
the polysilicon layer 44 thereafter.
[0028] The at least one dielectric layer 46 may be composed of one
single dielectric layer or a plurality of dielectric layers. In
this embodiment, a plurality of dielectric layers are deposited on
the polysilicon layer 44, in which the dielectric layers include a
hard mask 48, an advanced patterning film (APF) 50 from Applied
Materials, Inc., and a dielectric anti-reflective coating (DARC)
52. In this embodiment, the hard mask 48 could be selected from a
material consisting of SiON, SiO.sub.2, TEOS, or a combination
thereof, and the DARC 52 may be formed from an organic polymer
anti-reflective coating material, such as a silicon-rich silicon
oxynitride layer. A patterned resist 54 is formed on the DARC
thereafter.
[0029] An etching is then carried out by using the patterned resist
54 as mask to remove a portion of the DARC 52 underneath for
forming a patterned DARC 52. Despite the patterned resist 54 is
used directly as an etching mask for patterning the DARC 52
underneath, a trimming process could be conducted before the DARC
52 is etched. After the DARC 52 is patterned, a trimming process is
conducted to narrow the width of the patterned resist 54 and the
patterned DARC 52. The trimming process 56 may be accomplished by a
plasma etch using gases such as oxygen, ozone, CF.sub.4, CHF.sub.3
or HBr/O.sub.2, and if the target layer to be trimmed were resist
material, ashing may be used.
[0030] As shown in FIG. 6, after trimming the patterned resist 54
and the DARC 52, an etching process is carried out by using the
patterned resist 54 and DARC 52 as mask to remove a portion of the
APF 50 underneath. Depending on the etchant used for removing the
APF 50, the patterned resist 54 could be removed as the APF 50 is
patterned, or could be removed by a separate etching step prior to
the patterning of the APF 50, which is also within the scope of the
present invention. After the pattern of the DARC 52 is transferred
to the APF 50, another trimming process 58 is conducted to narrow
the width of the DARC 52 and the APF 50. The etching gas used in
this trimming process 58 could be identical or different from the
etching gas used in the previous trimming step 56.
[0031] As shown in FIG. 7, after trimming the patterned DARC 52 and
the APF 50, an etching process is carried out by using the trimmed
DARC 52 and APF 50 as mask to remove a portion of the hard mask 48
underneath. Depending on the etchant used for removing the hard
mask 48, the DARC 52 could be removed as the hard mask 48 is
patterned, or could be removed by a separate etching step prior to
the patterning of the hard mask 48, which is also within the scope
of the present invention. After the pattern of the APF 50 is
transferred to the hard mask 48, another trimming process 60 is
conducted to narrow the width of the APF 50 and the hard mask 48.
The etching gas used in this trimming process 60 could be identical
or different from the etching gas used in the previous trimming
steps 56 or 58.
[0032] Similar to the aforementioned embodiment, even though three
trimming processes 56, 58, 60 are disclosed in this embodiment,
operators could choose to perform only two or all three of these
trimming process 56, 58, 60 throughout the fabrication.
[0033] For instance, if only the trimming processes 58 and 60 were
selected to be performed throughout the fabrication, operators
could omit the trimming process 24 by using the un-trimmed
patterned resist 54 and DARC 52 directly as mask to pattern the APF
50 and perform the subsequent trimming processes 58 and 60 as
mentioned previously.
[0034] Moreover, despite the aforementioned embodiment strips the
patterned resist 54 after the trimming process 56 by either a
separate etching process or along with the patterning of the APF
50, the patterned resist 54 could also be remained on the DARC 52
until exposing the surface of the polysilicon layer 44. In other
words, after trimming the patterned resist 54 and the DARC 52, one
ore more etching process could be carried by using the patterned
resist 54 and DARC 52 as mask to pattern the APF 50 and hard mask
48 until exposing the surface of the polysilicon layer 44. After
the polysilicon layer 44 is exposed, another trimming process is
conducted to trim the patterned resist 54, the patterned DARC 52,
patterned APF 50, and the patterned hard mask 48 before
transferring the pattern to the polysilicon layer 44. This approach
of performing at least two trimming process that all involves the
trimming of patterned resist is also within the scope of the
present invention.
[0035] As shown in FIG. 8, after the patterned APF 50 and the hard
mask 48 are trimmed, an etching is performed by using the patterned
APF 50 and the hard mask 48 as mask to remove a portion of the
polysilicon layer 44 underneath. The patterned APF 50 and the hard
mask 48 could be removed by another etching thereafter.
[0036] The patterned polysilicon layer 44 is preferably used as a
gate electrode of a metal-oxide semiconductor (MOS) device, and
after the patterned polysilicon 44 is formed, typical MOS
fabrication involving the formation of offset spacer, lightly doped
drain, main spacer, source/drain region, epitaxial layers,
salicides, and contact plugs could be employed to form a MOS
structure. As the fabrication of these MOS structure elements are
commonly known to those skilled in the art in this field, the
details of which are omitted herein for the sake of brevity.
[0037] Overall, the present invention conducts at least two
trimming process through the fabrication of a semiconductor
structure, such as a polysilicon gate of a MOS device. By applying
two or more trimming process on the patterned resist and dielectric
layers above the designated polysilicon layer, issued such as line
lost or line collapse during the trimming procedure of gate layer
formation could be improved substantially.
[0038] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *