U.S. patent application number 13/645215 was filed with the patent office on 2013-01-31 for interface apparatus, calculation processing apparatus, interface generation apparatus, and circuit generation apparatus.
This patent application is currently assigned to Sony Corporation. The applicant listed for this patent is Sony Corporation. Invention is credited to Hideki Kazama.
Application Number | 20130031311 13/645215 |
Document ID | / |
Family ID | 42398645 |
Filed Date | 2013-01-31 |
United States Patent
Application |
20130031311 |
Kind Code |
A1 |
Kazama; Hideki |
January 31, 2013 |
INTERFACE APPARATUS, CALCULATION PROCESSING APPARATUS, INTERFACE
GENERATION APPARATUS, AND CIRCUIT GENERATION APPARATUS
Abstract
There is provided is an interface apparatus including: a stream
converter receiving write-addresses and write-data, storing the
received data in a buffer, and sorting the stored write-data in the
order of the write-addresses to output the write-data as
stream-data; a cache memory storing received stream-data if a
load-signal indicates that the stream-data are necessarily loaded
and outputting data stored in a storage device corresponding to an
input cache-address as cache-data; a controller determining whether
or not data allocated with a read-address have already been loaded,
outputting the load-signal instructing the loading on the cache
memory if not loaded, and outputting a load-address indicating a
load-completed-address of the cache memory; and at least one
address converter calculating which one of the storage devices the
allocated data are stored in, by using the load-address, outputting
the calculated value as the cache-address to the cache memory, and
outputting the cache-data as read-data.
Inventors: |
Kazama; Hideki; (Kanagawa,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Sony Corporation; |
Tokyo |
|
JP |
|
|
Assignee: |
Sony Corporation
Tokyo
JP
|
Family ID: |
42398645 |
Appl. No.: |
13/645215 |
Filed: |
October 4, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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12694556 |
Jan 27, 2010 |
8307160 |
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13645215 |
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Current U.S.
Class: |
711/130 ;
711/118; 711/E12.038 |
Current CPC
Class: |
G06F 12/084
20130101 |
Class at
Publication: |
711/130 ;
711/118; 711/E12.038 |
International
Class: |
G06F 12/08 20060101
G06F012/08 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 30, 2009 |
JP |
2009-019893 |
Claims
1. An interface generation apparatus comprising: a stream converter
to receive write addresses and write data, to store the received
data in a buffer, and to sort the write data stored in the buffer
in the order of the write addresses to output the write data as
stream data; a cache memory to store received stream data in a
storage device if a load signal is in a state of indicating that it
is necessary that the stream data are loaded and to output data
stored in the storage device corresponding to a cache address as
cache data if the cache address is input; a controller to determine
whether or not data allocated with address information on reading
have already been loaded on the cache memory, to output the load
signal instructing loading on the cache memory if the allocated
data are not loaded on the cache memory as a result of the
determination, and to output a load address indicating a
load-completed address of the cache memory; and at least one
address converter to calculate a value representing which of
storage devices of the cache memory the data allocated with the
read address are stored in, by using the load address indicating
the load-completed address of the cache memory, to output the
calculated value as the cache address to the cache memory, and to
output the cache data input from the cache memory as read data.
2. The interface generation apparatus according to claim 1,
wherein: the stream converter outputs the stream data only during a
time that a stream receivable signal from the cache memory is in a
receivable state, and the cache memory stores the stream data
received from the stream converter in internal storage devices if
the stream receivable signal is changed into the receivable
state.
3. The interface generation apparatus according to claim 1 or 2,
wherein: the stream converter outputs the write data receivable
signal in the receivable state to a side of supplying the write
data if the buffer is not full so that the write data is
receivable, and a write data receivable signal is changed into a
non-receivable state if the buffer is full so that the write data
is not receivable.
4. The interface generation apparatus according to claim 1, further
comprising a selector to selectively input the stream data and test
data to the cache memory.
5. The interface generation apparatus according to claim 1, further
comprising a consistency verification unit to verify whether or not
the data access is consistent with the interface apparatus.
6. The interface generation apparatus according to claim 5, wherein
the consistency verification unit includes a write address
consistency verification unit to verify consistency of the write
address and a read address consistency verification unit to verify
consistency of the address information on reading.
7. The interface generation apparatus according to claim 6, wherein
the write address consistency verification unit calculates a
capacity of the storage devices, which are necessary for an inner
portion of the stream converter, from an output order of the write
addresses and checks whether or not the calculated value of the
capacity is larger than an actual value of the capacity of the
storage devices of the stream converter.
8. The interface generation apparatus according to claim 6, wherein
the read address consistency verification unit calculates a
capacity of the storage devices, which are necessary for the cache
memory, from an output order of the address information on the
reading and checks whether or not the calculated value of the
capacity is larger than an actual value of the capacity of the
storage devices of the cache memory.
9. A calculation processing apparatus comprising: a first
calculation unit; a second calculation unit; and an interface
generation apparatus that performs data transmission by using
address allocation between the first calculation unit and the
second calculation unit, wherein the interface generation apparatus
includes: a stream converter to receive write addresses and write
data from the first calculation unit, to store the received data in
a buffer, and to sort the write data stored in the buffer in the
order of the write addresses to output the write data as stream
data; a cache memory to store received stream data in a storage
device if a load signal is in a state of indicating that it is
necessary that the stream data are loaded and to output data stored
in the storage device corresponding to a cache address as cache
data if the cache address is input; a controller to determine
whether or not data allocated with address information on reading
have already been loaded on the cache memory by the second
calculation unit, to output the load signal instructing the loading
on the cache memory if the allocated data are not loaded on the
cache memory as a result of the determination, and to output a load
address indicating a load-completed address of the cache memory;
and at least one address converter to calculate a value
representing which one of the storage devices of the cache memory
the data allocated with the read address are stored in, by using
the load address indicating the load-completed address of the cache
memory, to output the calculated value as the cache address to the
cache memory, and to output to the second calculation unit the
cache data input from the cache memory as read data.
10. An interface generation apparatus for generating an interface
apparatus, wherein the interface generation apparatus comprises: a
stream converter to receive write addresses and write data, to
store the received data in a buffer, and to sort the write data
stored in the buffer in the order of the write addresses to output
the write data as stream data; a cache memory to store received
stream data in a storage device if a load signal is in a state of
indicating that it is necessary that the stream data are loaded and
to output data stored in the storage device corresponding to a
cache address as cache data if the cache address is input; a
controller to determine whether or not data allocated with address
information on reading have already been loaded on the cache
memory, to output the load signal instructing the loading on the
cache memory if the allocated data are not loaded on the cache
memory as a result of the determination, and to output a load
address indicating a load-completed address of the cache memory;
and at least one address converter to calculate a value
representing which one of the storage devices of the cache memory
the data allocated with the read address are stored in, by using
the load address indicating the load-completed address of the cache
memory, to output the calculated value as the cache address to the
cache memory, and to output the cache data input from the cache
memory as read data, wherein the interface generation apparatus
comprises: a circuit information storage unit that stores circuit
description information of a circuit connected to an interface that
is an object of generation; and an interface configuration
information output unit to analyze specifications, which are to be
satisfied by the interface, based at least in part on the circuit
description information read from the circuit information storage
unit.
11. The interface generation apparatus according to claim 10,
wherein: the interface configuration information output unit reads
the circuit description from the circuit information storage unit,
converts the circuit description into internal database, extracts
all values and equations output as the address information on
reading, calculates differences among all combinations in the
extracted address calculation equation, sets a value obtained by
adding a predetermined value to a maximum value among the
calculated differences to a necessary capacity of the cache memory;
and the cache memory comprises storage devices corresponding to the
capacity.
12. A circuit generation apparatus for generating a calculation
unit connected to an interface apparatus, wherein the interface
apparatus comprises: a stream converter to receive write addresses
and write data, to store the received data in a buffer, and to sort
the write data stored in the buffer in the order of the write
addresses to output the write data as stream data; a cache memory
to store received stream data in a storage device if a load signal
is in a state of indicating that it is necessary that the stream
data are loaded and to output data stored in the storage device
corresponding to a cache address as cache data if the cache address
is input; a controller to determine whether or not data allocated
with address information on reading have already been loaded on the
cache memory, to output the load signal instructing the loading on
the cache memory if the allocated data are not loaded on the cache
memory as a result of the determination, and to output a load
address indicating a load-completed address of the cache memory;
and at least one address converter to calculate a value
representing which one of the storage devices of the cache memory
the data allocated with the read address are stored in, by using
the load address indicating the load-completed address of the cache
memory, to output the calculated value as the cache address to the
cache memory, and to output the cache data input from the cache
memory as read data, wherein the circuit generation apparatus
comprises: a circuit description storage unit to store description
expressing functions of the calculation unit connected to the
interface apparatus; an array access replacement unit to extract
reading and writing with respect to an array, which is to be an
object of generation of the interface apparatus, from the circuit
description read from the circuit description storage unit and to
perform replacement with description expressing a communication
protocol for connection to the interface apparatus; and a detailed
circuit generation apparatus to generate detailed circuit
description from description that is subject to replacement of
array access.
Description
RELATED APPLICATIONS
[0001] This Application claims the benefit under 35 U.S.C.
.sctn.120 of U.S. application Ser. No. 12/694,556, entitled
"INTERFACE APPARATUS, CALCULATION PROCESSING APPARATUS, INTERFACE
GENERATION APPARATUS, AND CIRCUIT GENERATION APPARATUS" filed on
Jan. 27, 2010, which is herein incorporated by reference in its
entirety. Foreign priority benefits are claimed under 35 U.S.C.
.sctn.119(a)-(d) or 35 U.S.C. .sctn.365(b) of Japanese application
number 2009-019893, filed Jan. 30, 2009.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to an interface apparatus,
which is adapted as an interface between calculation units that
perform data transmission by using address allocation, a
calculation processing apparatus, an interface generation
apparatus, and circuit generation apparatus.
[0004] 2. Description of the Related Art
[0005] In general, in order to perform data transmission by address
allocation, a large-capacity storage device is disposed between
calculation units (for example, refer to Japanese Patent No.
3644380).
[0006] FIG. 1 is a block diagram illustrating an example of a
calculation processing apparatus employing a general data
transmission method.
[0007] The calculation processing apparatus 10 shown in FIG. 1
includes a first calculation unit 11, a second calculation unit 12,
a main storage unit 13, and an address selector 14.
[0008] In addition, in FIG. 1, WDT, WADR, WCTL, RDT, RADR, and ADR
denotes write data, a write address, a write control signal, read
data, a read address, and a selected address, respectively.
[0009] In the calculation processing apparatus 10 shown in FIG. 1,
the write data WDT output from the first calculation unit 11 are
stored at a position allocated with the write address WADR in the
main storage unit 13.
[0010] Next, in the calculation processing apparatus 10, the second
calculation unit 12 reads data at a position allocated with the
read address RADR from the storage device, so that the data
transmission from the first calculation unit 11 to the second
calculation unit 12 is performed.
[0011] In addition, in general, in the case where the transmission
rate of the large-capacity main storage unit is low and too much
time is taken for the data transmission, a cache memory is disposed
between the calculation unit and the main storage unit (for
example, refer to Japanese Unexamined Patent Application
Publication No. 8-16467).
[0012] FIG. 2 is a block diagram illustrating an example of a
calculation processing apparatus using a cache memory.
[0013] A calculation processing apparatus 10A shown in FIG. 2 is
configured by disposing a cache memory 15 to the configuration of
the calculation processing apparatus 10 shown in FIG. 1.
[0014] In the calculation processing apparatus 10A of FIG. 2, the
write data WDT output from the first calculation unit 11 are
temporarily written in the small-capacity, high-rate cache memory
15. Next, the second calculation unit 12 reads the data allocated
with the read address RADR from the cache memory 15, so that the
data transmission from the first calculation unit 11 to the second
calculation unit 12 is performed.
[0015] The cache memory 15 periodically writes the write data WDT
stored in the cache memory 15 in the main storage unit 13 in a
collective manner.
[0016] In addition, in the case where the data allocated with the
read address RADR do not exist in the cache memory 15, the cache
memory 15 reads data from a storage device corresponding to the
read address RADR in the main storage unit 13 and outputs the data
as the read data RDT.
[0017] In the data transmission method shown in FIG. 1, since it is
necessary that the main storage unit has the storage devices
uniquely corresponding to the addresses indicated by the write
address WADR and the read address RADR, large-capacity storage
devices have to be provided, so that there is a disadvantage in
that the area of circuits is increased.
[0018] For example, in the technology disclosed in Japanese Patent
No. 3644380, as shown in FIG. 13 of Japanese Patent No. 3644380,
when two processors communicate with each other, it is necessary
that a main memory connected to a memory controller is used.
Therefore, there is a disadvantage in that the large-capacity
storage devices have to be provided.
[0019] In the data transmission method shown in FIG. 2, the number
of times of accessing a low-rate main storage unit 13 is reduced,
so that high-rate data transmission may be effectively
implemented.
[0020] However, since it is necessary that the main storage unit 13
has storage devices uniquely corresponding to the addresses ADR
indicated by the write address WADR and the read address RADR,
large-capacity storage devices have to be provided, so that the
disadvantageous problem in that the area of circuits is increased
is not solved.
[0021] For example, in the technology disclosed in Japanese
Unexamined Patent Application Publication No. 8-16467, as shown in
FIG. 1 of Japanese Unexamined Patent Application Publication No.
8-16467, in the related art, the cache memory temporarily stores
the data read from the main memory or temporarily stores the data
that are to be written in the main memory.
[0022] Therefore, in the configuration of the technology, the data
transmission may not be performed without the main memory. Since it
is necessary that the storage devices uniquely corresponding to the
addresses are provided, there is a disadvantage in that the
large-capacity storage devices must be provided to the main
memory.
[0023] As described above, in the configuration shown in FIGS. 1
and 2, if there is no large-capacity storage device uniquely
corresponding to the addresses output from the calculation unit,
there is a problem in that the data transmission may not be
performed.
[0024] Therefore, there is contrived a configuration where the main
storage unit is removed from the configuration of FIG. 2, and as
shown in FIG. 3, the first calculation unit 11 and the second
calculation unit 12 communicate with each other by using only the
cache memory 15.
[0025] According to the configuration, a capacity of a storage
device that is necessary for the interface apparatus may be
reduced.
[0026] However, in the configuration shown in FIG. 3, although
there are data that are not read by the second calculation unit 12,
the first calculation unit 11 updates the contents of the cache
memory 15, and thus, there is a problem in that the data necessary
for the second calculation unit 12 may be overwritten. In this
case, the data transmission may not be properly performed.
[0027] In addition, in the configuration shown in FIG. 3, there is
a problem in that it is necessary to increase the number of data
stored in the cache memory 15 so as to reduce concerns that the
data transmission will be incorrectly performed.
SUMMARY OF THE INVENTION
[0028] It is desirable to provide an interface apparatus capable of
connecting calculation units by using the minimum number of storage
devices, thereby surely performing data transmission by using
address allocation even in the case where the number of data stored
in a cache memory is set to a minimum, a calculation processing
apparatus, an interface generation apparatus, and a circuit
generation apparatus therefor.
[0029] According to a first embodiment of the present invention,
there is provided an interface apparatus including: a stream
converter that receives write addresses and write data, stores the
received data in a buffer, and sorts the write data stored in the
buffer in the order of the write addresses to output the write data
as stream data; a cache memory that stores received stream data in
a storage device if a load signal is in a state of indicating that
it is necessary that the stream data are loaded and that outputs
data stored in the storage device corresponding to a cache address
as cache data if the cache address is input; a controller that
determines whether or not data allocated with address information
on reading have already been loaded on the cache memory, that
outputs the load signal instructing the loading on the cache memory
if the allocated data are not loaded on the cache memory as a
result of the determination, and that outputs a load address
indicating a load-completed address of the cache memory; and at
least one address converter that calculates a value representing
which one of the storage devices of the cache memory the data
allocated with the read address are stored in, by using the load
address indicating the load-completed address of the cache memory,
that outputs the calculated value as the cache address to the cache
memory, and that outputs the cache data input from the cache memory
as read data.
[0030] According to a second embodiment of the present invention,
there is provided a calculation processing apparatus including: a
first calculation unit; a second calculation unit; and an interface
apparatus that performs data transmission by using address
allocation between the first calculation unit and the second
calculation unit, wherein the interface apparatus includes: a
stream converter that receives write addresses and write data from
the first calculation unit, stores the received data in a buffer,
and sorts the write data stored in the buffer in the order of the
write addresses to output the write data as stream data; a cache
memory that stores received stream data in a storage device if a
load signal is in a state of indicating that it is necessary that
the stream data are loaded and that outputs data stored in the
storage device corresponding to a cache address as cache data if
the cache address is input; a controller that determines whether or
not data allocated with address information on reading have already
been loaded on the cache memory by the second calculation unit,
that outputs the load signal instructing the loading on the cache
memory if the allocated data are not loaded on the cache memory as
a result of the determination, and that outputs a load address
indicating a load-completed address of the cache memory; and at
least one address converter that calculates a value representing
which one of the storage devices of the cache memory the data
allocated with the read address are stored in, by using the load
address indicating the load-completed address of the cache memory,
that outputs the calculated value as the cache address to the cache
memory, and that outputs to the second calculation unit the cache
data input from the cache memory as read data.
[0031] According to a third embodiment of the present invention,
there is provided an interface generation apparatus for generating
an interface apparatus, wherein the interface apparatus includes: a
stream converter that receives write addresses and write data,
stores the received data in a buffer, and sorts the write data
stored in the buffer in the order of the write addresses to output
the write data as stream data; a cache memory that stores received
stream data in a storage device if a load signal is in a state of
indicating that it is necessary that the stream data are loaded and
that outputs data stored in the storage device corresponding to a
cache address as cache data if the cache address is input; a
controller that determines whether or not data allocated with
address information on reading have already been loaded on the
cache memory, that outputs the load signal instructing the loading
on the cache memory if the allocated data are not loaded on the
cache memory as a result of the determination, and that outputs a
load address indicating a load-completed address of the cache
memory; and at least one address converter that calculates a value
representing which one of the storage devices of the cache memory
the data allocated with the read address are stored in, by using
the load address indicating the load-completed address of the cache
memory, that outputs the calculated value as the cache address to
the cache memory, and that outputs the cache data input from the
cache memory as read data, and wherein the interface generation
apparatus includes: a circuit information storage unit that stores
circuit description information of a circuit connected to an
interface that is an object of generation; and an interface
configuration information output unit that analyzes specifications,
which are to be satisfied by the interface, based on the circuit
description information read from the circuit information storage
unit.
[0032] According to a fourth embodiment of the present invention,
there is provided a circuit generation apparatus for generating a
calculation unit connected to an interface apparatus, wherein the
interface apparatus includes: a stream converter that receives
write addresses and write data, stores the received data in a
buffer, and sorts the write data stored in the buffer in the order
of the write addresses to output the write data as stream data; a
cache memory that stores received stream data in a storage device
if a load signal is in a state of indicating that it is necessary
that the stream data are loaded and that outputs data stored in the
storage device corresponding to a cache address as cache data if
the cache address is input; a controller that determines whether or
not data allocated with address information on reading have already
been loaded on the cache memory, that outputs the load signal
instructing the loading on the cache memory if the allocated data
are not loaded on the cache memory as a result of the
determination, and that outputs a load address indicating a
load-completed address of the cache memory; and at least one
address converter that calculates a value representing which one of
the storage devices of the cache memory the data allocated with the
read address are stored in, by using the load address indicating
the load-completed address of the cache memory, that outputs the
calculated value as the cache address to the cache memory, and that
outputs the cache data input from the cache memory as read data,
and wherein the circuit generation apparatus includes: a circuit
description storage unit that stores description expressing
functions of the calculation unit connected to the interface
apparatus; an array access replacement unit that extracts reading
and writing with respect to an array, which is to be an object of
generation of the interface apparatus, from the circuit description
read from the circuit description storage unit and performs
replacement with description expressing a communication protocol
for connection to the interface apparatus; and a detailed circuit
generation apparatus that generates detailed circuit description
from description that is subject to replacement of array
access.
[0033] According to the invention, since the calculation units may
be connected to each other by using the minimum number of storage
devices, even in the case where the number of data stored in the
cache memory is set to a minimum, the data transmission using
address allocation may be surely performed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0034] FIG. 1 is a block diagram illustrating an example of a
calculation processing apparatus employing a general data
transmission method.
[0035] FIG. 2 is a block diagram illustrating an example of a
calculation processing apparatus using a cache memory.
[0036] FIG. 3 is a block diagram illustrating another example of a
calculation processing apparatus using a cache memory.
[0037] FIG. 4 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a first embodiment of the
invention.
[0038] FIG. 5 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a second embodiment of the
invention.
[0039] FIG. 6 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a third embodiment of the
invention.
[0040] FIG. 7 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a fourth embodiment of the
invention.
[0041] FIG. 8 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a fifth embodiment of the
invention.
[0042] FIG. 9 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a sixth embodiment of the
invention.
[0043] FIG. 10 is a block diagram illustrating an example of an
interface generation apparatus according to the first to sixth
embodiments.
[0044] FIG. 11 is a diagram illustrating an example of
specifications that is to be satisfied by an interface that is
analyzed by the interface generation apparatus of FIG. 10.
[0045] FIG. 12 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a seventh embodiment of the
invention.
[0046] FIG. 13 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to an eighth embodiment of the
invention.
[0047] FIG. 14 is a block diagram illustrating an example of a
configuration where an address consistency verification unit is
provided to the calculation processing apparatus employing a
general data transmission method.
[0048] FIG. 15 is a block diagram illustrating a circuit generation
apparatus that generates a calculation circuit that is to be
connected to an interface generation apparatus according to
embodiments of the invention.
[0049] FIG. 16 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a ninth embodiment of the
invention.
[0050] FIG. 17 is a diagram illustrating an example of a
configuration of a stream converter according to embodiments of the
invention.
[0051] FIG. 18 is a diagram illustrating an example of a
configuration of a cache memory according to embodiments of the
invention.
[0052] FIG. 19 is a diagram illustrating an example of a
configuration of a controller according to embodiments of the
invention.
[0053] FIG. 20 is a diagram illustrating an example of a
configuration of an address converter according to embodiments of
the invention.
[0054] FIG. 21 is a diagram illustrating a relationship between the
pre-load address and read address that are generated by a second
calculation unit of FIG. 16 and a capacity of a cache memory.
[0055] FIG. 22 is a diagram illustrating an example of expression
of specifications of a first calculation unit.
[0056] FIG. 23 is a diagram illustrating an example of expression
of specifications of a second calculation unit.
[0057] FIG. 24 is a diagram illustrating an example of a
configuration of a stream converter in the case where the first
calculation unit expressed by FIG. 22 is connected.
[0058] FIG. 25 is a diagram illustrating an example of a pre-load
address, a read address, and another read address that are output
from the second calculation unit having the specifications shown in
FIG. 23.
[0059] FIG. 26 is a diagram illustrating an example of a
configuration of a cache memory which is to be connected to the
second calculation unit having the specifications shown in FIG.
23.
[0060] FIG. 27 is a diagram illustrating an example of a
configuration of a controller and an address converter that
correspond to only the connection to the second calculation unit
shown in FIG. 23.
[0061] FIG. 28 is a diagram illustrating a flowchart of operations
of an interface configuration information output unit in the
interface generation apparatus shown in FIG. 10.
[0062] FIG. 29 is a diagram illustrating an example of circuit
description of a calculation unit.
[0063] FIG. 30 is a diagram illustrating an example of difference
in a calculation equation for addresses extracted from circuit
description shown in FIG. 29.
[0064] FIG. 31 is a diagram illustrating an example of a
configuration of a calculation processing apparatus employing a
verification interface apparatus according to embodiments of the
invention.
[0065] FIG. 32 is a diagram illustrating a flowchart of operations
of a write address consistency verification unit in the
verification interface apparatus shown in FIG. 31.
[0066] FIG. 33 is a diagram illustrating a detailed table listing
exemplary operations of a write address consistency verification
unit in the verification interface apparatus shown in FIG. 32.
[0067] FIG. 34 is a diagram illustrating a flowchart of operations
of a read address consistency verification unit in the verification
interface apparatus shown in FIG. 31.
[0068] FIG. 35 is a diagram illustrating a detailed table listing
exemplary operations of a read address consistency verification
unit in the verification interface apparatus shown in FIG. 34.
[0069] FIG. 36 is a diagram illustrating a flowchart of operations
of an array access replacement unit in the circuit generation
apparatus shown in FIG. 15.
[0070] FIG. 37 is a diagram illustrating an example of circuit
description stored in a circuit description storage unit.
[0071] FIG. 38 is a diagram illustrating an example where array
access is replaced with description of performing connection to an
interface apparatus.
[0072] FIG. 39 is a diagram illustrating another example of circuit
description stored in a circuit description storage unit.
[0073] FIG. 40 is a diagram illustrating another example where
array access is replaced with description of performing connection
to an interface apparatus.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0074] Hereinafter, exemplary embodiments of the invention are
described with reference to the attached drawings.
[0075] In addition, the description is made in the following
order.
[0076] 1. First Embodiment (First Example of Configuration of
Interface Apparatus)
[0077] 2. Second Embodiment (Second Example of Configuration of
Interface Apparatus)
[0078] 3. Third Embodiment (Third Example of Configuration of
Interface Apparatus)
[0079] 4. Fourth Embodiment (Fourth Example of Configuration of
Interface Apparatus)
[0080] 5. Fifth Embodiment (Fifth Example of Configuration of
Interface Apparatus)
[0081] 6. Sixth Embodiment (Sixth Example of Configuration of
Interface Apparatus)
[0082] 7. Seventh Embodiment (Seventh Example of Configuration of
Interface Apparatus)
[0083] 8. Eighth Embodiment (Eighth Example of Configuration of
Interface Apparatus)
[0084] 9. Ninth Embodiment (Ninth Example of Configuration of
Interface Apparatus)
[0085] 10. Detailed Examples of Configuration
1. First Embodiment
[0086] FIG. 4 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a first embodiment of the
invention.
[0087] As shown in FIG. 4, the calculation processing apparatus 100
according to the first embodiment includes a first calculation unit
110, a second calculation unit 120, a stream converter 130, a cache
memory 140, a controller 150A, and an address converter 160.
[0088] In addition, the stream converter 130, the cache memory 140,
the controller 150A, and the address converter 160 constitutes an
interface apparatus 200.
[0089] Examples of configurations of the stream converter 130, the
cache memory 140, the controller 150A, and the address converter
160 are described later in detail.
[0090] In FIG. 4, WADR, WDT, SWDTRB, STMD, and STMRB denote a write
address, write data, a write data receivable signal, stream data,
and a stream receivable signal, respectively.
[0091] In addition, in FIG. 4, PLADR, RADR, RDT, SLD, LADR, CADR,
and CDT denote a pre-load address, a read address, read data, a
load signal, a load address, a cache address, and cache data,
respectively.
[0092] In addition, address information associated with reading
includes a pre-load address PLADR and a read address RADR.
[0093] The first calculation unit 110 outputs the write addresses
WADR, of which order is regular, and the write data WDT to the
stream converter 130.
[0094] For example, in the case where the write data receivable
signal SWDTRB from the stream converter 130 indicates receivable,
the first calculation unit 110 outputs the write data WDT to the
stream converter 130.
[0095] For example, in the case where the write data receivable
signal SWDTRB from the stream converter 130 indicates
non-receivable, the first calculation unit 110 stops outputting the
write data WDT to the stream converter 130.
[0096] The second calculation unit 120 outputs the pre-load address
PLADR to the controller 150A.
[0097] The second calculation unit 120 outputs the read address
RADR to the address converter 160 and receives the read data RDT
from the address converter 160.
[0098] The stream converter 130 receives the write address WADR and
the write data WDT from the first calculation unit 110 and stores
the received data in an internal buffer.
[0099] The stream converter 130 arranges the write data WDT stored
in the internal buffer in the order of the write addresses WADR and
outputs the arranged write data as the stream data STMD to the
cache memory 140.
[0100] The stream converter 130 outputs the stream data STMD only
during the time that the stream receivable signal STMRB from the
cache memory 140 is in the receivable state.
[0101] If the internal buffer is not full and the write data are
receivable, the stream converter 130 outputs the write data
receivable signal SWDTRB in the receivable state to the first
calculation unit 110.
[0102] In addition, if the internal buffer is full and the write
data are non-receivable, the stream converter 130 changes the write
data receivable signal SWDTRB into a non-receivable state.
[0103] If the load signal SLD from the controller 150A is in the
state indicating that it is necessary to load the stream data STMD,
the cache memory 140 changes the stream receivable signal STMRB
into a receivable state.
[0104] If the stream receivable signal STMRB is changed into the
receivable state, the cache memory 140 stores in the internal
storage device the stream data STMD received from the stream
converter 130.
[0105] In the case where the internal storage device finishes
storing all the stream data STMD, the cache memory 140 erases the
data in the order from the oldest data stored in the internal
storage device.
[0106] If the cache address CADR is input from the address
converter 160, the cache memory 140 outputs the data stored in the
storage device corresponding to the cache address CADR as cache
data CDT to the address converter 160.
[0107] The controller 150A determines whether or not the data
allocated with the pre-load address PLADR input from the second
calculation unit 120 are already loaded on the cache memory
140.
[0108] As a result, if the allocated data are not loaded on the
cache memory 140, the controller 150A outputs a load signal SLD
instructing loading to the cache memory 140.
[0109] In addition, the controller 150A outputs to the address
converter 160 a load address signal LADR indicating a
load-completed address of the cache memory 140.
[0110] The address converter 160 calculates a value representing
which one of the storage devices of the cache memory 140 the data
allocated with the read address RADR are stored in, by using the
load address LADR indicating a load-completed address of the cache
memory 140.
[0111] The address converter 160 outputs the calculated value as a
cache address CADR to the cache memory 140.
[0112] In addition, the address converter 160 outputs the input
cache data CDT as read data RDT to the second calculation unit
120.
[0113] It should be noted that, in the interface apparatus 200
according to the first embodiment, the write address WADR and the
read address RADR are configured in a regular order in various
calculation such as an imaging process. In the interface apparatus
200, the write data WDT from the first calculation unit 110 are
sorted in the order of the write addresses by the stream converter
130 to be converted into the stream data STMD.
[0114] In the interface apparatus 200, the controller 150A
determines based on the read address RADR from the second
calculation unit 120 whether or not the cache memory 140 is to
receive the stream data STMD.
[0115] In the first embodiment, due to the above configuration,
even in the case where the number of data stored in the cache
memory 140 is set to a minimum, the interface apparatus 200 capable
of surely performing data transmission may be implemented.
[0116] In addition, in the configurations shown in FIGS. 1 and 2,
pairs of an address and data are necessarily stored in the cache
memory.
[0117] However, in the interface apparatus 200 according to the
first embodiment, since the stream converter 130 sorts the write
data WDT in the order of the write addresses WADR, values of
addresses are not necessarily stored in the cache memory 140.
[0118] Accordingly, in the first embodiment, the number of storage
devices of the cache memory 140 may be reduced, and the
configuration of the cache memory may be simplified.
2. Second Embodiment
[0119] FIG. 5 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a second embodiment of the
invention.
[0120] The interface apparatus 200A according to the second
embodiment is different from the interface apparatus 200 according
to the first embodiment in the following points.
[0121] The controller 150A of the interface apparatus 200A
determines whether or not the data allocated with the read address
RADR input from the second calculation unit 120 are already loaded
on the cache memory 140.
[0122] If not loaded, the controller 150A outputs a load signal SLD
instructing loading to the cache memory 140.
[0123] In addition, the controller 150A outputs to the address
converter 160 a load address signal LADR indicating a
load-completed address of the cache memory 140.
[0124] The other configurations are the same as those of the first
embodiment.
[0125] According to the second embodiment, the same effects as the
aforementioned effects of the first embodiment may be obtained.
3. Third Embodiment
[0126] FIG. 6 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a third embodiment of the
invention.
[0127] An interface apparatus 200B according to the third
embodiment is different from the interface apparatus 200 according
to the first embodiment in that a plurality of the address
converters (two address converters in the embodiment) are disposed,
so that the second calculation unit 120 may be configured to read a
plurality of data.
[0128] The controller 150B determines whether or not the data
allocated with the pre-load address PLADR input from the second
calculation unit 120 are already loaded on the cache memory
140.
[0129] As a result, if the allocated data are not loaded on the
cache memory 140, the controller 150B outputs a load signal SLD
instructing loading to the cache memory 140.
[0130] The controller 150B outputs to the address converter 160B-1
a load address signal LADR1 indicating a load-completed address of
the cache memory 140.
[0131] In addition, the controller 150B outputs to the address
converter 160B-2 a load address signal LADR2 indicating a
load-completed address of the cache memory 140.
[0132] The address converter 160B-1 calculates a value representing
which one of the storage devices of the cache memory 140 the data
allocated with the read address RADR1 are stored in, by using the
load address LADR1 indicating a load-completed address of the cache
memory 140.
[0133] The address converter 160B-1 outputs the calculated value as
a cache address CADR1 to the cache memory 140.
[0134] In addition, the address converter 160B-1 outputs the input
cache data CDT1 as read data RDT1 to the second calculation unit
120.
[0135] The address converter 160B-2 calculates a value representing
which one of the storage devices of the cache memory 140 the data
allocated with the read address RADR2 are stored in, by using the
load address LADR2 indicating a load-completed address of the cache
memory 140.
[0136] The address converter 160B-2 outputs the calculated value as
a cache address LADR2 to the cache memory 140.
[0137] In addition, the address converter 160B-2 outputs the input
cache data CDT2 as read data RDT2 to the second calculation unit
120.
[0138] The other configurations are the same as those of the first
embodiment.
[0139] According to the third embodiment, the same effects as the
aforementioned effects of the first embodiment may be obtained, and
a plurality of data may be read.
[0140] In addition, although the number of address converters is
two in the example shown in FIG. 6, the number may be larger than
two.
4. Fourth Embodiment
[0141] FIG. 7 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a fourth embodiment of the
invention.
[0142] The interface apparatus 200C according to fourth embodiment
is different from the interface apparatus 200B according to the
third embodiment in the following points.
[0143] The controller 150C of the interface apparatus 200C
determines whether or not the data allocated with the read address
RADR1 input from the second calculation unit 120 are already loaded
on the cache memory 140.
[0144] If not loaded, the controller 150C outputs a load signal SLD
instructing loading to the cache memory 140.
[0145] In addition, the controller 150C outputs to the address
converter 160B-1 a load address signal LADR1 indicating a
load-completed address of the cache memory 140.
[0146] The controller 150C determines whether or not the data
allocated with the read address RADR2 input from the second
calculation unit 120 are already loaded on the cache memory
140.
[0147] If not loaded, the controller 150C outputs a load signal SLD
instructing loading to the cache memory 140.
[0148] In addition, the controller 150C outputs to the address
converter 160B-2 a load address signal LADR2 indicating a
load-completed address of the cache memory 140.
[0149] The other configurations are the same as those of the third
embodiment.
[0150] According to the fourth embodiment, the same effects as the
aforementioned effects of the third embodiment may be obtained.
5. Fifth Embodiment
[0151] FIG. 8 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a fifth embodiment of the
invention.
[0152] The interface apparatus 200D according to the fifth
embodiment is different from the interface apparatus 200 according
to the first embodiment in the following points.
[0153] The interface apparatus 200D includes a selector 170 which
switches the data input from the first calculation unit 110 and
test data TDT in response to a test mode switching signal TMSW so
as to input the stream data STMD to the cache memory 140.
[0154] In addition, the interface apparatus 200D allows the cache
memory 140 to supply the stream receivable signal STMRB as a test
data receivable signal TDTRB to a test circuit (not shown).
[0155] The other configurations are the same as those of the first
embodiment.
[0156] According to the fifth embodiment, the same effects as the
aforementioned effects of the first embodiment may be obtained, and
the test using the test data may be performed.
6. Sixth Embodiment
[0157] FIG. 9 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a sixth embodiment of the
invention.
[0158] The interface apparatus 200E according to the sixth
embodiment is different from the interface apparatus 200A according
to the second embodiment in the following points.
[0159] The interface apparatus 200E includes a selector 170E which
switches the data input from the first calculation unit 110 and
test data TDT in response to a test mode switching signal TMSW so
as to input the stream data STMD to the cache memory 140.
[0160] In addition, the interface apparatus 200E allows the cache
memory 140 to supply the stream receivable signal STMRB as a test
data receivable signal TDTRB to a test circuit (not shown).
[0161] The other configurations are the same as those of the second
embodiment.
[0162] According to the sixth embodiment, the same effects as the
aforementioned effects of the second embodiment may be obtained,
and the test using the test data may be performed.
Example of Configuration of Interface Generation Apparatus
[0163] Now, a generation apparatus for the interface apparatus
According to the embodiment of the invention is described.
[0164] FIG. 10 is a block diagram illustrating an example of an
interface generation apparatus according to the first to sixth
embodiments.
[0165] The interface generation apparatus 210 shown in FIG. 10
includes a circuit information storage unit 211, an interface
configuration information output unit 212, an interface
configuration information storage unit 213, a generation unit 214,
and an interface storage unit 215.
[0166] The circuit information storage unit 211 stores information
on a circuit connected to an interface that is an object of
generation.
[0167] The interface configuration information output unit 212
analyzes, for example, specifications that are to be satisfied by
the interface as shown in FIG. 11 from the circuit information and
outputs the results of the analysis as interface configuration
information to the interface configuration information storage unit
213.
[0168] The specifications that are to be satisfied by the interface
shown in FIG. 11 are as follows.
[0169] 1. Buffer Capacity of Stream Converter 130
[0170] 2. Types of storage Devices Used for Buffer of Stream
Converter 130
[0171] 3. Capacity of Cache Memory 140
[0172] 4. Types of storage Devices Used for Cache Memory 140
[0173] 5. Number of Input of Read Address RADR
[0174] 6. Pattern of Change in Pre-Load Address PLADR
[0175] 7. Relationship between Read Addresses
[0176] The interface configuration information storage unit 213
stores interface configuration information.
[0177] The generation unit 214 generates the interface apparatuses
shown in FIGS. 4, 5, 6, 7, 8, and 9 based on the interface
configuration information stored in the interface configuration
information storage unit 213.
[0178] The interface storage unit 215 stores the interfaces
generated by the generation unit 214.
[0179] In addition, detailed process of the interface generation
apparatus 210 shown in FIG. 10 are described later.
7. Seventh Embodiment
[0180] FIG. 12 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a seventh embodiment of the
invention.
[0181] The interface apparatus 200F according to the seventh
embodiment is different from the interface apparatus 200 according
to the first embodiment in the following points.
[0182] The interface apparatus 200F is configured to include an
address consistency verification unit in addition to the
configuration of the interface apparatus 200.
[0183] The interface apparatus 200F includes a write address
consistency verification unit 180 for verifying the consistency of
the write address WADR and a read address consistency verification
unit 190 for verifying the consistency of the pre-load address
PLADR and the consistency of the read address RADR.
[0184] The write address consistency verification unit 180
calculates a capacity of storage devices that are necessary for an
inner portion of the stream converter 130 from the output order of
the write addresses WADR.
[0185] Next, the write address consistency verification unit 180
checks whether or not the calculated value of the capacity is
larger than an actual value of the capacity of storage devices of
the stream converter 130.
[0186] The read address consistency verification unit 190
calculates a capacity of storage devices that are necessary for the
cache memory 140 from the output order of the pre-load address
PLADR and the read address RADR.
[0187] Next, the read address consistency verification unit 190
checks whether or not the calculated value of the capacity is
larger than an actual value of the capacity of storage devices of
the cache memory 140.
[0188] The other configurations are the same as those of the first
embodiment.
[0189] According to the seventh embodiment, the same effects as the
aforementioned effects of the first embodiment may be obtained, and
the consistency of the write address and the consistency of the
read address may be accurately verified.
8. Eighth Embodiment
[0190] FIG. 13 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to an eighth embodiment of the
invention.
[0191] The interface apparatus 200G according to the eighth
embodiment is different from the interface apparatus 200A according
to the second embodiment in the following points.
[0192] The interface apparatus 200G is configured to include an
address consistency verification unit in addition to the
configuration of the interface apparatus 200A.
[0193] The interface apparatus 200G includes a write address
consistency verification unit 180G for verifying the consistency of
the write address WADR and a read address consistency verification
unit 190G for verifying the consistency of the read address
RADR.
[0194] The write address consistency verification unit 180G
calculates a capacity of storage devices that are necessary for an
inner portion of the stream converter 130 from the output order of
the write addresses WADR.
[0195] Next, the write address consistency verification unit 180G
checks whether or not the calculated value of the capacity is
larger than an actual value of the capacity of storage devices of
the stream converter 130.
[0196] The read address consistency verification unit 190G
calculates a capacity of storage devices that are necessary for the
cache memory 140 from the output order of the read address
RADR.
[0197] Next, the read address consistency verification unit 190G
checks whether or not the calculated value of the capacity is
larger than an actual value of the capacity of storage devices of
the cache memory 140.
[0198] The other configurations are the same as those of the second
embodiment.
[0199] According to the eighth embodiment, the same effects as the
aforementioned effects of the second embodiment may be obtained,
and the consistency of the write address and the consistency of the
read address may be accurately verified.
[0200] FIG. 14 is a block diagram illustrating an example of a
configuration where an address consistency verification unit is
provided to the calculation processing apparatus employing a
general data transmission method.
[0201] The calculation processing apparatus 100H shown in FIG. 14
includes a first calculation unit 110, a second calculation unit
120, a main storage unit 220, and an address selector 230.
[0202] The calculation processing apparatus 100H also includes a
write address consistency verification unit 180H and a read address
consistency verification unit 190H.
[0203] In addition, the main storage unit 220, the address selector
230, the write address consistency verification unit 180H, and the
read address consistency verification unit 190H constitutes an
interface apparatus 200H.
[0204] In addition, in FIG. 14, WDT, WADR, WCTL, RDT, RADR, and ADR
denote write data, a write address, a write control signal, read
data, a read address, and a selected address, respectively.
[0205] In the calculation processing apparatus 100H shown in FIG.
14, the write data WDT output from the first calculation unit 110
are stored at a position allocated with the write address WADR in
the main storage unit 220.
[0206] Next, in the calculation processing apparatus 100H, the
second calculation unit 120 reads data at a position allocated with
the read address RADR from the storage device, so that the data
transmission from the first calculation unit 110 to the second
calculation unit 120 is performed.
[0207] The write address consistency verification unit 180H
calculates a capacity of storage devices that are necessary for an
inner portion of the main storage unit 220 from the output order of
the write addresses WADR.
[0208] Next, the write address consistency verification unit 180H
checks whether or not the calculated value of the capacity is
larger than an actual value of the capacity of storage devices of
the main storage unit 220.
[0209] The read address consistency verification unit 190H
calculates a capacity of storage devices that are necessary for the
main storage unit 220 from the output order of the read address
RADR.
[0210] Next, the read address consistency verification unit 190H
checks whether or not the calculated value of the capacity is
larger than an actual value of the capacity of storage devices of
the main storage unit 220.
[0211] Only the write address and the read address are important in
the case of checking whether or not the write address WADR from the
first calculation unit 110 or the read address RADR from the second
calculation unit 120 is consistent with the interface
apparatus.
[0212] Therefore, any interface apparatus having an address
consistency verifying function, which has a configuration different
from those of the interface apparatuses according to the first to
eighth embodiments, may be employed.
Example of Configuration of Calculation Circuit Generation
Apparatus for Calculation Circuit Connected to Interface Generation
Apparatus
[0213] Now, a circuit generation apparatus that generates a
calculation circuit that is to be connected to an interface
generation apparatus according to embodiments of the invention is
described.
[0214] FIG. 15 is a block diagram illustrating the circuit
generation apparatus that generates a calculation circuit that is
to be connected to an interface generation apparatus according to
embodiments of the invention.
[0215] As shown in FIG. 15, the circuit generation apparatus 240
includes a circuit description storage unit 241, an array access
replacement unit 242, a detailed circuit generation apparatus 243,
and a detailed circuit description storage unit 244.
[0216] The circuit description storage unit 241 stores description
representing functions of the calculation unit that is connected to
the interface apparatus according to the embodiment of the
invention.
[0217] The array access replacement unit 242 extracts reading and
writing with respect to the array, which is to be an object of
generation of the interface apparatus, from the circuit description
read from the circuit description storage unit 241 and performs
replacement with the description representing a communication
protocol for connection to the interface apparatus.
[0218] The detailed circuit generation apparatus 243 generates, for
example, detailed circuit description such as RTL or netlist by
using a general high-level composition technique or a logic
composition technique.
[0219] The detailed circuit description storage unit 244 stores the
generated detailed circuit description.
[0220] Next, the configuration of the interface apparatus according
to the embodiment is described in detail.
9. Ninth Embodiment
[0221] FIG. 16 is a block diagram illustrating an example of a
configuration of a calculation processing apparatus employing an
interface apparatus according to a ninth embodiment of the
invention.
[0222] The interface apparatus 200I according to the ninth
embodiment is different from the interface apparatus 200B according
to the third embodiment in the following points.
[0223] In other words, the first calculation unit 110 outputs the
write valid signal VWRT to the stream converter 130I.
[0224] The second calculation unit 120 outputs the pre-load address
valid signal VPLADR to the controller 150I.
[0225] The stream converter 130I outputs the stream valid signal
VSTM to the cache memory 140I.
[0226] The cache memory 140I outputs the loading number receivable
signal LDNRB to the controller 150I and outputs the pre-load
completed signal CMPL to the second calculation unit 120.
[0227] The controller 150I outputs the pre-load address receivable
signal PLADRRB to the second calculation unit 120.
[0228] In addition, the controller 150I outputs the loading number
LDN and the loading number valid signal VLDN to the cache memory
140I.
[0229] Similarly to the calculation processing apparatus 100B shown
in FIG. 6, in the calculation processing apparatus 100I as well as
the interface apparatus 200I, the second calculation unit 120 reads
the write data WDT output from the first calculation unit 110 two
by two.
[0230] In the case where the write data receivable signal SWDTRB
output from the stream converter 130I is set to an active "1 (high
level: H)", the first calculation unit 110 performs the following
outputting.
[0231] The first calculation unit 110 outputs the write address
WADR and the write data WDT, so that the write valid signal VWRT is
set to the active "1(H)".
10. Examples of Detailed Configurations
Example of Configuration of Stream Converter
[0232] FIG. 17 is a diagram illustrating an example of a
configuration of a stream converter according to embodiments of the
invention.
[0233] The stream converter 130I shown in FIG. 17 includes a buffer
131, a counter 132, a determination unit 133, a selector 134,
two-input AND gates 135 to 137, and two-input
[0234] OR gates 138 and 139.
[0235] The stream converter 130I also includes a buffer 131 for
storing pairs of the write data WDT and the write address WADR
therein.
[0236] In addition, the stream converter 130I maintains the address
ADR of the write data that are to be output as next stream data by
using the counter 132.
[0237] For example, when the count-up signal CNUP which is output
from the AND gate 137 becomes "1(H)", the counter 132 counts up by
1.
[0238] When both of the stream valid signal VSTM and the stream
receivable signal STMRB become "1", the stream converter 130I
transmits the stream data STMD. The stream valid signal VSTM and
the stream receivable signal STMRB are input to the AND gate 137.
However, when both of the stream valid signal VSTM and the stream
receivable signal STMRB becomes "1", the counter 132 counts up by
1.
[0239] The determination unit 133 determines whether or not the
value of the counter 132 is equal to the write address WADR. A
determination signal S133 as the determination result is output to
a negative input terminal of the AND gate 135, an input terminal of
the AND gate 136, and a control terminal of the selector 134.
[0240] If the value of the counter 132 is equal to the write
address WADR, the determination unit 133 sets the signal S133 to
"1(H)". If not equal, determination unit 133 sets the signal S133
to "0(L)".
[0241] If the determination signal S133 is "1", the selector 134
outputs the write data WDT as stream data STMD.
[0242] If the determination signal S133 is "0", the selector 134
outputs the buffer read data BFRDT read from the buffer 131 as
stream data STMD.
[0243] In the case where the value of the counter 132 is equal to
the value of the write address WADR so that the determination
signal S133 is set to "1" and so that the write valid signal VWRT
is set to "1", the output signal S136 of the AND gate 136 becomes
"1".
[0244] Accordingly, the stream converter 130I sets the stream valid
signal VSTM to "1" by using the OR gate 138 and outputs the write
data WDT from the selector 134 as the stream data STMD.
[0245] In the case where the value of the counter 132 is not equal
to the value of the write address WADR so that the determination
signal S133 is set to "0" and so that the write valid signal VWRT
is set to "1", the buffer write valid signal VBFWRT becomes "1", so
that the write data WDT are stored in the buffer 131.
[0246] If the storable area of the buffer 131 is full, the buffer
131 sets the buffer full signal BFFL to "1".
[0247] In addition, the value of the counter 132 is also used as a
read address BFRADR of the buffer 131.
[0248] The buffer 131 compares a list of stored addresses ADR with
the read address BFRADR of the buffer 131, and if there is found a
consistent address, the buffer 131 outputs the data, which are
stored as a pair of the address, as buffer read data BFRDT.
[0249] Next, the buffer 131 sets the buffer read data valid signal
VBFRDT to "1" and erases the output data from the buffer.
[0250] If the buffer full signal BFFL is "1" and if the stream
receivable signal STMRB is "0", since the stream converter 130I
does not receive the write data, the write data receivable signal
SWDTRB is set to inactive "0".
Example of Configuration of Cache Memory
[0251] FIG. 18 is a diagram illustrating an example of a
configuration of a cache memory according to embodiments of the
invention.
[0252] The cache memory 140I shown in FIG. 18 includes a stream
receiving controller 141, a buffer 142, and a two-input AND gate
143.
[0253] When the loading number valid signal VLDN is "1(H)", the
stream receiving controller 141 receives the loading number
LDN.
[0254] The AND gate 143 performs a logic AND operation on the
stream receivable signal STMRB and the stream valid signal VSTM and
outputs the result thereof as the valid stream receiving signal
VSTMR to the stream receiving controller 141.
[0255] The valid stream receiving signal VSTMR becomes "1" in the
case where the stream receivable signal STMRB is set to "1" and the
stream valid signal VSTM is set to "1".
[0256] Since the loading is performed once every time the valid
stream receiving signal VSTMR becomes "1", the stream receiving
controller 141 maintains the stream receivable signal STMRB to "1"
until the valid stream receiving signal VSTMR becomes "1", that is,
the number of times equal to the loading number LDN.
[0257] When receiving the loading number LDN, the stream receiving
controller 141 sets the loading number receivable signal LDNRB and
the pre-load completed signal CMPL to "0".
[0258] In addition, when the valid stream receiving signal VSTMR
becomes "1", that is, the same number of times as the loading
number LDN, the stream receiving controller 141 sets the loading
number receivable signal LDNRB and the pre-load completed signal
CMPL to "1".
[0259] The buffer 142 stores the last input stream data STMD in the
address ADR0 and the stream data STMD, which are input in the
one-preceding address ADR, every time the address ARD increases by
one. Writing of the stream data STMD in the buffer 142 is performed
when the buffer write valid signal VBFWRTC becomes "1".
[0260] For example, as shown in FIG. 18, the stream data input at
the time point n are stored in the address ADR0, and the stream
data input at the time point n-1 are stored in the address ADR1. In
addition, the stream data input at the time point n-2 are stored in
the address ADR2, and the stream data input at the time point n-3
are stored in the address ADR3.
[0261] In this state, if the buffer write valid signal VBFWRTC
becomes "1", and if the stream data D(n+1) are input, the values
are updated so that D(n+1), D(n), D(n-1), and D(n-2) are stored in
the address ADR0, the address ADR1, the address ADR2, and the
address ADR3.
[0262] In addition, the buffer 142 shown in FIG. 18 receives the
cache addresses CADR1 and CADR 2 and outputs the data stored in the
storage devices corresponding to the addresses as cache data CDT1
and CDT2.
Example of Configuration of Controller
[0263] FIG. 19 is a diagram illustrating an example of a
configuration of a controller according to embodiments of the
invention.
[0264] The controller 150I shown in FIG. 19 includes a selector
151, a latch 152 that is constructed with flip-flop, a subtractor
153, and a two-input AND gate 154.
[0265] As shown in FIG. 19, the controller 150I outputs the
pre-load address valid signal VPLADR as a loading number valid
signal VLDN.
[0266] In addition, the controller 150I outputs the loading number
receivable signal LDNRB as a pre-load address receivable signal
PLADRRB.
[0267] The selector 151 selects one of the pre-load address PLADR
newly input in response to the output signal S154 of the AND gate
154 and the old pre-load address PPLADR latched in the latch 152
and outputs the selected address to the latch 152.
[0268] The subtractor 153 subtracts the old pre-load address PPLADR
latched in the latch 152 from the newly input pre-load address
PLADR.
[0269] In this manner, if the old pre-load address PPLADR is
subtracted from the input pre-load address PLADR, the resulting
value of subtraction becomes the number of data that are not loaded
on the cache memory 140I.
[0270] The controller 150I outputs the value as the loading number
LDN to the cache memory 140I.
[0271] In the case where both the pre-load address valid signal
VPLADR and the pre-load address receivable signal PLADRRB are "1",
the controller 150I updates the old pre-load address PPLADR and the
load address LADR with the value of the newly input pre-load
address PLADR.
Example of Configuration of Address Converter
[0272] FIG. 20 is a diagram illustrating an example of a
configuration of an address converter according to embodiments of
the invention.
[0273] The address converter 160I shown in FIG. 20 includes a
subtractor 161.
[0274] As shown in FIG. 20, the address converter 160I outputs the
cache data CDT from the cache memory 140I as the read data RDT.
[0275] The cache memory 140I stores the data corresponding to the
load address LADR in the address ADR0 and the data having the same
value as that of the address ADR1 in the address that is lower by 1
than the load address LADR.
[0276] Therefore, when the subtractor 161 subtracts the read
address RADR from the load address LADR, the result of the
subtraction becomes the address of the cache memory 140I.
[0277] The address converter 160I outputs the cache address CADR
obtained in the subtraction to the cache memory 140I.
[0278] In the calculation processing apparatus 100I shown in FIG.
16, before the second calculation unit 120 outputs the read address
RADR1 and the read address RADR2, the second calculation unit 120
outputs the pre-load address PLADR that satisfies the following
relationship shown in FIG. 21. In addition, in the following
equations, CMC denotes a capacity of the cache memory 140I.
PLADR.gtoreq.RADR1
PLADR.gtoreq.RADR2
PLADR-RADR1+1.ltoreq.CMC
PLADR-RADR2+1.ltoreq.CMC [Equation 1]
[0279] The second calculation unit 120 stands by until the pre-load
completed signal CMPL becomes "1(H)", outputs the read address
RADR1 and the read address RADR2, and receives the read data RDT1
and the read data RDT2.
[0280] The stream converter 130I shown in FIG. 17, the cache memory
140I shown in FIG. 18, the controller 150I shown in FIG. 19, and
the address converter 160I shown in FIG. 20 may be implemented with
more optimal configurations according to the specifications of the
first calculation unit 110 and the second calculation unit 120.
[0281] For example, it may be assumed that the first calculation
unit 110 has the specifications shown in FIG. 22 and the second
calculation unit 120 has the specifications shown in FIG. 23.
[0282] As shown in FIG. 22, the write address WADR output from the
first calculation unit 110 is increased by 1 from 0, that is, in
this order of 0, 1, 2, 3, . . . , WIDTH-1.
[0283] The order of the write addresses WADR is the same s the
order of the stream data that the stream converter 130I sorts and
outputs.
[0284] Therefore, the function of sorting the write data is not
necessary for the stream converter 130I.
[0285] In the case where the stream converter 130I is connected to
the first calculation unit 110 expressed by FIG. 22, as shown in
FIG. 24, the stream converter 130I may be configured to output the
write data WDT as the stream data STMD.
[0286] The pre-load address PLADR, the read address RADR1, and the
read address RADR2 output from the second calculation unit 120
having the specifications shown in FIG. 23 are illustrated in FIG.
25.
[0287] Since two data, that is, the predicted address and the
one-preceding address thereof, are used, cache memory 140I in the
case of the second calculation unit 120 expressed in FIG. 23 may be
provided with only two storage devices.
[0288] In the case where the cache memory 140I includes two storage
devices, the cache address may be constructed with one bit.
[0289] As shown in FIG. 25, since the loading number LDN is
typically 1 and the cache address CADR1 is typically 0, any
calculation unit for calculating the loading number LDN and the
cache address CADR1 is not necessary.
[0290] As shown in FIG. 25, since the cache address CADR1 is 0 or
1, a calculation unit for calculating the cache address CADR2 may
have a 1-bit width.
[0291] In summary, in the interface apparatus that is to be
connected to the second calculation unit 120 having the
specifications shown in FIG. 23, the cache memory 140J may be
configured as shown in FIG. 26, and the controller 150J and the
address converter 160J may be configured as shown in FIG. 27.
[0292] As shown in FIG. 26, the configuration of the cache memory
140J corresponding to the connection to the second calculation unit
120 expressed in FIG. 23 is optimized as the configuration where
the internal buffer 142J includes only two storage devices 1421 and
1422 corresponding to the two data. The buffer 142J shown in FIG.
26 includes selectors 1423 to 1425 in addition to the storage
devices 1421 and 1422. The storage devices 1421 and 1422 are
constructed with, for example, flip-flops.
[0293] In addition, the configurations of the controller 150J and
the address converter 160J corresponding to the connection to the
second calculation unit 120 expressed in FIG. 23 are shown in FIG.
27.
[0294] In the example shown in FIG. 27, the controller 150J is not
provided with a subtractor, and a lower bit selector 155 is
disposed at the input stage for the pre-load address PLADR.
[0295] Similarly, a lower bit selector 162 is disposed at the input
state for the read address RADR2 in the address converter
160J-2.
[0296] In the embodiment, the calculation using the pre-load
address PLADR and the read address RADR is optimized so as to have
a 1-bit width, and the configuration is optimized so that the
loading number LDN is fixed to 1 and the cache address CADR1 is set
to 0.
[0297] In this manner, by optimizing the configuration of the
interface apparatus according to the specifications of the
connected calculation unit, the interface apparatus having a small
overhead may be implemented.
[0298] Now, the processes of the interface generation apparatus 210
shown in FIG. 10 are described in detail.
[0299] Herein, the operations of the interface configuration
information output unit 212 shown in FIG. 10 are described with
reference to FIGS. 28, 29, and 30.
[0300] FIG. 28 is a diagram illustrating a flowchart of operations
of the interface configuration information output unit 212 in the
interface generation apparatus shown in FIG. 10.
[0301] FIG. 29 is a diagram illustrating an example of circuit
description of a calculation unit.
[0302] FIG. 30 is a diagram illustrating an example of difference
in a calculation equation for addresses extracted from circuit
description shown in FIG. 29.
[0303] First, interface configuration information output unit 212
reads the circuit description of the calculation unit from the
circuit information storage unit 211 and converts the circuit
description into internal database in the interface configuration
information output unit 212 (ST1).
[0304] Next, the interface configuration information output unit
212 extracts all the values or equations output as the read address
RADR (ST2).
[0305] For example, in the case where the circuit description of
the calculation unit expressed in FIG. 29 is read, since there are
four read addresses RADR which are output: x output from
[pre_load_address]; x output from [read_address_a]; x and (x-1)
output from [read_address_b], the three x's and one (x-1) are
extracted.
[0306] Next, the interface configuration information output unit
212 calculates differences among all combinations in the extracted
address calculation equation (ST3).
[0307] For example, in the case of the address calculation equation
extracted from the circuit description shown in FIG. 29, the
difference between x's is 0, and the difference between (x-1) and x
is 1 as shown in FIG. 30.
[0308] The value obtained by adding 1 to the maximum value among
the calculated differences is set to a capacity of the storage
devices that are necessary for the cache memory 140.
[0309] Finally, the value of 2 that is obtained by adding 1 to the
maximum value, which is 1 among the calculated differences is
output as a necessary capacity of the cache memory (ST4).
[0310] In this manner, the interface generation apparatus 210 shown
in FIG. 10 generates the interface based on the interface
configuration information output from the interface configuration
information output unit 212.
[0311] In the example shown in FIG. 29, as the interface
configuration information, (capacity of cache memory 140)=2 is
output. Based on the information, the interface apparatus including
the cache memory 140 having the storage device having a capacity
CMC2 as shown in FIG. 26 is generated.
[0312] Next, an example of the verification interface apparatus
according to an embodiment of the invention is described.
[0313] FIG. 31 is a diagram illustrating an example of a
configuration of a calculation processing apparatus employing the
verification interface apparatus according to embodiments of the
invention.
[0314] The verification interface apparatus 200K of the calculation
processing apparatus 100K shown in FIG. 31 has the same
configuration as that of the interface apparatus 200G of the
calculation processing apparatus 100G shown in FIG. 13.
[0315] However, the interface apparatus 200K is different from the
interface apparatus 200G in that the write valid signal VWRT, the
stream valid signal VSTM, and the read address valid signal VRADR
are used.
[0316] Herein, an example of operations of the write address
consistency verification unit 180K of the verification interface
apparatus shown in FIG. 31 is described.
[0317] FIG. 32 is a diagram illustrating a flowchart of operations
of the write address consistency verification unit 180K in the
verification interface apparatus shown in FIG. 31.
[0318] First, "list" which stores information of the write address
WADR is reset to null, and "next" which stores the write address
WADR of the write data WDT that are to be output as the next stream
data STMD is reset to 0 (ST11).
[0319] Next, the write address consistency verification unit 180K
waits for updating of the write address WADR (ST12), and in the
case where the write valid signal VWRT becomes "1" at the time of
the updating, the write address consistency verification unit 180K
adds the value of the write address to the "list" (ST13 and
ST14).
[0320] The write address consistency verification unit 180K checks
whether or not there is a write address WADR registered in the
"list" that is equal to the "next" (ST15).
[0321] If there is an equal write address in Step ST15, the write
address consistency verification unit 180K erases the equal write
address from the "list" and perform "next"="next"+1 (ST16) and
returns to the step of checking again whether or not there is a
write address registered in the "list" that is equal to the
"next".
[0322] If there is no equal write address in Step ST15, the write
address consistency verification unit 180K checks the number of
write addresses registered in the "list" is equal to or smaller
than the buffer capacity of the stream converter included in the
interface apparatus (ST17).
[0323] If the number exceeds the buffer capacity, the write
addresses that the stream converter in the interface apparatus may
not be able to cope with may be input, an alarm is displayed, and
the process is ended (ST18).
[0324] If the number does not exceed the buffer capacity, it is
checked whether or not the simulation is completed (ST19), and if
the simulation is completed, the process is ended. If the
simulation is not completed, the write address consistency
verification unit 180K waits for the updating of the next write
address.
[0325] FIG. 33 is a diagram illustrating a detailed table listing
exemplary operations of the write address consistency verification
unit in the verification interface apparatus shown in FIG. 32.
[0326] FIG. 33 illustrates the write addresses WADR and the write
valid signals VWRT that are input at the time point t, the internal
states of the write address consistency verification unit 180K, and
the occurrence of the alarm display in the case where the buffer
capacity of the stream converter 130 is 2.
[0327] At the time point to, since the write valid signal VWRT is
"0", no operation is performed.
[0328] At the time point t1, since the write valid signal VWRT is
"1", the write address WADR0 is input to the "list".
[0329] Next, as a result of comparison, the addresses registered to
the "next" and the "list" are equal to the address ADR0. Therefore,
the address of 0 is erased from the "list", so that the "list"
returns to null. In addition, since 1 is added to the "next", the
value of the "next" becomes 1.
[0330] At the time point t2, the write address WADR4 is added to
the "list". Since the address ADR of the "list" is not equal to
that of the "next", the "list" becomes {4}, and the "next" becomes
1.
[0331] At the time point t3, the write address WADR2 is added to
the "list". Since the address ADR of the "list" is not equal to
that of the "next", the "list" becomes {4, 2}, and the "next"
becomes 1.
[0332] At the time point t4, the write address WADR1 is added to
the "list". Since the address {4, 2, 1} of the "list" is equal to
the "next"=1, 1 is erased from the "list", the "list" becomes {4,
2}, and the "next" becomes 2.
[0333] Next, it is checked again whether the address of the "list"
is equal to the "next" by comparing the address {4, 2} of the
"list" with the "next"=2, and 2 is erased from the "list", so that
the "list" becomes {4}, and the "next" becomes 3.
[0334] At the time point t5, the write address WADR5 is added to
the "list", so that the "list" is set to {4, 5} and so that the
"next" is set to 3.
[0335] At the time point t6, the write address WADR6 is added to
the "list", so that the "list" is set to {4, 5, 6} and so that the
"next" is set to 3. At this time, the number of addresses
registered in the "list" becomes 3, and since the number exceeds
the buffer capacity of 2 of the stream converter 130, the alarm is
displayed and the operation is ended.
[0336] Next, an example of operations of the read address
consistency verification unit 190K of the verification interface
apparatus shown in FIG. 31 is described.
[0337] FIG. 34 is a diagram illustrating a flowchart of operations
of the read address consistency verification unit 190K in the
verification interface apparatus shown in FIG. 31.
[0338] First, the read address consistency verification unit 190K
resets the "max" that stores the maximum value of the addresses,
which are read up to the current time point, to -1 (ST21).
[0339] Next, read address consistency verification unit 190K waits
for the updating the read address RADR (ST22).
[0340] Next, in the case where the read address valid signal VRADR
becomes "1" at the time of the updating (ST23), the read address
consistency verification unit 190K checks whether or not the read
address is larger than the "max" (ST24). If the read address is
larger than the "max", the read address consistency verification
unit 190K replaces the value of the "max" with the value of the
read address (ST25).
[0341] After the updating of the "max", the read address
consistency verification unit 190K checks whether the (max-read
address+1) indicating the necessary cache memory capacity is larger
than a real cache memory capacity (ST26).
[0342] If the (max-read address+1) is larger than the cache memory
capacity in Step ST26, an alarm is displayed, and the operation is
ended (ST27).
[0343] If the (max-read address+1) is not larger than the cache
memory capacity in Step ST26, the read address consistency
verification unit 190K finally checks whether the simulation is
completed (ST28). If the simulation is completed, the operation is
ended. If the simulation is not completed, the read address
consistency verification unit 190K waits for the updating of the
next read address.
[0344] FIG. 35 is a diagram illustrating a detailed table listing
exemplary operations of the read address consistency verification
unit in the verification interface apparatus shown in FIG. 34.
[0345] FIG. 35 illustrates the read addresses RADR and the read
address valid signals VRADR that are input at the time points t,
the internal states of the read address consistency verification
unit 190K, and the occurrence of the alarm display in the case
where the capacity of the storage devices of the cache memory 140
is 2.
[0346] At the time point to, since the read address valid signal
VRADR is "0", any operation is not performed.
[0347] At the time point t1, since the read address valid signal
VRADR is "1", by comparing the "max"=-1 with the read address of 1,
the read address is larger than the "max", so that the read address
of 1 is inserted into the "max".
[0348] Next, it is checked whether or not the (max-read address+1)
exceeds the capacity of the cache memory 140, that is, 2. Since the
(max-read address+1) is 1(=1-1+1), the (max-read address+1) does
not exceed the capacity.
[0349] As the calculation proceeds in this manner, at the time pint
5, the (max-read address+1) becomes 3, which exceeds the cache
memory capacity of 2. Therefore, at the time point t5, the alarm
displayed, and the operation is ended.
[0350] Next, the processes performed by the circuit generation
apparatus 240 shown in FIG. 15 are described in detail.
[0351] Herein, operations of the array access replacement unit 242
shown in FIG. 15 are described with reference to FIGS. 36, 37, and
38.
[0352] FIG. 36 is a diagram illustrating a flowchart of the
operations of the array access replacement unit 242 in the circuit
generation apparatus shown in FIG. 15.
[0353] FIG. 37 is a diagram illustrating an example of circuit
description stored in a circuit description storage unit.
[0354] FIG. 38 is a diagram illustrating an example where array
access is replaced with description of performing connection to an
interface apparatus.
[0355] First, the array access replacement unit 242 reads the
circuit description of the calculation unit from the circuit
description storage unit 241 and converts the circuit description
into the internal database of the array access replacement unit 242
(ST31).
[0356] Next, the array access replacement unit 242 extracts the
write access to the array that is the object of generation the
interface (ST32), and replace a portion of performing the extracted
write access to the array with the description for connection to
the interface apparatus according to the embodiment (ST33).
[0357] At the time of the replacement, first, the extracted write
access to the array is removed, and next, the description of
outputting the write address WADR and the write data WDT to the
interface apparatus is added to the position where the write access
to the array is removed. The write address WADR is set to the value
of index of the array, and the write data WDT are the data that are
written in the array.
[0358] Next, the array access replacement unit 242 extracts the
read access from the array that is the object of generation the
interface (ST34), and replaces a portion of performing the
extracted read access from the array with the description for
connection to the interface apparatus according to the embodiment
(ST35).
[0359] At the time of the replacement, first, the extracted read
access from the array is removed, and next, the description of
outputting the read address RADR and inputting the read data RDT
with respect to the interface apparatus is added to the position
where the read access from the array is removed.
[0360] The read address is set to the value of index of the array,
and the value of the received read data is inserted into a variable
where the value of reading the array is inserted.
[0361] Finally, the array access replacement unit 242 extracts the
description of allocating the pre-load address (ST36), and replaces
the description with the description for connection to the
interface apparatus (ST37).
[0362] At the time of the replacement, first, the description of
allocating the pre-load address is removed, and next, the
description of outputting the pre-load address PLADR to the
interface apparatus is added to the position where the description
of allocating the pre-load address is removed. The pre-load address
PLADR is set to the value of the description allocated to the
pre-load address.
[0363] FIGS. 37 and 38 illustrate a detailed example of the
operation of the array access replacement unit shown in FIG.
36.
[0364] The circuit description expressed in FIG. 37 is stored in
the circuit description storage unit 241. The array is set to the
array that is the object of generation of the interface, and the
pre-load address is allocated with the comment
"//pre_load_address=".
[0365] In this case, as shown in FIG. 38, the array access is
replaced with the description where the connection to the interface
apparatus is performed.
[0366] FIGS. 39 and 40 illustrate another example of the operation
of the array access replacement unit shown in FIG. 36.
[0367] Unlike the example of FIGS. 37 and 38 where the array that
is the object of generation of the interface is a one-dimensional
array, the array in the example of FIGS. 39 and 40 is a
two-dimensional array. In addition, the array that is the object of
generation of the interface may be a three-or-more dimensional
array.
[0368] In the circuit generation apparatus 240 shown in FIG. 15,
the array access replacement unit 242 inputs the generated circuit
description to the detailed circuit generation apparatus 243 so
that the circuit description is converted into the more detailed
circuit description.
[0369] The detailed circuit generation apparatus 243 use a general
operation composition method.
[0370] The detailed circuit generation apparatus 243 determines
detailed calculation timings of the circuit description expressed
by the C language having a high level of abstraction, which is
output from the array access replacement unit 242, and generates
the circuit description that is more detailed than the circuit
description expressed in a register transfer level or a
netlist.
[0371] According to the embodiments described above, the following
effects may be obtained.
[0372] The interface apparatus of connecting calculation units of
accessing data by using address allocation may be implemented with
storage devices having minimum capacity, so that area of circuits
may be reduced.
[0373] Even in the case where the calculation unit may be easily
designed by using the specifications for accessing data by using
the address allocation, in the technology in the related art, the
specifications for accessing data by using the address allocation
may not be used as the specifications of the calculation unit in
order to prevent an increase in the area of circuits. Therefore,
there is a problem in that the design of the calculation unit is
complicated.
[0374] However, by the interface apparatus According to the
embodiments of the invention, the calculation units of accessing
data by using the address allocation may be connected to each other
with a practical area of circuits, the efficiency of design of the
calculation unit may be improved.
[0375] Particularly, in general, in many cases of developing
algorithms, the calculation unit of accessing data by using the
address allocation may be designed.
[0376] By using the interface apparatus according to the
embodiments of the invention, since the description generated in
the development of algorithms may be directly used again for the
design of circuits, the same design processes are prevented from
being performed in the development of algorithms and the design of
circuits, the number of design processes may be greatly
reduced.
[0377] In addition, the invention are not limited to the
aforementioned embodiments, but various changes and modifications
may be made by those skilled in the art within the scope of the
invention without departing from the spirit of the invention.
[0378] In addition, the aforementioned methods may be implemented
by a program including the aforementioned procedures, which are
executed by a CPU of a computer.
[0379] In addition, the program may be recorded on a recording
medium such as a semiconductor memory, a magnetic disc, an optical
disc, and a floppy (registered trade mark) disc, and a computer, in
which the recording medium is set, may be configured to access and
execute the program.
[0380] The present application contains subject matter related to
that disclosed in Japanese Priority Patent Application JP
2009-019893 filed in the Japan Patent Office on Jan. 30, 2009, the
entire content of which is hereby incorporated by reference.
[0381] It should be understood by those skilled in the art that
various modifications, combinations, sub-combinations and
alterations may occur depending on design requirements and other
factors insofar as they are within the scope of the appended claims
or the equivalents thereof.
* * * * *