U.S. patent application number 13/302940 was filed with the patent office on 2013-01-17 for power supply system for memories.
This patent application is currently assigned to HON HAI PRECISION INDUSTRY CO., LTD.. The applicant listed for this patent is BO TIAN, KANG WU. Invention is credited to BO TIAN, KANG WU.
Application Number | 20130016578 13/302940 |
Document ID | / |
Family ID | 47481635 |
Filed Date | 2013-01-17 |
United States Patent
Application |
20130016578 |
Kind Code |
A1 |
WU; KANG ; et al. |
January 17, 2013 |
POWER SUPPLY SYSTEM FOR MEMORIES
Abstract
A power supply system for memory modules includes a control unit
and a voltage regulator. The control unit includes a basic
input/output system (BIOS) and a control chip connected to the
BIOS. The BIOS controls the control chip to output a control signal
according to the number of the memory modules mounted in memory
slots. The voltage regulator is connected to the control chip
through first and second general purpose input/output (GPIO) buses.
The voltage regulator receives the control signal from the control
chip through the first and second GPIO buses and regulates power
supply modes, to output different phase voltages to the memory
modules mounted in the memory slots.
Inventors: |
WU; KANG; (Shenzhen City,
CN) ; TIAN; BO; (Shenzhen City, CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
WU; KANG
TIAN; BO |
Shenzhen City
Shenzhen City |
|
CN
CN |
|
|
Assignee: |
HON HAI PRECISION INDUSTRY CO.,
LTD.
Tu-Cheng
TW
HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
Shenzhen City
CN
|
Family ID: |
47481635 |
Appl. No.: |
13/302940 |
Filed: |
November 22, 2011 |
Current U.S.
Class: |
365/226 |
Current CPC
Class: |
G11C 5/04 20130101; G06F
1/26 20130101; G11C 5/147 20130101 |
Class at
Publication: |
365/226 |
International
Class: |
G11C 5/14 20060101
G11C005/14 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 13, 2011 |
CN |
201110195312.9 |
Claims
1. A power supply system applicable to memory modules mounted in
memory slots, the power supply system comprising: a control unit
comprising a basic input/output system (BIOS) and a control chip
connected to the BIOS and the memory slots, wherein the BIOS
controls the control chip to output a control signal according to
the number of the memory modules mounted in the memory slots; and a
voltage regulator connected to the control chip through first and
second general purpose input/output (GPIO) buses, wherein the
voltage regulator receives the control signal from the control chip
through the first and second GPIO buses and regulates power supply
modes, to output different phase voltages to the memory modules
mounted in the memory slots.
2. The power supply system of claim 1, further comprising a pull-up
circuit, wherein the pull-up circuit comprises at least one
resistor, a first end of the at least one resistor is connected to
a power source, and a second end of the at least one resistor is
connected to at least one of the GPIO bus.
3. The power supply system of claim 1, wherein the control chip is
a platform controller hub.
4. The power supply system of claim 1, wherein the control chip is
a south bridge chip.
5. The power supply system of claim 1, wherein when the number of
the memory module mounted in the memory slot is less than 3, the
power supply modes of the voltage regulator is regulated to a
one-phase power mode by the BIOS; when the number of the memory
module mounted in the memory slot is greater than 3 and less than
6, the power supply modes of the voltage regulator is regulated to
a two-phase power mode by the BIOS; when the number of the memory
module mounted in the memory slot is greater than 6, the power
supply modes of the voltage regulator is regulated to a full
multiphase power mode by the BIOS.
6. The power supply system of claim 1, wherein the memory slots are
dual in-line memory module memory slots.
Description
BACKGROUND
[0001] 1. Technical Field
[0002] The present disclosure relates to a power supply system for
memories.
[0003] 2. Description of Related Art
[0004] Many memory modules are mounted in memory slots in a
computer system for adding storage capacity. These memory modules
receive voltage from a voltage regulator arranged on a motherboard
of the computer system through the memory slots. However, the
voltage regulator will provide full multiphase power to these
memory slots, which may not be fully utilized, thus wasting energy.
Therefore, there is room for improvement in the art.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Many aspects of the embodiments can be better understood
with reference to the following drawings. The components in the
drawings are not necessarily drawn to scale, the emphasis instead
being placed upon clearly illustrating the principles of the
present embodiments. Moreover, in the drawings, like reference
numerals designate corresponding parts throughout the several
views.
[0006] FIG. 1 is a block diagram of a power supply system for
memories in accordance with an exemplary embodiment of the present
disclosure.
[0007] FIG. 2 is a circuit diagram of the power supply system of
FIG. 1.
DETAILED DESCRIPTION
[0008] The disclosure, including the drawings, is illustrated by
way of example and not by way of limitation. References to "an" or
"one" embodiment in this disclosure are not necessarily to the same
embodiment, and such references mean at least one.
[0009] Referring to FIG. 1, a power supply system 1 is used for
providing voltages to memory modules 20 which are mounted in memory
slots 60 of a motherboard (not shown). The power supply system 1 in
accordance with an exemplary embodiment includes a control unit 10,
a pull-up circuit 30, and a voltage regulator 40. The control unit
10 is connected between the memory slots 60 and the pull-up circuit
30. The voltage regulator 40 is connected between the memory slots
60 and the pull-up circuit 30.
[0010] Referring to FIG. 2, in one embodiment, the memory slots 60
include eight dual in-line memory module (DIMM) memory slots. The
control unit 10 includes a basic input/output system (BIOS) 100 and
a control chip 102 connected to the BIOS 100. The control chip 102
is a platform controller hub (PCH) chip or a south bridge chip. The
control chip 102 outputs a control signal to the voltage regulator
40 through first and second general purpose input/output (GPIO)
buses 50 and 70. The control chip 102 reads information, such as
storage capacity, frequencies, types, and locations of the memory
modules 20, which are mounted in the memory slots 60 through a
system management bus (SMBus) 80. The information of the memory
modules 20 can be displayed, for conveniently regulating power
supply modes of the voltage regulator 40 by the BIOS 100.
[0011] The pull-up circuit 30 includes resistors R1 and R2. First
ends of the resistors R1 and R2 are connected to a power source
VCC, and second ends of the resistors R1 and R2 are respectively
connected to the first and second GPIO buses 50 and 70. When the
first and second GPIO buses 50 and 70 receive high level signals,
the resistors R1 and R2 stabilize the high level signals from the
control chip 102 to the voltage regulator 40. In other embodiments,
the pull-up circuit 30 is not inserted to save cost if stabilizing
is not needed for the application.
[0012] In use, power supply modes of the voltage regulator 40 can
be regulated by the BIOS 100. For example, when the number of the
memory modules 20 mounted in the memory slots 60 is less than 3,
the power supply mode of the voltage regulator 40 is regulated to a
one-phase power mode. When the number of the memory modules 20
mounted in the memory slots 60 is greater than 3 and less than 6,
the power supply mode of the voltage regulator 40 is regulated to a
two-phase power mode. When the number of the memory modules 20
mounted in the memory slots 60 is greater than 6, the power supply
mode of the voltage regulator 40 is regulated to a full multiphase
power mode.
[0013] When the voltage regulator 40 are regulated to the one-phase
power mode by the BIOS 100, the control chip 102 outputs low level
signals to the voltage regulator 40 through the first and second
GPIO buses 50 and 70. Thus, the voltage regulator 40 outputs
one-phase power to the memory modules 20 mounted in the memory
slots 60. When the voltage regulator 40 is regulated to the
two-phase power mode by the BIOS 100, the control chip 102 outputs
a low level signal and a high level signal to the voltage regulator
40 respectively through the first and second GPIO buses 50 and 70.
Thus, the voltage regulator 40 outputs two-phase power to the
memory modules 20 mounted in the memory slots 60. When the voltage
regulator 40 is regulated to the full multiphase power mode by the
BIOS 100, the control chip 102 outputs high level signals to the
voltage regulator 40 through the first and second GPIO buses 50 and
70. Thus, the voltage regulator 40 outputs full multiphase power to
the memory modules 20 mounted in the memory slots 60. In a default
power mode of the voltage regulator 40, namely, the power supply
mode of the voltage regulator 40 not regulated by the BIOS 100, the
control chip 102 outputs high level signals to the voltage
regulator 40 through the first and second GPIO buses 50 and 70,
namely, the voltage regulator 40 outputs full multiphase power to
the memory modules 20 mounted in the memory slots 60.
[0014] The power supply system 1 can control the power supply modes
of the voltage regulator 40 by the BIOS 100, to make the voltage
regulator 40 output different voltages to the memory modules 20
according to the number of the memory modules 20 mounted in the
memory slots 60. Therefore, the power supply system 1 saves
energy.
[0015] Even though numerous characteristics and advantages of the
disclosure have been set forth in the foregoing description,
together with details of the structure and function of the
disclosure, the disclosure is illustrative only, and changes may be
made in detail, especially in matters of shape, size, and the
arrangement of parts within the principles of the disclosure to the
full extent indicated by the broad general meaning of the terms in
which the appended claims are expressed.
* * * * *