U.S. patent application number 13/622612 was filed with the patent office on 2013-01-17 for nonvolatile semiconductor memory device and method of manufacturing the same.
The applicant listed for this patent is Shosuke Fujii, Jun Fujiki, Atsuhiro Kinoshita, Kiwamu Sakuma. Invention is credited to Shosuke Fujii, Jun Fujiki, Atsuhiro Kinoshita, Kiwamu Sakuma.
Application Number | 20130015519 13/622612 |
Document ID | / |
Family ID | 44648630 |
Filed Date | 2013-01-17 |
United States Patent
Application |
20130015519 |
Kind Code |
A1 |
Fujii; Shosuke ; et
al. |
January 17, 2013 |
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING
THE SAME
Abstract
According to one embodiment, a nonvolatile semiconductor memory
device includes first to n-th semiconductor layers which are
stacked in a first direction perpendicular to a surface of a
semiconductor substrate and which extend in a second direction
parallel to the surface of the semiconductor substrate, an
electrode which extends in the first direction along side surfaces
of the first to n-th semiconductor layers, the side surfaces of the
first to n-th semiconductor layers exposing in a third direction
perpendicular to the first and second directions, and first to n-th
charge storage layers located between the first to n-th
semiconductor layers and the electrode respectively. The first to
n-th charge storage layers are separated from each other in areas
between the first to n-th semiconductor layers.
Inventors: |
Fujii; Shosuke;
(Yokohama-shi, JP) ; Sakuma; Kiwamu;
(Yokohama-shi, JP) ; Fujiki; Jun; (Yokohama-shi,
JP) ; Kinoshita; Atsuhiro; (Kamakura-shi,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Fujii; Shosuke
Sakuma; Kiwamu
Fujiki; Jun
Kinoshita; Atsuhiro |
Yokohama-shi
Yokohama-shi
Yokohama-shi
Kamakura-shi |
|
JP
JP
JP
JP |
|
|
Family ID: |
44648630 |
Appl. No.: |
13/622612 |
Filed: |
September 19, 2012 |
Current U.S.
Class: |
257/324 ;
257/E21.18; 257/E29.309; 438/479 |
Current CPC
Class: |
H01L 27/11521 20130101;
H01L 27/11551 20130101; H01L 27/11565 20130101; H01L 27/11578
20130101; H01L 27/11519 20130101 |
Class at
Publication: |
257/324 ;
438/479; 257/E29.309; 257/E21.18 |
International
Class: |
H01L 29/792 20060101
H01L029/792; H01L 21/28 20060101 H01L021/28 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 19, 2010 |
JP |
PCT/JP2010/054771 |
Claims
1. A nonvolatile semiconductor memory device comprising: a
semiconductor substrate; first to n-th semiconductor layers (n is a
natural number equal to or more than 2) which are stacked in a
first direction perpendicular to a surface of the semiconductor
substrate and which extend in a second direction parallel to the
surface of the semiconductor substrate; an electrode which extends
in the first direction along side surfaces of the first to n-th
semiconductor layers, the side surfaces of the first to n-th
semiconductor layers exposing in a third direction perpendicular to
the first and second directions; and first to n-th charge storage
layers located between the first to n-th semiconductor layers and
the electrode respectively, wherein the first to n-th charge
storage layers are separated from each other in areas between the
first to n-th semiconductor layers.
2. The device of claim 1, wherein the uppermost layer among the
first to n-th semiconductor layers is a dummy layer in which dummy
cells as non-memory cells are provided.
3. The device of claim 2, wherein a width of the uppermost layer in
the first direction is wider than a width of the semiconductor
layer except the uppermost layer in the first direction.
4. The device of claim 1, wherein the first to n-th charge storage
layers are separated by insulators between the first to n-th
semiconductor layers.
5. The device of claim 1, wherein the first to n-th charge storage
layers comprise materials respectively, and the first to n-th
charge storage layers are separated by oxides of the materials.
6. The device of claim 1, wherein the first to n-th charge storage
layers are separated by cavities between the first to n-th
semiconductor layers.
7. The device of claim 1, wherein the first to n-th charge storage
layers are silicon nitride, and are separated by silicon
oxynitride.
8. The device of claim 1, wherein the first to n-th charge storage
layers are covered with the electrode and are independently each
other.
9. A nonvolatile semiconductor memory device comprising: a
semiconductor substrate; semiconductor layers which are stacked in
a first direction perpendicular to a surface of the semiconductor
substrate and which extend in a second direction parallel to the
surface of the semiconductor substrate; and memory strings which
use the semiconductor layers as channels respectively, wherein the
memory strings comprises electrodes which extend in the first
direction along side surfaces of the semiconductor layers and
charge storage layers located between the semiconductor layers and
the electrodes respectively, the side surfaces of the semiconductor
layers are exposed in a third direction perpendicular to the first
and second directions, and the charge storage layers are separated
from each other in areas between the semiconductor layers.
10. The device of claim 9, wherein the uppermost layer among the
semiconductor layers is a dummy layer in which dummy cells as
non-memory cells are provided.
11. The device of claim 10, wherein a width of the uppermost layer
in the first direction is wider than a width of the semiconductor
layer except the uppermost layer in the first direction.
12. The device of claim 10, wherein the charge storage layers are
separated by insulators between the semiconductor layers.
13. The device of claim 9, wherein the first to n-th charge storage
layers comprise materials respectively, and the first to n-th
charge storage layers are separated by oxides of the materials.
14. The device of claim 9, wherein the charge storage layers are
separated by cavities between the semiconductor layers.
15. The device of claim 9, wherein the charge storage layers are
silicon nitride, and are separated by silicon oxynitride.
16. The device of claim 9, wherein the charge storage layers are
covered with the electrodes and are independently each other.
17. A method of manufacturing a nonvolatile semiconductor memory
device, the method comprising: forming a stacked layer structure
comprising a first insulating layer, a first semiconductor layer, .
. . an n-th insulating layer, an n-th semiconductor layer, and an
(n+1)-th insulating layer (n is a natural number equal to or more
than 2) which are stacked in order thereof in a first direction
perpendicular to a surface of a semiconductor substrate, the
stacked layer structure extending in a second direction parallel to
the surface of the semiconductor substrate; forming first to n-th
recesses extending in the second direction by etching side surfaces
of the first to n-th semiconductor layers which are exposed in a
third direction perpendicular to the first and second directions;
forming first to n-th charge storage layers on the side surfaces of
the first to n-th semiconductor layers which are exposed in the
third direction, the first to n-th recesses filled with the first
to n-th charge storage layers; forming an electrode which extends
in the first direction along with side surfaces of the first to
n-th charge storage layers which are exposed in the third
direction; exposing the n-th semiconductor layer and the n-th
charge storage layer in the first direction by etching the (n+1)-th
insulating layer using the electrode as a mask; and separating the
first to n-th charge storage layers in the second direction by
etching the n-th charge storage layer, the n-th insulating layer, .
. . the first charge storage layer using the electrode and the n-th
semiconductor layer as masks.
18. A method of manufacturing a nonvolatile semiconductor memory
device, the method comprising: forming a stacked layer structure
comprising a first temporary layer, a first semiconductor layer, .
. . an n-th temporary layer, an n-th semiconductor layer, and an
(n+1)-th temporary layer (n is a natural number equal to or more
than 2) that are stacked in order thereof in a first direction
perpendicular to a surface of a semiconductor substrate, the
stacked layer structure extending in a second direction parallel to
the surface of the semiconductor substrate; forming first to n-th
recesses extending in the second direction by etching side surfaces
of the first to n-th semiconductor layers which are exposed in a
third direction perpendicular to the first and second directions;
forming first to n-th charge storage layers on the side surfaces of
the first to n-th semiconductor layers which are exposed in the
third direction, the first to n-th recesses filled with the first
to n-th charge storage layers; forming an electrode which extends
in the first direction along with side surfaces of the first to
n-th charge storage layers which are exposed in the third
direction; exposing the n-th semiconductor layer and the n-th
charge storage layer in the first direction by etching the (n+1)-th
temporary layer using the electrode as a mask; separating the first
to n-th charge storage layers in the second direction by etching
the n-th charge storage layer, the n-th temporary layer, . . . the
first charge storage layer using the electrode and the n-th
semiconductor layer as masks; and selectively removing the first to
(n+1)-th temporary layers.
19. A method of manufacturing a nonvolatile semiconductor memory
device, the method comprising: forming a stacked layer structure
comprising a first temporary layer, a first semiconductor layer, .
. . an n-th temporary layer, an n-th semiconductor layer, and an
(n+1)-th temporary layer (n is a natural number equal to or more
than 2) that are stacked in order thereof in a first direction
perpendicular to a surface of a semiconductor substrate, the
stacked layer structure extending in a second direction parallel to
the surface of the semiconductor substrate; forming a stacked layer
structure comprising a first gate insulating layer, a combined
charge storage layer, a second gate insulating layer, and an
electrode that are stacked in order, the stacked layer structure
extending in the first direction along with side surfaces of the
first to n-th semiconductor layers which are exposed in a third
direction perpendicular to the first and second directions;
selectively removing the first to (n+1)-th temporary layers; and
forming first to n-th charge storage layers which are separated by
selectively oxidizing the combined charge storage layer from
regions in which the first to (n+1)-th temporary layers are
removed.
20. A method of manufacturing a nonvolatile semiconductor memory
device, the method comprising: forming a stacked layer structure
comprising a first insulating layer, a first semiconductor layer, .
. . an n-th insulating layer, an n-th semiconductor layer, and an
(n+1)-th insulating layer (n is a natural number equal to or more
than 2) which are stacked in order thereof in a first direction
perpendicular to a surface of a semiconductor substrate, the
stacked layer structure extending in a second direction parallel to
the surface of the semiconductor substrate; forming first to n-th
recesses extending in the second direction by etching side surfaces
of the first to n-th semiconductor layers which are exposed in a
third direction perpendicular to the first and second directions;
forming first to n-th charge storage layers on the side surfaces of
the first to n-th semiconductor layers which are exposed in the
third direction, the first to n-th recesses filled with the first
to n-th charge storage layers; exposing side surfaces of the first
to n-th charge storage layers which are exposed in a first
direction by etching side surfaces of the first to (n+1)-th
insulating layers; forming an electrode which extends in the first
direction, the electrode covering side surfaces of the first to
n-th charge storage layers which are exposed in the third direction
and side surfaces of the first to n-th charge storage layers which
are exposed in the first direction; exposing the n-th semiconductor
layer and the n-th charge storage layer in the first direction by
etching the (n+1)-th insulating layer using the electrode as a
mask; and separating the first to n-th charge storage layers in the
second direction by etching the n-th charge storage layer, the n-th
insulating layer, . . . the first charge storage layer using the
electrode and the n-th semiconductor layer as masks.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Continuation Application of PCT
Application No. PCT/JP2010/054771, filed Mar. 19, 2010, the entire
contents of which are incorporated herein by reference.
FIELD
[0002] Embodiments described herein relate generally to a
nonvolatile semiconductor memory device and a method of
manufacturing the same.
BACKGROUND
[0003] A NAND-type flash memory is widespread as a storage device
for a large volume of data. At present, memory cells are
miniaturized for cost reduction and capacity increase per bit.
Further miniaturization in the future is demanded. However, further
miniaturization of the flash memory involves many problems to be
solved, such as the development of lithography technology, a short
channel effect, inter-element interference, and the inhibition of
inter-element variations. Therefore, there is a strong possibility
that future continuous improvement of storage density only by the
development of simple in-plane miniaturization technology is
difficult.
[0004] Accordingly, there has been suggested a three-dimensional
stacked layer type semiconductor memory as a new technique for
increasing capacity that does not rely on the miniaturization of
the lithography technology. The advantage of this three-dimensional
stacked layer type semiconductor memory is that memory cells can be
formed into a three-dimensional configuration without a substantial
increase of processes and that a high memory capacity can be
obtained at low cost.
[0005] A memory cell of the three-dimensional stacked layer type
semiconductor memory that is generally used is a
silicon/oxide/nitride/oxide/silicon (SONOS) type. The problems in
putting the SONOS type memory cell into practical use include the
improvement of writing/erasing characteristics and cycling
resistance. That is, improving the writing/erasing characteristics
and the cycling resistance is important in putting the
three-dimensional stacked layer type semiconductor memory that uses
the SONOS type memory cell into practical use.
[0006] Our intensive studies on this point have proved that in
order to improve the above-mentioned characteristics, the
composition of silicon nitride, when used as a charge storage
layer, is preferably closer to the excess of silicon (silicon-rich
SiN) than a stoichiometric composition.
[0007] However, silicon-rich SiN is said to have a relatively
shallow in-film trap level, and it is known that trapped electrons
are apt to diffuse because of, for example, hopping conduction
between trap levels. In the meantime, charge storage layers of
memory cells are physically combined in the three-dimensional
stacked layer type semiconductor memory.
[0008] Therefore, the problem caused when the three-dimensional
stacked layer type semiconductor memory is formed by the SONOS type
memory cells that use silicon-rich SiN for the charge storage
layers is the loss of data because of the diffusion of electrons
injected into the charge storage layer of a memory cell to the
charge storage layer of another adjacent memory cell.
[0009] This can be prevented by the charge storage layers
structured to be independent for the respective memory cells in a
memory cell array of the three-dimensional stacked layer type
semiconductor memory.
[0010] If such a new device structure and a manufacturing method to
obtain this structure are developed, the three-dimensional stacked
layer type semiconductor memory can use, as the charge storage
layer, an insulator such as silicon-rich SiN that is expected to be
improved in characteristics, and can also use, as the charge
storage layer, a conductor as an electrically floating gate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a view showing an overall structure of a first
embodiment;
[0012] FIG. 2 is a view showing the structure of the first
embodiment;
[0013] FIG. 3 is a view showing a first modification of the first
embodiment;
[0014] FIG. 4 is a view showing a second modification of the first
embodiment;
[0015] FIG. 5 is a view showing a first example of a NAND cell unit
structure;
[0016] FIG. 6 is a view taken along the line VI-VI of FIG. 5;
[0017] FIG. 7 is a view taken along the line VII-VII of FIG. 5;
[0018] FIG. 8 is a view showing a second example of a NAND cell
unit structure;
[0019] FIG. 9 is a view taken along the line IX-IX of FIG. 8;
[0020] FIG. 10 is a view taken along the line X-X of FIG. 8;
[0021] FIG. 11 is a view showing a third example of a NAND cell
unit structure;
[0022] FIG. 12 is a view taken along the line XII-XII of FIG.
11;
[0023] FIG. 13 is a view taken along the line XIII-XIII of FIG.
11;
[0024] FIGS. 14A to 14L are diagrams, each showing a first example
of a manufacturing method of the first embodiment;
[0025] FIGS. 15A to 15N are diagrams, each showing a second example
of a manufacturing method of the first embodiment;
[0026] FIG. 16 is a view showing an overall structure of a second
embodiment;
[0027] FIG. 17 is a view showing the structure of the second
embodiment;
[0028] FIG. 18 is a view showing a modification of the second
embodiment;
[0029] FIGS. 19A to 19E are diagrams, each showing a manufacturing
method of the second embodiment;
[0030] FIG. 20 is a view showing an overall structure of a third
embodiment;
[0031] FIG. 21 is a view showing the structure of the third
embodiment;
[0032] FIG. 22 is a view showing a first modification of the third
embodiment;
[0033] FIG. 23 is a view showing a second modification of the third
embodiment;
[0034] FIGS. 24A to 24M are diagrams, each showing a manufacturing
method of the third embodiment; and
[0035] FIG. 25 is a view showing an overall structure of a fourth
embodiment.
DETAILED DESCRIPTION
[0036] In general, according to one embodiment, a nonvolatile
semiconductor memory device comprises: a semiconductor substrate;
first to n-th semiconductor layers (n is a natural number equal to
or more than 2) which are stacked in a first direction
perpendicular to a surface of the semiconductor substrate and which
extend in a second direction parallel to the surface of the
semiconductor substrate; an electrode which extends in the first
direction along side surfaces of the first to n-th semiconductor
layers, the side surfaces of the first to n-th semiconductor layers
exposing in a third direction perpendicular to the first and second
directions; and first to n-th charge storage layers located between
the first to n-th semiconductor layers and the electrode
respectively, wherein the first to n-th charge storage layers are
separated from each other in areas between the first to n-th
semiconductor layers.
[0037] Hereinafter, embodiments will be described in detail with
reference to the drawings.
1. Basic Concept
[0038] According to the basic concept of the embodiment, a
three-dimensional stacked layer type semiconductor memory comprises
first to n-th semiconductor layers (n is a natural number equal to
or more than 2) which are stacked to be isolated from one another
in a first direction perpendicular to the surface of a
semiconductor substrate and which extend in a second direction
parallel to the surface of the semiconductor substrate, an
electrode which extends in the first direction along the side
surfaces of the first to n-th semiconductor layers in a third
direction intersecting at right angles with the first and second
directions, and first to n-th charge storage layers located between
the first to n-th semiconductor layers and the electrode, wherein
the first to n-th charge storage layers are independent of one
another for the improvement of writing/erasing characteristics and
cycling resistance.
[0039] Here, that the first to n-th charge storage layers are
independent means that the first to n-th charge storage layers are
physically separated, more specifically, that elements different
from the elements comprising the first to n-th charge storage
layers are present between the charge storage layers.
[0040] In general, the first to n-th charge storage layers are
physically combined in a conventional three-dimensional stacked
layer type semiconductor memory. However, this causes a problem of
the loss of data because of the diffusion of electrons injected
into the charge storage layer of a memory cell to the charge
storage layer of another adjacent memory cell.
[0041] Thus, according to the embodiment, in the three-dimensional
stacked layer type semiconductor memory, the first to n-th charge
storage layers are independent of one another for the improvement
of writing/erasing characteristics and cycling resistance.
[0042] In the meantime, the independence of the charge storage
layers according to the embodiment cannot be accomplished simply by
converting the independence of the charge storage layers used in a
conventional two-dimensional NAND flash memory. This is because a
two-dimensionally structured memory cell cannot be directly used as
a three-dimensionally structured memory cell.
[0043] Therefore, from the viewpoint of the memory cell
characteristics and the prevention of the increased complexity of
the number of manufacturing processes, the independence of the
charge storage layers according to the embodiment is accomplished
by using one of elements between the first to n-th semiconductor
layers and the oxide of a material comprising the first to n-th
charge storage layers to physically separate the first to n-th
charge storage layers.
[0044] A specific manufacturing method to obtain the
three-dimensional stacked layer type semiconductor memory according
to the embodiment is described in detail in the following
embodiments.
[0045] The embodiment suggests a structure in which charge storage
layers are independent for the respective memory cells, and is
therefore applicable not only to a SONOS type memory cell that uses
silicon-rich SiN as a charge storage layer but also to a floating
gate type memory cell that uses, as a charge storage layer, a
conductor serving as an electrically floating gate.
2. Embodiments
(1) First Embodiment
A. Structure
[0046] FIG. 1 shows a nonvolatile semiconductor memory device as
the first embodiment. FIG. 2 shows a structure in which second gate
insulating layer 6(1)c and control gate electrode 6(1)d are
eliminated from the structure shown in FIG. 1.
[0047] Semiconductor substrate 1 is, for example, a silicon
substrate. A fin-type stacked layer structure extending in a
y-direction parallel to the surface of semiconductor substrate 1 is
disposed on semiconductor substrate 1.
[0048] This fin-type stacked layer structure comprises first
insulating layer 2, first semiconductor layer 3a, second insulating
layer 4a, second semiconductor layer 3b, third insulating layer 4b,
third semiconductor layer 3c, fourth insulating layer 4c, fourth
semiconductor layer 3d, and fifth insulating layer 5 that are
stacked in a z-direction perpendicular to the surface of
semiconductor substrate 1.
[0049] First to fifth insulating layers 2, 4a to 4c, and 5 may be
made of any insulator, and silicon oxide, for example, can be used.
First to fourth semiconductor layers 3a to 3d are made of, for
example, silicon.
[0050] On the x-direction side of first to fourth semiconductor
layers 3 (3a, 3b, 3c, and 3d), stacked layer structure 6(1) in
which first gate insulating layer 6(1)a, charge storage layer
6(1)b, second gate insulating layer 6(1)c, and control gate
electrode 6(1)d are stacked in order in the x-direction is
disposed.
[0051] First gate insulating layer 6(1)a is a tunnel insulating
layer through which a tunnel current runs, and is made of, for
example, silicon oxide. Charge storage layer 6(1)b is a layer for
storing a charge, and its charge amount is controlled by the tunnel
current.
[0052] Charge storage layer 6(1)b is made of an insulator or a
conductor. When charge storage layer 6(1)b is an insulator (e.g.,
silicon nitride), a memory cell is a SONOS type. When charge
storage layer 6(1)b is a conductor (e.g., conductive polysilicon),
a memory cell is a floating gate type.
[0053] Charge storage layers 6(1)b are independent for the
respective memory cells. In particular, four charge storage layers
6(1)b, . . . arranged in the z-direction are physically separated
from one another by elements between first to fourth semiconductor
layers 3 (3a, 3b, 3c, and 3d), in the present embodiment, by second
to fourth insulating layers 4 (4a, 4b, and 4c).
[0054] Second gate insulating layer 6(1)c prevents a leakage
current between charge storage layer 6(1)b and control gate
electrode 6(1)d. Second gate insulating layer 6(1)c comprises, for
example, a stacked layer structure or a material having a high
dielectric constant to increase the coupling ratio of the memory
cells and improve writing/erasing characteristics.
[0055] When the memory cell is the SONOS type, second gate
insulating layer 6(1)c is generally called a block insulating
layer. When the memory cell is the floating gate type, second gate
insulating layer 6(1)c is generally called an inter-electrode
insulating layer.
[0056] Control gate electrode 6(1)d functions as a word line, and
extends in the x-direction on the z-direction side of fifth
insulating layer 5 and extends in the z-direction on the
x-direction side of first to fourth semiconductor layers 3 (3a, 3b,
3c, and 3d).
[0057] That is, control gate electrode 6(1)d covers four charge
storage layers 6(1)b, . . . , and extends across the fin-type
stacked layer structure in the x-direction.
[0058] Stacked layer structures 6(2) and 6(3) have the same
structure as stacked layer structure 6(1).
[0059] By the device structure described above, a string of memory
cells connected in series in the y-direction, that is, a NAND
string is formed in each of first to fourth semiconductor layers 3
(3a, 3b, 3c, and 3d). Here, the NAND string formed in first
semiconductor layer 3a is NAND1, the NAND string formed in second
semiconductor layer 3b is NAND2, the NAND string formed in third
semiconductor layer 3c is NAND3, and the NAND string formed in
fourth semiconductor layer 3d is NAND4.
[0060] Charge storage layers 6(1)b of the memory cells that
constitute these NAND strings are independent for the respective
memory cells. That is, charge storage layers 6(1)b, . . . are
physically separated from one another by second to fourth
insulating layers 4 (4a, 4b, and 4c). Therefore, the reliability of
the three-dimensional stacked layer type semiconductor memory can
be improved.
B. Material Examples
[0061] Materials best suited to the generations of the
semiconductor memories can be properly selected as the materials
that constitute the elements of the device structure shown in FIG.
1 and FIG. 2.
[0062] For example, first gate insulating layer 6(1)a can be
SiO.sub.2, charge storage layer 6(1)b can be Si.sub.3N.sub.4,
second gate insulating layer 6(1)c can be Al.sub.2O.sub.3, and
control gate electrode 6(1)d can be NiSi.
[0063] First gate insulating layer 6(1)a may be silicon oxynitride,
or a stacked layer structure of silicon oxide and silicon nitride.
First gate insulating layer 6(1)a may include silicon
nanoparticles, metal ions, or the like.
[0064] Charge storage layer 6(1)b may be made of at least one of
the materials selected from the group consisting of Si.sub.xN.sub.y
having any composition ratio x, y of silicon and nitrogen, silicon
oxynitride (SiON), aluminum oxide (Al.sub.2O.sub.3), aluminum
oxynitride (AlON), hafnia (HfO.sub.2), hafnium aluminate
(HfAlO.sub.3), hafnia nitride (HfON), hafnium nitride-aluminate
(HfAlON), hafnium silicate (HfSiO), hafnium nitride-silicate
(HfSiON), lanthanum oxide (La.sub.2O.sub.3), and lanthanum
aluminate (LaAlO.sub.3).
[0065] Charge storage layer 6(1)b may otherwise be made of
impurity-added polysilicon or a conductor such as a metal.
[0066] Second gate insulating layer 6(1)c may be made of at least
one of the materials selected from the group consisting of silicon
oxide (SiO.sub.2), silicon oxynitride (SiON), aluminum oxide
(Al.sub.2O.sub.3), aluminum oxynitride (AlON), hafnia (HfO.sub.2),
hafnium aluminate. (HfAlO.sub.3), hafnia nitride (HfON), hafnium
nitride-aluminate (HfAlON), hafnium silicate (HfSiO), hafnium
nitride-silicate (HfSiON), lanthanum oxide (La.sub.2O.sub.3),
lanthanum aluminate (LaAlO.sub.3), and lanthanum aluminum silicate
(LaAlSiO).
[0067] Control gate electrode 6(1)d can be made of a metal compound
such as tantalum nitride (TaN), tantalum carbide (TaC), or titanium
nitride (TiN), or an electrically conductive metallic material such
as V, Cr, Mn, Y, Mo, Ru, Rh, Hf, Ta, W, Ir, Co, Ti, Er, Pt, Pd, Zr,
Gd, Dy, and Ho, and silicides of these substances.
C. First Modification
[0068] FIG. 3 shows a first modification of the first
embodiment.
[0069] The first modification is characterized in that the
uppermost layer among first to fourth semiconductor layers 3 (3a,
3b, 3c, and 3d), that is, fourth semiconductor layer 3d is dummy
layer DUMMY in which dummy cells as non-memory cells are
formed.
[0070] Fourth semiconductor layer 3d as the uppermost layer is used
as an etching mask in one step of first and second manufacturing
methods described later, and therefore tends to be damaged. Thus,
the NAND string formed in fourth semiconductor layer 3d is not used
as a memory cell, and is a dummy cell as a non-memory cell.
[0071] In this case, in order to improve the function of fourth
semiconductor layer 3d as a mask, the width of fourth semiconductor
layer 3d in the z-direction is preferably greater than the width of
first to third semiconductor layers 3a, 3b, and 3c in the
z-direction.
D. Second Modification
[0072] FIG. 4 shows a second modification of the first
embodiment.
[0073] The second modification is characterized in that four charge
storage layers 6(1)b, . . . arranged in the z-direction are
physically separated from one another by cavities (e.g., air gaps).
That is, in the second modification, the elements between first to
fourth semiconductor layers 3 (3a, 3b, 3c, and 3d) are
cavities.
[0074] When the memory cell is miniaturized, a parasitic
capacitance generated between charge storage layers 6(1)b is
increased, and wrong operation is caused by mutual interference. To
prevent this, the space between charge storage layers 6(1)b is
preferably a cavity having a low dielectric constant.
[0075] Although all of first to fifth insulating layers 2, 4a to
4c, and 5 in the first embodiment (FIG. 1 and FIG. 2) are changed
to cavities in this modification, some of the insulating layers may
be only changed to cavities. The cavity is preferably a complete
cavity, but the insulator may partly remain in the cavity.
[0076] The cavity can be changed to a porous insulator.
G. First Example of NAND Cell Unit
[0077] FIG. 5 shows a first example of a NAND cell unit structure.
FIG. 6 is a sectional view taken along the line VI-VI of FIG. 5.
FIG. 7 is a sectional view taken along the line VII-VII of FIG.
5.
[0078] This example shows the NAND cell unit structure as an
application of the first embodiment (FIG. 1 and FIG. 2). Therefore,
the same elements as those in the first embodiment are provided
with the same reference marks. This example is different from the
first embodiment in that the number of NAND strings NAND1, NAND2,
and NAND3 is three.
[0079] Fin-type stacked layer structure 9 comprises first
insulating layer 2, first semiconductor layer 3a, second insulating
layer 4a, second semiconductor layer 3b, third insulating layer 4b,
third semiconductor layer 3c, and fifth insulating layer 5 that are
stacked on semiconductor substrate 1 in the z-direction.
[0080] One end of fin-type stacked layer structure 9 in the
y-direction has a stepped structure. At one end of fin-type stacked
layer structure 9 in the y-direction, the side surfaces of first to
third semiconductor layers 3 (3a, 3b, and 3c) in the z-direction
are exposed. Contact plugs 7a, 7b, and 7c contact the side surfaces
of first to third semiconductor layers 3 (3a, 3b, and 3c) in the
z-direction, respectively.
[0081] Contact plugs 7a, 7b, and 7c connect bit lines BLa, BLb, and
BLc and NAND strings NAND1, NAND2, and NAND3, respectively.
[0082] At the other end of fin-type stacked layer structure 9 in
the y-direction, contact plug 8 passes through and contacts first
to third semiconductor layers 3 (3a, 3b, and 3c). Contact plug 8
connects source line SL and NAND strings NAND1, NAND2, and
NAND3.
[0083] Each of stacked layer structures 6(1), . . . 6(n-1), and
6(n) constitutes a memory cell.
[0084] Stacked layer structure 6(1) comprises first gate insulating
layer 6(1)a, charge storage layer 6(1)b, second gate insulating
layer 6(1)c, and control gate electrode 6(1)d. Other stacked layer
structures 6(2), . . . 6(n-1), and 6(n) have the same structure as
stacked layer structure 6(1).
[0085] Stacked layer structures 10 and 11 also have the same
structure as stacked layer structure 6(1).
[0086] Each of stacked layer structures 10 and 11 constitutes a
select transistor. Stacked layer structure 10 constitutes a
drain-side select transistor, and stacked layer structure 11
constitutes a source-side select transistor.
[0087] As described above, the NAND strings according to the first
embodiment can be used to constitute a NAND cell unit, so that a
highly reliable three-dimensional NAND flash memory can be
obtained.
F. Second Example of NAND Cell Unit
[0088] FIG. 8 shows a second example of a NAND cell unit structure.
FIG. 9 is a sectional view taken along the line IX-IX of FIG. 8.
FIG. 10 is a sectional view taken along the line X-X of FIG. 8.
[0089] This example shows the NAND cell unit structure as an
application of the first modification (FIG. 3). Therefore, the same
elements as those in the first embodiment are provided with the
same reference marks. This example is different from the first
modification in that the number of NAND strings NAND1, NAND2, and
NAND3 is three.
[0090] Fin-type stacked layer structure 9 comprises first
insulating layer 2, first semiconductor layer 3a, second insulating
layer 4a, second semiconductor layer 3b, third insulating layer 4b,
third semiconductor layer 3c, and fifth insulating layer 5 that are
stacked on semiconductor substrate 1 in the z-direction.
[0091] One end of fin-type stacked layer structure 9 in the
y-direction has a stepped structure. At one end of fin-type stacked
layer structure 9 in the y-direction, the side surfaces of first to
third semiconductor layers 3 (3a, 3b, and 3c) in the z-direction
are exposed. Contact plugs 7a and 7b contact the side surfaces of
first and second semiconductor layers 3a and 3b in the z-direction,
respectively.
[0092] Contact plugs 7a and 7b connect bit lines BLa and BLb and
NAND strings NAND1 and NAND2, respectively.
[0093] As third semiconductor layer 3c is dummy layer DUMMY, no
contact plug is connected to third semiconductor layer 3c.
[0094] At the other end of fin-type stacked layer structure 9 in
the y-direction, contact plug 8 passes through and contacts first
to third semiconductor layers 3 (3a, 3b, and 3c). Contact plug 8
connects source line SL and NAND strings NAND1, NAND2, and
NAND3.
[0095] Each of stacked layer structures 6(1), . . . 6(n-1), and
6(n) constitutes a memory cell. However, the dummy cell formed in
third semiconductor layer 3c as dummy layer DUMMY is an
exception.
[0096] Stacked layer structure 6(1) comprises first gate insulating
layer 6(1)a, charge storage layer 6(1)b, second gate insulating
layer 6(1)c, and control gate electrode 6(1)d. Other stacked layer
structures 6(2), . . . 6(n-1), and 6(n) have the same structure as
stacked layer structure 6(1).
[0097] Stacked layer structures 10 and 11 also have the same
structure as stacked layer structure 6(1).
[0098] Each of stacked layer structures 10 and 11 constitutes a
select transistor. However, a dummy transistor formed in third
semiconductor layer 3c as dummy layer DUMMY is an exception.
Stacked layer structure 10 constitutes a drain-side select
transistor, and stacked layer structure 11 constitutes a
source-side select transistor.
[0099] As described above, the NAND strings according to the first
modification can be used to constitute a NAND cell unit, so that a
highly reliable three-dimensional NAND flash memory can be
obtained.
G. Third Example of NAND Cell Unit
[0100] FIG. 11 shows a third example of a NAND cell unit structure.
FIG. 12 is a sectional view taken along the line XII-XII of FIG.
11. FIG. 13 is a sectional view taken along the line XIII-XIII of
FIG. 11.
[0101] This example is a modification of the first example of the
NAND cell unit structure. Therefore, the same elements as those in
FIG. 5 to FIG. 7 are provided with the same reference marks.
[0102] This example is different from the first example of the NAND
cell unit structure in that a drain-side select transistor
comprises three transistors connected in series. More specifically,
stacked layer structure 10 comprises three stacked layer structures
10a, 10b, and 10c. Stacked layer structures 10a, 10b, and 10c have
the same structure as stacked layer structure 10 in FIG. 5 to FIG.
7.
[0103] Impurity region 13a is provided in a part of first
semiconductor layer 3a covered with stacked layer structures 10a so
that the drain-side select transistor is always on (normally
on).
[0104] Similarly, impurity region 13b is provided in a part of
second semiconductor layer 3b covered with stacked layer structures
10b so that the drain-side select transistor is normally on.
Impurity region 13c is provided in a part of second semiconductor
layer 3c covered with stacked layer structures 10c so that the
drain-side select transistor is normally on.
[0105] Such a structure allows contact plug 7 to be also shared at
one end of fin-type stacked layer structure 9 in the y-direction.
That is, contact plug 7 passes through and contacts first to third
semiconductor layers 3 (3a, 3b, and 3c).
[0106] Contact plug 7 connects bit line BL and NAND strings NAND1,
NAND2, and NAND3.
[0107] Details of the third example of the NAND cell unit structure
are described, for example, in International Patent Application
(PCT/JP2009/060803).
H. Other Examples of NAND Cell Unit
[0108] Stacked layer structures 10a, 10b, and 10c shown in FIG. 11
to FIG. 13 can be used in the first embodiment (FIG. 1 and FIG.
2).
[0109] Stacked layer structures 10a, 10b, and 10c shown in FIG. 11
to FIG. 13 can be used in the first modification (FIG. 3).
[0110] The cell unit structure shown in FIG. 5 to FIG. 7, the cell
unit structure shown in FIG. 8 to FIG. 10, and stacked layer
structures 10a, 10b, and 10c shown in FIG. 11 to FIG. 13 can be
used in the second modification (FIG. 4).
[0111] It is also possible to use a combination of these
structures.
I. First Manufacturing Method
[0112] A method of manufacturing the structures according to the
first embodiment (FIG. 1 and FIG. 2) and the first modification
(FIG. 3) is described below with reference to FIG. 14A to FIG. 14L.
In each of these drawings, (a) is a plan view, (b) is a side view
from the x-direction, and (c) is a side view from the
y-direction.
[0113] First, as shown in FIG. 14A, first insulating layer 2, first
semiconductor layer 3a, second insulating layer 4a, second
semiconductor layer 3b, third insulating layer 4b, third
semiconductor layer 3c, fourth insulating layer 4c, fourth
semiconductor layer 3d, and fifth insulating layer 5 are
sequentially formed in the z-direction perpendicular to the surface
of semiconductor substrate 1.
[0114] Here, semiconductor substrate 1 is, for example, a p-type
silicon substrate having a plane direction (100) and a specific
resistance of 10 to 20 .OMEGA.cm. First to fifth insulating layers
2, 4a to 4c, and 5 are made of silicon oxide. First to fourth
semiconductor layers 3a to 3d are made of silicon.
[0115] First to fifth insulating layers 2, 4a to 4c, and 5 and
first to fourth semiconductor layers 3a to 3d are then fabricated
by a photo engraving process (PEP) and anisotropic dry etching, and
a fin-type stacked layer structure extending in the y-direction
parallel to the surface of semiconductor substrate 1 is formed.
[0116] As shown in FIG. 14B, the side surfaces of first to fourth
semiconductor layers 3a to 3d in the x-direction are then
selectively etched in the x-direction by isotropic dry etching. As
a result, the side surfaces of first to fourth semiconductor layers
3a to 3d in the x-direction are set back, and first to fourth
recesses 21a to 21d extending in the y-direction are formed.
[0117] As shown in FIG. 14C, the side surfaces of first to fourth
semiconductor layers 3a to 3d in the x-direction are then thermally
oxidized, and first gate insulating layers (e.g., silicon oxide) 6a
are formed on the side surfaces of first to fourth semiconductor
layers 3a to 3d in the x-direction.
[0118] As shown in FIG. 14D, charge storage layer 6b covering the
fin-type stacked layer structure is then formed. A material such as
silicon nitride or conductive polysilicon can be used as charge
storage layer 6b.
[0119] As shown in FIG. 14E, charge storage layer 6b is then
selectively etched by anisotropic dry etching. As a result, charge
storage layer 6b only remains in first to fourth recesses 21a to
21d on the side surfaces of first to fourth semiconductor layers 3a
to 3d in the x-direction.
[0120] That is, fifth insulating layer 5 is exposed when uppermost
charge storage layer 6b is removed. Therefore, fifth insulating
layer 5 is used as a mask to further etch charge storage layer 6b,
and first to fourth charge storage layers 6b are then formed in
first to fourth recesses 21a to 21d, respectively.
[0121] Here, as fifth insulating layer 5 functions as a mask for
etching charge storage layer 6b, the width of fifth insulating
layer 5 in the z-direction may be greater than the width of each of
first to fourth insulating layers 2, 4a to 4c in the
z-direction.
[0122] If the function of fifth insulating layer 5 as the mask is
regarded as important, fifth insulating layer 5 may be formed by a
method and a material different from first to fourth insulating
layers 2, 4a to 4c (e.g., a stacked layer structure of different
insulating layers).
[0123] At this point, first to fourth charge storage layers 6b are
separated in the z-direction.
[0124] As shown in FIG. 14F, second gate insulating layer 6c and
control gate electrode 6d that cover the fin-type stacked layer
structure (including first to fourth charge storage layers 6b) are
then formed. A material such as aluminum oxide can be used as
second gate insulating layer 6c, and a material such as nickel
silicide can be used as control gate electrode 6d.
[0125] As shown in FIG. 14G, second gate insulating layer 6c and
control gate electrode 6d are fabricated by the PEP and anisotropic
dry etching, and control gate electrodes (word lines) 6d, . . . are
formed. Control gate electrodes (word lines) 6d, . . . extend in
the x-direction on the z-direction side of fifth insulating layer
5, and extend in the z-direction on the x-direction side of first
to fourth charge storage layers 6b.
[0126] As shown in FIG. 14H, fifth insulating layer 5 is then
selectively etched by anisotropic dry etching. At the same time,
control gate electrodes 6d, . . . function as masks for the
anisotropic dry etching. Therefore, in parts that are not covered
by control gate electrodes 6d, . . . , fifth insulating layer 5 is
selectively removed, and the side surfaces of fourth semiconductor
layer 3d and fourth charge storage layer 6b in the z-direction are
exposed.
[0127] As shown in FIG. 14I, fourth charge storage layer 6b is then
selectively etched by anisotropic dry etching. At the same time,
control gate electrodes 6d, . . . and fourth semiconductor layer 3d
function as masks for the anisotropic dry etching.
[0128] Therefore, as the part of fourth charge storage layer 6b
that is not covered by control gate electrodes 6d, . . . is
selectively removed, fourth charge storage layers 6b, . . .
separated in the y-direction are formed on the x-direction side of
fourth semiconductor layer 3d.
[0129] As shown in FIG. 14J, fourth insulating layer 4c is then
selectively etched by anisotropic dry etching. At the same time,
control gate electrodes 6d, . . . and fourth semiconductor layer 3d
function as masks for the anisotropic dry etching.
[0130] Therefore, in parts that are not covered by control gate
electrodes 6d, . . . and fourth semiconductor layer 3d, fourth
insulating layer 4c is selectively removed, and the side surface of
third charge storage layer 6b in the z-direction is exposed.
[0131] As shown in FIG. 14K, third charge storage layer 6b is then
selectively etched by anisotropic dry etching. At the same time,
control gate electrodes 6d, . . . and fourth semiconductor layer 3d
function as masks for the anisotropic dry etching.
[0132] Therefore, as the part of third charge storage layer 6b that
is not covered by control gate electrodes 6d, . . . is selectively
removed, third charge storage layers 6b, . . . separated in the
y-direction are formed on the x-direction side of third
semiconductor layer 3c.
[0133] Similarly, second charge storage layers 6b, . . . separated
in the y-direction are formed on the x-direction side of second
semiconductor layer 3b, and first charge storage layers 6b, . . .
separated in the y-direction are formed on the x-direction side of
first semiconductor layer 3a.
[0134] As shown in FIG. 14L, charge storage layers 6b, . . .
physically separated for the respective memory cells are formed by
the process described above. This prevents a situation where a
charge in a charge storage layer moves to another charge storage
layer in first to fourth charge storage layers 6b, . . . , so that
satisfactory data retention characteristics can be obtained.
[0135] In the manufacturing method according to the present
embodiment, as apparent from FIG. 14I to FIG. 14K, uppermost fourth
semiconductor layer 3d functions as the etching mask during the
etching to accomplish the independence of the charge storage
layers.
[0136] Therefore, it is preferable that fourth semiconductor layer
3d is a dummy layer and that the width of fourth semiconductor
layer 3d in the z-direction is greater than the width of each of
first to third semiconductor layers 3a to 3c in the
z-direction.
J. Second Manufacturing Method
[0137] A method of manufacturing the structure according to the
second modification (FIG. 4) is described below with reference to
FIG. 15A to FIG. 15N. In each of these drawings, (a) is a plan
view, (b) is a side view from the x-direction, and (c) is a side
view from the y-direction.
[0138] First, as shown in FIG. 15A, first temporary layer 12a,
first semiconductor layer 3a, second temporary layer 12b, second
semiconductor layer 3b, third temporary layer 12c, third
semiconductor layer 3c, fourth temporary layer 12d, fourth
semiconductor layer 3d, and fifth temporary layer 12e are
sequentially formed in the z-direction perpendicular to the surface
of semiconductor substrate 1.
[0139] Here, semiconductor substrate 1 is, for example, a p-type
silicon substrate having a plane direction (100) and a specific
resistance of 10 to 20 .OMEGA.cm. First to fifth temporary layers
12a to 12e are made of silicon germanium. First to fourth
semiconductor layers 3a to 3d are made of silicon.
[0140] In the case of a stacked layer structure of silicon and
silicon germanium, these materials are alternately stacked by
epitaxial growth, and monocrystalline silicon can be obtained.
Thus, characteristic variations among first to fourth semiconductor
layers (silicon channels) 3a to 3d are reduced, and the channel
mobility of the silicon channels can be improved.
[0141] First to fifth temporary layers 12a to 12e and first to
fourth semiconductor layers 3a to 3d are then fabricated by the PEP
and anisotropic dry etching, and a fin-type stacked layer structure
extending in the y-direction parallel to the surface of
semiconductor substrate 1 is formed.
[0142] As shown in FIG. 15B, the side surfaces of first to fourth
semiconductor layers 3a to 3d in the x-direction are then
selectively etched by the isotropic dry etching. As a result, the
side surfaces of first to fourth semiconductor layers 3a to 3d in
the x-direction are set back, and first to fourth recesses 21a to
21d extending in the y-direction are formed.
[0143] As shown in FIG. 15C, the side surfaces of first to fourth
semiconductor layers 3a to 3d in the x-direction are then thermally
oxidized, and first gate insulating layers (e.g., silicon oxide) 6a
are formed on the side surfaces of first to fourth semiconductor
layers 3a to 3d in the x-direction.
[0144] As shown in FIG. 15D, charge storage layer 6b covering the
fin-type stacked layer structure is then formed. A material such as
silicon nitride or conductive polysilicon can be used as charge
storage layer 6b.
[0145] As shown in FIG. 15E, charge storage layer 6b is then
selectively etched by anisotropic dry etching. As a result, charge
storage layer 6b only remains in first to fourth recesses 21a to
21d on the side surfaces of first to fourth semiconductor layers 3a
to 3d in the x-direction.
[0146] That is, fifth temporary layer 12e is exposed when uppermost
charge storage layer 6b is removed. Therefore, fifth temporary
layer 12e is used as a mask to further etch charge storage layer
6b, and first to fourth charge storage layers 6b are then formed in
first to fourth recesses 21a to 21d, respectively.
[0147] Here, as fifth temporary layer 12e functions as a mask for
etching charge storage layer 6b, the width of fifth temporary layer
12e in the z-direction may be greater than the width of each of
first to fourth temporary layers 12a to 12d in the z-direction.
[0148] If the function of fifth temporary layer 12e as the mask is
regarded as important, fifth temporary layer 12e may be formed by a
method and a material different from first to fourth temporary
layers 12a to 12d.
[0149] At this point, first to fourth charge storage layers 6b are
separated in the z-direction.
[0150] As shown in FIG. 15F, second gate insulating layer 6c and
control gate electrode 6d that cover the fin-type stacked layer
structure (including first to fourth charge storage layers 6b) are
then formed. A material such as aluminum oxide can be used as
second gate insulating layer 6c, and a material such as nickel
silicide can be used as control gate electrode 6d.
[0151] As shown in FIG. 15G, second gate insulating layer 6c and
control gate electrode 6d are fabricated by the PEP and anisotropic
dry etching, and control gate electrodes (word lines) 6d, . . . are
formed. Control gate electrodes (word lines) 6d, . . . extend in
the x-direction on the z-direction side of fifth temporary layer
12e, and extend in the z-direction on the x-direction side of first
to fourth charge storage layers 6b.
[0152] As shown in FIG. 15H, fifth temporary layer 12e is then
selectively etched by anisotropic dry etching. At the same time,
control gate electrodes 6d, . . . function as masks for the
anisotropic dry etching. Therefore, in parts that are not covered
by control gate electrodes 6d, . . . , fifth temporary layer 12e is
selectively removed, and the side surfaces of fourth semiconductor
layer 3d and fourth charge storage layer 6b in the z-direction are
exposed.
[0153] As shown in FIG. 15I, fourth charge storage layer 6b is then
selectively etched by anisotropic dry etching. At the same time,
control gate electrodes 6d, . . . and fourth semiconductor layer 3d
function as masks for the anisotropic dry etching.
[0154] Therefore, as the part of fourth charge storage layer 6b
that is not covered by control gate electrodes 6d, . . . is
selectively removed, fourth charge storage layers 6b, . . .
separated in the y-direction are formed on the x-direction side of
fourth semiconductor layer 3d.
[0155] As shown in FIG. 15J, fourth temporary layer 12d is then
selectively etched by anisotropic dry etching. At the same time,
control gate electrodes 6d, . . . and fourth semiconductor layer 3d
function as masks for the anisotropic dry etching.
[0156] Therefore, in parts that are not covered by control gate
electrodes 6d, . . . and fourth semiconductor layer 3d, fourth
temporary layer 12d is selectively removed, and the side surface of
third charge storage layer 6b in the z-direction is exposed.
[0157] As shown in FIG. 15K, third charge storage layer 6b is then
selectively etched by anisotropic dry etching. At the same time,
control gate electrodes 6d, . . . and fourth semiconductor layer 3d
function as masks for the anisotropic dry etching.
[0158] Therefore, as the part of third charge storage layer 6b that
is not covered by control gate electrodes 6d, . . . is selectively
removed, third charge storage layers 6b, . . . separated in the
y-direction are formed on the x-direction side of second
semiconductor layer 3b.
[0159] Similarly, second charge storage layers 6b, . . . separated
in the y-direction are formed on the x-direction side of second
semiconductor layer 3b, and first charge storage layers 6b, . . .
separated in the y-direction are formed on the x-direction side of
first semiconductor layer 3a.
[0160] As shown in FIG. 15L, charge storage layers 6b, . . .
physically separated for the respective memory cells are formed by
the process described above. This prevents a situation where a
charge in a charge storage layer moves to another charge storage
layer in first to fourth charge storage layers 6b, . . . , so that
satisfactory data retention characteristics can be obtained.
[0161] As shown in FIG. 15M, first to fifth temporary layers 12a to
12e are then selectively removed by isotropic dry etching, and
cavities 22, . . . are formed on upper and lower sides (z-direction
sides) of first to fourth semiconductor layers 3a to 3d.
[0162] In FIG. 15L, first to fifth temporary layers 12a to 12e can
be easily removed by isotropic dry etching because the space
between control gate electrodes 6d, . . . and the space between
first to fourth semiconductor layers 3a to 3d (first to fourth
charge storage layers 6b, . . . ) are exposed.
[0163] Although cavities 22, . . . may be as they are, cavities 22,
. . . may be filled with insulating layers (e.g., silicon oxide) 13
as shown in FIG. 15N. In this case, insulating layers 13 may be
porous insulating layers.
[0164] In the manufacturing method according to the present
embodiment as well, as apparent from FIG. 15I to FIG. 15K,
uppermost fourth semiconductor layer 3d functions as the etching
mask during the etching to accomplish the independence of the
charge storage layers.
[0165] Therefore, it is preferable that fourth semiconductor layer
3d is a dummy layer and that the width of fourth semiconductor
layer 3d in the z-direction is greater than the width of each of
first to third semiconductor layers 3a to 3c in the
z-direction.
K. Summary
[0166] As described above, according to the first embodiment, a
structure in which charge storage layers are independent for the
respective memory cells is formed without a substantial increase in
the number of processes, and it is thereby possible to provide high
reliability of the three-dimensional stacked layer type
semiconductor memory.
(2) Second Embodiment
A. Structure
[0167] FIG. 16 shows a nonvolatile semiconductor memory device as
the second embodiment. FIG. 17 shows a structure in which second
gate insulating layer 6(1)c and control gate electrode 6(1)d are
eliminated from the structure shown in FIG. 16.
[0168] Semiconductor substrate 1 is, for example, a silicon
substrate. A fin-type stacked layer structure extending in a
y-direction parallel to the surface of semiconductor substrate 1 is
disposed on semiconductor substrate 1.
[0169] This fin-type stacked layer structure comprises first
insulating layer 2, first semiconductor layer 3a, second insulating
layer 4a, second semiconductor layer 3b, third insulating layer 4b,
third semiconductor layer 3c, fourth insulating layer 4c, fourth
semiconductor layer 3d, and fifth insulating layer 5 that are
stacked in a z-direction perpendicular to the surface of
semiconductor substrate 1.
[0170] First to fifth insulating layers 2, 4a to 4c, and 5 may be
made of any insulator, and silicon oxide, for example, can be used.
First to fourth semiconductor layers 3a to 3d are made of, for
example, silicon.
[0171] On the x-direction side of first to fourth semiconductor
layers 3 (3a, 3b, 3c, and 3d), stacked layer structure 6(1) in
which first gate insulating layer 6(1)a, charge storage layer
6(1)b, second gate insulating layer 6(1)c, and control gate
electrode 6(1)d are stacked in order in the x-direction is
disposed.
[0172] First gate insulating layer 6(1)a is a tunnel insulating
layer through which a tunnel current runs, and is made of, for
example, silicon oxide. Charge storage layer 6(1)b is a layer for
storing a charge, and its charge amount is controlled by the tunnel
current.
[0173] Charge storage layer 6(1)b is made of an insulator or a
conductor. When charge storage layer 6(1)a is an insulator (e.g.,
silicon nitride), a memory cell is a SONOS type. When charge
storage layer 6(1)a is a conductor (e.g., conductive polysilicon),
a memory cell is a floating gate type.
[0174] Charge storage layers 6(1)b are independent for the
respective memory cells. In particular, four charge storage layers
6(1)b, . . . arranged in the z-direction are physically separated
from one another by oxide (e.g., silicon oxynitride when charge
storage layer 6(1)b is silicon nitride) 14 of the material that
constitutes four charge storage layers 6(1)b, . . . .
[0175] Second gate insulating layer 6(1)c prevents a leakage
current between charge storage layer 6(1)b and control gate
electrode 6(1)d. Second gate insulating layer 6(1)c comprises, for
example, a stacked layer structure or a material having a high
dielectric constant to increase the coupling ratio of the memory
cells and improve writing/erasing characteristics.
[0176] When the memory cell is the SONOS type, second gate
insulating layer 6(1)c is generally called a block insulating
layer. When the memory cell is the floating gate type, second gate
insulating layer 6(1)c is generally called an inter-electrode
insulating layer.
[0177] Control gate electrode 6(1)d functions as a word line, and
extends in the x-direction on the z-direction side of fifth
insulating layer 5 and extends in the z-direction on the
x-direction side of first to fourth semiconductor layers 3 (3a, 3b,
3c, and 3d).
[0178] That is, control gate electrode 6(1)d covers four charge
storage layers 6(1)b, . . . , and extends across the fin-type
stacked layer structure in the x-direction.
[0179] Stacked layer structures 6(2) and 6(3) have the same
structure as stacked layer structure 6(1).
[0180] By the device structure described above, a string of memory
cells connected in series in the y-direction, that is, a NAND
string is formed in each of first to fourth semiconductor layers 3
(3a, 3b, 3c, and 3d). Here, the NAND string formed in first
semiconductor layer 3a is NAND1, the NAND string formed in second
semiconductor layer 3b is NAND2, the NAND string formed in third
semiconductor layer 3c is NAND3, and the NAND string formed in
fourth semiconductor layer 3d is NAND4.
[0181] Charge storage layers 6(1)b of the memory cells that
constitute these NAND strings are independent for the respective
memory cells. That is, charge storage layers 6(1)b, . . . are
physically separated from one another by oxide 14 of the material
that constitutes four charge storage layers 6(1)b, . . . .
Therefore, the reliability of the three-dimensional stacked layer
type semiconductor memory can be improved.
B. Material Examples
[0182] Materials best suited to the generations of the
semiconductor memories can be properly selected as the materials
that constitute the elements of the device structure shown in FIG.
16 and FIG. 17.
[0183] Examples of materials for first gate insulating layer 6(1)a,
charge storage layer 6(1)b, second gate insulating layer 6(1)c, and
control gate electrode 6(1)d are the same as those according to the
first embodiment and are therefore not described here.
C. Modification
[0184] FIG. 18 shows a modification of the second embodiment.
[0185] This modification is characterized in that four charge
storage layers 6 (6(1)b, . . . ) arranged in the z-direction are
physically separated from one another by cavities (e.g., air gaps).
That is, in this modification, the elements between first to fourth
semiconductor layers 3 (3a, 3b, 3c, and 3d) are cavities.
[0186] When the memory cell is miniaturized, a parasitic
capacitance generated between charge storage layers 6(1)b is
increased, and wrong operation is caused by mutual interference. To
prevent this, the space between charge storage layers 6(1)b is
preferably a cavity having a low dielectric constant.
[0187] Although all of first to fifth insulating layers 2, 4a to
4c, and 5 in the second embodiment (FIG. 16 and FIG. 17) are
changed to cavities in this modification, some of the insulating
layers may be only changed to cavities. The cavity is preferably a
complete cavity, but the insulator may partly remain in the
cavity.
[0188] The cavity can be changed to a porous insulator.
D. Example of NAND Cell Unit
[0189] A NAND cell unit structure to which the second embodiment
(FIG. 16 and FIG. 17) is applied can be the NAND cell unit
structure shown in FIG. 5 to FIG. 7 or the NAND cell unit structure
shown in FIG. 11 to FIG. 13. However, in these NAND cell unit
structures, a NAND cell unit part needs to be changed to the
structure shown in FIG. 16 and FIG. 17.
[0190] In the modification of the second embodiment (FIG. 18), the
cell unit structure shown in FIG. 5 to FIG. 7 or the cell unit
structure shown in FIG. 11 to FIG. 13 can be used. However, in
these NAND cell unit structures, a NAND cell unit part needs to be
changed to the structure shown in FIG. 18.
E. Manufacturing Method
[0191] A method of manufacturing the structures according to the
second embodiment (FIG. 16 and FIG. 17) and its modification (FIG.
18) is described below with reference to FIG. 19A to FIG. 19E. In
each of these drawings, (a) is a plan view, (b) is a side view from
the x-direction, and (c) is a side view from the y-direction.
[0192] First, as shown in FIG. 19A, first temporary layer 12a,
first semiconductor layer 3a, second temporary layer 12b, second
semiconductor layer 3b, third temporary layer 12c, third
semiconductor layer 3c, fourth temporary layer 12d, fourth
semiconductor layer 3d, and fifth temporary layer 12e are
sequentially formed in the z-direction perpendicular to the surface
of semiconductor substrate 1.
[0193] Here, semiconductor substrate 1 is, for example, a p-type
silicon substrate having a plane direction (100) and a specific
resistance of 10 to 20 .OMEGA.cm. First to fifth temporary layers
12a to 12e are made of silicon germanium. First to fourth
semiconductor layers 3a to 3d are made of silicon.
[0194] In the case of a stacked layer structure of silicon and
silicon germanium, these materials are alternately stacked by
epitaxial growth, and monocrystalline silicon can be obtained.
Thus, characteristic variations among first to fourth semiconductor
layers (silicon channels) 3a to 3d are reduced, and the channel
mobility of the silicon channels can be improved.
[0195] First to fifth temporary layers 12a to 12e and first to
fourth semiconductor layers 3a to 3d are then fabricated by the PEP
and anisotropic dry etching, and a fin-type stacked layer structure
extending in the y-direction parallel to the surface of
semiconductor substrate 1 is formed.
[0196] As shown in FIG. 19B, the side surfaces of first to fourth
semiconductor layers 3a to 3d in the x-direction, the side surfaces
of first to fourth temporary layers 12a to 12d in the x-direction,
and the side surfaces of fifth temporary layer 12e in the
x-direction and the z-direction are then thermally oxidized, and
first gate insulating layers (e.g., silicon oxide) 6a are formed on
the side surfaces of first to fourth semiconductor layers 3a to 3d
in the x-direction.
[0197] Combined charge storage layer 6b covering the fin-type
stacked layer structure (first gate insulating layers 6a), second
gate insulating layer 6c, and control gate electrode 6d are then
sequentially formed.
[0198] A material such as silicon nitride or conductive polysilicon
can be used as combined charge storage layer 6b. A material such as
aluminum oxide can be used as second gate insulating layer 6c, and
a material such as nickel silicide can be used as control gate
electrode 6d.
[0199] First gate insulating layer 6a, combined charge storage
layer 6b, second gate insulating layer 6c, and control gate
electrode 6d are fabricated by the PEP and anisotropic dry etching,
and control gate electrodes (word lines) 6d, . . . are formed.
Control gate electrodes (word lines) 6d, . . . extend in the
x-direction on the z-direction side of fifth temporary layer 12e,
and extend in the z-direction on the x-direction side of first to
fourth charge storage layers 6b.
[0200] In this stage, first gate insulating layer 6a, combined
charge storage layer 6b, and second gate insulating layer 6c have
the same shape as control gate electrode 6d, and are covered by
control gate electrode 6d.
[0201] As shown in FIG. 19C, first to fifth temporary layers 12a to
12e are then selectively removed by isotropic dry etching, and
cavities 22, . . . are formed on upper and lower sides (z-direction
sides) of first to fourth semiconductor layers 3a to 3d.
[0202] In FIG. 19B, first to fifth temporary layers 12a to 12e can
be easily removed by isotropic dry etching because the space
between control gate electrodes 6d, . . . and the space between
first to fourth semiconductor layers 3a to 3d (first to fourth
charge storage layers 6b, . . . ) are exposed.
[0203] As shown in FIG. 19D, combined charge storage layer 6b is
selectively oxidized from the regions in which first to fifth
temporary layers 12a to 12e are removed.
[0204] For example, by annealing in an atmosphere containing
oxygen, the oxidizing of combined charge storage layer 6b is
carried out from the regions in which first to fifth temporary
layers 12a to 12e are removed.
[0205] At this moment, combined charge storage layer 6b is not
oxidized between first to fourth semiconductor layers 3a to 3d and
control gate electrode 6d. Therefore, combined charge storage layer
6b is changed to charge storage layers 6b, . . . physically
separated from one another by oxide 14 of combined charge storage
layer 6b.
[0206] Here, the side surfaces of charge storage layers 6b, . . .
in the x-direction are covered by first to fourth semiconductor
layers 3a to 3d and control gate electrode 6d, and the side
surfaces of charge storage layers 6b, . . . in the y-direction and
the z-direction are covered by oxide 14 of combined charge storage
layer 6b.
[0207] This effectively prevents the diffusion of an impurity such
as carbon to charge storage layers 6b, . . . in the subsequent
process, for example, in the process of forming an interlayer
insulating layer.
[0208] In the meantime, although cavities 22, . . . may be as they
are, cavities 22, . . . may be filled with insulating layers (e.g.,
silicon oxide) 15 as shown in FIG. 19E. In this case, insulating
layers 15 may be porous insulating layers.
F. Summary
[0209] As described above, according to the second embodiment, a
structure in which charge storage layers are independent for the
respective memory cells is formed without a substantial increase in
the number of processes, and it is thereby possible to provide high
reliability of the three-dimensional stacked layer type
semiconductor memory.
(3) Third Embodiment
A. Structure
[0210] FIG. 20 shows a nonvolatile semiconductor memory device as
the third embodiment. FIG. 21 shows a structure in which second
gate insulating layer 6(1)c and control gate electrode 6(1)d are
eliminated from the structure shown in FIG. 20.
[0211] Semiconductor substrate 1 is, for example, a silicon
substrate. A fin-type stacked layer structure extending in a
y-direction parallel to the surface of semiconductor substrate 1 is
disposed on semiconductor substrate 1.
[0212] This fin-type stacked layer structure comprises first
insulating layer 2, first semiconductor layer 3a, second insulating
layer 4a, second semiconductor layer 3b, third insulating layer 4b,
third semiconductor layer 3c, fourth insulating layer 4c, fourth
semiconductor layer 3d, and fifth insulating layer 5 that are
stacked in a z-direction perpendicular to the surface of
semiconductor substrate 1.
[0213] First to fifth insulating layers 2, 4a to 4c, and 5 may be
made of any insulator, and silicon oxide, for example, can be used.
First to fourth semiconductor layers 3a to 3d are made of, for
example, silicon.
[0214] On the x-direction side of first to fourth semiconductor
layers 3 (3a, 3b, 3c, and 3d), stacked layer structure 6(1) in
which first gate insulating layer 6(1)a, charge storage layer
6(1)b, second gate insulating layer 6(1)c, and control gate
electrode 6(1)d are stacked in order in the x-direction is
disposed.
[0215] First gate insulating layer 6(1)a is a tunnel insulating
layer through which a tunnel current runs, and is made of, for
example, silicon oxide. Charge storage layer 6(1)b is a layer for
storing a charge, and its charge amount is controlled by the tunnel
current.
[0216] Charge storage layer 6(1)b is made of an insulator or a
conductor. When charge storage layer 6(1)a is an insulator (e.g.,
silicon nitride), a memory cell is a SONOS type. When charge
storage layer 6(1)a is a conductor (e.g., conductive polysilicon),
a memory cell is a floating gate type.
[0217] Charge storage layers 6(1)b are independent for the
respective memory cells. In particular, four charge storage layers
6(1)b, . . . arranged in the z-direction are physically separated
from one another by elements between first to fourth semiconductor
layers 3 (3a, 3b, 3c, and 3d), in the present embodiment, by second
to fourth insulating layers 4 (4a, 4b, and 4c).
[0218] Second gate insulating layer 6(1)c prevents a leakage
current between charge storage layer 6(1)b and control gate
electrode 6(1)d. Second gate insulating layer 6(1)c comprises, for
example, a stacked layer structure or a material having a high
dielectric constant to increase the coupling ratio of the memory
cells and improve writing/erasing characteristics.
[0219] When the memory cell is the SONOS type, second gate
insulating layer 6(1)c is generally called a block insulating
layer. When the memory cell is the floating gate type, second gate
insulating layer 6(1)c is generally called an inter-electrode
insulating layer.
[0220] Control gate electrode 6(1)d functions as a word line, and
extends in the x-direction on the z-direction side of fifth
insulating layer 5 and extends in the z-direction on the
x-direction side of first to fourth semiconductor layers 3 (3a, 3b,
3c, and 3d).
[0221] That is, control gate electrode 6(1)d covers four charge
storage layers 6(1)b, . . . , and extends across the fin-type
stacked layer structure in the x-direction.
[0222] Here, the side surfaces of four charge storage layers 6(1)b,
. . . in the x-direction project as compared with the x-direction
side surfaces of first to fifth insulating layers 2, 4a to 4c, and
5 located above and under charge storage layers 6(1)b, Therefore,
control gate electrode 6(1)d covers the side surfaces of four
charge storage layers 6(1)b, . . . in the x-direction and their
side surfaces in the z-direction, so that writing/erasing
characteristics can be improved by the improvement of the coupling
ratio of the memory cells.
[0223] Stacked layer structures 6(2) and 6(3) have the same
structure as stacked layer structure 6(1).
[0224] By the device structure described above, a string of memory
cells connected in series in the y-direction, that is, a NAND
string is formed in each of first to fourth semiconductor layers 3
(3a, 3b, 3c, and 3d). Here, the NAND string formed in first
semiconductor layer 3a is NAND1, the NAND string formed in second
semiconductor layer 3b is NAND2, the NAND string formed in third
semiconductor layer 3c is NAND3, and the NAND string formed in
fourth semiconductor layer 3d is NAND4.
[0225] Charge storage layers 6(1)b of the memory cells that
constitute these NAND strings are independent for the respective
memory cells. That is, charge storage layers 6(1)b, . . . are
physically separated from one another by second to fourth
insulating layers 4 (4a, 4b, and 4c). Therefore, the reliability of
the three-dimensional stacked layer type semiconductor memory can
be improved.
B. Material Examples
[0226] Materials best suited to the generations of the
semiconductor memories can be properly selected as the materials
that constitute the elements of the device structure shown in FIG.
20 and FIG. 21.
[0227] Examples of materials for first gate insulating layer 6(1)a,
charge storage layer 6(1)b, second gate insulating layer 6(1)c, and
control gate electrode 6(1)d are the same as those according to the
first embodiment and are therefore not described here.
C. First Modification
[0228] FIG. 22 shows a first modification of the third
embodiment.
[0229] The first modification is characterized in that the
uppermost layer among first to fourth semiconductor layers 3 (3a,
3b, 3c, and 3d), that is, fourth semiconductor layer 3d is dummy
layer DUMMY in which dummy cells as non-memory cells are
formed.
[0230] Fourth semiconductor layer 3d as an uppermost layer is used
as an etching mask in one step of a manufacturing method described
later, and therefore tends to be damaged. Thus, the NAND string
formed in fourth semiconductor layer 3d is not used as a memory
cell, and is a dummy cell as a non-memory cell.
[0231] In this case, in order to improve the function of fourth
semiconductor layer 3d as a mask, the width of fourth semiconductor
layer 3d in the z-direction is preferably greater than the width of
first to third semiconductor layers 3a, 3b, and 3c in the
z-direction.
D. Second Modification
[0232] FIG. 23 shows a second modification of the third
embodiment.
[0233] The second modification is characterized in that four charge
storage layers 6(1)b, . . . arranged in the z-direction are
physically separated from one another by cavities (e.g., air gaps).
That is, in the second modification, the elements between first to
fourth semiconductor layers 3 (3a, 3b, 3c, and 3d) are
cavities.
[0234] When the memory cell is miniaturized, a parasitic
capacitance generated between charge storage layers 6(1)b is
increased, and wrong operation is caused by mutual interference. To
prevent this, the space between charge storage layers 6(1)b is
preferably a cavity having a low dielectric constant.
[0235] Although all of first to fifth insulating layers 2, 4a to
4c, and 5 in the third embodiment (FIG. 20 and FIG. 21) are changed
to cavities in this modification, some of the insulating layers may
be only changed to cavities. The cavity is preferably a complete
cavity, but the insulator may partly remain in the cavity.
[0236] The cavity can be changed to a porous insulator.
D. Example of NAND Cell Unit
[0237] A NAND cell unit structure to which the third embodiment
(FIG. 20 and FIG. 21) is applied can be the NAND cell unit
structure shown in FIG. 5 to FIG. 7 or the NAND cell unit structure
shown in FIG. 11 to FIG. 13.
[0238] A NAND cell unit structure to which the first modification
(FIG. 22) is applied can be the NAND cell unit structure shown in
FIG. 8 to FIG. 10 or the NAND cell unit structure shown in FIG. 11
to FIG. 13.
[0239] A NAND cell unit structure to which the second modification
(FIG. 23) is applied can be the NAND cell unit structure shown in
FIG. 5 to FIG. 7, the NAND cell unit structure shown in FIG. 8 to
FIG. 10, or the NAND cell unit structure shown in FIG. 11 to FIG.
13.
[0240] However, in these NAND cell unit structures, a NAND cell
unit part needs to be changed to the structure shown in FIG. 20 to
FIG. 23.
E. Manufacturing Method
[0241] The structures according to the third embodiment (FIG. 20
and FIG. 21) and the first modification (FIG. 22) can be
manufactured in the same way as shown FIG. 14A to FIG. 14L. The
structure according to the second modification (FIG. 23) can be
manufactured in the same way as shown FIG. 15A to FIG. 15N.
[0242] A method of manufacturing the structures according to the
third embodiment (FIG. 20 and FIG. 21) is described below with
reference to FIG. 24A to FIG. 24M. In each of these drawings, (a)
is a plan view, (b) is a side view from the x-direction, and (c) is
a side view from the y-direction.
[0243] First, as shown in FIG. 24A, first insulating layer 2, first
semiconductor layer 3a, second insulating layer 4a, second
semiconductor layer 3b, third insulating layer 4b, third
semiconductor layer 3c, fourth insulating layer 4c, fourth
semiconductor layer 3d, and fifth insulating layer 5 are
sequentially formed in the z-direction perpendicular to the surface
of semiconductor substrate 1.
[0244] Here, semiconductor substrate 1 is, for example, a p-type
silicon substrate having a plane direction (100) and a specific
resistance of 10 to 20 .OMEGA.cm. First to fifth insulating layers
2, 4a to 4c, and 5 are made of silicon oxide. First to fourth
semiconductor layers 3a to 3d are made of silicon.
[0245] First to fifth insulating layers 2, 4a to 4c, and 5 and
first to fourth semiconductor layers 3a to 3d are then fabricated
by the PEP and anisotropic dry etching, and a fin-type stacked
layer structure extending in the y-direction parallel to the
surface of semiconductor substrate 1 is formed.
[0246] As shown in FIG. 24B, the side surfaces of first to fourth
semiconductor layers 3a to 3d in the x-direction are then
selectively etched in the x-direction by isotropic dry etching. As
a result, the side surfaces of first to fourth semiconductor layers
3a to 3d in the x-direction are set back, and first to fourth
recesses 21a to 21d extending in the y-direction are formed.
[0247] As shown in FIG. 24C, the side surfaces of first to fourth
semiconductor layers 3a to 3d in the x-direction are then thermally
oxidized, and first gate insulating layers (e.g., silicon oxide) 6a
are formed on the side surfaces of first to fourth semiconductor
layers 3a to 3d in the x-direction.
[0248] As shown in FIG. 24D, charge storage layer 6b covering the
fin-type stacked layer structure is then formed. A material such as
silicon nitride or conductive polysilicon can be used as charge
storage layer 6b.
[0249] As shown in FIG. 24E, charge storage layer 6b is then
selectively etched by anisotropic dry etching. As a result, charge
storage layer 6b only remains in first to fourth recesses 21a to
21d on the side surfaces of first to fourth semiconductor layers 3a
to 3d in the x-direction.
[0250] That is, fifth insulating layer 5 is exposed when uppermost
charge storage layer 6b is removed. Therefore, fifth insulating
layer 5 is used as a mask to further etch charge storage layer 6b,
and first to fourth charge storage layers 6b are then formed in
first to fourth recesses 21a to 21d, respectively.
[0251] Here, as fifth insulating layer 5 functions as a mask for
etching charge storage layer 6b, the width of fifth insulating
layer 5 in the z-direction may be greater than the width of each of
first to fourth insulating layers 2, 4a to 4c in the
z-direction.
[0252] If the function of fifth insulating layer 5 as the mask is
regarded as important, fifth insulating layer 5 may be formed by a
method and a material different from first to fourth insulating
layers 2, 4a to 4c (e.g., a stacked layer structure of different
insulating layers).
[0253] At this point, first to fourth charge storage layers 6b are
separated in the z-direction.
[0254] As shown in FIG. 24F, first to fifth insulating layers 2, 4a
to 4c, and 5 are then selectively etched by isotropic dry etching.
Accordingly, the side surfaces of first to fifth insulating layers
2, 4a to 4c, and 5 in the x-direction are set back in the
x-direction, and the side surface of charge storage layer 6b in the
x-direction projects as compared with the side surfaces of first to
fifth insulating layers 2, 4a to 4c, and 5 in the x-direction.
[0255] As shown in FIG. 24G, second gate insulating layer 6c and
control gate electrode 6d that cover the fin-type stacked layer
structure (including first to fourth charge storage layers 6b) are
then formed. A material such as aluminum oxide can be used as
second gate insulating layer 6c, and a material such as nickel
silicide can be used as control gate electrode 6d.
[0256] As shown in FIG. 24H, second gate insulating layer 6c and
control gate electrode 6d are fabricated by the PEP and anisotropic
dry etching, and control gate electrodes (word lines) 6d, . . . are
formed. Control gate electrodes (word lines) 6d, . . . extend in
the x-direction on the z-direction side of fifth insulating layer
5, and extend in the z-direction on the x-direction side of first
to fourth charge storage layers 6b.
[0257] Here, control gate electrodes (word lines) 6d, . . . cover
the side surfaces of first to fourth charge storage layers 6b in
the x-direction and at least part of their side surfaces in the
z-direction. Therefore, the coupling ratio of the memory cells can
be improved.
[0258] As shown in FIG. 24I, fifth insulating layer 5 is then
selectively etched by anisotropic dry etching. At the same time,
control gate electrodes 6d, . . . function as masks for the
anisotropic dry etching. Therefore, in parts that are not covered
by control gate electrodes 6d, . . . , fifth insulating layer 5 is
selectively removed, and the side surfaces of fourth semiconductor
layer 3d and fourth charge storage layer 6b in the z-direction are
exposed.
[0259] As shown in FIG. 24J, fourth charge storage layer 6b is then
selectively etched by anisotropic dry etching. At the same time,
control gate electrodes 6d, . . . and fourth semiconductor layer 3d
function as masks for the anisotropic dry etching.
[0260] Therefore, as the part of fourth charge storage layer 6b
that is not covered by control gate electrodes 6d, . . . is
selectively removed, fourth charge storage layers 6b, . . .
separated in the y-direction are formed on the x-direction side of
fourth semiconductor layer 3d.
[0261] As shown in FIG. 24K, fourth insulating layer 4c is then
selectively etched by anisotropic dry etching. At the same time,
control gate electrodes 6d, . . . and fourth semiconductor layer 3d
function as masks for the anisotropic dry etching.
[0262] Therefore, in parts that are not covered by control gate
electrodes 6d, . . . and fourth semiconductor layer 3d, fourth
insulating layer 4c is selectively removed, and the side surface of
third charge storage layer 6b in the z-direction is exposed.
[0263] As shown in FIG. 24L, third charge storage layer 6b is then
selectively etched by anisotropic dry etching. At the same time,
control gate electrodes 6d, . . . and fourth semiconductor layer 3d
function as masks for the anisotropic dry etching.
[0264] Therefore, as the part of third charge storage layer 6b that
is not covered by control gate electrodes 6d, . . . is selectively
removed, third charge storage layers 6b, . . . separated in the
y-direction are formed on the x-direction side of third
semiconductor layer 3c.
[0265] Similarly, second charge storage layers 6b, . . . separated
in the y-direction are formed on the x-direction side of second
semiconductor layer 3b, and first charge storage layers 6b, . . .
separated in the y-direction are formed on the x-direction side of
first semiconductor layer 3a.
[0266] As shown in FIG. 24M, charge storage layers 6b, . . .
physically separated for the respective memory cells are formed by
the process described above. This prevents a situation where a
charge in a charge storage layer moves to another charge storage
layer in first to fourth charge storage layers 6b, . . . , so that
satisfactory data retention characteristics can be obtained.
[0267] In the manufacturing method according to the present
embodiment, as apparent from FIG. 24J to FIG. 24L, uppermost fourth
semiconductor layer 3d functions as the etching mask during the
etching to accomplish the independence of the charge storage
layers.
[0268] Therefore, it is preferable that fourth semiconductor layer
3d is a dummy layer and that the width of fourth semiconductor
layer 3d in the z-direction is greater than the width of each of
first to third semiconductor layers 3a to 3c in the
z-direction.
G. Summary
[0269] As described above, according to the third embodiment, a
structure in which charge storage layers are independent for the
respective memory cells is formed without a substantial increase in
the number of processes, and it is thereby possible to provide high
reliability of the three-dimensional stacked layer type
semiconductor memory.
3. Others (Fourth Embodiment)
[0270] All of the embodiments described above concern a double gate
type memory cell in which the charge storage layers are located on
both sides of the fin-type stacked layer structure in the
x-direction. However, in all of these embodiments, insulating layer
19 can be provided in the fin-type stacked layer structure, and a
three-dimensional stacked layer type semiconductor memory having a
single gate type memory cell can be formed, as shown in FIG.
25.
[0271] Such a structure allows the improvement in the degree of
integration of the memory cells and higher capacity of the
memory.
[0272] The same elements in FIG. 25 as those in FIG. 11 are
provided with the same reference marks and are thus not described
in detail.
4. Conclusion
[0273] According to the embodiment, a structure in which charge
storage layers are independent for the respective memory cells is
formed without a substantial increase in the number of processes,
and it is thereby possible to provide high reliability of the
three-dimensional stacked layer type semiconductor memory.
[0274] The embodiment is industrially enormously advantageous to,
for example, a file memory capable of high-speed random writing, a
mobile terminal capable of high-speed downloading, a mobile player
capable of high-speed downloading, a semiconductor memory for
broadcasting devices, a drive recorder, a home video, a
high-capacity buffer memory for communication, and a semiconductor
memory for a security camera.
[0275] While certain embodiments have been described, these
embodiments have been presented by way of example only, and are not
intended to limit the scope of the inventions. Indeed, the novel
embodiments described herein may be embodied in a variety of other
forms; furthermore, various omissions, substitutions and changes in
the form of the embodiments described herein may be made without
departing from the spirit of the inventions. The accompanying
claims and their equivalents are intended to cover such forms or
modifications as would fall within the scope and spirit of the
inventions.
* * * * *