U.S. patent application number 13/167764 was filed with the patent office on 2012-12-27 for systems and methods for non-binary decoding.
This patent application is currently assigned to LSI Corporation. Invention is credited to Wu Chang, Yang Han, Zongwang Li, Chung-Li Wang, Changyou Xu, Shaohua Yang.
Application Number | 20120331370 13/167764 |
Document ID | / |
Family ID | 47363024 |
Filed Date | 2012-12-27 |
United States Patent
Application |
20120331370 |
Kind Code |
A1 |
Li; Zongwang ; et
al. |
December 27, 2012 |
Systems and Methods for Non-Binary Decoding
Abstract
Various embodiments of the present invention provide systems and
methods for data processing. A data processing circuit is disclosed
that includes: a data detector circuit, a first symbol constrained
arrangement circuit, and a second symbol constrained arrangement
circuit. The data detector circuit is operable to apply a data
detection algorithm to a combination of a first input data set and
a decoded data set to yield a detected output that includes a
number of non-binary symbols. The first symbol constrained
arrangement circuit is operable to receive the detected output and
to re-arrange the detected output in accordance with a first
arrangement algorithm to yield a re-arranged output. The bits for
at least one non-binary symbol from the detected output are
maintained together in the re-arranged output. The second symbol
constrained arrangement circuit is operable to receive a second
input data set and to re-arrange the second data input in
accordance with a second arrangement algorithm to yield the decoded
data set. The bits for at least one non-binary symbol from the
second input data set are maintained together in the decoded data
set output.
Inventors: |
Li; Zongwang; (San Jose,
CA) ; Chang; Wu; (Santa Clara, CA) ; Wang;
Chung-Li; (San Jose, CA) ; Xu; Changyou;
(Fremont, CA) ; Yang; Shaohua; (San Jose, CA)
; Han; Yang; (Sunnyvale, CA) |
Assignee: |
LSI Corporation
|
Family ID: |
47363024 |
Appl. No.: |
13/167764 |
Filed: |
June 24, 2011 |
Current U.S.
Class: |
714/795 ;
714/E11.03 |
Current CPC
Class: |
H03M 13/1171 20130101;
H04L 1/0047 20130101; H03M 13/255 20130101; H03M 13/134
20130101 |
Class at
Publication: |
714/795 ;
714/E11.03 |
International
Class: |
G06F 11/08 20060101
G06F011/08 |
Claims
1. A data processing circuit, the circuit comprising: a data
detector circuit operable to apply a data detection algorithm to a
combination of a first input data set and a decoded data set to
yield a detected output, wherein the detected output includes a
number of non-binary symbols; a first symbol constrained
arrangement circuit operable to receive the detected output and to
re-arrange the detected output in accordance with a first
arrangement algorithm to yield a re-arranged output, wherein the
bits for at least one non-binary symbol from the detected output
are maintained together in the re-arranged output; and a second
symbol constrained arrangement circuit operable to receive a second
input data set and to re-arrange the second data input in
accordance with a second arrangement algorithm to yield the decoded
data set, wherein the bits for at least one non-binary symbol from
the second input data set are maintained together in the decoded
data set output.
2. The circuit of claim 1, wherein the circuit is implemented as
part of an integrated circuit.
3. The circuit of claim 1, wherein the circuit is implemented as
part of a device selected from a group consisting of: a storage
device, and a wireless data transfer device.
4. The circuit of claim 3, wherein the storage device is a hard
disk drive.
5. The circuit of claim 1, wherein the first arrangement algorithm
is the inverse of the second arrangement algorithm.
6. The circuit of claim 1, wherein the first arrangement algorithm
is the inverse of a third arrangement algorithm applied to yield
the first input data set.
7. The circuit of claim 1, wherein the data detection algorithm is
selected from a group consisting of: a Viterbi algorithm data
detection algorithm, and a maximum a posteriori data detection
algorithm.
8. The circuit of claim 1, wherein the circuit further comprises: a
data decoder circuit operable to apply a data decoding algorithm to
the re-arranged output to yield the second input data set.
9. The circuit of claim 8, wherein the data decoding algorithm is a
non-binary data decoding algorithm tailored for the non-binary
symbols.
10. The circuit of claim 9, wherein the non-binary symbols are
selected from a group consisting of: two bit symbols, and three bit
symbols.
11. A method for data processing, the method comprising: receiving
a first data input having at least a first non-binary symbol;
receiving a second data input having at least a second non-binary
symbol, wherein the second non-binary symbol corresponds to the
first non-binary symbol; re-arranging the second data input
according to a second arrangement algorithm to yield a decoded data
set, wherein the bits of the second non-binary symbol are placed
together in the decoded data set; applying a data detection
algorithm to the first data input and the decoded data set to yield
a detected output, wherein the detected output includes the first
non-binary symbol; and re-arranging the detected output according
to a first arrangement algorithm to yield a re-arranged output,
wherein the bits of the first non-binary symbol are placed together
in the re-arranged output.
12. The method of claim 11, wherein the method further comprises:
applying a decoding algorithm to the re-arranged output to yield
the second data input.
13. The method of claim 11, wherein the second arrangement
algorithm is the inverse of the first arrangement algorithm.
14. A data processing system, the system comprising: an analog
front end circuit operable to receive an analog signal from a
channel; an analog to digital converter circuit operable to convert
the analog signal into a series of digital samples; an equalizer
circuit operable to equalize the series of digital samples to yield
a first input data set; a data detector circuit operable to apply a
data detection algorithm to a combination of a first input data set
and a decoded data set to yield a detected output, wherein the
detected output includes a number of non-binary symbols; a first
symbol constrained arrangement circuit operable to receive the
detected output and to re-arrange the detected output in accordance
with a first arrangement algorithm to yield a re-arranged output,
wherein the bits for at least one symbol from the detected output
are maintained together in the re-arranged output; a second symbol
constrained arrangement circuit operable to receive a second data
input and to re-arrange the second data input in accordance with a
second arrangement algorithm to yield the decoded data set, wherein
the bits for at least one symbol from the second data set are
maintained together in the re-arranged output; and a data decoder
circuit operable to apply a data decoding algorithm to the
re-arranged output to yield the second input data set.
15. The system of claim 14, wherein the system is a storage device,
and wherein the channel includes a magnetic storage medium.
16. The system of claim 14, wherein the system is a wireless data
transfer device, and wherein the channel includes a wireless data
transmission medium.
17. The system of claim 14, wherein the first arrangement algorithm
is the inverse of the second arrangement algorithm.
18. The system of claim 14, wherein the first arrangement algorithm
is the inverse of a third arrangement algorithm applied to yield
the first input data set.
19. The system of claim 14, wherein the data detection algorithm is
selected from a group consisting of: a Viterbi algorithm data
detection algorithm, and a maximum a posteriori data detection
algorithm.
20. The system of claim 14, wherein the data decoding algorithm is
a non-binary data decoding algorithm tailored for the non-binary
symbols.
Description
BACKGROUND OF THE INVENTION
[0001] The present inventions are related to systems and methods
for data processing, and more particularly to non-binary based data
decoding.
[0002] Various data transfer systems have been developed including
storage systems, cellular telephone systems, and radio transmission
systems. In each of the systems data is transferred from a sender
to a receiver via some medium. For example, in a storage system,
data is sent from a sender (i.e., a write function) to a receiver
(i.e., a read function) via a storage medium. In such systems,
errors are introduced to the data during the transmission and
recovery processes. In some cases, such errors can be detected by
applying encoding/decoding techniques such as low density parity
check encoding/decoding. In some cases such encoding/decoding
techniques may require complex and bandwidth intense
functionality.
[0003] Hence, there exists a need in the art for advanced systems
and methods for error correction in data processing systems.
BRIEF SUMMARY OF THE INVENTION
[0004] The present inventions are related to systems and methods
for data processing, and more particularly to non-binary based data
decoding.
[0005] Various embodiments of the present invention provide data
processing circuits that include: a data detector circuit, a first
symbol constrained arrangement circuit, and a second symbol
constrained arrangement circuit. The data detector circuit is
operable to apply a data detection algorithm to a combination of a
first input data set and a decoded data set to yield a detected
output that includes a number of non-binary symbols. The first
symbol constrained arrangement circuit is operable to receive the
detected output and to re-arrange the detected output in accordance
with a first arrangement algorithm to yield a re-arranged output.
The bits for at least one non-binary symbol from the detected
output are maintained together in the re-arranged output. The
second symbol constrained arrangement circuit is operable to
receive a second input data set and to re-arrange the second data
input in accordance with a second arrangement algorithm to yield
the decoded data set. The bits for at least one non-binary symbol
from the second input data set are maintained together in the
decoded data set output.
[0006] In some instances of the aforementioned embodiments, the
circuit is implemented as part of an integrated circuit. In various
instances of the aforementioned embodiments, the circuit is
implemented as part of a storage device, or a wireless data
transfer device. In some particular cases, the aforementioned
storage device is a hard disk drive.
[0007] In one or more instances of the aforementioned embodiments,
the first arrangement algorithm is the inverse of the second
arrangement algorithm. In various instances of the aforementioned
embodiments, the first arrangement algorithm is the inverse of a
third arrangement algorithm applied to yield the first input data
set. In some cases, the data detection algorithm may be, but is not
limited to, a Viterbi algorithm data detection algorithm, or a
maximum a posteriori data detection algorithm.
[0008] In some instances of the aforementioned embodiments, the
circuit further includes a data decoder circuit that is operable to
apply a data decoding algorithm to the re-arranged output to yield
the second input data set. In some such instances, the data
decoding algorithm is a non-binary data decoding algorithm tailored
for the non-binary symbols. These non-binary symbols may be two or
more bits each.
[0009] Other embodiments of the present invention provide methods
for data processing that include: receiving a first data input
having at least a first non-binary symbol; receiving a second data
input having at least a second non-binary symbol that corresponds
to the first non-binary symbol; re-arranging the second data input
according to a second arrangement algorithm to yield a decoded data
set such that the bits of the second non-binary symbol are placed
together in the decoded data set; applying a data detection
algorithm to the first data input and the decoded data set to yield
a detected output that includes the first non-binary symbol; and
re-arranging the detected output according to a first arrangement
algorithm to yield a re-arranged output such that the bits of the
first non-binary symbol are placed together in the re-arranged
output.
[0010] This summary provides only a general outline of some
embodiments of the invention. Many other objects, features,
advantages and other embodiments of the invention will become more
fully apparent from the following detailed description, the
appended claims and the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] A further understanding of the various embodiments of the
present invention may be realized by reference to the figures which
are described in remaining portions of the specification. In the
figures, like reference numerals are used throughout several
figures to refer to similar components. In some instances, a
sub-label consisting of a lower case letter is associated with a
reference numeral to denote one of multiple similar components.
When reference is made to a reference numeral without specification
to an existing sub-label, it is intended to refer to all such
multiple similar components.
[0012] FIG. 1 depicts a data processing circuit including a
non-binary decoder circuit in accordance with one or more
embodiments of the present invention;
[0013] FIG. 2 depicts a format enhanced data detecting circuit in
accordance with some embodiments of the present invention;
[0014] FIG. 3 depicts a reduced data transfer formatting map that
may be used in relation to different embodiments of the present
invention;
[0015] FIG. 4 is a flow diagram showing a reduced format to
expanded format translation process in accordance with one or more
embodiments of the present invention;
[0016] FIG. 5a is a flow diagram showing a process of performing
data detection based on reduced format vectors in accordance with
one or more embodiments of the present invention;
[0017] FIG. 5b is a flow diagram showing an expanded format to
reduced format translation process in accordance with one or more
embodiments of the present invention;
[0018] FIG. 6 graphically depicts an example reduced data transfer
input and output process for a two bit symbol;
[0019] FIG. 7 graphically depicts an example reduced data transfer
input and output process for a three bit symbol;
[0020] FIGS. 8-9 are flow diagrams showing methods in accordance
with some embodiments of the present invention for performing
symbol constrained shuffling and de-shuffling;
[0021] FIG. 10 shows a storage system including a read channel
module with a symbol based data processing circuit in accordance
with various embodiments of the present invention; and
[0022] FIG. 11 depicts a data transmission system including a
receiver with a symbol based data processing circuit in accordance
with various embodiments of the present invention;
DETAILED DESCRIPTION OF THE INVENTION
[0023] The present inventions are related to systems and methods
for data processing, and more particularly to non-binary based data
decoding.
[0024] Various embodiments of the present invention provide for
non-binary symbol based data processing. In some cases, the data
processing includes shuffling or otherwise re-arranging transfer
data using a symbol constrained approach. Such a symbol constrained
shuffling approach may provide enhanced error recovery performance
when compared with bit level shuffling approaches. In various
cases, a reduced format data transfer may be employed that yields a
reduced circuit area when compared with non-reduced format
approaches. Based upon the disclosure provided herein, one of
ordinary skill in the art will recognize a variety of advantages in
addition to or alternative to those discussed herein.
[0025] Turning to FIG. 1, a data processing circuit 100 including a
non-binary decoder circuit 150 is shown in accordance with one or
more embodiments of the present invention. Data processing circuit
100 includes an analog front end circuit 190 that receives an
analog input 191. Analog input 191 may be received, for example,
from a read/write head assembly (not shown) disposed in relation to
a storage medium (not shown). As another example, analog input 191
may be received from a transmission medium (not shown) via a
receiver (not shown). Based upon the disclosure provided herein,
one of ordinary skill in the art will recognize a variety of
sources of analog input 191.
[0026] Prior to transmission or writing to a storage medium or to a
transmission medium (collectively referred to as a "channel"), the
data represented by analog input 191 was shuffled. Such shuffling
involves rearranging the order of an encoded data set. In
transferring data across a channel there is a possibility that
local regions of the data will become corrupt due to, for example,
electronics noise and/or media defects. Such localized corruption
is often referred to as burst errors. By shuffling the data, the
effects of localized data corruption can be spread across a wider
range of the data set increasing the possibility that the error
correction capability in data processing circuit 100 can recover
the data set affected by the localized corruption. Said another
way, burst errors corrupt a large number of successive bits that
without adjustment may overwhelm a downstream data processing
circuit. It has been determined that non-binary symbols included
within a data set also provide a valuable tool in mitigating the
effects of localized data corruption. Thus, in some embodiments of
the present invention, the shuffling is done on a non-binary symbol
by symbol basis (i.e., the integrity of the non-binary symbols
within the data set is maintained by assuring that bits
corresponding to the same symbol are not separated during the
shuffling process). Such an approach maintains the symbol integrity
of the shuffled data, allowing data detector circuit 105 to rely on
the symbols to enhance error recovery.
[0027] Examples of such symbol constrained shuffling are
graphically presented in relation to FIGS. 6-7. Turning to FIG. 6,
a graphic 600 depicts an example of the symbol constrained shuffle
process. In particular, a non-shuffled data set 610 includes a
number of binary values (b.sub.0, b.sub.1, b.sub.2, b.sub.3,
b.sub.4, b.sub.5 . . . b.sub.n-3, b.sub.n-2, b.sub.n-1, b.sub.n).
In some cases, non-shuffled data set 610 includes between five
hundred and several thousand data bits. In this example, the bits
are assembled into two bit symbols (S.sub.0, S.sub.1, S.sub.2 . . .
S.sub.n-1, S.sub.n). A shuffled data set 620 is shown where bits
corresponding to the respective two bit symbols are rearranged
without separating the bits within the symbols. In particular, bits
b.sub.n-1, b.sub.n corresponding to symbol S.sub.n are maintained
together but moved to a different location in the data set, bits
b.sub.0, b.sub.1 corresponding to symbol S.sub.0 are maintained
together but moved to a different location in the data set, bits
b.sub.0, b.sub.1 corresponding to symbol S.sub.0 are maintained
together but moved to a different location in the data set, bits
b.sub.n-3, b.sub.n-2 corresponding to symbol S.sub.n-1 are
maintained together but moved to a different location in the data
set, bits b.sub.2, b.sub.3 corresponding to symbol S.sub.1 are
maintained together but moved to a different location in the data
set, and bits b.sub.4, b.sub.5 corresponding to symbol S.sub.2 are
maintained together but moved to a different location in the data
set.
[0028] Turning to FIG. 7, a graphic 700 depicts an example of the
symbol constrained shuffle process. In particular, a non-shuffled
data set 710 includes a number of binary values (b.sub.0, b.sub.1,
b.sub.2, b.sub.3, b.sub.4, b.sub.5 . . . b.sub.n-5, b.sub.n-4,
b.sub.n-3, b.sub.n-2, b.sub.n-1, b.sub.n). Again, in some cases
non-shuffled data set 710 includes between five hundred and several
thousand data bits. In this example, the bits are assembled into
three bit symbols (S.sub.0, S.sub.1 . . . S.sub.n-1, S.sub.n). A
shuffled data set 720 is shown where bits corresponding to the
symbols are rearranged without separating the three bit symbols. In
particular, bits b.sub.n-5, b.sub.n-4, b.sub.n-3 corresponding to
symbol S.sub.n-1 are maintained together but moved to a different
location in the data set, bits b.sub.3, b.sub.4, b.sub.5
corresponding to symbol S.sub.1 are maintained together but moved
to a different location in the data set, bits b.sub.n-2, b.sub.n-1,
b.sub.n corresponding to symbol S.sub.n are maintained together but
moved to a different location in the data set, and bits b.sub.0,
b.sub.1, b.sub.2 corresponding to symbol S.sub.1 are maintained
together but moved to a different location in the data set. Of
note, while FIGS. 6-7 show examples using two bit and three bit,
respectively, other symbol lengths are possible.
[0029] Referring again to FIG. 1, analog front end circuit 190
processes analog input 191 and provides a processed analog signal
192 to an analog to digital converter circuit 195. Analog front end
circuit 190 may include, but is not limited to, an analog filter
and an amplifier circuit as are known in the art. Based upon the
disclosure provided herein, one of ordinary skill in the art will
recognize a variety of circuitry that may be included as part of
analog front end circuit 190. An analog to digital converter
circuit 195 converts processed analog signal 192 into a
corresponding series of digital samples 101. Analog to digital
converter circuit 195 may be any circuit known in the art that is
capable of producing digital samples corresponding to an analog
input signal. Based upon the disclosure provided herein, one of
ordinary skill in the art will recognize a variety of analog to
digital converter circuits that may be used in relation to
different embodiments of the present invention.
[0030] Digital samples 101 are provided to an equalizer circuit 102
that provides an equalized output 103. In some embodiments of the
present invention, equalizer circuit 102 is a digital finite
impulse response (DIFR) circuit as are known in the art. Based upon
the disclosure provided herein, one of ordinary skill in the art
will recognize a variety of equalizer circuits that may be used in
relation to different embodiments of the present invention.
Equalized output 103 is stored in a Y-sample buffer circuit 185
that maintains a number of data sets allowing for multiple global
iterations passing the given data set through a data detector
circuit 105 and non-binary data decoder circuit 150. The size of
Y-sample buffer circuit 185 may be selected to provide sufficient
buffering such that a data set received as equalized output 103
remains available at least until a first iteration processing of
that same data set is complete and the processed data is available
in a central queue buffer circuit 120 as more fully described
below. Y-sample buffer circuit 185 provides the data sets 187 to
data detector circuit 105.
[0031] Data detector circuit 105 may be any data detector circuit
known in the art. For example, in some embodiments of the present
invention, data detector circuit 105 is a Viterbi algorithm data
detector circuit. As another example, in some embodiments of the
present invention, data detector circuit 105 is a maximum a
posteriori data detector circuit. Based upon the disclosure
provided herein, one of ordinary skill in the art will recognize a
variety of data detection algorithms that may be implemented by
data detector circuit 105. In some particular embodiments of the
present invention, data detector circuit 105 may be a format
enhanced data detecting circuit as discussed in relation to FIG. 2
below. Data detector circuit provides a detected output 113 that
corresponds to the received data input.
[0032] Detected output 113 is provided to a symbol constrained
de-shuffle circuit 115 that applies a de-shuffling algorithm to
detected output 113 to yield a de-shuffled output 118. The
shuffling algorithm applied by symbol constrained de-shuffle
circuit 115 is the reverse of that applied to the encoded data set
incorporated in analog input 191. In particular, the integrity of
the symbols included within the data set was maintained in the
shuffling process and is also maintained in the de-shuffling
process. An example of the de-shuffling process applied by
de-shuffle circuit 115 is depicted in FIGS. 6-7. In particular,
referring to FIG. 6, shuffled data set 620 is translated to a
de-shuffled data set 630 where symbol S.sub.0 is returned to its
original position with bits b.sub.0, b.sub.1 maintained together;
symbol S.sub.1 is returned to its original position with bits
b.sub.2, b.sub.3 maintained together; symbol S.sub.3 is returned to
its original position with bits b.sub.4, b.sub.5 maintained
together; symbol S.sub.n-1 is returned to its original position
with bits b.sub.n-3, b.sub.n-2 maintained together; and symbol
S.sub.n is returned to its original position with bits b.sub.n-1,
b.sub.n maintained together. Similarly, referring to FIG. 7,
shuffled data set 720 is translated to a de-shuffled data set 730
where symbol S.sub.0 is returned to its original position with bits
b.sub.0, b.sub.1, b.sub.2 maintained together; symbol S.sub.1 is
returned to its original position with bits b.sub.3, b.sub.4,
b.sub.5 maintained together; symbol S.sub.n-1 is returned to its
original position with bits b.sub.n-5, b.sub.n-4, b.sub.n-3
maintained together; symbol S.sub.n is returned to its original
position with bits b.sub.n-2, b.sub.n-1, b.sub.n maintained
together.
[0033] De-shuffled output 118 is stored to a central queue buffer
circuit 120 where it awaits processing by a non-binary decoder
circuit 150. Central queue buffer circuit 120 is a storage circuit
capable of maintaining data sets provided by data detector circuit
105 and data sets provided by non-binary decoder circuit 150. In
some cases, central queue buffer circuit 120 is a dual port memory
allowing accesses by two requestors at a time. In other cases,
central queue buffer circuit 120 is a single port memory allowing
accesses by only one requestor at a time. In various cases, a write
after read access is used to increase the usage of a single port
implementation.
[0034] Data sets previously processed by data detector circuit 105
are decoded by non-binary decoder circuit 150. Non-binary decoder
circuit 150 applies a non-binary decoding algorithm to the received
data set. In some cases, the non-binary decoding algorithm is a low
density parity check algorithm designed to operate on non-binary
symbols. In operation, non-binary decoder circuit 150 loads a data
set 123 from central queue buffer circuit 120 into one of a ping
memory 135 or a pong memory 140 included as part of a ping/pong
memory circuit 130. At the same time, non-binary decoder circuit
150 applies the non-binary decoding algorithm to a data set 143
that was previously stored to the other of ping memory 135 or pong
memory 140. As the non-binary decoding algorithm is processing,
results in the form of a data set 146 are written to the one of the
ping memory 135 or pong memory 140 holding the data that is
currently being decoded. Where the decoding process fails to
converge, non-binary decoder circuit 150 causes the decoded data
set 146 from ping-pong memory circuit 130 to be written to central
queue circuit 120 as a data set 126.
[0035] Data set 126 may then be pulled from central queue buffer
circuit 120 as a data set 163 that is provided to a symbol
constrained shuffle circuit 160. Symbol constrained shuffle circuit
160 reverses the shuffling that was applied by symbol constrained
de-shuffle circuit 115. Symbol constrained shuffle circuit 160
provides a resulting shuffled output 166 to data detector circuit
105. Data detector circuit 105 applies a data detection algorithm
to the combination of shuffled output 166 and the corresponding
data set 187 from Y-sample buffer circuit 185. The resulting output
is provided as detected output 113.
[0036] The shuffling applied by symbol constrained shuffle circuit
160 involves rearranging the order of data set 163. It has been
determined that non-binary symbols included within a data set
provide a valuable tool in mitigating the effects of localized data
corruption. Thus, in some embodiments of the present invention, the
shuffling performed by symbol constrained shuffle circuit 160 is
done on a non-binary symbol by symbol basis (i.e., the integrity of
the non-binary symbols within the data set is maintained by
assuring that bits corresponding to the same symbol are not
separated during the shuffling process). Such an approach maintains
the symbol integrity of the shuffled data, allowing data detector
circuit 105 to rely on the symbols to enhance error recovery.
[0037] Examples of such symbol constrained shuffling are
graphically presented in relation to FIGS. 6-7. Turning to FIG. 6,
a graphic 600 depicts an example of the symbol constrained shuffle
process. In particular, a non-shuffled data set 610 includes a
number of binary values (b.sub.0, b.sub.1, b.sub.2, b.sub.3,
b.sub.4, b.sub.5 . . . b.sub.n-3, b.sub.n-2, b.sub.n-1, b.sub.n).
In some cases, non-shuffled data set includes between five hundred
and several thousand data bits. In this example, the bits are
assembled into two bit symbols (S.sub.0, S.sub.1, S.sub.2 . . .
S.sub.n-1, S.sub.n). A shuffled data set 620 is shown where bits
corresponding to the symbols are rearranged without separating the
two bit symbols. In particular, bits b.sub.n-1, b.sub.n
corresponding to symbol S.sub.n are maintained together but moved
to a different location in the data set, bits b.sub.0, b.sub.1
corresponding to symbol S.sub.0 are maintained together but moved
to a different location in the data set, bits b.sub.0, b.sub.1
corresponding to symbol S.sub.0 are maintained together but moved
to a different location in the data set, bits b.sub.n-3, b.sub.n-2
corresponding to symbol S.sub.n-1 are maintained together but moved
to a different location in the data set, bits b.sub.2, b.sub.3
corresponding to symbol S.sub.1 are maintained together but moved
to a different location in the data set, and bits b.sub.4, b.sub.5
corresponding to symbol S.sub.2 are maintained together but moved
to a different location in the data set.
[0038] Turning to FIG. 7, a graphic 700 depicts an example of the
symbol constrained shuffle process. In particular, a non-shuffled
data set 710 includes a number of binary values (b.sub.0, b.sub.1,
b.sub.2, b.sub.3, b.sub.4, b.sub.5 . . . b.sub.n-5, b.sub.n-4,
b.sub.n-3, b.sub.n-2, b.sub.n-1, b.sub.n). Again, in some cases
non-shuffled data set includes between five hundred and several
thousand data bits. In this example, the bits are assembled into
three bit symbols (S.sub.0, S.sub.1 . . . S.sub.n-1, S.sub.n). A
shuffled data set 720 is shown where bits corresponding to the
symbols are rearranged without separating the three bit symbols. In
particular, bits b.sub.n-5, b.sub.n-4, b.sub.n-3 corresponding to
symbol S.sub.n-1 are maintained together but moved to a different
location in the data set, bits b.sub.3, b.sub.4, b.sub.5
corresponding to symbol S.sub.1 are maintained together but moved
to a different location in the data set, bits b.sub.n-2, b.sub.n-1,
b.sub.n corresponding to symbol S.sub.n are maintained together but
moved to a different location in the data set, and bits b.sub.0,
b.sub.1, b.sub.2 corresponding to symbol S.sub.1 are maintained
together but moved to a different location in the data set. Again,
while FIGS. 6-7 show examples using two bit and three bit,
respectively, other symbol lengths are possible.
[0039] Alternatively, where the processing of the data set
maintained in ping-pong memory 130 converges, the converged data is
written out to one of hard decision memory circuit 170 as a data
set 153. The data set maintained in hard decision memory circuit
170 is provided as a data set 173 to a symbol constrained shuffle
circuit 175. Symbol constrained shuffle circuit 175 operates
similar to the previously described symbol constrained shuffle
circuit 160 to yield a shuffled output 178 to a codeword reorder
circuit 180.
[0040] Data processing circuit 100 allows for performance of a
variable number of local and global iterations through data
detector circuit 105 and non-binary decoder circuit 150 depending
upon the introduced data. A codeword reorder circuit 180 receives
any out of order codewords as data sets 178, and reorders the data
sets prior to providing them as a data output 183.
[0041] Turning to FIG. 2, a format enhanced data detecting circuit
200 is shown in accordance with some embodiments of the present
invention. Format enhanced data detecting circuit 200 may be use in
place of data detector circuit 105 of FIG. 1. Data detecting
circuit 200 receives a data input 287 from a Y-sample buffer (not
shown), a reduced vector 266 from a data decoder circuit (not
shown), and provides a reduced vector 213. In the case where data
detecting circuit 200 is used in place of data detector circuit
105, data input 287 corresponds to data sets 187, reduced vector
266 corresponds to shuffled output 166, and reduced vector 213
corresponds to detected output 113. Format enhanced data detecting
circuit 200 allows for transferring detected outputs and decoded
outputs to/from a data detector circuit in a reduced format that
saves circuit area.
[0042] Reduced vector 266 is provided to a symbol vector
translation circuit 210. Symbol vector translation circuit 210
translates reduced vector 266 into an expanded vector 215. The
format of expanded vector 215 is as follows:
EV.sub.i={L0.sub.i, L1.sub.i, . . . LN.sub.1},
where i indicates the instance of expanded vector 215 (i.e., the
particular data element of a codeword), and L0-LN are soft decision
data corresponding to each possible value of a corresponding
symbol. For example, where two bit symbols are used, there are four
possible values for a symbol (i.e., `00`, `01`, `10`, `11`). In
such a case, expanded vector 215 includes four soft decision values
(L0 corresponding to a likelihood that `00` is the appropriate hard
decision, L1 corresponding to a likelihood that `01` is the
appropriate hard decision, L2 corresponding to a likelihood that
`10` is the appropriate hard decision, and L3 corresponding to a
likelihood that `11` is the appropriate hard decision). Thus,
expanded vector 215 is of the form:
EV.sub.i={L0.sub.i, L1.sub.i, L3.sub.i}.
As another example, where three bit symbols are used, there are
eight possible values for the symbol (i.e., `000`, `001`, `010`,
`011`, `100`, `101`, `110`, `111`). In such a case, expanded vector
215 includes eight soft decision values (L0 corresponding to a
likelihood that `000` is the appropriate hard decision, L1
corresponding to a likelihood that `001` is the appropriate hard
decision, L2 corresponding to a likelihood that `010` is the
appropriate hard decision, L3 corresponding to a likelihood that
`011` is the appropriate hard decision, L4 corresponding to a
likelihood that `100` is the appropriate hard decision, L5
corresponding to a likelihood that `101` is the appropriate hard
decision, L6 corresponding to a likelihood that `110` is the
appropriate hard decision, L7 corresponding to a likelihood that
`111` is the appropriate hard decision). Thus, expanded vector 215
is of the form:
EV.sub.i={L0.sub.i, L1.sub.i, L3.sub.i, L5.sub.i, L6.sub.i,
L7.sub.i}.
[0043] The reduced vector is provided in the following format:
RVi={HD.sub.i, L[A].sub.i, L[B].sub.i, . . . L[N].sub.i),
where i indicates the instance of reduced vector 266 (i.e., the
particular data element of a codeword), and L[A]-L[N] correspond to
soft decision data corresponding to each of the values of the
symbol that were not selected as the hard decision (HD). For
example, where two bit symbols are used, there are four possible
values for a symbol (i.e., `00`, `01`, `10`, `11`). In such a case,
reduced vector 266 includes the hard decision and three soft
decision values. In particular, if HD is `00` then the three soft
decision values corresponding to normalized values of the
likelihood of selecting HD as `01`, `10` and `11`, respectively.
Alternatively, if HD is `01` then the three soft decision values
correspond to normalized values of the likelihood of selecting HD
as `00`, `10` and `11`, respectively; if HD is `10` then the three
soft decision values correspond to normalized values of the
likelihood of selecting HD as `00`, `01` and `11`, respectively;
and if HD is `11` then the three soft decision values correspond to
normalized values of the likelihood of selecting HD as `00`, `10`
and `10`, respectively. Thus, reduced vector 266 is of the
form:
RV.sub.i={HD.sub.i, L[A].sub.i, L[B].sub.i, L[C].sub.i}.
As another example, where three bit symbols are used, there are
eight possible values for the symbol (i.e., `000`, `001`, `010`,
`011`, `100`, `101`, `110`, `111`). In such a case, reduced vector
266 includes the HD and seven soft decision values. In particular,
if HD is `000` then the seven soft decision values correspond to
normalized values of the likelihood of selecting HD as `001`,
`010`, `011`, `100`, `101`, `110` and `111`, respectively.
Alternatively, if HD is `001` then the seven soft decision values
correspond to normalized values of the likelihood of selecting HD
as `000`, `010`, `011`, `100`, `101`, `110` and `111`,
respectively; if HD is `010` then the seven soft decision values
correspond to normalized values of the likelihood of selecting HD
as `000`, `001`, `011`, `100`, `101`, `110` and `111`,
respectively; if HD is `011` then the seven soft decision values
correspond to normalized values of the likelihood of selecting HD
as `000`, `001`, `010`, `100`, `101`, `110` and `111`,
respectively; if HD is `100` then the seven soft decision values
correspond to normalized values of the likelihood of selecting HD
as `000`, `001`, `010`, `011`, `101`, `110` and `111`,
respectively; if HD is `101` then the seven soft decision values
correspond to normalized values of the likelihood of selecting HD
as `000`, `001`, `010`, `011`, `100`, `110` and `111`,
respectively; if HD is `110` then the seven soft decision values
correspond to normalized values of the likelihood of selecting HD
as `000`, `001`, `010`, `011`, `100`, `101` and `111`,
respectively; and if HD is `111` then the seven soft decision
values correspond to normalized values of the likelihood of
selecting HD as `000`, `001`, `010`, `011`, `100`, `101` and `110`,
respectively. Thus, reduced vector 266 is of the form:
RV.sub.i={HD.sub.i, L[A].sub.i, L[B].sub.i, L[C].sub.i, L[D].sub.i,
L[E].sub.i, L[F].sub.i, L[G].sub.i}.
[0044] Symbol vector input translation circuit 210 operates to
recreate the normalized likelihood values expected in expanded
vector 215. Using an example where two bit symbols are represented
by HD, (i.e., where HD, can be one of four symbols), the following
pseudocode represents the recreation of expanded vector 215 from
reduced vector 266 based upon a translation table 300 of FIG.
3:
TABLE-US-00001 IF(HD.sub.i = `00`) { L0.sub.i = 0; L1.sub.i = L[A];
L2.sub.i = L[B]; L3.sub.i = L[C] } ELSE IF(HD.sub.i = `01`) {
L0.sub.i = L[A]; L1.sub.i = 0; L2.sub.i = L[C]; L3.sub.i = L[B] }
ELSE IF(HD.sub.i = `10`) { L0.sub.i = L[B]; L1.sub.i = L[C];
L2.sub.i = 0; L3.sub.i = L[A] } ELSE IF(HD.sub.i = `11`) { L0.sub.i
= L[C]; L1.sub.i = L[B]; L2.sub.i = L[A]; L3.sub.i = 0 }
The resulting expanded vector 215 is then provided as:
EV.sub.i={L0.sub.i, L1.sub.i, L2.sub.i, L3.sub.i}.
[0045] As previously suggested, the process can be expanded to
handle translation of vectors where HD, represents a symbol of
three or more bits.
[0046] Expanded vector 215 and data input 287 are provided to a
data detector core circuit 220. Data detector core circuit 220
applies a data detection algorithm on data input 287 using soft
information (i.e., likelihood data) provided from expanded vector
215. On the first global iteration processing data input 287, the
data for expanded vector 215 is set equal to zero. Data detector
core circuit 220 may apply any data detection algorithm known in
the art that produces branch metric values 223 (i.e.,
BM.sub.0-BM.sub.q). As some examples, data detector core circuit
220 may apply a maximum a posteriori data detection algorithm or a
Viterbi data detection algorithm. Based upon the disclosure
provided herein, one of ordinary skill in the art will recognize a
variety of data detector algorithms known in the art. Branch metric
outputs 223 are provided to a log likelihood calculation circuit
230 that calculates the likelihood of each of branch metric outputs
223 yielding a number of log likelihood ratio values 235. Log
likelihood ratio values 235 correspond to the likelihood that each
of the given branch metric values 223 indicate the correct symbols.
Calculating the log likelihood ratios may be done as is known in
the art. In one particular embodiment of the present invention, the
log likelihood ratio is calculated in accordance with the following
equation:
LLR ( BM ) = Log [ Probability of a Given BM Highest Probability of
any BM ] . ##EQU00001##
[0047] These log likelihood ratio values are combined into expanded
vectors by an extrinsic normalization and format reduction circuit
240 as follows:
EV'.sub.i={L0'.sub.i, L1'.sub.i, . . . LN'.sub.i},
where i indicates the instance of the expanded vector corresponding
to a given symbol, and L0'-LN' correspond to the log likelihood
ratios corresponding to a given symbol. For example, where two bit
symbols are used, there are four possible values for a symbol
(i.e., `00`, `01`, `10`, `11`). In such a case, the expanded vector
includes four soft decision values (L0' corresponding to a
likelihood that `00` is the appropriate hard decision, L1'
corresponding to a likelihood that `01` is the appropriate hard
decision, L2' corresponding to a likelihood that `10` is the
appropriate hard decision, and L3' corresponding to a likelihood
that `11` is the appropriate hard decision). Thus, the expanded
vector is of the form:
EV'.sub.i={L0'.sub.i, L1'.sub.i, L2'.sub.i, L3'.sub.i}.
In this case, one expanded vector is generated for each four log
likelihood ratio values 235.
[0048] As another example, where three bit symbols are used, there
are eight possible values for the symbol (i.e., `000`, `001`,
`010`, `011`, `100`, `101`, `110`, `111`). In such a case, expanded
vector 215 includes eight soft decision values (L0' corresponding
to a likelihood that `000` is the appropriate hard decision, L1'
corresponding to a likelihood that `001` is the appropriate hard
decision, L2' corresponding to a likelihood that `010` is the
appropriate hard decision, L3' corresponding to a likelihood that
`011` is the appropriate hard decision, L4' corresponding to a
likelihood that `100` is the appropriate hard decision, L5'
corresponding to a likelihood that `101` is the appropriate hard
decision, L6' corresponding to a likelihood that `110` is the
appropriate hard decision, L7' corresponding to a likelihood that
`111` is the appropriate hard decision). Thus, the expanded vector
is of the form:
EV'.sub.i={L0'.sub.i, L1'.sub.i, L2'.sub.i, L4'.sub.i, L5'.sub.i,
L6'.sub.i, L7'.sub.i}.
In this case, one expanded vector is generated for each eight log
likelihood ratio values 235.
[0049] In addition, extrinsic normalization and format reduction
circuit 240 subtracts expanded vector 215 from the corresponding
expanded vector generated from the log likelihood data 235 from log
likelihood calculation circuit in accordance with the following
equations:
Subtracted EV.sub.i (SEV)=EV-EV.sub.i={L0'.sub.i-L0.sub.i,
L1'.sub.i-L1.sub.i, . . . LN'.sub.i-LN.sub.i}.
For convenience, the subtracted values are indicated by double
primes as follows:
L0''.sub.i-L0'.sub.i-L0.sub.i;
L1''.sub.i-L1'.sub.i-L1.sub.i;
L2''.sub.i=L2'.sub.i-L2.sub.i'; and
L3''.sub.i=L3'.sub.i-L.sub.3.sub.i.
[0050] Extrinsic normalization and format reduction circuit 240
then normalizes the subtracted, expanded vector outputs by
subtracting the maximum L value from all of the L values as shown
in the following equation:
Normalized EV.sub.i(NEV)={L0''.sub.i-L''max, L1''.sub.i-L''max, . .
. LN''.sub.i-L'max}.
Thus, the L value corresponding to the maximum log likelihood ratio
becomes zero, and all of the other values are normalized to the
maximum L value. For example, where L0'' is the maximum L value, it
is subtracted from all other L values (e.g., L1' . . . LN'). Thus,
the value in the L0'' position is zero, and all others are
normalized to the maximum.
[0051] The instances of normalized expanded vector (NEV) are then
converted to the reduced vector format. The format conversion to
the reduced format conversion includes providing a hard decision
output corresponding to the maximum L value, and including the
normalized and subtracted L values other than the maximum L value.
Thus, for example, where two bit symbols are used, there are four
possible values for a symbol (i.e., `00`, `01`, `10`, `11`). In
such a case, the normalized/subtracted expanded vector is
represented as:
NEV={L0''.sub.i-L''max, L1''.sub.i-L''max, L2''.sub.i-L''max,
L3''.sub.i-L''max,}.
This normalized/subtracted expanded vector is converted to the
reduced vector format represented as:
RV.sub.i{HD.sub.i, L[A].sub.i, L[B].sub.i, L[C].sub.i}.
where HD.sub.i is the symbol corresponding to the maximum L value
[i.e., the maximum of (L0''.sub.i-L0.sub.i), (L1''.sub.i-L1.sub.i),
(L2''.sub.i-L2.sub.i) or (L3''.sub.i-L3.sub.i)]; and L[A], L[B],
L[C] correspond to a respective one of the non-maximum values of
(L0''.sub.i-L0.sub.i), (L1''.sub.i-L1.sub.i), (L2''.sub.i-L2.sub.i)
or (L3''.sub.i-L3.sub.i). In particular, the value of A in L[A],
the value of B in L[B] and the value of C in L[C] are calculated as
a bitwise XOR with HD, in accordance with the following pseudocode
that relies on the row and column information of a translation
table 300 of FIG. 3:
TABLE-US-00002 IF(HD.sub.i = `00`) { A = HD.sub.i XOR `01`; /*
i.e., (L1``.sub.i- L1.sub.i) is included as L[A] */ B = HD.sub.i
XOR `10`; /* i.e., (L2``.sub.i- L2.sub.i) is included as L[B] */ C
= HD.sub.i XOR `11` /* i.e., (L3``.sub.i- L3.sub.i) is included as
L[C] */ } ELSE IF(HD.sub.i = `01`) { A = HD.sub.i XOR `01`; /*
i.e., (L0``.sub.i- L0.sub.i) is included as L[A] */ B = HD.sub.i
XOR `10`; /* i.e., (L3``.sub.i- L3.sub.i) is included as L[B] */ C
= HD.sub.i XOR `11` /* i.e., (L2``.sub.i- L2.sub.i) is included as
L[C] */ } ELSE IF(HD.sub.i = `10`) { A = HD.sub.i XOR `01`; /*
i.e., (L3``.sub.i- L3.sub.i) is included as L[A] */ B = HD.sub.i
XOR `10`; /* i.e., (L0``.sub.i- L0.sub.i) is included as L[B] */ C
= HD.sub.i XOR `11` /* i.e., (L1``.sub.i- L1.sub.i) is included as
L[C] */ } ELSE IF(HD.sub.i = `11`) { A = HD.sub.i XOR `01`; /*
i.e., (L2``.sub.i- L2.sub.i) is included as L[A] */ B = HD.sub.i
XOR `10`; /* i.e., (L1``.sub.i- L1.sub.i) is included as L[B] */ C
= HD.sub.i XOR `11` /* i.e., (L0``.sub.i- L0.sub.i) is included as
L[C] */ }
This approach can be expanded to handle symbols of three or more
bits.
[0052] The resulting reduced vectors are provided as reduced vector
outputs 213. Where two bit symbols are employed, one reduced vector
is created for each four log likelihood ratio values 235. Where
three bit symbols are employed, one reduced vector is created for
each eight log likelihood ratio values 235. These reduced vectors
may be provided, for example, to a downstream data decoder circuit
(not shown).
[0053] Turning to FIG. 4 a flow diagram 400 shows a reduced format
to expanded format translation process in accordance with one or
more embodiments of the present invention. Following flow diagram
400, a reduced vector is received (block 405). Where two bit
symbols are represented there are four possible values for the
symbol (i.e., `00`, `01`, `10`, `11`), and the reduced vector is in
the form of RV.sub.i={HD.sub.i, L[A].sub.i, L[B].sub.i,
L[C].sub.i}, where HD.sub.i represents the two bit symbol
corresponding to the highest log likelihood ratio (i.e., L value),
and L[A].sub.i, L[B].sub.i and L[C].sub.i correspond to the log
likelihood ratios (i.e., soft decision data) for the three values
of the two bit symbol that were not selected as HD.sub.i. The
reduced vector may be received, for example, from a data decoder
circuit, a memory, or a de-shuffling circuit as were more fully
discussed above in relation to FIG. 1. It should be noted that
while flow diagram 400 is described with reference to two bit
symbols that the same process can be expanded for use in relation
to symbols of three or more bits.
[0054] The hard decision (i.e., HD.sub.i) and log likelihood
information (i.e., L[A].sub.i, L[B].sub.i, L[C].sub.i) from the
reduced vector are segregated for use in conversion to an expanded
vector (block 410). It is determined whether the hard decision is
`00` (block 415). Where the hard decision is `00` (block 415), the
values of L0.sub.i, L1.sub.i, L2.sub.i, L3.sub.i are assigned
values as follow:
L0.sub.1=0;
L1.sub.i=L[A].sub.i;
L2.sub.i=L[B].sub.i; and
L3.sub.i=L[C].sub.i
(block 420). Otherwise, where the hard decision is not `00` (block
415), it is determined whether the hard decision is `01` (block
425). Where the hard decision is `01` (block 425), the values of
L0.sub.i, L1.sub.i, L2.sub.i, L3.sub.i are assigned values as
follow:
L0.sub.i=L[A].sub.i;
L1.sub.i=0;
L2.sub.i=L[C].sub.i; and
L3.sub.i=L[B].sub.i
(block 430). Otherwise, where the hard decision is not `01` (block
425), it is determined whether the hard decision is `10` (block
435). Where the hard decision is `10` (block 435), the values of
L0.sub.i, L1.sub.i, L2.sub.i, L3.sub.i are assigned values as
follow:
L0.sub.i=L[B].sub.i;
L1.sub.i=L[C];
L2.sub.i=0; and
L3.sub.i=L[A].sub.i
(block 440). Otherwise, where the hard decision is not `10` (block
435), the values of L0.sub.i, L1.sub.i, L2.sub.i, L3.sub.i are
assigned values as follow:
L0.sub.i=L[C].sub.i;
L1.sub.i=L[B];
L2.sub.i=L[A]; and
L3.sub.i=0
(block 450). These assigned values are assembled into an expanded
vector with the format:
{L0.sub.i, L1.sub.i, L.sub.2.sub.i, L3.sub.i}.
[0055] Turning to FIG. 5a, a flow diagram 500 shows a process of
performing data detection based on reduced format vectors in
accordance with one or more embodiments of the present invention.
Following flow diagram 500, a data input is received (block 505).
The data input includes a series of bits that represent a
corresponding series of symbols. The symbols may include two or
more bits depending upon the particular implementation. Thus, while
flow diagram 500 is described with reference to two bit symbols
that the same process can be expanded for use in relation to
symbols of three or more bits. In addition, an expanded vector is
received (block 510). The expanded vector is in the form of
{L0.sub.i, L1.sub.i, L2.sub.i, L3.sub.i}, and includes soft
decision data corresponding to the data input that was derived, for
example, from a previous data decoding process. The received data
is correlated with the expanded vector (block 515). This includes
correlating the soft decision information in the expanded vector
with corresponding symbols in the received data.
[0056] A data detection algorithm is then applied to the received
data using the soft decision in the expanded vector to guide or
influence the data detection process (block 520). This data
detection process may be any data detection process known in the
art that is capable of being guided by previously developed soft
decision information. As some examples, the data detection process
may be a Viterbi algorithm data detection or a maximum a posteriori
data detection. Based upon the disclosure provided herein, one of
ordinary skill in the art will recognize a variety of data
detection processes that may be used in relation to different
embodiments of the present invention. The data detection process
yields a number of log likelihood outputs indicating the likelihood
of particular values for each symbol.
[0057] The log likelihood outputs corresponding to each symbol are
assembled together into expanded vectors (block 525). For example,
where two bit symbols are used, four log likelihood outputs
corresponding to the four possible values of the two bit symbol are
gathered together into an expanded vector with the format
{L0'.sub.i, L1'.sub.i, L2'.sub.i, L3'.sub.i}. As another example,
where three bit symbols are used, eight log likelihood outputs
corresponding to the eight possible values of the two bit symbol
are gathered together into an expanded vector with the format
{L0'.sub.i, L1'.sub.i, L2'.sub.i, L3'.sub.i, L4'.sub.i, L5'.sub.i,
L6'.sub.i, L7'.sub.i}. The expanded vector originally received is
subtracted from the expanded vector generated as part of the data
detection process (block 530). Using the two bit symbol example,
the subtraction is performed in accordance with the following
equation:
SEV={(L0'.sub.i-L0.sub.i), (L1.sub.i-L1.sub.i),
(L2'.sub.i-L2.sub.i), (L3'.sub.i-L3.sub.i)},
where SEV stands for subtracted, expanded vector. The resulting
subtracted values may be represented by the following symbols for
simplicity:
L0''.sub.i=(L0'.sub.i-L0.sub.i);
L1''.sub.i=(L1'.sub.i-L1.sub.i);
L2''.sub.i=(L2'.sub.i-L2.sub.i); and
L3''.sub.i=(L3'.sub.i-L3.sub.i).
The highest of L0''.sub.i, L1''.sub.i, L2''.sub.i, and L3''.sub.i,
is identified and the remaining likelihood values are normalized to
this identified value to yield normalized vectors (block 535). The
normalization is done by subtracting the identified highest value
from each of the other values in accordance with the following
equation:
Normalized EV.sub.i(NEV)={L''.sub.i-L''max, L1''.sub.i-L''max,
L2''.sub.i-L''max, L3''.sub.i-L''max},
where NEV stands for normalized, expanded vector. Then, the
normalized, expanded vector is converted from the expanded vector
format into a reduced vector format (block 540).
[0058] Turning to FIG. 5b, a flow diagram 501 shows a method for
converting from the expanded format to the reduced format in
accordance with one or more embodiments of the present invention.
Following flow diagram 501, the symbol corresponding to the highest
likelihood in the normalized, expanded vector is selected as the
hard decision (HD,) (block 506). For example, where two bit symbols
are used having four possible symbol values (i.e., `00`, `01`,
`10`, `11`) and the likelihood that has the highest value is
L0''.sub.i, the `00` symbol is selected as the hard decision; where
the likelihood that has the highest value is L1''.sub.i, the `01`
symbol is selected as the hard decision; where the likelihood that
has the highest value is L2''.sub.i, the `10` symbol is selected as
the hard decision; and where the likelihood that has the highest
value is L3''.sub.i, the `11` symbol is selected as the hard
decision.
[0059] It is determined whether HD.sub.i is `00` (block 511). Where
HD.sub.i is `00` (block 511), the values of L[A], L[B], L[C] are
assigned values as follow:
L[A].sub.i=L1''.sub.i-L''max;
L[B].sub.i=L2'.sub.i-L'max; and
L[C].sub.i=L3''.sub.i-L''max
(block 516). Otherwise, it is determined whether HD.sub.i is `01`
(block 521). Where HD.sub.i is `01` (block 521), the values of
L[A], L[B], L[C] are assigned values as follow:
L[A].sub.i=L0''.sub.i-L''max;
L[B].sub.i=L3'.sub.i-L'max; and
L[C].sub.i=L2''.sub.i-L''max
(block 526). Otherwise, it is determined whether HD.sub.i is `10`
(block 531). Where HD.sub.i is `10` (block 531), the values of
L[A], L[B], L[C] are assigned values as follow:
L[A].sub.i=L3''.sub.i-L''max;
L[B].sub.i=L0'.sub.i-L'max; and
L[C].sub.i=L1''.sub.i-L''max
(block 536). Otherwise, HD.sub.i is `11` and the values of L[A],
L[B], L[C] are assigned values as follow:
L[A].sub.i=L2''.sub.i-L''max;
L[B].sub.i=L1'.sub.i-L'max; and
L[C].sub.i=L0''.sub.i-L''max
(block 541). With the aforementioned values set, the values are
assembled into a reduced vector with the format :
{HD.sub.i, L[A].sub.i, L[B].sub.i, L[C].sub.i}
(block 546).
[0060] Turning to FIG. 8, a flow diagram 800 shows a method in
accordance with some embodiments of the present invention for
performing symbol constrained de-shuffling. Following flow diagram
800, a shuffled input is received (block 805). The shuffled input
may be similar to that described above in relation to shuffled data
set 620 of FIG. 6. The data set may have been shuffled after
encoding and prior to transfer via, for example, a storage medium
or a wireless transfer medium. Alternatively, the shuffled data set
may have been shuffled after being processed by a data decoder
circuit.
[0061] The sets of bits corresponding to symbols are identified
(block 810). Using graphic 600 as an example, the bit pairs in
shuffled data set 620 (i.e., b.sub.0 and b.sub.1, b.sub.2 and
b.sub.3, b.sub.4 and b.sub.5, b.sub.n-3 and b.sub.n-2, and
b.sub.n-1 and b.sub.n) are identified as respective inseparable
symbols (S.sub.0, S.sub.1, S.sub.2, S.sub.n-1, and S.sub.n). An
initial one of the identified symbols is selected (block 815). This
selected symbol is then moved to another location in a de-shuffled
codeword in accordance with a de-shuffle algorithm (block 820). The
de-shuffle algorithm may be a map that reverses the location of a
symbol that was applied during a preceding shuffle process. It is
determined whether the last symbol in the shuffled input has been
processed (block 825). Where it is not the last symbol (block 825),
the next symbol in the shuffled input is selected for processing
(block 830), and the processes of blocks 820-825 are repeated for
the next symbol. Alternatively, where it is the last symbol (block
825), the resulting de-shuffled codeword is provided (block 835).
This de-shuffled codeword may be provided, for example, to a
downstream data decoder circuit.
[0062] Turning to FIG. 9, a flow diagram 900 shows a method in
accordance with some embodiments of the present invention for
performing symbol constrained shuffling. Following flow diagram
900, a de-shuffled input is received (block 905). The de-shuffled
input may be similar to that described above in relation to
de-shuffled data set 610 of FIG. 6. The data set may have been
de-shuffled prior to providing it to a data decoder circuit.
[0063] The sets of bits corresponding to symbols are identified
(block 910). Using graphic 600 as an example, the bit pairs in
de-shuffled data set 610 (i.e., b.sub.0 and b.sub.1, b.sub.2 and
b.sub.3, b.sub.4 and b.sub.5, b.sub.n-3 and b.sub.n-2, and
b.sub.n-1 and b.sub.n) are identified as respective inseparable
symbols (S.sub.0, S.sub.1, S.sub.2, S.sub.n-1, and S.sub.n). An
initial one of the identified symbols is selected (block 915). This
selected symbol is then moved to another location in a shuffled
codeword in accordance with a shuffle algorithm (block 920). The
shuffle algorithm may be a map that sets forth a location of a
symbol within a shuffled codeword. The shuffle algorithm is the
reverse of the de-shuffle algorithm. It is determined whether the
last symbol in the de-shuffled input has been processed (block
925). Where it is not the last symbol (block 925), the next symbol
in the de-shuffled input is selected for processing (block 930),
and the processes of blocks 920-925 are repeated for the next
symbol. Alternatively, where it is the last symbol (block 925), the
resulting shuffled codeword is provided (block 935). This shuffled
codeword may be provided, for example, to a data detector
circuit.
[0064] Turning to FIG. 10, a storage system 1000 including a read
channel circuit 1010 with a symbol based data processing circuit in
accordance with various embodiments of the present invention.
Storage system 1000 may be, for example, a hard disk drive. Storage
system 1000 also includes a preamplifier 1070, an interface
controller 1020, a hard disk controller 1066, a motor controller
1068, a spindle motor 1072, a disk platter 1078, and a read/write
head 1076. Interface controller 1020 controls addressing and timing
of data to/from disk platter 1078. The data on disk platter 1078
consists of groups of magnetic signals that may be detected by
read/write head assembly 1076 when the assembly is properly
positioned over disk platter 1078. In one embodiment, disk platter
1078 includes magnetic signals recorded in accordance with either a
longitudinal or a perpendicular recording scheme.
[0065] In a typical read operation, read/write head assembly 1076
is accurately positioned by motor controller 1068 over a desired
data track on disk platter 1078. Motor controller 1068 both
positions read/write head assembly 1076 in relation to disk platter
1078 and drives spindle motor 1072 by moving read/write head
assembly to the proper data track on disk platter 1078 under the
direction of hard disk controller 1066. Spindle motor 1072 spins
disk platter 1078 at a determined spin rate (RPMs). Once read/write
head assembly 1078 is positioned adjacent the proper data track,
magnetic signals representing data on disk platter 1078 are sensed
by read/write head assembly 1076 as disk platter 1078 is rotated by
spindle motor 1072. The sensed magnetic signals are provided as a
continuous, minute analog signal representative of the magnetic
data on disk platter 1078. This minute analog signal is transferred
from read/write head assembly 1076 to read channel 1010 via
preamplifier 1070. Preamplifier 1070 is operable to amplify the
minute analog signals accessed from disk platter 1078. In turn,
read channel circuit 1010 decodes and digitizes the received analog
signal to recreate the information originally written to disk
platter 1078. This data is provided as read data 1003 to a
receiving circuit. As part of processing the received information,
read channel circuit 1010 performs a symbol based data processing.
Such a symbol based data processing may utilize a format enhanced
detecting circuit such as that described above in relation to FIG.
2, and/or may operate similar to that described above in relation
to FIGS. 3-5. Alternatively, or in addition, read channel circuit
1010 may perform a symbol based internal data decoding such as that
described in relation to FIG. 1 above, and/or may operate similar
to that described in relation to FIGS. 6-9 above. A write operation
is substantially the opposite of the preceding read operation with
write data 1001 being provided to read channel circuit 1010. This
data is then encoded and written to disk platter 1078.
[0066] It should be noted that storage system 1000 may be
integrated into a larger storage system such as, for example, a
RAID (redundant array of inexpensive disks or redundant array of
independent disks) based storage system. It should also be noted
that various functions or blocks of storage system 1000 may be
implemented in either software or firmware, while other functions
or blocks are implemented in hardware.
[0067] Turning to FIG. 11, a data transmission system 1100
including a receiver 1195 with a symbol based data processing
circuit is shown in accordance with different embodiments of the
present invention. Data transmission system 1100 includes a
transmitter 1193 that is operable to transmit encoded information
via a transfer medium 1197 as is known in the art. The encoded data
is received from transfer medium 1197 by receiver 1195. Receiver
1195 incorporates the a symbol based data processing circuit. Such
an optimized a symbol based data processing circuit may utilize a
format enhanced data detecting circuit such as that described above
in relation to FIG. 2, and/or may operate similar to that described
above in relation to FIGS. 3-5. Alternatively, or in addition, read
channel circuit 1010 may perform a symbol based internal data
decoding such as that described in relation to FIG. 1 above, and/or
may operate similar to that described in relation to FIGS. 6-9
above.
[0068] It should be noted that the various blocks discussed in the
above application may be implemented in integrated circuits along
with other functionality. Such integrated circuits may include all
of the functions of a given block, system or circuit, or only a
subset of the block, system or circuit. Further, elements of the
blocks, systems or circuits may be implemented across multiple
integrated circuits. Such integrated circuits may be any type of
integrated circuit known in the art including, but are not limited
to, a monolithic integrated circuit, a flip chip integrated
circuit, a multichip module integrated circuit, and/or a mixed
signal integrated circuit. It should also be noted that various
functions of the blocks, systems or circuits discussed herein may
be implemented in either software or firmware. In some such cases,
the entire system, block or circuit may be implemented using its
software or firmware equivalent. In other cases, the one part of a
given system, block or circuit may be implemented in software or
firmware, while other parts are implemented in hardware.
[0069] In conclusion, the invention provides novel systems,
devices, methods and arrangements for performing data processing.
While detailed descriptions of one or more embodiments of the
invention have been given above, various alternatives,
modifications, and equivalents will be apparent to those skilled in
the art without varying from the spirit of the invention. For
example, one or more embodiments of the present invention may be
applied to various data storage systems and digital communication
systems, such as, for example, tape recording systems, optical disk
drives, wireless systems, and digital subscriber line systems.
Therefore, the above description should not be taken as limiting
the scope of the invention, which is defined by the appended
claims.
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