U.S. patent application number 13/531237 was filed with the patent office on 2012-12-27 for multilayer ceramic capacitor.
This patent application is currently assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD.. Invention is credited to Young Ghyu AHN, Byoung Hwa Lee, Dong Seok Park, Min Cheol Park, Sang Soo Park.
Application Number | 20120327556 13/531237 |
Document ID | / |
Family ID | 47361634 |
Filed Date | 2012-12-27 |
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United States Patent
Application |
20120327556 |
Kind Code |
A1 |
AHN; Young Ghyu ; et
al. |
December 27, 2012 |
MULTILAYER CERAMIC CAPACITOR
Abstract
There is provided a multilayer ceramic capacitor, including: a
multilayer body in which a plurality of dielectric layers are
stacked in a thickness direction; and inner electrode layers formed
within the multilayer body and including first and second inner
electrodes disposed to be opposed to each other; wherein a ratio
(MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1
represents an area of the multilayer body in a cross section of the
multilayer body taken in a length and thickness direction, and MA1
represents an area of a first margin part in the cross section of
the multilayer body taken in the length and thickness direction,
the first margin part being a portion of the multilayer body, other
than a first capacitance forming part thereof in which the first
and second inner electrodes overlap in the thickness direction.
Inventors: |
AHN; Young Ghyu; (Yongin,
KR) ; Lee; Byoung Hwa; (Seongnam, KR) ; Park;
Min Cheol; (Gwangmyeong, KR) ; Park; Sang Soo;
(Suwon, KR) ; Park; Dong Seok; (Seoul,
KR) |
Assignee: |
SAMSUNG ELECTRO-MECHANICS CO.,
LTD.
|
Family ID: |
47361634 |
Appl. No.: |
13/531237 |
Filed: |
June 22, 2012 |
Current U.S.
Class: |
361/321.2 |
Current CPC
Class: |
H01G 4/12 20130101; H01G
4/30 20130101; H01G 4/012 20130101 |
Class at
Publication: |
361/321.2 |
International
Class: |
H01G 4/12 20060101
H01G004/12 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 23, 2011 |
KR |
10-2011-0061343 |
Claims
1. A multilayer ceramic capacitor, comprising: a multilayer body in
which a plurality of dielectric layers are stacked in a thickness
direction; and inner electrode layers formed within the multilayer
body and including first and second inner electrodes disposed to be
opposed to each other while having each dielectric layer disposed
therebetween and having respective ends alternately exposed to
sides of the multilayer body, opposing each other; wherein a ratio
(MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1
represents an area of the multilayer body in a cross section of the
multilayer body taken in a length and thickness direction, and MA1
represents an area of a first margin part in the cross section of
the multilayer body taken in the length and thickness direction,
the first margin part being a portion of the multilayer body, other
than a first capacitance forming part thereof in which the first
and second inner electrodes overlap in the thickness direction in
the cross section of the multilayer body taken in the length and
thickness direction.
2. The multilayer ceramic capacitor of claim 1, wherein a ratio
(C1/A1) of C1 to A1 is between 0.35 and 2.0, wherein A1 represents
an area of a first length margin part in the cross section of the
multilayer body taken in the length and thickness direction, the
first length margin part being a portion of the first margin part
extending from the first capacitance forming part in a length
direction, and C1 represents an area of a first thickness margin
part in the cross section of the multilayer body taken in the
length and thickness direction, the first thickness margin part
being a portion of the first margin part extending from the first
capacitance forming part in a thickness direction in the cross
section of the multilayer body taken in the length and thickness
direction.
3. The multilayer ceramic capacitor of claim 1, wherein a ratio
(MA2/CA2) of MA2 to CA2 is between 0.10 and 0.28, wherein CA2
represents an area of the multilayer body in a cross section of the
multilayer body taken in a width and thickness direction, and MA2
represents an area of a second margin part in the cross section of
the multilayer body taken in the width and thickness direction, the
second margin part being a portion of the multilayer body, other
than a second capacitance forming part thereof in which the first
and second inner electrodes overlap in the thickness direction in
the cross section of the multilayer body taken in the width and
thickness direction.
4. The multilayer ceramic capacitor of claim 3, wherein a ratio
(C2/B1) of C2 to B1 is between 0.30 and 1.35, wherein B1 represents
an area of a first width margin part in the cross section of the
multilayer body taken in the width and thickness direction, the
first width margin part being a portion of the second margin part
extending from the second capacitance forming part in a width
direction in the cross section of the multilayer body taken in the
width and thickness direction, and C2 represents an area of a
second thickness margin part in the cross section of the multilayer
body taken in the width and thickness direction, the second
thickness margin part being a portion of the second margin part
extending from the second capacitance forming part in a thickness
direction in the cross section of the multilayer body taken in the
width and thickness direction.
5. The multilayer ceramic capacitor of claim 1, wherein a thickness
of the dielectric layer is 3 .mu.m or less.
6. The multilayer ceramic capacitor of claim 1, wherein an average
particle diameter of ceramic powder particles used for the
dielectric layer is 0.3 .mu.m or less.
7. A multilayer ceramic capacitor, comprising: a multilayer body in
which a plurality of dielectric layers are stacked in a thickness
direction; and inner electrode layers formed within the multilayer
body and including first and second inner electrodes disposed to be
opposed to each other while having each dielectric layer disposed
therebetween and having respective ends alternately exposed to
sides of the multilayer body, opposing each other; wherein a ratio
(MA2/CA2) of MA2 to CA2 is between 0.10 and 0.28, wherein CA2
represents an area of the multilayer body in a cross section of the
multilayer body taken in a width and thickness direction, and MA2
represents an area of a second margin part in the cross section of
the multilayer body taken in the width and thickness direction, the
second margin part being a portion of the multilayer body, other
than a second capacitance forming part in which the first and
second inner electrodes overlap in the thickness direction in the
cross section of the multilayer body taken in the width and
thickness direction.
8. The multilayer ceramic capacitor of claim 7, wherein a ratio
(C2/B1) of C2 to B1 is between 0.30 and 1.35, wherein B1 represents
an area of a first width margin part in the cross section of the
multilayer body taken in the width and thickness direction, the
first width margin part being a portion of the second margin part
extending from the second capacitance forming part in a width
direction in the cross section of the multilayer body taken in the
width and thickness direction, and C2 represents an area of a
second thickness margin part in the cross section of the multilayer
body taken in the width and thickness direction, the second
thickness margin part being a portion of the second margin part
extending from the second capacitance forming part in a thickness
direction in the cross section of the multilayer body taken in the
width and thickness direction.
9. The multilayer ceramic capacitor of claim 7, wherein a thickness
of the dielectric layer is 3 .mu.m or less.
10. The multilayer ceramic capacitor of claim 7, wherein an average
particle diameter of ceramic powder particles used for the
dielectric layer is 0.3 .mu.m or less.
11. A multilayer ceramic capacitor, comprising: a multilayer body
including a dielectric layer having a thickness of 3 .mu.m or less;
and first and second inner electrodes having the dielectric layer
disposed therebetween, wherein the number of grains disposed
between the first and second inner electrodes is 10 or more in a
thickness direction of the dielectric layer, and a ratio (MA1/CA1)
of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an
area of the multilayer body in a cross section of the multilayer
body taken in a length and thickness direction, and MA1 represents
an area of a first margin part in the cross section of the
multilayer body taken in the length and thickness direction, the
first margin part being a portion of the multilayer body, other
than a first capacitance forming part thereof in which the first
and second inner electrodes overlap in the thickness direction in
the cross section of the multilayer body taken in the length and
thickness direction.
12. The multilayer ceramic capacitor of claim 11, wherein a ratio
(C1/A1) of C1 to A1 is between 0.35 and 2.0, wherein A1 represents
an area of a first length margin part in the cross section of the
multilayer body taken in the length and thickness direction, the
first length margin part being a portion of the first margin part
extending from the first capacitance forming part in a length
direction, and C1 represents an area of a first thickness margin
part in the cross section of the multilayer body taken in the
length and thickness direction, the first thickness margin part
being a portion of the first margin part extending from the first
capacitance forming part in a thickness direction in the cross
section of the multilayer body taken in the length and thickness
direction.
13. The multilayer ceramic capacitor of claim 11, wherein a ratio
(MA2/CA2) of MA2 to CA2 is between 0.10 and 0.28, wherein CA2
represents an area of the multilayer body in a cross section of the
multilayer body taken in a width and thickness direction, and MA2
represents an area of a second margin part in the cross section of
the multilayer body taken in the width and thickness direction, the
second margin part being a portion of the multilayer body, other
than a second capacitance forming part thereof in which the first
and second inner electrodes overlap in the thickness direction in
the cross section of the multilayer body taken in the width and
thickness direction.
14. The multilayer ceramic capacitor of claim 13, wherein a ratio
(C2/B1) of C2 to B1 is between 0.30 and 1.35, wherein B1 represents
an area of a first width margin part in the cross section of the
multilayer body taken in the width and thickness direction, the
first width margin part being a portion of the second margin part
extending from the second capacitance forming part in a width
direction in the cross section of the multilayer body taken in the
width and thickness direction, and C2 represents an area of a
second thickness margin part in the cross section of the multilayer
body taken in the width and thickness direction, the second
thickness margin part being a portion of the second margin part
extending from the second capacitance forming part in a thickness
direction in the cross section of the multilayer body taken in the
width and thickness direction.
15. A multilayer ceramic capacitor, comprising: a multilayer body
including a dielectric layer having a thickness of 3 .mu.m or less;
and first and second inner electrodes having the dielectric layer
disposed therebetween, wherein the number of grains disposed
between the first and second inner electrodes is 10 or more in a
thickness direction of the dielectric layer, and a ratio (MA2/CA2)
of MA2 to CA2 is between 0.10 and 0.28, wherein CA2 represents an
area of the multilayer body in a cross section of the multilayer
body taken in a width and thickness direction, and MA2 represents
an area of a second margin part in the cross section of the
multilayer body taken in the width and thickness direction, the
second margin part being a portion of the multilayer body, other
than a second capacitance forming part thereof in which the first
and second inner electrodes overlap in the thickness direction in
the cross section of the multilayer body taken in the width and
thickness direction.
16. The multilayer ceramic capacitor of claim 15, wherein a ratio
(C2/B1) of C2 to B1 is between 0.30 and 1.35, wherein B1 represents
an area of a first width margin part in the cross section of the
multilayer body taken in the width and thickness direction, the
first width margin part being a portion of the second margin part
extending from the second capacitance forming part in a width
direction in the cross section of the multilayer body taken in the
width and thickness direction, and C2 represents an area of a
second thickness margin part in the cross section of the multilayer
body taken in the width and thickness direction, the second
thickness margin part being a portion of the second margin part
extending from the second capacitance forming part in a thickness
direction in the cross section of the multilayer body taken in the
width and thickness direction.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the priority of Korean Patent
Application No. 10-2011-0061343 filed on Jun. 23, 2011, in the
Korean Intellectual Property Office, the disclosure of which is
incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a multilayer ceramic
capacitor, and more particularly, to a multilayer ceramic capacitor
capable of reducing acoustic noise and implementing high
capacitance while suppressing generation of delamination.
[0004] 2. Description of the Related Art
[0005] Generally, electronic components using a ceramic material,
such as a capacitor, an inductor, a piezoelectric element, a
varistor, or a thermistor, or the like, include a ceramic body made
of a ceramic material, inner electrodes formed within the ceramic
body, and outer electrodes mounted on a surface of the ceramic body
so to be connected to the inner electrodes.
[0006] Among ceramic electronic components, a multilayer ceramic
capacitor has been widely used as a component for mobile
communication devices, such as computers, PDAs, mobile phones, or
the like, due to advantages such as miniaturization, high
capacitance, ease of mounting, or the like.
[0007] Recently, with the recent trend toward an increase in small
multi-functional electronics, demand for small multi-functional
multilayer ceramic capacitors has also increased. Asa result, a
multilayer ceramic capacitor in which the thickness of a dielectric
layer is reduced and the number of multilayered layers thereof is
increased has recently been manufactured.
[0008] However, acoustic noise generated due to a piezoelectric
phenomenon of the multilayer ceramic capacitor using a
ferroelectric material may cause serious defects in some electronic
devices.
[0009] Acoustic noise may be a factor in noise generation in
electronic devices equipped with the multilayer ceramic
capacitor.
SUMMARY OF THE INVENTION
[0010] An aspect of the present invention provides a small-sized
and high-capacitance multilayer ceramic capacitor having high
reliability and reduced acoustic noise while suppressing a
generation of delaminations.
[0011] According to an embodiment of the present invention, there
is provided a multilayer ceramic capacitor, including: a multilayer
body in which a plurality of dielectric layers are stacked in a
thickness direction; and inner electrode layers formed within the
multilayer body and including first and second inner electrodes
disposed to be opposed to each other while having each dielectric
layer disposed therebetween and having respective ends alternately
exposed to sides of the multilayer body, opposing each other;
wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20,
wherein CA1 represents an area of the multilayer body in a cross
section of the multilayer body taken in a length and thickness
direction, and MA1 represents an area of a first margin part in the
cross section of the multilayer body taken in the length and
thickness direction, the first margin part being a portion of the
multilayer body, other than a first capacitance forming part
thereof in which the first and second inner electrodes overlap in
the thickness direction in the cross section of the multilayer body
taken in the length and thickness direction.
[0012] A ratio (C1/A1) of C1 to A1 may be between 0.35 and 2.0,
wherein A1 represents an area of a first length margin part in the
cross section of the multilayer body taken in the length and
thickness direction, the first length margin part being a portion
of the first margin part extending from the first capacitance
forming part in a length direction, and C1 represents an area of a
first thickness margin part in the cross section of the multilayer
body taken in the length and thickness direction, the first
thickness margin part being a portion of the first margin part
extending from the first capacitance forming part in a thickness
direction in the cross section of the multilayer body taken in the
length and thickness direction.
[0013] A ratio (MA2/CA2) of MA2 to CA2 may be between 0.10 and
0.28, wherein CA2 represents an area of the multilayer body in a
cross section of the multilayer body taken in a width and thickness
direction, and MA2 represents an area of a second margin part in
the cross section of the multilayer body taken in the width and
thickness direction, the second margin part being a portion of the
multilayer body, other than a second capacitance forming part
thereof in which the first and second inner electrodes overlap in
the thickness direction in the cross section of the multilayer body
taken in the width and thickness direction.
[0014] A ratio (C2/B1) of C2 to B1 may be between 0.30 and 1.35,
wherein B1 represents an area of a first width margin part in the
cross section of the multilayer body taken in the width and
thickness direction, the first width margin part being a portion of
the second margin part extending from the second capacitance
forming part in a width direction in the cross section of the
multilayer body taken in the width and thickness direction, and C2
represents an area of a second thickness margin part in the cross
section of the multilayer body taken in the width and thickness
direction, the second thickness margin part being a portion of the
second margin part extending from the second capacitance forming
part in a thickness direction in the cross section of the
multilayer body taken in the width and thickness direction.
[0015] A thickness of the dielectric layer may be 3 .mu.m or
less.
[0016] An average particle diameter of ceramic powder particles
used for the dielectric layer may be 0.3 .mu.m or less.
[0017] According to another embodiment of the present invention,
there is provided a multilayer ceramic capacitor, including: a
multilayer body in which a plurality of dielectric layers are
stacked in a thickness direction; and inner electrode layers formed
within the multilayer body and including first and second inner
electrodes disposed to be opposed to each other while having each
dielectric layer disposed therebetween and having respective ends
alternately exposed to sides of the multilayer body, opposing each
other; wherein a ratio (MA2/CA2) of MA2 to CA2 is between 0.10 and
0.28, wherein CA2 represents an area of the multilayer body in a
cross section of the multilayer body taken in a width and thickness
direction, and MA2 represents an area of a second margin part in
the cross section of the multilayer body taken in the width and
thickness direction, the second margin part being a portion of the
multilayer body, other than a second capacitance forming part in
which the first and second inner electrodes overlap in the
thickness direction in the cross section of the multilayer body
taken in the width and thickness direction.
[0018] A ratio (C2/B1) of C2 to B1 may be between 0.30 and 1.35,
wherein B1 represents an area of a first width margin part in the
cross section of the multilayer body taken in the width and
thickness direction, the first width margin part being a portion of
the second margin part extending from the second capacitance
forming part in a width direction in the cross section of the
multilayer body taken in the width and thickness direction, and C2
represents an area of a second thickness margin part in the cross
section of the multilayer body taken in the width and thickness
direction, the second thickness margin part being a portion of the
second margin part extending from the second capacitance forming
part in a thickness direction in the cross section of the
multilayer body taken in the width and thickness direction.
[0019] A thickness of the dielectric layer may be 3 .mu.m or
less.
[0020] An average particle diameter of ceramic powder particles
used for the dielectric layer may be 0.3 .mu.m or less.
[0021] According to another embodiment of the present invention,
there is provided a multilayer ceramic capacitor, including: a
multilayer body including a dielectric layer having a thickness of
3 .mu.m or less; and first and second inner electrodes having the
dielectric layer disposed therebetween, wherein the number of
grains disposed between the first and second inner electrodes is 10
or more in a thickness direction of the dielectric layer, and a
ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1
represents an area of the multilayer body in a cross section of the
multilayer body taken in a length and thickness direction, and MA1
represents an area of a first margin part in the cross section of
the multilayer body taken in the length and thickness direction,
the first margin part being a portion of the multilayer body, other
than a first capacitance forming part thereof in which the first
and second inner electrodes overlap in the thickness direction in
the cross section of the multilayer body taken in the length and
thickness direction.
[0022] A ratio (C1/A1) of C1 to A1 may be between 0.35 and 2.0,
wherein A1 represents an area of a first length margin part in the
cross section of the multilayer body taken in the length and
thickness direction, the first length margin part being a portion
of the first margin part extending from the first capacitance
forming part in a length direction, and C1 represents an area of a
first thickness margin part in the cross section of the multilayer
body taken in the length and thickness direction, the first
thickness margin part being a portion of the first margin part
extending from the first capacitance forming part in a thickness
direction in the cross section of the multilayer body taken in the
length and thickness direction.
[0023] A ratio (MA2/CA2) of MA2 to CA2 may be between 0.10 and
0.28, wherein CA2 represents an area of the multilayer body in a
cross section of the multilayer body taken in a width and thickness
direction, and MA2 represents an area of a second margin part in
the cross section of the multilayer body taken in the width and
thickness direction, the second margin part being a portion of the
multilayer body, other than a second capacitance forming part
thereof in which the first and second inner electrodes overlap in
the thickness direction in the cross section of the multilayer body
taken in the width and thickness direction.
[0024] A ratio (C2/B1) of C2 to B1 may be between 0.30 and 1.35,
wherein B1 represents an area of a first width margin part in the
cross section of the multilayer body taken in the width and
thickness direction, the first width margin part being a portion of
the second margin part extending from the second capacitance
forming part in a width direction in the cross section of the
multilayer body taken in the width and thickness direction, and C2
represents an area of a second thickness margin part in the cross
section of the multilayer body taken in the width and thickness
direction, the second thickness margin part being a portion of the
second margin part extending from the second capacitance forming
part in a thickness direction in the cross section of the
multilayer body taken in the width and thickness direction.
[0025] According to another embodiment of the present invention,
there is provided a multilayer ceramic capacitor, including: a
multilayer body including a dielectric layer having a thickness of
3 .mu.m or less; and first and second inner electrodes having the
dielectric layer disposed therebetween, wherein the number of
grains disposed between the first and second inner electrodes is 10
or more in a thickness direction of the dielectric layer, and a
ratio (MA2/CA2) of MA2 to CA2 is between 0.10 and 0.28, wherein CA2
represents an area of the multilayer body in a cross section of the
multilayer body taken in a width and thickness direction, and MA2
represents an area of a second margin part in the cross section of
the multilayer body taken in the width and thickness direction, the
second margin part being a portion of the multilayer body, other
than a second capacitance forming part thereof in which the first
and second inner electrodes overlap in the thickness direction in
the cross section of the multilayer body taken in the width and
thickness direction.
[0026] A ratio (C2/B1) of C2 to B1 may be between 0.30 and 1.35,
wherein B1 represents an area of a first width margin part in the
cross section of the multilayer body taken in the width and
thickness direction, the first width margin part being a portion of
the second margin part extending from the second capacitance
forming part in a width direction in the cross section of the
multilayer body taken in the width and thickness direction, and C2
represents an area of a second thickness margin part in the cross
section of the multilayer body taken in the width and thickness
direction, the second thickness margin part being a portion of the
second margin part extending from the second capacitance forming
part in a thickness direction in the cross section of the
multilayer body taken in the width and thickness direction.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The above and other aspects, features and other advantages
of the present invention will be more clearly understood from the
following detailed description taken in conjunction with the
accompanying drawings, in which:
[0028] FIG. 1 is an exterior perspective view of a multilayer
ceramic capacitor according to an embodiment of the present
invention;
[0029] FIG. 2 is a cross-sectional view of the multilayer ceramic
capacitor of FIG. 1 according to the embodiment of the present
invention, taken along direction A-A';
[0030] FIG. 3 is a cross-sectional view of the multilayer ceramic
capacitor of FIG. 1 according to another embodiment of the present
invention, taken along direction A-A';
[0031] FIG. 4 is a cross-sectional view of the multilayer ceramic
capacitor of FIG. 1 according to the embodiment of the present
invention, taken along direction B-B';
[0032] FIG. 5 is a cross-sectional view of the multilayer ceramic
capacitor of FIG. 1 according to another embodiment of the present
invention, taken along direction B-B';
[0033] FIG. 6 is an enlarged view of X shown in FIG. 3; and
[0034] FIG. 7 is an enlarged view of Y shown in FIG. 5.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0035] Embodiments of the present invention will now be described
in detail with reference to the accompanying drawings. However, it
should be noted that the spirit of the present invention is not
limited to the embodiments set forth herein and those skilled in
the art and understanding the present invention can easily
accomplish retrogressive inventions or other embodiments included
in the spirit of the present invention by the addition,
modification, and removal of components within the same spirit, but
those are construed as being included in the spirit of the present
invention.
[0036] FIG. 1 is an exterior perspective view of a multilayer
ceramic capacitor according to an embodiment of the present
invention. FIGS. 2 and 3 are cross-sectional views of the
multilayer ceramic capacitor of FIG. 1, taken along direction A-A'.
FIGS. 4 and 5 are cross-sectional views of the multilayer ceramic
capacitor of FIG. 1, taken along direction B-B';
[0037] FIG. 6 is an enlarged view of X shown in FIG. 3. FIG. 7 is
an enlarged view of Y shown in FIG. 5.
[0038] Referring to FIGS. 1 to 5, a multilayer ceramic capacitor
100 according to an embodiment of the present invention may include
a multilayer body 110 and outer electrodes 130.
[0039] The multilayer body 110 may have a rectangular
parallelepiped shape. In the embodiment of the present invention,
surfaces in a lamination direction are defined as a top face Tf and
a bottom face Bf, surfaces in a length direction are defined as
first and second short faces Sf1 and Sf2, and surfaces in a width
direction are defined as first and second long faces Lf1 and Lf2,
respectively.
[0040] Meanwhile, with regard to the multilayer ceramic capacitor
in the embodiment of the present invention, a `length direction`
may be defined as an `L` direction shown in FIG. 1. Likewise, a
`width direction` may be defined as a `W` direction and a
`thickness direction` may be defined as a `T` direction. Here, the
`thickness direction` may have the same conception as a direction
of stacked dielectric layers, that is, a `lamination
direction.`
[0041] The multilayer body 110 may be formed by laminating a
plurality of dielectric layers in the thickness direction T. The
plurality of dielectric layers constituting the multilayer body 110
may be in a fired state so as not to confirm a boundary between
adjacent dielectric layers.
[0042] Herein, each dielectric layer may be formed of a ceramic
powder having a high dielectric permittivity and the ceramic powder
used herein may include, but is not limited to, barium titanate
(BaTiO.sub.3) powder, strontium titanate (SrTiO.sub.3) powder, or
the like.
[0043] In the embodiment of the present invention, a thickness of
one of the plurality of dielectric layers may be 3 .mu.m or less
and an average particle diameter of fired grains disposed in the
single dielectric layer may be 0.3 .mu.m or less. That is, the
average grain size of the dielectric layer may be 1/10 or less of
the thickness of the dielectric layer. Therefore, the number of
grains disposed between two inner electrodes or in the single
dielectric layer may be 10 or more in the thickness direction of
the dielectric layer.
[0044] In the embodiment of the present invention, the thickness of
the dielectric layer may mean an average thickness of a dielectric
layer that is disposed between inner electrode layers 121 and 122.
The average thickness of the dielectric layer may be measured by
image-scanning a cross-section in the length direction of the
multilayer body 110 through a scanning electron microscope (SEM),
as shown in FIG. 2. As shown in FIG. 2, for example, the average
thickness may be acquired by measuring thicknesses of a dielectric
layer in 30 positions in the length direction thereof, the 30
positions being located at equal intervals, from an extracted image
of the dielectric layer obtained by scanning a cross-section taken
in a length-thickness direction (L-T) at the center of the
multilayer body 110 in the width direction, through the SEM, and
then averaging the values of the measured thicknesses. The 30
positions located at equal intervals may be determined in a
capacitance formation part referring to a region on which the first
and second internal electrodes 121 and 122 are overlapped. In
addition, in a case in which the measurement of an average value is
executed with respect to 10 dielectric layers or more, the average
thickness of each of the dielectric layers may be more
generalized.
[0045] In addition, the average thickness of the dielectric layer
may also be measured from an image obtained by scanning a cross
section taken in a width and thickness direction W-T at the center
of the multilayer body 110 in the length direction through the
SEM.
[0046] In this case, the center of the multilayer body 110 in the
width direction or the length direction thereof may be defined as a
point within a range of 30% of the width or the length of the
multilayer body from the center of the multilayer body 110 in the
width or length direction.
[0047] Meanwhile, the average grain size of the dielectric layer
may be measured by analyzing a cross sectional photograph of the
dielectric layer extracted through the SEM. For example, the
average grain size of the dielectric layer may be measured by using
grain size measurement software that supports an average grain size
standard measurement method defined in American Society for Testing
and Materials (ASTM) E112.
[0048] The inside of the multilayer body 110 may be provided with a
plurality of inner electrode layers 120. The inner electrode layers
120 are disposed on the dielectric layers in the lamination
direction of the dielectric layers so as to be opposed to each
other while having the single dielectric layer disposed
therebetween.
[0049] The plurality of inner electrode layers 120 may be made of a
conductive metal, for example, Ni or a Ni alloy. The Ni alloy may
include Mn, Cr, Co, or Al, together with Ni. The inner electrode
layers 120 may be formed by printing a conductive paste including a
metal powder such as nickel (Ni), or the like, on a surface of a
ceramic green sheet forming the dielectric layers in a
predetermined pattern. The embodiment of the present invention is
not limited thereto, but the thickness of each inner electrode
layer may be 0.7 .mu.m or less.
[0050] In addition, according to the embodiment of the present
invention, 200 or more dielectric layers, or 500 or more dielectric
layers, each having the inner electrode layers 120 formed thereon
may be laminated.
[0051] The plurality of internal electrodes 120 may include a
plurality of first internal electrodes 121 and a plurality of
second internal electrodes 122, having opposing polarities. The
first inner electrode 121 and the second inner electrode 122 may be
alternately laminated so as to be opposed to each other according
to the lamination direction thereof, having the dielectric layer
disposed therebetween.
[0052] The plurality of the first internal electrodes 121 may have
one ends exposed to the first short face Sf1 of the multilayer body
110, while the plurality of second internal electrodes 122 may have
one ends opposed to the exposed ends of the first internal
electrodes 121 in the length direction and exposed to the second
short face Sf2.
[0053] One ends of the plurality of the first internal electrodes
121 exposed to the first short face Sf1 may be connected to a first
external electrode 131, while one ends of the plurality of second
internal electrodes 122 exposed to the second short face Sf2 may be
connected to a second external electrode 132.
[0054] The outer electrodes 130 may include the first outer
electrode 131 and the second outer electrode 132 formed on two
sides of the multilayer body 110, facing each other. As shown in
FIG. 1, the first outer electrode 131 may be formed to cover the
first short side Sf1 of the multilayer body 110 and the second
outer electrode 132 may be formed to cover the second short side
Sf2.
[0055] In the embodiment of the present invention, the first outer
electrode 131 and the second outer electrode 132 may be formed to
cover both short sides of the multilayer body 110, but the
embodiment of the present invention is not limited thereto.
Therefore, the first and second outer electrodes 131 and 132 may be
formed to cover both long sides Lf1 and Lf2 of the multilayer body
110.
[0056] The first outer electrode 131 and the second outer electrode
132 may be electrically separated from each other. The first outer
electrode 131 may be electrically connected to the one ends of the
first inner electrodes 121 exposed to the first short side Sf1 of
the multilayer body 110 and the second outer electrode 132 may be
electrically connected to the one ends of the second inner
electrodes 122 exposed to the second short side Sf2 facing the
first short side Sf1 of the multilayer body 110 in the length
direction. As a result, the outer electrodes 130 may serve as
external terminals.
[0057] The outer electrodes 130 may be made of copper, a copper
(Cu) alloy, or the like.
[0058] Hereinafter, electrical characteristics of the multilayer
ceramic capacitor according to the embodiment of the present
invention will be described.
[0059] In the multilayer body 110, capacitance may be formed in a
portion ("overlapping portion") in which the plurality of first
inner electrodes 121 and the plurality of second inner electrodes
122 overlap in the lamination direction, and the remaining portion
other than the above portion may serve to protect the portion in
which the capacitance is formed. Hereinafter, the overlapping
portion may be referred to as a capacitance forming part and the
remaining portion other than the capacitance forming part may be
referred to as a margin part.
[0060] When voltage is applied to the multilayer body 110, the
multilayer body 110 is distorted due to a piezoelectric phenomenon.
The distortion may be caused by a first capacitance forming part
C.sub.LT.
[0061] In particular, when the multilayer body 110 is mounted on a
circuit board such that the first and second inner electrodes 121
and 122 are parallel with the surface of the circuit board, a point
of the multilayer body 100, in which distortion thereof becomes
maximal, may be the central portion of the multilayer body 110. In
this case, a first margin part M.sub.LT serves to suppress the
distortion of the multilayer body 110.
[0062] According to the embodiment of the present invention an area
ratio of the first margin part M.sub.LT may be set to be in a
predetermined range to effectively suppress the distortion of the
multilayer body 110 and reduce vibrations in the multilayer body
111 and the circuit board to thereby reduce acoustic noise.
[0063] The thickness of the dielectric layer may be reduced and at
the same time, the average grain size within each dielectric layer
may be set to be 1/10 or less of the thickness of the dielectric
layer so as to reduce the acoustic noise, whereby a multilayer
ceramic capacitor having low dielectric permittivity may be
implemented.
[0064] As described above, when the multilayer ceramic capacitor
having low dielectric permittivity may be implemented by reducing
the thickness of the dielectric layer and the average grain size
within the dielectric layer, the acoustic noise may be reduced.
[0065] However, a reduction in acoustic noise is remarkably reduced
in the multilayer ceramic capacitor manufactured in such a manner
that a distance between the first and second inner electrodes 121
and 122 within the multilayer body 110, that is, the thickness of
the dielectric layer is set to be 3 .mu.m or less and the number of
grains within the dielectric layer is 10 or more.
[0066] This can be more clearly appreciated from the following
Table 1.
TABLE-US-00001 TABLE 1 Dielectric Acoustic Thickness Grain Size
noise No (td, .mu.m) (Dc, .mu.m) td/Dc (dB) 1 4.3 0.68 6.3 43.7 2
0.58 7.4 43.1 3 0.43 10.0 36.3 4 0.26 16.5 33.1 5 2.8 0.59 4.7 43.2
6 0.45 6.2 42.1 7 0.26 10.8 41.0 8 0.16 17.5 40.5 9 1.9 0.60 3.2
43.6 10 0.44 4.5 42.6 11 0.25 7.6 41.7 12 0.16 11.9 40.8
[0067] In this case, samples, experimental objects, were
manufactured as follows.
[0068] First, a plurality of ceramic green sheets having a
thickness required for several experimental conditions were
prepared by applying slurries including powder such as barium
titanate (BaTiO3), and the like, to carrier films and drying the
carrier films having the slurries applied thereto, whereby
dielectric layers were formed.
[0069] Next, inner electrodes were formed using a conductive paste
for a nickel inner electrode on the green sheets through a screen,
and then 370 green sheets were laminated and the thickness of a
cover layer was differently set to be 10 to 100 .mu.m, whereby a
ceramic laminate was manufactured.
[0070] The ceramic laminate was subjected to isostatic pressing
under a pressure condition of 1,000 kgf/cm.sup.2 at 85.degree.
C.
[0071] The pressed ceramic laminate was cut into individual chips
and the cut chips were subjected to a debinder-treatment while
being maintained at 230.degree. C. for 60 hours in atmosphere.
Thereafter, the chips were fired at 1200.degree. C. in a reduction
atmosphere under an oxygen partial pressure of 10.sup.-11 atm to
10.sup.-10 atm lower than a Ni/NiO balance oxygen partial pressure
such that the inner electrodes are not oxidized. After firing, the
size of the chips was 3.2 mm.times.1.6 mm.times.1.6 mm
(L.times.W.times.T), and thicknesses of the dielectric layers and
grain sizes thereof were shown in the above Table 1.
[0072] Referring to Table 1, when low dielectric permittivity is
implemented by reducing the grain sizes under conditions in which
the dielectric thickness is 4.3 .mu.m as in samples 1 to 4, it
could be appreciated that magnitude in acoustic noise is remarkably
reduced. However, when low dielectric permittivity is implemented
by reducing the grain sizes under conditions in which the
dielectric thickness is about 3 .mu.m or less as in samples 5 to
12, it could be appreciated that a reduction in acoustic noise is
insignificant even in a case in which td/Dc, that is, a ratio of
the grain size to the dielectric thickness is 1/10 or less.
[0073] Therefore, when the dielectric thickness is small, it could
be appreciated that a reduction effect in acoustic noise may be
further increased only in the case of adding separate conditions in
addition to a reduction in the grain size.
[0074] Referring to FIG. 2, when the multilayer body 110 is cut in
the length and thickness direction, the cross section (L-T cross
section) taken in the length and thickness direction of the
multilayer body 110 may be referred to a first cross section. In
the first cross section, a portion in which the first and second
inner electrodes 121 and 122 overlap in the thickness direction may
be referred to as the first capacitance forming part C.sub.LT, and
a portion other than the first capacitance forming part C.sub.LT
may be referred to as the first margin part M.sub.LT.
[0075] In the embodiment of the present invention, a ratio MA1/CA1
of an area MA1 of the first margin part M.sub.LT to an area CA1 of
the first cross section may be between 0.07 and 0.20. When the
MA1/CA1 is below 0.07, acoustic noise may be increased to 40 dB or
more and delaminations may occur, and when the MA1/CA1 exceeds
0.20, capacitance may be degraded to 9 .mu.F or less.
[0076] Referring to FIG. 3, in the first margin part M.sub.LT, a
portion extending from the first capacitance forming part C.sub.LT
in the length direction is referred to as a first length margin
part M.sub.LT1 and a portion extending from the first capacitance
forming part C.sub.LT in the thickness direction may be referred to
as a first thickness margin part M.sub.LT2.
[0077] In the embodiment of the present invention, a ratio C1/A1 of
an area C1 of the first thickness margin part M.sub.LT2 to an area
A1 of the first length margin part M.sub.LT1 may be between 0.35
and 2.0. When the C1/A1 is below 0.35 or exceeds 2.0, acoustic
noise may be increased to 40 dB or more.
[0078] A method of measuring the area of the cross section of the
multilayer body 100 will be described with reference to FIGS. 6 and
7.
[0079] The area of the cross section or the area of the margin part
shown in the embodiments of FIGS. 2 and 3 is difficult to have a
complete linear boundary due to the plastic deformation of the
multilayer body 100 or the inner electrode layers 120, but may be
measured based on a substantially linear virtual line.
[0080] However, the boundary between the first and second inner
electrodes 121 and 122 forming the capacitance forming part may be
unclear. When the first and second inner electrodes 121 and 122 are
deformed due to the firing, the ends of the first and second inner
electrodes 121 and 122 may be offset as shown in FIGS. 6 and 7.
[0081] In this case, in order to measure the areas of the margin
part and the capacitance forming part, the areas may be measured
based on, as a boundary, intermediate values Xm and Ym between
portions Xmax and Ymax in which offset deformation is greatest and
portions Xmin and Ymin in which offset deformation is lowest, in
the ends of the inner electrodes.
[0082] In this case, based on a distance between a side of the
multilayer body 100 and the inner electrodes 121 and 122, the
portions in which offset deformation is greatest correspond to a
case in which the distance between the one side of the multilayer
body 100 and the ends of the inner electrodes 121 and 122 is
smallest and the portions in which offset deformation is lowest
correspond to a case in which the distance between the one side of
the multilayer body 100 and the ends of the inner electrodes 121
and 122 is greatest.
[0083] Referring to FIG. 4, when the multilayer body 110 is cut in
the width and thickness direction, the cross section (W-T cross
section) taken in the width and thickness direction of the
multilayer body 110 may be referred to a second cross section. In
the second cross section, a portion in which the first and second
inner electrodes 121 and 122 overlap in the thickness direction may
be referred to as a second capacitance forming part C.sub.WT, and a
portion other than the second capacitance forming part C.sub.WT may
be referred to as a second margin part M.sub.WT.
[0084] In the embodiment of the present invention, a ratio MA2/CA2
of an area MA2 of the second margin part M.sub.WT to an area CA2 of
the second cross section may be between 0.10 and 0.28. When the
MA2/CA2 is below 0.10, acoustic noise may be increased to 40 dB or
more and delaminations may occur, and when the MA2/CA2 exceeds
0.28, capacitance may be degraded to 9 .mu.F or less.
[0085] Referring to FIG. 5, in the second margin part M.sub.WT, a
portion extending from the second capacitance forming part C.sub.WT
in the width direction is referred to as a first width margin part
M.sub.WT1 and a portion extending from the second capacitance
forming part C.sub.WT in the thickness direction may be referred to
as a second thickness margin part M.sub.WT2.
[0086] In the embodiment of the present invention, a ratio C2/B1 of
an area C2 of the second thickness margin part M.sub.WT2 to an area
B1 of the first width margin part M.sub.WT1 may be between 0.3 and
1.35. When the C1/A1 is below 0.3 or exceeds 1.35, acoustic noise
may be increased to 40 dB or more.
[0087] Hereinafter, the embodiment of the present will be described
in detail with reference to Examples and Comparative Examples for
the more detailed understanding of the present invention. The scope
of the present invention is not limited to Examples.
EXAMPLE
[0088] The multilayer ceramic capacitor according to the Example of
the present invention was manufactured as follows.
[0089] First, a plurality of ceramic green sheets having a
thickness of 3.9 .mu.m were prepared by applying slurries including
powder such as barium titanate (BaTiO3), and the like, to carrier
films and drying the carrier films having the slurries applied
thereto, whereby dielectric layers were formed.
[0090] Next, inner electrodes were formed using a conductive paste
for a nickel inner electrode on the green sheets through a screen
including multilayer ceramic capacitor patterns, the L margin and
the W margin of which are set to be different from each other and
then, 370 green sheets were laminated and the thickness of a cover
layer was differently set to be 10 to 100 .mu.m, whereby a ceramic
laminate was manufactured.
[0091] The ceramic laminate was subjected to isostatic pressing
under a pressure condition of 1000 kgf/cm2 at 85.degree. C.
[0092] The pressed ceramic laminate was cut into individual chips
and the cut chips were subjected to a debinder-treatment while
being maintained at 230.degree. C. for 60 hours in the atmosphere.
Thereafter, the chips were fired at 1200.degree. C. in a reduction
atmosphere under an oxygen partial pressure of 10.sup.-11 atm to
10.sup.-10 atm lower than an Ni/NiO balance oxygen partial pressure
such that the inner electrodes are not oxidized. After firing, the
thickness of the dielectric layer was 2.7 .mu.m, the average
particle diameter of ceramic powder used in the dielectric layer
was 0.27 .mu.m, and the size of the chips was 3.2 mm.times.1.6
mm.times.1.6 mm (L.times.W.times.T).
[0093] Next, the multilayer ceramic capacitor was manufactured by
processes, such as an outer electrode process, a plating process,
and the like.
[0094] In this case, the samples of the multilayer ceramic
capacitor were variously manufactured according to the area ratio
of each of the margin parts.
[0095] The following Table 2 is a table in which acoustic noise,
capacitance, and the incidence of delamination are compared
according to the area ratio of the margin part to the cross section
of the multilayer body. The noise (acoustic noise) was measured in
an anechoic chamber by applying a pulse wave of 3Vpp to DC voltage
of 12.5V, the capacitance of 100 samples was measured at 1 kHz, and
the incidence of delamination was represented by performing the
internal analysis on 100 samples.
TABLE-US-00002 TABLE 2 Acoustic L-T Cross Section W-T Cross Section
Capacitance Noise Delam. No. CA1 MA1 MA1/CA1 CA2 MA2 MA2/CA2
(.mu.F) (dB) (%) 1* 4.867 0.204 0.042 2.524 0.152 0.06 12.89 45.1
78 2* 4.877 0.232 0.048 2.519 0.173 0.069 12.75 45.3 44 3* 4.930
0.265 0.054 2.539 0.198 0.078 12.72 44.8 26 4* 4.925 0.303 0.061
2.558 0.226 0.088 12.51 43.4 18 5 4.952 0.346 0.07 2.561 0.257 0.1
12.36 33.9 0 6 4.891 0.391 0.08 2.527 0.289 0.114 11.96 33.8 0 7
4.867 0.446 0.092 2.526 0.329 0.13 11.63 33.4 0 8 4.838 0.509 0.105
2.503 0.372 0.149 11.19 32.5 0 9 4.911 0.588 0.12 2.547 0.429 0.169
11.03 31.4 0 10 4.895 0.673 0.138 2.547 0.489 0.192 10.59 31.0 0 11
4.863 0.770 0.158 2.530 0.554 0.219 10.1 30.1 0 12 4.886 0.887
0.181 2.532 0.632 0.249 9.64 28.7 0 13 4.892 1.020 0.209 2.534
0.720 0.284 9.09 27.5 0 14* 4.836 1.167 0.241 2.509 0.814 0.324
8.37 26.4 0 15* 4.870 1.349 0.277 2.521 0.927 0.368 7.78 25.3 0 16*
4.869 1.554 0.319 2.514 1.051 0.418 7.03 24.5 0 17* 4.895 1.794
0.367 2.523 1.193 0.473 6.28 23.5 0 CA1: the area of the first
cross section (L-T cross section) of the multilayer body, MA1: the
area of the first margin part M.sub.LT, CA2: the area of the second
cross section (W-T cross section) of the multilayer body, MA2: the
area of the second margin part M.sub.WT, *Comparative Example
[0096] Referring to Table 2, samples 1 to 4 and 14 to 17 are
Comparative Examples and samples 5 to 13 are Examples.
[0097] It could be appreciated that in samples 5 to 13
corresponding to the Examples of the present invention, acoustic
noise is 27.5 to 33.9 dB, which is more remarkably reduced than in
samples 1 to 4 corresponding to Comparative Examples. In addition,
in samples 5 to 13 corresponding to Examples of the present
invention, the incidence of delamination is 0%, which results in
securing the excellent reliability and capacitance may be 9 .mu.F
or more, for example, 9.09 to 12.36 .mu.F, which results in
securing high capacitance.
[0098] Meanwhile, it could be appreciated that in samples 1 to 4
corresponding to Comparative Examples, capacitance is high as 12
.mu.F or more but acoustic noise is 43 dB or more and the incidence
of delamination is also increased. It could be appreciated that in
samples 14 to 17 corresponding to Comparative Examples, the
incidence of delamination is 0% and the acoustic noise is
remarkably reduced to 27 dB or less while the capacitance is
suddenly reduced.
[0099] Therefore, it could be appreciated that in the Examples of
the present invention, the incidence of delamination may be reduced
and high capacitance may be realized while remarkably reducing
acoustic noise, as compared with Comparative Examples.
[0100] The following Table 3 is a table in which acoustic noise,
capacitance, and the incidence of delamination are compared
according to the area ratio of each of the margin parts.
TABLE-US-00003 TABLE 3 Acoustic L-T Cross Section W-T Cross Section
Capacitance Noise Delam. No. A1 C1 C1/A1 B1 C2 C2/B1 (.mu.F) (dB)
(%) 21* 0.293 0.027 0.09 0.179 0.014 0.08 10.51 42.1 12 22* 0.258
0.056 0.22 0.161 0.028 0.18 10.7 40.8 0 23 0.242 0.085 0.35 0.143
0.043 0.30 10.92 32.0 0 24 0.203 0.114 0.56 0.129 0.058 0.45 11.1
31.4 0 25 0.169 0.145 0.86 0.116 0.073 0.63 11.31 31.0 0 26 0.134
0.177 1.32 0.094 0.089 0.96 11.37 31.5 0 27 0.104 0.208 2.0 0.078
0.106 1.35 11.47 33.4 0 28* 0.077 0.238 3.1 0.064 0.12 1.88 11.47
41.0 0 29* 0.056 0.273 4.9 0.047 0.139 2.94 11.8 42.2 10 30* 0.034
0.307 9.03 0.027 0.158 5.80 11.84 44.3 60 A1: the area of the first
length margin part M.sub.LT1, C1: the area of the first thickness
margin part M.sub.LT2, B1: the area of the first width margin part
M.sub.WT1, C2: the area of the second thickness margin part
M.sub.WT2, *Comparative Example
[0101] Referring to Table 3, samples 21, 22, and 28 to 30 are
Comparative Examples and samples 23 to 27 are Examples of the
present invention.
[0102] It could be appreciated that in samples 23 to 27
corresponding to the Examples of the present invention, acoustic
noise is 31 to 33.4 dB, which is more remarkably reduced than in
samples 21, 22, and 28 to 30 corresponding to the Comparative
Examples. In addition, in samples 23 to 27 corresponding to the
Examples of the present invention, the incidence of delamination is
0%, which results in securing the excellent reliability and
capacitance may be 11 .mu.F or more, for example, 10.92 to 11.47
.mu.F, which results in securing high capacitance.
[0103] Meanwhile, samples 28 to 30 corresponding to the Comparative
Examples, the capacitance is high as approximately 11.5 .mu.F, but
the acoustic noise is 41 dB or more. In particular, it is shown
that in samples 29 and 30, the incidence of delamination is high as
10% or more. In samples 1 and 2 corresponding to the Comparative
Examples, the acoustic noise is 40 dB or more and the capacitance
is reduced to 10.7 .mu.F or less. In particular, it is shown that
in sample 1, the incidence of delamination is 12%, which results in
degrading the reliability.
[0104] Therefore, it could be appreciated that in the Examples of
the present invention, the incidence of delamination may be reduced
and high capacitance may be realized while acoustic noise are
remarkably reduced, as compared with the Comparative Examples.
[0105] As set forth above, according to embodiments of the present
invention, there is provided a small-sized and high-capacitance
multilayer ceramic capacitor having high reliability and reduced
acoustic noise while suppressing a generation of delaminations.
[0106] Although the embodiments of the present invention have been
described in detail, they are only examples. It will be appreciated
by those skilled in the art that various modifications and
equivalent other embodiments are possible from the present
invention. Accordingly, the actual technical protection scope of
the present invention must be determined by the spirit of the
appended claims.
* * * * *