U.S. patent application number 13/598259 was filed with the patent office on 2012-12-27 for display apparatus and display-apparatus driving method.
This patent application is currently assigned to Sony Corporation. Invention is credited to Seiichiro Jinta, Takao Tanikame.
Application Number | 20120327138 13/598259 |
Document ID | / |
Family ID | 41256777 |
Filed Date | 2012-12-27 |
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United States Patent
Application |
20120327138 |
Kind Code |
A1 |
Tanikame; Takao ; et
al. |
December 27, 2012 |
DISPLAY APPARATUS AND DISPLAY-APPARATUS DRIVING METHOD
Abstract
Disclosed herein is a driving method for driving a display
apparatus, the display apparatus including: N.times.M light
emitting units; M scan lines; N data lines; a driving circuit
provided for each of the light emitting units to serve as a circuit
having a signal writing transistor, a device driving transistor, a
capacitor and a first switch circuit; and a light emitting
device.
Inventors: |
Tanikame; Takao; (Kanagawa,
JP) ; Jinta; Seiichiro; (Aichi, JP) |
Assignee: |
Sony Corporation
Tokyo
JP
|
Family ID: |
41256777 |
Appl. No.: |
13/598259 |
Filed: |
August 29, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12385692 |
Apr 16, 2009 |
8289239 |
|
|
13598259 |
|
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Current U.S.
Class: |
345/690 |
Current CPC
Class: |
G09G 2310/0262 20130101;
G09G 3/3233 20130101; G09G 3/3291 20130101; G09G 2310/062 20130101;
G09G 2300/0847 20130101; G09G 2300/0861 20130101; G09G 2300/0819
20130101; G09G 2310/0251 20130101; G09G 2330/02 20130101; G09G 3/20
20130101 |
Class at
Publication: |
345/690 |
International
Class: |
G09G 5/10 20060101
G09G005/10 |
Foreign Application Data
Date |
Code |
Application Number |
May 1, 2008 |
JP |
2008-119839 |
Dec 16, 2008 |
JP |
2008-319828 |
Claims
1. A display apparatus comprising: a plurality of scan lines; a
plurality of data lines; a plurality of light emitting units
respectively comprising a driving circuit, the driving circuit
having a first transistor, a second transistor, and a third
transistor; and a light emitting device provided for each of the
light emitting units to serve as a device for emitting light at a
luminance according to a driving current output by the device
driving transistor to the light emitting device, wherein in each of
the light emitting units, the first transistor is connected between
a first node and one of the data lines, the second transistor is
connected between the first node and the light emitting device, and
the third transistor is connected between the one of the data lines
and a gate of the second transistor.
2. The display apparatus according to claim 1, wherein the light
emitting devices are organic electric luminescence light emitting
devices.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a Continuation Application of U.S. patent
application Ser. No. 12/385,692, filed Apr. 16, 2009, which claims
priority from Japanese Application No.: 2008-119839, filed on May
1, 2008 and Japanese Application No.: 2008-319828, filed on Dec.
16, 2008, the entire contents of which are incorporated herein by
reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] In general, the present invention relates to a display
apparatus and a driving method for driving the display apparatus.
More particularly, the present invention relates to a display
apparatus employing light emitting units, which each have a light
emitting device and a driving circuit for driving the light
emitting device, and relates to a driving method for driving the
display apparatus.
[0004] 2. Description of the Related Art
[0005] As already known in general, there is a light emitting unit
having a light emitting device and a driving circuit for driving
the light emitting device. A typical example of the light emitting
device is an organic EL (Electro Luminescence) light emitting
device. In addition, a display apparatus employing the light
emitting units is also already commonly known. The luminance of
light emitted by the light emitting unit is determined by the
magnitude of the driving current. A typical example of such a
display apparatus is an organic EL display apparatus which employs
organic EL light emitting devices. In addition, in the same way as
a liquid-crystal display apparatus, the display apparatus employing
the light emitting units adopts one of commonly known driving
methods such as a simple matrix method and an active matrix method.
In comparison with the simple matrix method, the active matrix
method has a demerit that the active matrix method entails a
complicated configuration of the driving circuit. However, the
active matrix method offers a variety of merits such as a
capability of increasing the luminance of light emitted by the
light emitting device.
[0006] As already known, there are a variety of active-matrix
driving circuits which each employ transistors and a capacitor.
Such a driving circuit serves as a circuit for driving the light
emitting device included in the same light emitting unit as the
driving circuit. For example, Japanese Patent Laid-open No.
2005-31630 discloses an organic EL display apparatus employing
light emitting units, which each have an organic EL light emitting
device and a driving circuit for driving the organic EL light
emitting device, and discloses a driving method for driving the
organic EL display apparatus. The driving circuit employs six
transistors and one capacitor. In the following description, the
driving circuit employing six transistors and one capacitor is
referred to as a 6T r/1C driving circuit. FIG. 15 is a diagram
showing an equivalent circuit of the 6T r/1C driving circuit
included in a light emitting unit located at the intersection of an
mth matrix row and an nth matrix column in a two-dimensional matrix
in which N.times.M light emitting units employed in a display
apparatus are laid out. It is to be noted that the light emitting
units are sequentially scanned by a scan circuit 101 in row units
on a row-after-row basis.
[0007] The 6T r/1C driving circuit employs a signal writing
transistor TR.sub.W, a device driving transistor TR.sub.D and a
capacitor C.sub.1 in addition to a first transistor TR.sub.1, a
second transistor TR.sub.2, a third transistor TR.sub.3 and a
fourth transistor TR.sub.4.
[0008] A specific one of the source and drain areas of the signal
writing transistor TR.sub.W is connected to a data line DTL.sub.n
whereas the gate electrode of the signal writing transistor
TR.sub.W is connected to a scan line SCL.sub.m. A specific one of
the source and drain areas of the device driving transistor
TR.sub.D is connected to the other one of the source and drain
areas of the signal writing transistor TR.sub.W through a first
node ND.sub.1. A specific one of the terminals of the capacitor
C.sub.1 is connected to a first power-supply line PS.sub.1 to which
a reference voltage is applied. In the typical light emitting unit
shown in the diagram of FIG. 15, the reference voltage is a
reference voltage V.sub.CC to be described later. The other one of
the terminals of the capacitor C.sub.1 is connected to the gate
electrode of the device driving transistor TR.sub.D through a
second node ND.sub.2. The scan line SCL.sub.m is connected to the
scan circuit 101 whereas the data line DTL.sub.n is connected to a
signal outputting circuit 102.
[0009] A specific one of the source and drain areas of the first
transistor TR.sub.1 is connected to the second node ND.sub.2
whereas the other one of the source and drain areas of the first
transistor TR.sub.1 is connected to the other one of the source and
drain areas of the device driving transistor TR.sub.D. The first
transistor TR.sub.1 serves as a first switch circuit connected
between the second node ND.sub.2 and the other one of the source
and drain areas of the device driving transistor TR.sub.D.
[0010] A specific one of the source and drain areas of the second
transistor TR.sub.2 is connected to a third power-supply line
PS.sub.3 to which a predetermined initialization voltage V.sub.Ini
for initializing an electric potential appearing on the second node
ND.sub.2 is applied. The initialization voltage V.sub.Ini is
typically -4 volts. The other one of the source and drain areas of
the second transistor TR.sub.2 is connected to the second node
ND.sub.2. The second transistor TR.sub.2 serves as a second switch
circuit connected between the second node ND.sub.2 and the third
power-supply line PS.sub.3 to which the predetermined
initialization voltage V.sub.Ini is applied.
[0011] A specific one of the source and drain areas of the third
transistor TR.sub.3 is connected to the first power-supply line
PS.sub.1 to which the predetermined reference voltage V.sub.CC of
typically 10 volts is applied. The other one of the source and
drain areas of the third transistor TR.sub.3 is connected to the
first node ND.sub.1. The third transistor TR.sub.3 serves as a
third switch circuit connected between the first node ND.sub.1 and
the first power-supply line PS.sub.1 to which the predetermined
reference voltage V.sub.CC is applied.
[0012] A specific one of the source and drain areas of the fourth
transistor TR.sub.4 is connected to the other one of the source and
drain areas of the device driving transistor TR.sub.D whereas the
other one of the source and drain areas of the fourth transistor
TR.sub.4 is connected to a specific one of the terminals of a light
emitting device ELP. The specific one of the terminals of the light
emitting device ELP is the anode electrode of the light emitting
device ELP. The fourth transistor TR.sub.4 serves as a fourth
switch circuit connected between the other one of the source and
drain areas of the device driving transistor TR.sub.D and the
specific terminal of the light emitting device ELP.
[0013] The gate electrodes of the signal writing transistor
TR.sub.W and the first transistor TR.sub.1 are connected to the
scan line SCL.sub.m whereas the gate electrode of the second
transistor TR.sub.2 is connected to a scan line SCL.sub.m-1
provided for a matrix row right above a matrix row associated with
the scan line SCL.sub.m. The gate electrodes of the third
transistor TR.sub.3 and the fourth transistor TR.sub.4 are
connected to a third/fourth-transistor control line CL.sub.m.
[0014] Each of the transistors is a TFT (Thin Film Transistor) of a
p-channel type. The light emitting device ELP is provided typically
on an inter-layer insulation layer which is created to cover the
driving circuit. The anode electrode of the light emitting device
ELP is connected to the other one of the source and drain areas of
the fourth transistor TR.sub.4 whereas the cathode electrode of the
light emitting device ELP is connected to a second power-supply
line PS.sub.2 for supplying a cathode voltage V.sub.Cat of
typically -10 volts to the cathode electrode. Reference notation
C.sub.EL denotes the parasitic capacitance of the light emitting
device ELP.
[0015] It is impossible to prevent the threshold voltage of a TFT
from varying to a certain degree from transistor to transistor.
Variations of the threshold voltage of the device driving
transistor TR.sub.D cause variations of the magnitude of a driving
current flowing through the light emitting device ELP. If the
magnitude of the driving current flowing through the light emitting
device ELP varies from a light emitting unit to another, the
uniformity of the luminance of the display apparatus deteriorates.
It is thus necessary to prevent the magnitude of the driving
current flowing through the light emitting device ELP from being
affected by variations of the threshold voltage of the device
driving transistor TR.sub.D. As will be described later, the light
emitting device ELP is driven in such a way that the luminance of
light emitted by the light emitting device ELP is not affected by
variations of the threshold voltage of the device driving
transistor TR.sub.D.
[0016] By referring to diagrams of FIGS. 16A and 16B, the following
description explains a driving method for driving an light emitting
device ELP employed in a light emitting unit located at the
intersection of an mth matrix row and an nth matrix column of a
two-dimensional matrix in which N.times.M light emitting units
employed in a display apparatus are laid out. FIG. 16A is a model
timing diagram showing timing charts of signals appearing on the
scan line SCL.sub.m-1, the scan line SCL.sub.m and the
third/fourth-transistor control line CL.sub.m. On the other hand,
FIG. 16B and FIGS. 16C and 16D are model circuit diagrams showing
the turned-on and turned-off states of the transistors employed in
the driving circuit. For the sake of convenience, in the following
description, the scan period in which the scan line SCL.sub.m-1 is
scanned is referred to as the (m-1) th horizontal scan period
whereas the scan period in which the scan line SCL.sub.m is scanned
is referred to as the mth horizontal scan period.
[0017] As shown in the timing diagram of FIG. 16A, during the (m-1)
th horizontal scan period, a second-node electric-potential
initialization process is carried out. The second-node
electric-potential initialization process is explained in detail by
referring to the circuit diagram of FIG. 16B as follows. At the
beginning of the (m-1) th horizontal scan period, an electric
potential appearing on the scan line SCL.sub.m-1 is changed from a
high level to a low level but an electric potential appearing on
the third/fourth-transistor control line CL.sub.m is conversely
changed from a low level to a high level. It is to be noted that,
at that time, an electric potential appearing on the scan line
SCL.sub.m is sustained at a high level. Thus, during the (m-1) th
horizontal scan period, each of the signal writing transistor
TR.sub.W, the first transistor TR.sub.4, the third transistor
TR.sub.3 and the fourth transistor TR.sub.4 is put in a turned-off
state whereas the second transistor TR.sub.2 is put in a turned-on
state.
[0018] In these states, the initialization voltage V.sub.Ini for
initializing the second node ND.sub.2 is applied to the second node
ND.sub.2 by way of the second transistor TR.sub.2 which has been
set in a turned-on state. Thus, during this period, the second-node
electric-potential initialization process is carried out.
[0019] Then, as shown in the timing diagram of FIG. 16A, during the
mth horizontal scan period, the electric potential appearing on the
scan line SCL.sub.m is changed from a high level to a low level in
order to put the signal writing transistor TR.sub.W in a turned-on
state so that the video signal V.sub.Sig appearing on the data line
DTL.sub.n is written into the first node ND.sub.1 by way of the
signal writing transistor TR.sub.W. During this mth horizontal scan
period, a threshold-voltage cancelling process is also carried out.
To put it concretely, the second node ND.sub.2 is electrically
connected to the other one of the source and drain areas of the
device driving transistor TR.sub.D. When the electric potential
appearing on the scan line SCL.sub.m is changed from a high level
to a low level in order to put the signal writing transistor
TR.sub.W in a turned-on state, the video signal V.sub.Sig appearing
on the data line DTL.sub.n is written into the first node ND.sub.1
by way of the signal writing transistor TR.sub.W. As a result, the
electric potential appearing on the second node ND.sub.2 rises to a
level obtained by subtracting the threshold voltage V.sub.th of the
device driving transistor TR.sub.D from the video signal
V.sub.Sig.
[0020] The processes described above are explained in detail by
referring to the diagrams of FIGS. 16A and 16C as follows. At the
beginning of the mth horizontal scan period, the electric potential
appearing on the scan line SCL.sub.m-1 is changed from a low level
to a high level but the electric potential appearing on the scan
line SCL.sub.m is conversely changed from a high level to a low
level. It is to be noted that, at that time, the electric potential
appearing on the third/fourth-transistor control line CL.sub.m is
sustained at the high level. Thus, during the mth horizontal scan
period, each of the signal writing transistor TR.sub.W and the
first transistor TR.sub.1 is put in a turned-on state whereas each
of the second transistor TR.sub.2, the third transistor TR.sub.3
and the fourth transistor TR.sub.4 is conversely put in a
turned-off state.
[0021] The second node ND.sub.2 is electrically connected to the
other one of the source and drain areas of the device driving
transistor TR.sub.D through the first transistor TR.sub.1 which has
been put in a turned-on state. When the electric potential
appearing on the scan line SCL.sub.m is changed from a high level
to a low level in order to put the signal writing transistor
TR.sub.W in a turned-on state, the video signal V.sub.Sig appearing
on the data line DTL.sub.n is written into the first node ND.sub.1
by way of the signal writing transistor TR.sub.W. As a result, the
electric potential appearing on the second node ND.sub.2 rises to a
level obtained by subtracting the threshold voltage V.sub.th of the
device driving transistor TR.sub.D from the video signal
V.sub.Sig.
[0022] That is to say, if the electric potential appearing on the
second node ND.sub.2 connected to the gate electrode of the device
driving transistor TR.sub.D has been initialized at a level putting
the device driving transistor TR.sub.D in a turned-on state at the
beginning of the mth horizontal scan period by carrying out the
second-node electric-potential initialization process during the
(m-1) th horizontal scan period, the electric potential appearing
on the second node ND.sub.2 rises toward the video signal V.sub.Sig
applied to the first node ND.sub.1. As the difference in electric
potential between the gate electrode and the specific one of the
source and drain areas of the device driving transistor TR.sub.D
attains the threshold voltage V.sub.th of the device driving
transistor TR.sub.D, however, the device driving transistor
TR.sub.D is put in a turned-off state in which the electric
potential appearing on the second node ND.sub.2 is about equal to
an electric-potential difference of (V.sub.Sig-V.sub.th).
[0023] Later on, a driving current flows from the first
power-supply line PS.sub.1 to the light emitting device ELP by way
of the device driving transistor TR.sub.D, driving the light
emitting device ELP to emit light.
[0024] The process is explained in detail by referring to the
diagrams of FIGS. 16A and 16D as follows. At the beginning of a
(m+1) th horizontal scan period not shown, the electric potential
appearing on the scan line SCL.sub.m is changed from a low level to
a high level. Afterwards, the electric potential appearing on the
third/fourth-transistor control line CL.sub.m is changed conversely
from a high level to a low level. It is to be noted that, at that
time, the electric potential appearing on the scan line SCL.sub.m-1
is sustained at a high level. As a result, each of the third
transistor TR.sub.3 and the fourth transistor TR.sub.4 is put in a
turned-on state whereas each of the signal writing transistor
TR.sub.W, the first transistor TR.sub.1 and the second transistor
TR.sub.2 is conversely put in a turned-off state.
[0025] During the (m+1) th horizontal scan period, a driving
voltage V.sub.CC is applied to the specific one of the source and
drain areas of the device driving transistor TR.sub.D through the
third transistor TR.sub.3 which has been put in the turned-on
state. The other one of the source and drain areas of the device
driving transistor TR.sub.D is connected to the specific electrode
of the light emitting device ELP by the fourth transistor TR.sub.4
which has been put in the turned-on state.
[0026] Since the driving current flowing through the light emitting
device ELP is a source-to-drain current I.sub.ds flowing from the
source area of the device driving transistor TR.sub.D to the drain
area of the same transistor, if the device driving transistor
TR.sub.D is ideally operating in a saturated region, the driving
current can be expressed by Eq. (A) given below. As shown in the
circuit diagram of FIG. 16D, the source-to-drain current I.sub.ds
is flowing to the light emitting device ELP, and the light emitting
device ELP is emitting light at a luminance determined by the
magnitude of the source-to-drain current I.sub.ds.
I.sub.ds=k*.mu.*(V.sub.gs-V.sub.th).sup.2 (A)
[0027] In the above equation, reference notation .mu. denotes the
effective mobility of the device driving transistor TR.sub.D
whereas reference notation L denotes the length of the channel of
the device driving transistor TR.sub.D. Reference notation W
denotes the width of the channel of the device driving transistor
TR.sub.D. Reference notation V.sub.gs denotes a voltage applied
between the source area of the device driving transistor TR.sub.D
and the gate electrode of the same transistor. Reference notation
C.sub.0X denotes a quantity expressed by the following
expression:
(Specific dielectric constant of the gate insulation layer of the
device driving transistor TR.sub.D).times.(Vacuum dielectric
constant)/(Thickness of the gate insulation layer of the device
driving transistor TR.sub.D)
[0028] Reference notation k denotes an expression as follows:
k=(1/2)*(W/L)*C.sub.0X
[0029] The voltage V.sub.gs applied between the source area of the
device driving transistor TR.sub.D and the gate electrode of the
same transistor is expressed as follows:
V.sub.gs.apprxeq.V.sub.CC-(V.sub.Sig-V.sub.th) (B)
[0030] By substituting the expression on the right-hand side of Eq.
(B) into the expression on the right-hand side of Eq. (A) to serve
as a replacement of the term V.sub.gs included in the expression on
the right-hand side of Eq. (A), Eq. (C) can be derived from Eq. (A)
as follows:
I ds = k * .mu. * ( V CC - ( V Sig - V th ) - V th ) 2 = k * .mu. *
( V CC - V Sig ) 2 ( C ) ##EQU00001##
[0031] As is obvious from Eq. (C), the source-to-drain current
I.sub.ds is not dependent on the threshold voltage V.sub.th of the
device driving transistor TR.sub.D. In other words, it is possible
to generate the source-to-drain current I.sub.ds in accordance with
the video signal V.sub.Sig as a current flowing to the light
emitting device ELP with a magnitude not affected by the threshold
voltage V.sub.th of the device driving transistor TR.sub.D. In
accordance with the driving method described above, variations of
the threshold voltage V.sub.th of the device driving transistor
TR.sub.D from transistor to transistor by no means have an effect
on the luminance of light emitted by the light emitting device
ELP.
SUMMARY OF THE INVENTION
[0032] In order to operate the driving circuit described above, the
display apparatus additionally requires a separate power-supply
line for supplying the driving voltage V.sub.CC, a separate
power-supply line for supplying the cathode voltage V.sub.Cat and a
separate power-supply line for supplying the initialization voltage
V.sub.Ini. If the layouts of wires and the driving circuit are to
be taken into consideration, however, it is desirable to provide
only few power-supply lines.
[0033] In order to solve the problems described above, inventors of
the present invention have innovated a display apparatus allowing
the number of power-supply lines to be reduced and innovated a
driving method for driving the display apparatus.
[0034] In order to solve the problems described above, there is
provided a display apparatus according an embodiment of to the
present invention or a display apparatus to which a driving method
according to the embodiment of the present invention is applied.
The display apparatus employs:
[0035] (1): N.times.M light emitting units laid out to form a
two-dimensional matrix composed of N matrix columns oriented in a
first direction and M matrix rows oriented in a second
direction;
[0036] (2): M scan lines each stretched in the first direction;
and
[0037] (3): N data lines each stretched in the second
direction.
[0038] Each of the light emitting units includes:
[0039] (4): a driving circuit, which has a signal writing
transistor, a device driving transistor, a capacitor and a first
switch circuit; and
[0040] (5): a light emitting device for emitting light at a
luminance according to a driving current output by the device
driving transistor.
[0041] In each of the light emitting units,
[0042] (A-1): a specific one of the source and drain areas of the
signal writing transistor is connected to one of the data
lines;
[0043] (A-2): the gate electrode of the signal writing transistor
is connected to one of the scan lines;
[0044] (B-1): a specific one of the source and drain areas of the
device driving transistor is connected to the other one of the
source and drain areas of the signal writing transistor through a
first node;
[0045] (C-1): a specific one of the terminals of the capacitor is
connected to a second power-supply line conveying a reference
voltage determined in advance;
[0046] (C-2): the other one of the terminals of the capacitor is
connected to the gate electrode of the device driving transistor
through a second node;
[0047] (D-1): a specific one of the terminals of the first switch
circuit is connected to the second node;
[0048] (D-2): the other one of the terminals of the first switch
circuit is connected to the other one of the source and drain areas
of the device driving transistor; and
[0049] (E): the driving circuit further has a second switch circuit
connected between the second node and a data line.
[0050] The driving method provided for the display apparatus
according to the embodiment of the present invention to serve as a
driving method for solving the problems described above has a
second-node electric-potential initialization process of applying a
predetermined initialization voltage appearing on the data line to
the second node by way of the second switch circuit put in a
turned-on state and, then, putting the second switch circuit in a
turned-off state in order to set an electric potential appearing on
the second node at a reference electric potential determined in
advance.
[0051] The display apparatus according to the embodiment of the
present invention is provided with a second switch circuit
connected between the second node and the data line. Thus, a
predetermined initialization voltage appearing on the data line can
be applied to the second node. Since a separate power-supply line
for applying the initialization voltage determined in advance to
the second node is not required, the number of power-supply lines
can be reduced. To put it more concretely, during every scan
period, the initialization voltage determined in advance needs to
be asserted on the data line to be followed by a video signal
asserted on the same data line to serve as a substitute for the
initialization voltage. A ratio of a sub-period occupied by the
initialization voltage determined in advance to a sub-period
occupied by the video signal needs to be properly determined at a
stage of designing the display apparatus.
[0052] As will be described later, in accordance with a driving
method provided by the embodiment of the present invention to serve
as a method for driving the display apparatus provided by the
embodiment of the present invention, the second switch circuit is
put in a turned-on state with a timing adjusted to a period used
for asserting the initialization voltage determined in advance on
the data line whereas the signal writing transistor is put in a
turned-on state with a timing adjusted to a period used for
asserting the video signal on the data line. Thus, even if the
separate power-supply line for applying the initialization voltage
determined in advance to the second node is eliminated, the display
apparatus can be driven without causing any problems.
[0053] In addition, the driving method provided by the embodiment
of the present invention to serve as a method for driving the
display apparatus provided by the embodiment of the present
invention has a signal writing process of changing an electric
potential appearing on the second node toward an electric
potential, which is obtained as a result of subtracting the
threshold voltage of the device driving transistor from the voltage
of a video signal appearing on the data line, by applying the video
signal to the first node by way of the signal writing transistor
which is put in a turned-on state by a signal appearing on the scan
line when the first switch circuit is put in a turned-on state in
order to put the second node in a state of being electrically
connected to the other one of the source and drain areas of the
device driving transistor. In this case, it is possible to provide
a desirable configuration in which, prior to the signal writing
process, the second-node electric-potential initialization process
described above is carried out. On top of that, the driving method
also has a light emission process of allowing a driving current,
which is generated by the device driving transistor by application
of a driving voltage determined in advance to the first node, to
flow to the light emitting device in order to drive the light
emitting device to emit light. In this case, it is possible to
provide a desirable configuration in which the light emission
process is carried out after the signal writing process described
above.
[0054] With the desirable configuration in which the light emission
process is carried out after the signal writing process, it is
possible to provide a desirable configuration including a
second-node electric-potential correction process to be carried out
between the signal writing process and the light emission process
as a process of changing an electric potential appearing on the
second node by applying a voltage having a magnitude determined in
advance to the first node for a time period determined in advance
with the first switch circuit already put in a turned-on state in
order to put the second node in a state of being electrically
connected to the other one of the source and drain areas of the
device driving transistor. In this case, the driving voltage
mentioned above can be applied to the first node to serve as the
voltage having a magnitude determined in advance.
[0055] The driving method provided for the display apparatus
according to the embodiment of the present invention to serve as a
driving method including the desirable configurations described
above can be configured to make use of a voltage with a fixed
magnitude as the initialization voltage. As an alternative, the
driving method is configured to make use of a voltage with a
magnitude varying in accordance with the video signal as the
initialization voltage. By making use of a voltage with a fixed
magnitude as the initialization voltage, the driving method offers
a merit that the configuration of a circuit for supplying the
initialization voltage can be made simple. By making use of a
voltage with a magnitude varying in accordance with the video
signal as the initialization voltage, on the other hand, the
driving method offers a merit that the electric potential appearing
on the second node can be changed in a short period of time by
execution of the signal writing process toward an electric
potential which is obtained as a result of subtracting the
threshold voltage of the device driving transistor from the voltage
of a video signal appearing on the data line.
[0056] In the case of the configuration of making use of a voltage
with a magnitude varying in accordance with the video signal as the
initialization voltage, the display apparatus is further provided
with a voltage conversion circuit having a voltage reduction
circuit. In this case, a video signal is supplied to the voltage
conversion circuit and, in execution of the second-node
electric-potential initialization process, the voltage reduction
circuit employed in the voltage conversion circuit applies a
voltage obtained as a result of subtracting a voltage having a
constant magnitude from the voltage of the video signal to the data
line as the initialization voltage.
[0057] The voltage conversion circuit and the voltage reduction
circuit employed in the voltage conversion circuit are not
prescribed in particular. In the case of a configuration in which
the input side of the voltage conversion circuit is used for
receiving a video signal and the output side of the voltage
conversion circuit is connected to the data line, the video signal
is supplied to the data line through the voltage reduction circuit
in the execution of the second-node electric-potential
initialization process. In the execution of the signal writing
process, on the other hand, the video signal is supplied to the
data line directly. The operation to supply the video signal to the
data line through the voltage reduction circuit is properly
switched to the operation to supply the video signal to the data
line directly and vice versa by making use of a commonly known
component such as a transistor. In addition, a circuit having a
generally known configuration can be used as the voltage reduction
circuit. The fact that the voltage reduction circuit can be
implemented as a diode-wired transistor makes it convenient to
manufacture typically the voltage reduction circuit and the driving
circuit for driving the light emitting device by carrying out the
same manufacturing process. For example, the voltage reduction
circuit is designed as two diode-wired transistors connected to
each other to form a series circuit. In this case, each of the
diode-wired transistors and the device driving transistor can be
designed as transistors of the same structure. In the case of a
voltage reduction circuit designed as two diode-wired transistors
connected to each other to form a series circuit, the voltage
reduction circuit applies a voltage obtained as a result of
subtracting twice the threshold voltage of the device driving
transistor from the voltage of the video signal to the data line as
the initialization voltage. The voltage reduction circuit designed
as two diode-wired transistors connected to each other to form a
series circuit offers a merit that the device driving transistor
can be set in a turned-on state after the second-node
electric-potential initialization process with a high degree of
reliability.
[0058] A display apparatus according to the embodiment of the
present invention and a display apparatus driven by adoption of a
driving method according to the embodiment of the present invention
are collectively referred to hereafter also as a display apparatus
provided by the embodiment. It is possible to provide the display
apparatus provided by the embodiment with a configuration in which
the driving circuit further employs:
[0059] (F): a third switch circuit connected between the first node
and a power-supply line conveying a driving voltage; and
[0060] (G): a fourth switch circuit connected between the other one
of the source and drain areas of the device driving transistor and
the specific one of the electrodes of the light emitting
device.
[0061] In addition, it is possible to configure the driving method
for driving the display apparatus provided by the embodiment to
serve as a display apparatus including the desirable configurations
described above to have the steps of:
[0062] (a): carrying out a second-node electric-potential
initialization process of sustaining each of the first, third and
fourth switch circuits in a turned-off state and applying the
predetermined initialization voltage appearing on the data line to
the second node by way of the second switch circuit put in a
turned-on state and, then, putting the second switch circuit in a
turned-off state in order to set an electric potential appearing on
the second node at a reference electric potential determined in
advance as the initialization voltage;
[0063] (b): carrying out a signal writing process of sustaining
each of the second, third and fourth switch circuits in a
turned-off state and putting the first switch circuit in a
turned-on state to put the second node in a state of being
electrically connected to the other one of the source and drain
areas of the device driving transistor so as to apply a video
signal appearing on one of the data lines to the first node by way
of the signal writing transistor put in a turned-on state by a
signal appearing on one of the scan lines in order to change an
electric potential appearing on the second node toward an electric
potential obtained as a result of subtracting the threshold voltage
of the device driving transistor from the video signal;
[0064] (c): applying a signal asserted on one of the scan lines to
the gate electrode of the signal writing transistor later on in
order put the signal writing transistor in a turned-off state;
and
[0065] (d): carrying out a light emission process of putting the
first switch circuit in a turned-off state, sustaining the second
switch circuit in a turned-off state, applying a driving voltage
determined in advance from the power-supply line to the first node
by way of the third switch circuit which has already been put in a
turned-on state and putting the other one of the source and drain
areas of the device driving transistor in a state of being
electrically connected to the specific one of the electrodes of the
light emitting device by way of the fourth transistor put in a
turned-on state so as to allow a driving current to flow from the
device driving transistor to the light emitting device in order to
drive the light emitting device.
[0066] In addition, it is possible to provide a configuration in
which, between the steps (c) and (d), a second-node
electric-potential correction process is carried out in order to
change an electric potential appearing on the second node by
applying the driving voltage as a voltage with a magnitude
determined in advance to the first node for a period determined in
advance with the first switch circuit sustained in a turned-on
state and the third switch circuit put in a turned-on state.
[0067] In the display apparatus provided by the embodiment, it is
possible to make use of a light emitting device emitting light at a
luminance determined by the magnitude of a driving current flowing
through the light emitting device to serve as the light emitting
device employed in every light emitting unit included in the
display apparatus. Typical examples of the light emitting device
are an organic EL (Electro Luminescence) light emitting device, an
inorganic EL light emitting device, an LED (light emitting diode)
light emitting device and a semiconductor laser light emitting
device. If construction of a color planar display apparatus is to
be taken into consideration, it is desirable to make use of the
organic EL light emitting device to serve as the light emitting
device employed in every light emitting unit included in the
display apparatus.
[0068] In the display apparatus provided by the embodiment, a
reference voltage determined in advance is supplied to a specific
one of the terminals of the capacitor. Thus, an electric potential
appearing on the specific one of the terminals of the capacitor is
sustained at the reference voltage determined in advance during an
operation carried out by the display apparatus. The magnitude of
the reference voltage determined in advance is not prescribed in
particular. For example, it is also possible to provide a desirable
configuration in which the specific one of the terminals of the
capacitor is connected to a power line conveying the driving
voltage and the driving voltage is applied as a reference voltage.
As an alternative, it is also possible to provide a desirable
configuration in which the specific one of the terminals of the
capacitor is connected to a power line conveying a predetermined
voltage to be applied to the other one of the electrodes of the
light emitting device and the specific one of the terminals of the
capacitor as a reference voltage.
[0069] In the display apparatus provided by the embodiment of the
present invention as a display apparatus with the desirable
configurations described above, a commonly known configuration and
a commonly known structure can be used respectively as the
configuration and structure of each of a variety of lines such as
the scan lines, the data lines and the power-supply lines. In
addition, a commonly known configuration and a commonly known
structure can be used respectively as the configuration and
structure of the light emitting device. To put it more concretely,
if an organic EL light emitting device is used to serve as the
light emitting device employed in every light emitting unit,
typically, the organic EL light emitting device can be configured
to include components such as an anode electrode, a hole transport
layer, a light emitting layer, an electron transport layer and a
cathode electrode. On top of that, a commonly known configuration
and a commonly known structure can be used respectively as the
configuration and structure of each of a variety of circuits such
as a scan circuit connected to the scan lines and a signal
outputting circuit connected to the data lines.
[0070] The display apparatus provided by the embodiment of the
present invention can have the configuration of the so-called
monochrome display apparatus. As an alternative, the display
apparatus provided by the embodiment of the present invention can
have a configuration in which a pixel includes a plurality of
sub-pixels. To put it more concretely, the display apparatus
provided by the embodiment of the present invention can have a
configuration in which a pixel includes three sub-pixels, i.e., a
red-light emitting sub-pixel, a green-light emitting sub-pixel and
a blue-light emitting sub-pixel. In addition, each of the three
sub-pixels having types different from each other can be a set
including an additional sub-pixel of a type determined in advance
or a plurality of additional sub-pixels having types different from
each other. For example, the set includes an additional sub-pixel
for emitting light having the white color for increasing the
luminance. As another example, the set includes an additional
sub-pixel for emitting light having a complementary color for
enlarging a color reproduction range. As a further example, the set
includes an additional sub-pixel for emitting light having the
yellow color for enlarging a color reproduction range. As a still
further example, the set includes an additional sub-pixel for
emitting light having the yellow and cyan colors for enlarging a
color reproduction range.
[0071] Each of the signal writing transistor and the device driving
transistor can be configured by making use of a TFT (Thin Film
Transistor) of a p-channel type. It is to be noted that the signal
writing transistor can be configured by making use of a TFT of an
n-channel type. Each of the first, second, third and fourth switch
circuits can be configured by making use of a commonly known
switching device such as a TFT. For example, each of the first,
second, third and fourth switch circuits can be configured by
making use of a TFT of the p-channel type or a TFT of the n-channel
type.
[0072] The capacitor employed in the driving circuit can be
typically configured to include a specific electrode, another
electrode and a dielectric layer sandwiched by the electrodes. The
dielectric layer is an insulation layer. Each of the transistors
and the capacitor, which compose the driving circuit, is created
within a certain plane. For example, each of the transistors and
the capacitor is created on a support body. If the light emitting
device is an organic EL light emitting device for example, the
light emitting device is created above the transistors and the
capacitor composing the device driving transistor through the
insulation layer. The other one of the source and drain areas of
the device driving transistor is connected to a specific one of the
electrodes of the light emitting device by way of another
transistor. In the typical configuration shown in the diagram of
FIG. 1, the specific electrode of the light emitting device is the
anode electrode. Please be advised that it is possible to provide a
configuration in which each of the transistors is created on a
semiconductor substrate or the like.
[0073] The technical phrase `the specific one of the two source and
drain areas of a transistor` may be used to imply the source or
drain area connected to a power supply in some cases. The turned-on
state of a transistor is a state in which a channel has been
created between the source and drain areas of the transistor. There
is not raised a question as to whether a current is flowing from
the specific one of the source and drain areas of the transistor to
the other one of the source and drain areas of the transistor or
vice versa in the turning-on state of the transistor. On the other
hand, the turned-off state of a transistor is a state in which no
channel has been created between the source and drain areas of the
transistor. A particular one of the source and drain areas of a
transistor is connected to a particular one of the source and drain
areas of another transistor by creating the particular source and
drain areas of the two transistors as areas occupying the same
region. In addition, it is possible to create a source or drain
area of a transistor from not only a conductive material, but also
a layer made of substances of different kinds. Typical examples of
the conductive material are poly-silicon and amorphous silicon
which include impurities. The substances for making the layer
include a metal, an alloy, conductive particles, a laminated
structure of a metal, an alloy and conductive particles as well as
an organic material (or a conductive polymer). In every timing
chart referred to in the following description, the length of a
time period along the horizontal axis representing the lapse of
time is no more than a model quantity and does not necessarily
represent a magnitude relative to a reference on the horizontal
axis.
[0074] In the display apparatus provided by the embodiment of the
present invention, the driving circuit further has a second switch
circuit connected between the second node and the data line. The
driving method can apply a predetermined initialization voltage to
the second node. Thus, it is not necessary to separately provide a
power-supply line for supplying the initialization voltage
determined in advance. Thus, the number of power-supply lines can
be reduced.
[0075] In accordance with a driving method provided by the
embodiment of the present invention to serve as a method for
driving the display apparatus provided by the embodiment of the
present invention, the second switch circuit is put in a turned-on
state with a timing adjusted to a period used for asserting the
initialization voltage determined in advance on the data line
whereas the signal writing transistor is put in a turned-on state
with a timing adjusted to a period used for asserting the video
signal on the data line. Thus, even if the separate power-supply
line for applying the initialization voltage determined in advance
to the second node is eliminated, the display apparatus can be
driven without causing any problems.
BRIEF DESCRIPTION OF THE DRAWINGS
[0076] The innovations and features of the present invention will
become clear from the following description of the preferred
embodiments given with reference to the accompanying diagrams, in
which:
[0077] FIG. 1 is a diagram showing an equivalent circuit of a
driving circuit employed in a light emitting unit located at the
intersection of an mth matrix row and an nth matrix column in a
two-dimensional matrix of N.times.M light emitting units employed
in a display apparatus according to a first embodiment;
[0078] FIG. 2 is a conceptual diagram showing the display apparatus
according to the first embodiment;
[0079] FIG. 3 is a model cross-sectional diagram showing the cross
section of a portion of the light emitting unit employed in the
display apparatus shown in the conceptual diagram of FIG. 2;
[0080] FIG. 4 is a timing diagram showing a model of timing charts
of signals involved in driving operations carried out by the
display apparatus according to the first embodiment;
[0081] FIGS. 5A to 5D are model circuit diagrams showing turned-on
and turned-off states of transistors in the driving circuit;
[0082] FIG. 6 is a diagram showing the equivalent circuit of a
driving circuit included in a light emitting unit located at the
intersection of an mth matrix row and an nth matrix column in a
two-dimensional matrix of N.times.M light emitting units employed
in a display apparatus according to a second embodiment;
[0083] FIG. 7 is a conceptual diagram showing the display apparatus
according to the second embodiment;
[0084] FIG. 8 is a timing diagram showing a model of timing charts
of signals involved in driving operations carried out by the
display apparatus according to the second embodiment;
[0085] FIGS. 9A and 9B are model circuit diagrams showing turned-on
and turned-off states of transistors in the driving circuit;
[0086] FIG. 10 is a diagram showing the equivalent circuit of a
driving circuit included in a light emitting unit located at the
intersection of an mth matrix row and an nth matrix column in a
two-dimensional matrix of N.times.M light emitting units employed
in a display apparatus according to a third embodiment;
[0087] FIG. 11 is a conceptual diagram showing the display
apparatus according to the third embodiment;
[0088] FIG. 12 is a circuit diagram showing a model of a voltage
conversion circuit employed in the third embodiment;
[0089] FIG. 13 is a model timing diagram showing timing charts
referred to in explanation of operations carried out by the voltage
conversion circuit as timing charts of turned-on and turned-off
states of signal switching sections as well as turned-on and
turned-off states of first and second transistors;
[0090] FIG. 14 is a model timing diagram showing timing charts of
driving operations carried out by the display apparatus as timing
charts to be referred to in explanation of a driving method
according to the third embodiment;
[0091] FIG. 15 is a diagram showing the equivalent circuit of a
driving circuit included in a light emitting unit located at the
intersection of an mth matrix row and an nth matrix column in a
two-dimensional matrix of N.times.M light emitting units employed
in a display apparatus;
[0092] FIG. 16A is a model timing diagram showing timing charts of
signals appearing on a scan line SCL.sub.m-1, a scan line SCL.sub.m
and a third/fourth-transistor control line CL.sub.m; and
[0093] FIG. 16B to 16D are model circuit diagrams showing turned-on
and turned-off states of transistors in the driving circuit.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0094] Preferred embodiments of the invention are explained by
referring to diagrams as follows.
First Embodiment
[0095] A first embodiment implements a display apparatus provided
by the present invention and a driving method provided by the
present invention to serve as a method for driving the display
apparatus. The display apparatus according to the first embodiment
of the present invention is an organic EL (Electro Luminescence)
display apparatus employing a plurality of light emitting units 10,
which each have an organic EL light emitting device ELP and a
driving circuit 11 for driving the organic EL light emitting
device. In the following description, the light emitting unit is
also referred to as a pixel circuit in some cases. First of all, an
outline of the display apparatus is explained.
[0096] The display apparatus according to the first embodiment is a
display apparatus employing a plurality of pixel circuits. Every
pixel circuit is configured to include a plurality of sub-pixel
circuits. Every sub-pixel circuit is the light emitting unit 10
which has a laminated structure composed of the driving circuit 11
and the light emitting device ELP connected to the driving circuit
11. FIG. 1 is a diagram showing an equivalent circuit of the
driving circuit 11 employed in the light emitting unit 10 located
at the intersection of an mth matrix row and an nth matrix column
in a two-dimensional matrix in which N.times.M light emitting units
10 employed in a display apparatus are laid out to form a
two-dimensional matrix composed of N columns and M rows where
suffix or notation m denotes an integer having a value of 1, 2, . .
. or M and notation n denotes an integer having a value of 1, 2, .
. . or N. FIG. 2 is a conceptual diagram showing the display
apparatus.
[0097] As shown in the conceptual diagram of FIG. 2, the display
apparatus employs:
[0098] (1): N.times.M light emitting units 10 laid out to form a
two-dimensional matrix composed of N matrix columns oriented in a
first direction and M matrix rows oriented in a second
direction;
[0099] (2): M scan lines SCL each stretched in the first direction;
and
[0100] (3): N data lines DTL each stretched in the second
direction.
[0101] Each of the scan lines SCL is connected to a scan circuit
101 whereas each of the data lines DTL is connected to a signal
outputting circuit 102. The conceptual diagram of FIG. 2 shows
3.times.3 light emitting units 10 centered at a light emitting unit
10 located at the intersection of the mth matrix row and the nth
matrix column. It is to be noted, however, that the configuration
shown in the conceptual diagram of FIG. 2 is no more than a typical
configuration. In addition, the conceptual diagram of FIG. 2 does
not show the power-supply lines PS.sub.1 and PS.sub.2 shown in the
diagram of FIG. 1 to serve as the first and second power-supply
lines for conveying the power-supply voltage V.sub.CC and the
cathode voltage V.sub.Cat respectively.
[0102] In the case of a color display apparatus, the
two-dimensional matrix composed of N matrix columns and M matrix
rows has (N/3).times.M pixel circuits. However, every pixel circuit
is configured to include three sub-pixels, i.e., a red-light
emitting sub-pixel, a green-light emitting sub-pixel and a
blue-light emitting sub-pixel. Thus, the two-dimensional matrix has
N.times.M sub-pixel circuits which are each the light emitting unit
10 described above. The light emitting units 10 are sequentially
scanned by the scan circuit 101 in row units on a row-after-row
basis at a display frame rate of FR times per second. That is to
say, (N/3) pixel circuits (or N sub-pixel circuits each functioning
as the light emitting unit 10) arranged along the mth matrix row
are driven at the same time where suffix or notation m denotes an
integer having a value of 1, 2, . . . or M. In other words, the
light emission and no-light emission timings of the N light
emitting devices 10 arranged along the mth matrix row are
controlled in the same way.
[0103] The light emitting unit 10 employs a driving circuit 11 and
a light emitting device ELP. The driving circuit 11 has a signal
writing transistor TR.sub.W, a device driving transistor TR.sub.D,
a capacitor C.sub.1 and a first switch circuit SW.sub.1 which is a
first transistor TR.sub.1 to be described later. A driving current
generated by the device driving transistor TR.sub.D flows to the
light emitting device ELP. In the light emitting unit 10 located at
the intersection of mth matrix row and the nth matrix column, a
specific one of the source and drain areas of the signal writing
transistor TR.sub.W is connected to the data line DTL.sub.n whereas
the gate electrode of the signal writing transistor TR.sub.W is
connected to the scan line SCL.sub.m. A specific one of the source
and drain areas of the device driving transistor TR.sub.D is
connected to the other one of the source and drain areas of the
signal writing transistor TR.sub.W through a first node ND.sub.1. A
specific one of the terminals of the capacitor C.sub.1 is connected
to the first power-supply line PS.sub.1 for conveying a reference
voltage determined in advance. In the case of the first embodiment
shown in the diagram of FIG. 1, the reference voltage determined in
advance is a predetermined driving voltage V.sub.CC to be described
later. The other one of the terminals of the capacitor C.sub.1 is
connected to the gate electrode of the device driving transistor
TR.sub.D through a second node ND.sub.2.
[0104] Each of the device driving transistor TR.sub.D and the
signal writing transistor TR.sub.W is a TFT of the p-channel type.
The device driving transistor TR.sub.D is a depletion-type
transistor. As will be described later, each of the first
transistor TR.sub.1, the second transistor TR.sub.2, the third
transistor TR.sub.3 and the fourth transistor TR.sub.4 is also a
TFT of the p-channel type. It is to be noted that the signal
writing transistor TR.sub.W can be implemented as a TFT of the
n-channel type.
[0105] A commonly known configuration and a commonly known
structure can be used respectively as the configuration and
structure of each of the scan circuit 101, the signal outputting
circuit 102, the scan line SCL and the data line DTL. By the same
token, a commonly known configuration and a commonly known
structure can be used respectively as the configuration and
structure of each of the third/fourth-transistor controlling
circuit 111 and the second-transistor controlling circuit 112 which
will be described later.
[0106] In the same way as the scan circuit 101, the signal
outputting circuit 102, the scan line SCL and the data line
DTL.sub.n a commonly known configuration and a commonly known
structure can be used respectively as the configuration and
structure of each of the third/fourth-transistor control line CS,
the second-transistor control line CL2, the first power-supply line
PS.sub.1 and the second power-supply line PS.sub.2 which will be
described later.
[0107] FIG. 3 is a model cross-sectional diagram showing the cross
section of a portion of the light emitting unit 10 employed in the
display apparatus shown in the conceptual diagram of FIG. 2. As
will be described later in detail, every transistor and the
capacitor C.sub.1 which are employed in the driving circuit 11 of
the light emitting unit 10 are created on a support body 20 whereas
the light emitting device ELP is created over the transistors and
the capacitor C.sub.1. Typically, a first inter-layer insulation
layer 40 is sandwiched between the light emitting device ELP and
the driving circuit 11 which employs the transistors and the
capacitor C.sub.1. The organic EL light emitting device ELP has a
commonly known configuration and a commonly known structure which
include components such as an anode electrode, a hole transport
layer, a light emitting layer, an electron transport layer and a
cathode electrode. It is to be noted that the model cross-sectional
diagram of FIG. 3 shows only the device driving transistor TR.sub.D
while the other transistors are concealed and, thus, invisible. The
other one of the source and drain areas of the device driving
transistor TR.sub.D is connected to the anode electrode of the
light emitting device ELP through the fourth transistor TR.sub.4
not shown in the model cross-sectional diagram of FIG. 3. A portion
connecting the fourth transistor TR.sub.4 to the anode electrode of
the light emitting device ELP is also concealed and, thus,
invisible in the model cross-sectional diagram of FIG. 3.
[0108] The device driving transistor TR.sub.D is configured to
include a gate electrode 31, a gate insulation layer 32 and a
semiconductor layer 33. To put it more concretely, the device
driving transistor TR.sub.D has a specific source or drain area 35
and the other source or drain area 36 which are provided on the
semiconductor layer 33 as well as a channel creation area 34.
Sandwiched by the specific source or drain area 35 and the other
source or drain area 36, the channel creation area 34 is a portion
pertaining to the semiconductor layer 33. Each of the other
transistors not shown in the model cross-sectional diagram of FIG.
3 has the same configuration as the device driving transistor
TR.sub.D.
[0109] The capacitor C.sub.1 has a capacitor electrode 37, a
dielectric layer composed of an extension of the gate insulation
layer 32 and another capacitor electrode 38. It is to be noted that
a portion connecting the capacitor electrode 37 to the gate
electrode 31 of the device driving transistor TR.sub.D and a
portion connecting the capacitor electrode 38 to the second
power-supply line PS.sub.2 are concealed and, thus, invisible.
[0110] The gate electrode 31 of the device driving transistor
TR.sub.D, a portion of the gate insulation layer 32 of the device
driving transistor TR.sub.D and capacitor electrode 37 of the
capacitor C.sub.1 are created on the support body 20. Components
such as the device driving transistor TR.sub.D and the capacitor
C.sub.1 are covered by the first inter-layer insulation layer 40.
On the first inter-layer insulation layer 40, the light emitting
device ELP is provided. The light emitting device ELP has an anode
electrode 51, a hole transport layer, a light emitting layer, an
electron transport layer and a cathode electrode 53. It is to be
noted that, in the model cross-sectional diagram of FIG. 3, the
hole transport layer, the light emitting layer and the electron
transport layer are shown as a single layer 52. On a portion
pertaining to the first inter-layer insulation layer 40 as a
portion on which the light emitting device ELP does not exist, a
second inter-layer insulation layer 54 is provided. On the second
inter-layer insulation layer 54 and the cathode electrode 53, a
transparent substrate 21 is placed. Light emitted by the light
emitting layer is radiated to the outside of the light emitting
unit 10 by way of the transparent substrate 21. The cathode
electrode 53 and the wire 39 serving as the second power-supply
line PS.sub.2 are connected to each other by contact holes 56 and
55 provided on the second inter-layer insulation layer 54 and the
first inter-layer insulation layer 40.
[0111] A method for manufacturing the display apparatus shown in
the conceptual diagram of FIG. 2 is explained as follows. First of
all, components are created properly on the support body 20 by
adoption of an already known method. The components include lines
such as the scan lines, the electrodes of the capacitor C.sub.1,
the transistors each made of semiconductor layers, the inter-layer
insulation layers and contact holes. Then, film-creation and
patterning processes are carried out also by adoption of an already
known method in order to form the light emitting device ELP.
Subsequently, the support body 20 completing the processes
described above is positioned to face the transparent substrate 21.
Finally the surroundings of the support body 20 and the transparent
substrate 21 are sealed in order to finish the process of
manufacturing the display apparatus. Later on, if necessary, wiring
to external circuits is provided.
[0112] Next, by referring to the diagrams of FIGS. 1 and 2, the
following description explains the driving circuit 11 employed in
the light emitting unit 10 located at the intersection of the mth
matrix row and the nth matrix column. As described before, the
other one of the source and drain areas of the signal writing
transistor TR.sub.W is connected to the specific one of the source
and drain areas of the device driving transistor TR.sub.D. On the
other hand, the specific one of the source and drain areas of the
signal writing transistor TR.sub.W is connected to the data line
DTL.sub.n. Operations to put the signal writing transistor TR.sub.W
in a turned-on and turned-off states are controlled by a signal
asserted on the scan line SCL.sub.m connected to the gate electrode
of the signal writing transistor TR.sub.W.
[0113] As will be described later in detail, the signal outputting
circuit 102 asserts an initialization voltage V.sub.Ini determined
in advance or a video signal V.sub.Sig for controlling the
luminance of light emitted by the light emitting device ELP on the
data line DTL.sub.n. The video signal V.sub.Sig is also referred to
as a driving signal or a luminance signal.
[0114] In a light emission state of the light emitting unit 10, the
device driving transistor TR.sub.D is driven to generate a
source-to-drain current I.sub.ds, the magnitude of which is
expressed by Eq. (1) given below. In the light emission state of
the light emitting unit 10, the specific one of the source and
drain areas of the device driving transistor TR.sub.D is
functioning as the source area whereas the other one of the source
and drain areas of the device driving transistor TR.sub.D is
functioning as the drain area. In order to make the following
description easy to write just for the sake of convenience, in the
following description, the specific one of the source and drain
areas of the device driving transistor TR.sub.D is referred to as
the source area whereas the other one of the source and drain areas
of the device driving transistor TR.sub.D is referred to as the
drain area in some cases. In Eq. (1) given below, reference
notation a denotes the effective mobility of the device driving
transistor TR.sub.D whereas reference notation L denotes the length
of the channel of the device driving transistor TR.sub.D. Reference
notation W denotes the width of the channel of the device driving
transistor TR.sub.D. Reference notation V.sub.gs denotes a voltage
applied between the source area of the device driving transistor
TR.sub.D and the gate electrode of the same transistor. Reference
notation V.sub.th denotes the threshold voltage of the device
driving transistor TR.sub.D. Reference notation C.sub.0X denotes a
quantity expressed by the following expression:
(Specific dielectric constant of the gate insulation layer of the
device driving transistor TR.sub.D).times.(Vacuum dielectric
constant)/(Thickness of the gate insulation layer of the device
driving transistor TR.sub.D)
[0115] Reference notation k denotes an expression as follows:
k.ident.(1/2)*(W/L)*C.sub.0X
I.sub.ds=k*.mu.*(V.sub.gs-V.sub.th).sup.2 (1)
[0116] The driving circuit 11 is provided with a first switch
circuit SW.sub.1 connected between the second node ND.sub.2 and the
other one of the source and drain areas of the device driving
transistor TR.sub.D. The first switch circuit SW.sub.1 is
implemented as the first transistor TR.sub.1. The specific one of
the source and drain areas of the first transistor TR.sub.1 is
connected to the second node ND.sub.2 whereas the other one of the
source and drain areas of the first transistor TR.sub.1 is
connected to the other one of the source and drain areas of the
device driving transistor TR.sub.D. In the same way as the driving
circuit described earlier by referring to the diagram of FIG. 15 in
the section having a title of "BACKGROUND OF THE INVENTION," in the
case of the first embodiment, the gate electrode of the first
transistor TR.sub.1 is connected to the scan line SCL.sub.m. Each
of the first transistor TR.sub.1 and the signal writing transistor
TR.sub.W is controlled by a signal asserted on the scan line
SCL.sub.m.
[0117] In addition, the driving circuit 11 is also provided with a
second switch circuit SW.sub.2 connected between the second node
ND.sub.2 and the data line DTL.sub.n. The second switch circuit
SW.sub.2 is implemented as the second transistor TR.sub.2. A
specific one of the source and drain areas of the second transistor
TR.sub.2 is connected to the data line DTL.sub.n whereas the other
one of the source and drain areas of the second transistor TR.sub.2
is connected to the second node ND.sub.2. The gate electrode of the
second transistor TR.sub.2 is connected to the second-transistor
control line CL2.sub.m. The second-transistor control line
CL2.sub.m is connected to the second-transistor controlling circuit
112. The second-transistor controlling circuit 112 applies a signal
to the gate electrode of the second transistor TR.sub.2 by way of
the second-transistor control line CL2.sub.m in order to control an
operation to put the second transistor TR.sub.2 in a turned-on
state or a turned-off state.
[0118] In addition, the driving circuit 11 is also provided with a
third switch circuit SW.sub.3 connected between the first node
ND.sub.1 and the first power-supply line PS.sub.4 for conveying the
driving voltage V.sub.CC to be described later. On top of that, the
driving circuit 11 is further provided with a fourth switch circuit
SW.sub.4 connected between the other one of the source and drain
areas of the device driving transistor TR.sub.D and a specific one
of the electrodes of the light emitting device ELP. The third
switch circuit SW.sub.3 is implemented as the third transistor
TR.sub.3. A specific one of the source and drain areas of the third
transistor TR.sub.3 is connected to the first power-supply line
PS.sub.4 whereas the other one of the source and drain areas of the
third transistor TR.sub.3 is connected to the first node ND.sub.1.
The fourth switch circuit SW.sub.4 is implemented as the fourth
transistor TR.sub.4. A specific one of the source and drain areas
of the fourth transistor TR.sub.4 is connected to the other one of
the source and drain areas of the device driving transistor
TR.sub.D whereas the other one of the source and drain areas of the
fourth transistor TR.sub.4 is connected to the specific one of the
electrodes of the light emitting device ELP. The other electrode of
the light emitting device ELP is the cathode electrode of the light
emitting device ELP. The cathode electrode of the light emitting
device ELP is connected to the second power-supply line PS.sub.2
for conveying a cathode voltage V.sub.Cat to be described later.
Reference notation C.sub.EL denotes the parasitic capacitance of
the light emitting device ELP.
[0119] In the same way as the driving circuit described earlier in
the section with a title of "BACKGROUND OF THE INVENTION" by
referring to the diagram shown in FIG. 15, in the first embodiment,
the gate electrodes of the third transistor TR.sub.3 and the fourth
transistor TR.sub.4 are connected to the third/fourth-transistor
control line CL.sub.m. The third/fourth-transistor control line
CL.sub.m is connected to the third/fourth-transistor controlling
circuit 111. The third/fourth-transistor controlling circuit 111
supplies a signal to the gate electrodes of the third transistor
TR.sub.3 and the fourth transistor TR.sub.4 through the
third/fourth-transistor control line CL.sub.m in order to put the
third transistor TR.sub.3 and the fourth transistor TR.sub.4 in a
turned-on state or a turned-off state.
[0120] In the explanation of the first an other embodiments, a
variety of voltages and electric potentials have the following
typical values even though the values shall be regarded as values
merely used in the explanation and are not to be interpreted as
limitations imposed on the voltages and the electric potentials. It
is to be noted that, in the case of a third embodiment to be
described later, a voltage with a magnitude varying in accordance
with the video signal is used as the initialization voltage
V.sub.Ini. Thus, as described later, the initialization voltage
V.sub.Ini has a variety of magnitudes.
[0121] Reference notation V.sub.Sig denotes a video signal for
controlling the luminance of light emitted by the light emitting
device ELP. The video signal V.sub.Sig has a typical value in the
range 0 volt representing the maximum luminance to 8 volts
representing the minimum luminance.
[0122] Reference notation V.sub.CC denotes a driving voltage. The
reference voltage V.sub.CC applied to the first power-supply line
PS.sub.1 has a typical value of 10 volts.
[0123] Reference notation V.sub.Ini denotes an initialization
voltage serves as a voltage for initializing an electric potential
appearing on the second node ND.sub.2. The initialization voltage
V.sub.Ini has a typical value of -4 volts.
[0124] Reference notation V.sub.th denotes the threshold voltage of
the device driving transistor TR.sub.D. The threshold voltage
V.sub.th has a typical value of 2 volts.
[0125] Reference notation V.sub.Cat denotes a voltage applied to
the second power-supply line PS.sub.2. The cathode voltage
V.sub.Cat has a typical value of -10 volts.
[0126] The following description explains driving operations
carried out by the display apparatus on the light emitting unit 10
located at the intersection of the mth matrix row and the nth
matrix column. In the following description, the light emitting
unit 10 located at the intersection of the mth matrix row and the
nth matrix column is also referred to simply as the (n, m)th light
emitting unit 10 or the (n, m)th sub-pixel circuit. The horizontal
scan period of the light emitting units 10 arranged along the mth
matrix row is referred to hereafter simply as the mth horizontal
scan period. To put it more concretely, the horizontal scan period
of the light emitting units 10 arranged along the mth matrix row is
the mth horizontal scan period of a currently displayed frame. The
driving operations described below are also carried out on other
embodiments to be described later.
[0127] A model of timing charts of signals involved in the driving
operations carried out by the display apparatus is shown in the
timing diagram of FIG. 4. FIGS. 5A and 5B are a plurality of model
circuit diagrams referred to in description of driving operations
carried out by the display apparatus. To be more specific, FIGS. 5A
to 5D are model circuit diagrams showing turned-on and turned-off
states of transistors in the driving circuit 11.
[0128] The driving method for the driving apparatus according to
the first embodiment has a second-node electric-potential
initialization process of applying a predetermined initialization
voltage V.sub.Ini appearing on the data line DTL.sub.n to the
second node ND.sub.2 by way of the second switch circuit SW.sub.2
put in a turned-on state and, then, putting the second switch
circuit SW.sub.2 in a turned-off state in order to set an electric
potential appearing on the second node ND.sub.2 at a reference
electric potential determined in advance. To put it more
concretely, the second-node electric-potential initialization
process is carried out during a period TP(1).sub.0 shown in the
timing diagram of FIG. 4.
[0129] The driving method according to the first embodiment has a
signal writing process of changing an electric potential appearing
on the second node ND.sub.2 toward an electric potential, which is
obtained as a result of subtracting the threshold voltage V.sub.th
of the device driving transistor TR.sub.D from the voltage of a
video signal V.sub.Sig appearing the data line DTL.sub.n, by
applying the video signal V.sub.Sig to the first node ND.sub.1 by
way of the signal writing transistor TR.sub.W which is put in a
turned-on state by a signal appearing the scan line SCL.sub.m when
the first switch circuit SW.sub.1 is put in a turned-on state in
order to put the second node ND.sub.2 in a state of being
electrically connected to the other one of the source and drain
areas of the device driving transistor TR.sub.D. It is to be noted
that, after a second-node electric-potential initialization process
has been completed, the signal writing process is carried out. To
put it more concretely, the signal writing process is carried out
during a period TP(1).sub.1 shown in the timing diagram of FIG.
4.
[0130] As described above, in the case of the first embodiment, the
initialization voltage V.sub.Ini is a voltage having a fixed
magnitude. Also in the case of a second embodiment to be described
later, the initialization voltage V.sub.Ini is a voltage having a
fixed magnitude.
[0131] The driving method according to the first embodiment is
provided with a light emission process of allowing a driving
current, which is generated by the device driving transistor
TR.sub.D by application of a driving voltage V.sub.CC determined in
advance to the first node ND.sub.1, to flow to the light emitting
device ELP in order to drive the light emitting device ELP to emit
light. It is to be noted that the light emission process is carried
out after a signal writing process. To put it more concretely, the
light emission process is carried out in a period TP(1).sub.2
immediately following a period TP(1).sub.1 allocated to the signal
writing process as shown in a timing diagram of FIG. 4. The
following description explains details of an operation carried out
in each period shown in the timing diagram of FIG. 4.
Period TP(1).sub.-1 (with Reference to FIGS. 4 and 5A)
[0132] The period TP(1).sub.-1 serving as the period of a light
emission process is the period in which the light emitting unit 10
serving as the (n, m)th sub-pixel circuit is in an immediately
preceding light emission state of emitting light at a luminance
according to a video signal V'.sub.Sig written right before. Each
of the third transistor TR.sub.3 and the fourth transistor TR.sub.4
is put in a turned-on state whereas each of the signal writing
transistor TR.sub.W, the first transistor TR.sub.1 and the second
transistor TR.sub.2 is conversely put in a turned-off state.
Through the light emitting device ELP employed in the light
emitting unit 10 serving as the (n, m)th sub-pixel circuit, the
source-to-drain current I'.sub.ds expressed by Eq. (4) to be
described later is flowing. Thus, the light emitting device ELP
employed in the light emitting unit 10 serving as the (n, m)th
sub-pixel circuit is emitting light with a luminance determined by
the source-to-drain current I'.sub.ds.
[0133] In every horizontal scan period, the signal outputting
circuit 102 asserts the initialization voltage V.sub.Ini on a data
line DTL.sub.n before the signal outputting circuit 102 asserts a
video signal V.sub.Sig on the same data line DTL.sub.n to serve as
a substitute for the initialization voltage V.sub.Ini. To put it
more concretely, in the (m-1)th horizontal period, the signal
outputting circuit 102 asserts the initialization voltage V.sub.Ini
on the data line DTL.sub.n before the signal outputting circuit 102
asserts a video signal V.sub.Sig.sub.--.sub.m-1 for the (n, m-1) th
sub-pixel circuit on the same data line DTL.sub.n. Reference
notation V.sub.Sig.sub.--.sub.m-1 denotes a video signal for the
(n, m-1) th sub-pixel circuit. A video signal for any other
sub-pixel circuit is denoted by a reference notation having the
same format as V.sub.Sig.sub.--.sub.1. Since each of the signal
writing transistor TR.sub.W and the first transistor TR.sub.1 is
sustained in a turned-off state, the electric potential (or the
voltage) appearing on each of the first node ND.sub.1 and the
second node ND.sub.2 does not change even if the electric potential
(or the voltage) appearing on the data line DTL.sub.n changes. In
actuality, the electric potential (or the voltage) appearing on
each of the first node ND.sub.1 and the second node ND.sub.2 may
change due to an electrostatic coupling effect of a parasitic
capacitor or the like. However, the change of the electric
potential (or the voltage) appearing on each of the first node
ND.sub.1 and the second node ND.sub.2 can normally be ignored. It
is to be noted that, also in every horizontal scan period leading
ahead of the (m-1) th horizontal period of the currently displayed
frame, the signal outputting circuit 102 asserts the initialization
voltage V.sub.1 on a data line DTL.sub.n before the signal
outputting circuit 102 asserts a video signal V.sub.Sig on the same
data line DTL.sub.n to serve as a substitute for the initialization
voltage V.sub.Ini. However, the timing diagram of FIG. 4 does not
show the operations.
Period TP(1).sub.0 (with Reference to FIGS. 4 and 5B)
[0134] The period TP(1).sub.0 serving as the period of the
second-node electric-potential initialization process is the first
half of the mth horizontal scan period of the currently displayed
frame. During the period TP(1).sub.0, each of the first switch
circuit SW.sub.1, the third switch circuit SW.sub.2 and the fourth
switch circuit SW.sub.4 is sustained in a turned-off state. After
the initialization voltage V.sub.Ini determined in advance is
applied from the data line DTL, to the second node ND.sub.2 by way
of the second switch circuit SW.sub.2 which has already been put in
a turned-on state, the second switch circuit SW.sub.2 is put in a
turned-off state in order to set an electric potential appearing on
the second node ND.sub.2 at a predetermined reference voltage. The
process of setting the electric potential appearing on the second
node ND.sub.2 at the initialization voltage V.sub.Ini determined in
advance is referred to as the second-node electric-potential
initialization process.
[0135] To put it more concretely, each of the signal writing
transistor TR.sub.W and the first transistor TR.sub.1 is sustained
in a turned-off state whereas each of the third transistor TR.sub.2
and the fourth transistor TR.sub.4 is changed from a turned-on
state to a turned-off state. Thus, the driving voltage V.sub.CC is
not applied to the first node ND'. In addition, the light emitting
device ELP is electrically disconnected from the device driving
transistor TR.sub.D. As a result, the source-to-drain current
I.sub.ds does not flow to the light emitting device ELP, putting
the light emitting device ELP in a no-light emission state. In
addition, the second transistor TR.sub.2 is changed from a
turned-off state to a turned-on state so that the initialization
voltage V.sub.1 determined in advance is applied from the data line
DTL.sub.n to the second node ND.sub.2 by way of the second
transistor TR.sub.2 put in a turned-on state. Then, the second
transistor TR.sub.2 is typically put in a turned-off state before
the video signal V.sub.Sig.sub.--.sub.m is asserted on the data
line DTL.sub.n. In this state, the driving voltage V.sub.CC is
applied to a specific one of the terminals of the capacitor
C.sub.1, and an electric potential appearing on the specific
terminal of the capacitor C.sub.1 is put in a state of being
sustained. Thus, the electric potential appearing on the second
node ND.sub.2 is sustained at a predetermined level which is the
level of the initialization voltage V.sub.Ini of -4 volts.
Period TP(1).sub.4 (with Reference to FIGS. 4 and 5C)
[0136] The period TP(1).sub.4 serving as the period of the signal
writing process is the second half of the mth horizontal scan
period of the currently displayed frame. In the period TP.sub.1,
each of the second switch circuit SW.sub.2, the third switch
circuit SW.sub.2 and the fourth switch circuit SW.sub.4 is
sustained in a turned-off state whereas the first switch circuit
SW.sub.4 is conversely put in a turned-on state. With the first
switch circuit SW.sub.1 put in a turned-on state, the second node
ND.sub.2 is put in a state of being electrically connected to the
other one of the source and drain areas of the device driving
transistor TR.sub.D by way of the first switch circuit SW.sub.1. In
this state, the video signal V.sub.Sig.sub.--.sub.m asserted on the
data line DTL.sub.n is supplied to the first node ND.sub.1 by way
of the signal writing transistor TR.sub.W which has already been
put in a turned-on state by a signal asserted on the scan line
SCL.sub.m so that the electric potential appearing on the second
node ND.sub.2 is raised toward a level obtained as a result of
subtracting the threshold voltage V.sub.th of the device driving
transistor TR.sub.D from the video signal V.sub.Sig.sub.--.sub.m.
The process of raising the electric potential appearing on the
second node ND.sub.2 toward such a level is referred to as the
signal writing process.
[0137] To put it more concretely, each of the second transistor
TR.sub.2, the third transistor TR.sub.3 and the fourth transistor
TR.sub.4 is sustained in a turned-off state whereas each of the
signal writing transistor TR.sub.W and the first transistor
TR.sub.4 is put in a turned-on state by a signal asserted on the
scan line SCL.sub.m. With the first transistor TR.sub.1 put in a
turned-on state, the second node ND.sub.2 is put in a state of
being electrically connected to the other one of the source and
drain areas of the device driving transistor TR.sub.D through the
first transistor TR.sub.1. In addition, the video signal V.sub.Sig,
asserted on the data line DTL.sub.n is supplied to the first node
ND.sub.1 by way of the signal writing transistor TR.sub.W which is
put in a turned-on state by a signal asserted on the scan line
SCL.sub.m so that the electric potential appearing on the second
node ND.sub.2 is changed to a level obtained as a result of
subtracting the threshold voltage V.sub.th of the device driving
transistor TR.sub.D from the video signal
V.sub.Sig.sub.--.sub.m.
[0138] That is to say, at the beginning of the period TP(1).sub.1,
the electric potential appearing on the second node ND.sub.2 has
been initialized for putting the device driving transistor TR.sub.D
in a turned-on state by carrying out the second-node
electric-potential initialization process during the period
TP.sub.0. In the period TP.sub.1, however, the electric potential
appearing on the second node ND.sub.2 is raised toward the electric
potential of the video signal V.sub.Sig.sub.--.sub.m applied to the
first node ND.sub.1. As the difference in electric potential
between the gate electrode of the device driving transistor
TR.sub.D and the specific one of the source and drain areas of the
device driving transistor TR.sub.D attains the threshold voltage
V.sub.th of the device driving transistor TR.sub.D, however, the
device driving transistor TR.sub.D is put in a turned-off state. In
this state, the electric potential V.sub.ND2 appearing on the
second node ND.sub.2 becomes equal to about
(V.sub.Sig.sub.--.sub.m-V.sub.th). That is to say, the electric
potential V.sub.ND2 appearing on the second node ND.sub.2 can be
expressed by Eq. (2) given below. It is to be noted that, prior to
the beginning of the (m+1) th horizontal scan period, a signal
appearing on the scan line SCL.sub.m puts each of the signal
writing transistor TR.sub.W and the first transistor TR.sub.1 in a
turned-off state.
V.sub.ND2.apprxeq.(V.sub.Sig.sub.--.sub.m-V.sub.th) (2)
Period TP(1).sub.2 (with Reference to FIGS. 4 and 5D)
[0139] During a period TP(1).sub.2 following the period
TP(1).sub.4, the first switch circuit SW.sub.1 is put in a
turned-off state whereas the second switch circuit SW.sub.2 is
sustained in a turned-off state and the driving voltage V.sub.CC
determined in advance is applied to the first node ND.sub.1 by way
of the third switch circuit SW.sub.3 which has already been put in
a turned-on state. The fourth switch circuit SW.sub.4 put in a
turned-on state puts the other one of the source and drain areas of
the device driving transistor TR.sub.D in a state of being
electrically connected the to a specific one of the electrodes of
the light emitting device ELP. In this state, the device driving
transistor TR.sub.D allows a source-to-drain current I.sub.ds to
flow to the light emitting device ELP. The process of allowing the
source-to-drain current I.sub.ds to flow to the light emitting
device ELP is referred to as the light emission process.
[0140] To put it more concretely, as described above, prior to the
start of the (m+1) th horizontal scan period, the first transistor
TR.sub.1 is put in a turned-off state whereas the second transistor
TR.sub.2 is sustained in a turned-off state. A signal asserted on
the third/fourth-transistor control line CL.sub.m changes the state
of the third transistor TR.sub.3 and the state of the fourth
transistor TR.sub.4 from a turned-off state to a turned-on state.
In these states, the predetermined reference voltage V.sub.CC is
applied to the first node ND.sub.1 by way of the third transistor
TRs which has already been put in the turned-on state. In addition,
by changing the state of the fourth transistor TR.sub.4 from a
turned-off state to a turned-on state, the other one of the source
and drain areas of the device driving transistor TR.sub.D is put in
a state of being electrically connected to a specific one of the
electrodes of the light emitting device ELP, allowing a
source-to-drain current I.sub.ds generated by the device driving
transistor TR.sub.D to flow to the light emitting device ELP to
serve as a driving current for driving the light emitting device
ELP to emit light.
[0141] Following Eq. (3) is derived from Eq. (2).
V.sub.gs.apprxeq.V.sub.CC-(V.sub.Sig.sub.--.sub.mV.sub.th) (3)
[0142] Thus, Eq. (1) can be changed to following Eq. (4).
I ds = k * .mu. * ( V gs - V th ) 2 = k * .mu. * ( V CC - V Sig _ m
( 4 ) ##EQU00002##
[0143] As is obvious from Eq. (4) given above, the source-to-drain
current I.sub.ds flowing to the light emitting device ELP is
proportional to the square of an electric-potential difference
(V.sub.CC-V.sub.Sig.sub.--m In other words, the source-to-drain
current I.sub.ds flowing to the light emitting device ELP is not
dependent on the threshold voltage V.sub.th of the device driving
transistor TR.sub.D. That is to say, the luminance (or the light
quantity) of light emitted by the light emitting device ELP is not
affected by the threshold voltage V.sub.th of the device driving
transistor TR.sub.D. The luminance of light emitted by the light
emitting device ELP employed in the (n, m)th light emitting unit 10
is a value determined by the source-to-drain current I.sub.ds
flowing to the light emitting device ELP.
[0144] The light emission state of the light emitting device ELP is
sustained till the (m-1) th horizontal scan period of the
immediately following frame. That is to say, the light emission
state of the light emitting device ELP is sustained till the end of
the period TP(1).sub.-1 of the immediately following frame.
[0145] At the end of the light emission state of the light emitting
device ELP, the series of processes of driving the light emitting
unit 10 serving as the (n, m)th sub-pixel circuit as described
above is completed.
[0146] In the display apparatus according to the first embodiment,
the predetermined initialization voltage V.sub.Ini asserted on the
data line DTL.sub.n is applied to the second node ND.sub.2 by way
of the second switch circuit SW.sub.2. Thus, a separate
power-supply line for supplying the initialization voltage
V.sub.Ini determined in advance is not required in particular. As a
result, the number of power-supply lines can be reduced.
[0147] In accordance with the driving method for driving the
display apparatus according to the first embodiment, the second
switch circuit SW.sub.2 is put in a turned-on state with a timing
adjusted to a period used for asserting the initialization voltage
V.sub.Ini determined in advance on the data line DTL.sub.n whereas
the signal writing transistor TR.sub.W is put in a turned-on state
with a timing adjusted to a period used for asserting the video
signal on the data line DTL.sub.n. Thus, even if the separate
power-supply line for applying the initialization voltage V.sub.Ini
determined in advance to the second node ND.sub.2 is eliminated,
the display apparatus can be driven without causing any
problems.
Second Embodiment
[0148] A second embodiment also implements the display apparatus
provided by the present invention and the driving method for
driving the display apparatus. The second embodiment is obtained by
modifying the first embodiment. The display apparatus according to
the second embodiment is different from the display apparatus
according to the first embodiment in that, in the case of the
display apparatus according to the second embodiment, the first
switch circuit SW.sub.1 is controlled by a signal other than the
signal asserted on the scan line SCL.sub.m and, in addition, the
third switch circuit SW.sub.3 and the fourth switch circuit
SW.sub.4 are controlled by signals different from each other.
[0149] The driving method according to the second embodiment is
different from the driving method according to the first embodiment
in that, in the case of the driving method according to the second
embodiment, between the signal writing process and the light
emission process, a second-node electric-potential correction
process is carried out so as to change an electric potential
appearing on the second node ND.sub.2 by applying a voltage with a
magnitude determined in advance to the first node ND.sub.1 for a
period determined in advance with the first switch circuit SW.sub.1
already put in a turned-on state in order to put the second node
ND.sub.2 in a state of being electrically connected to the other
one of the source and drain areas of the device driving transistor
TR.sub.D.
[0150] It is to be noted that, in the case of the second
embodiment, the driving voltage is applied to the first node
ND.sub.1 as the voltage with a magnitude determined in advance. To
put it more concretely, between the signal writing process and the
light emission process which are explained in the description of
the first embodiment, the second-node electric-potential correction
process is carried out by applying the driving voltage as the
voltage with a magnitude determined in advance to the first node
ND.sub.1 for a period determined in advance with the first switch
circuit SW.sub.1 sustained in a turned-on state and the third
switch circuit SW.sub.3 put in a turned-on state.
[0151] The display apparatus according to the second embodiment is
also an organic EL (Electro Luminescence) display apparatus defined
as a display apparatus employing light emitting units which each
have an organic EL light emitting device and a driving circuit for
driving the organic EL device. First of all, an outline of the
organic EL display apparatus is explained. FIG. 6 is a diagram
showing an equivalent circuit of the driving circuit 11 employed in
the light emitting unit 10 at an intersection of the nth matrix
column and the mth matrix row in a two-dimensional matrix of the
display apparatus according to the second embodiment in which light
emitting units are laid out to form the two-dimensional matrix.
FIG. 7 is a conceptual diagram showing the display apparatus. The
structure of the light emitting unit 10 employed in the second
embodiment is identical with the structure of the light emitting
unit 10 employed in the first embodiment.
[0152] The display apparatus according to the second embodiment is
different from the display apparatus according to the first
embodiment in that, in the case of the configuration of the display
apparatus according to the second embodiment, the first switch
circuit SW.sub.1 is controlled by a signal other than the signal
asserted on the scan line SCL.sub.m and, in addition, the third
switch circuit SW.sub.3 and the fourth switch circuit SW.sub.4 are
controlled by signals different from each other. Otherwise, the
configuration of the display apparatus according to the second
embodiment is identical with the configuration of the display
apparatus according to the first embodiment. In the second
embodiment, configuration elements identical with their respective
counterparts employed in the first embodiment are denoted by the
same reference notations and reference numerals as the
counterparts, and explanation of the identical configuration
elements is not repeated in order to avoid duplications of
descriptions.
[0153] In the same way as the first embodiment, the display
apparatus according to the first embodiment employs:
[0154] (1): N.times.M light emitting units 10 laid out to form a
two-dimensional matrix composed of N matrix columns oriented in a
first direction and M matrix rows oriented in a second
direction;
[0155] (2): M scan lines SCL each stretched in the first direction;
and
[0156] (3): N data lines DTL each stretched in the second
direction.
[0157] Each of the M scan lines SCL is connected to a scan circuit
101 whereas each of the N data lines DTL is connected to a signal
outputting circuit 102. The conceptual diagram of FIG. 7 shows
3.times.3 light emitting units 10 centered at a light emitting unit
10 located at the intersection of the mth matrix row and the nth
matrix column. It is to be noted, however, that the configuration
shown in the conceptual diagram of FIG. 7 is no more than a typical
configuration. In addition, the conceptual diagram of FIG. 7 does
not show the first power-supply line PS.sub.1 and the second
power-supply line PS.sub.2 which are shown in the diagram of FIG. 6
to serve as power-supply lines for conveying the driving voltage
V.sub.CC and the cathode voltage V.sub.Cat respectively.
[0158] In the case of the driving circuit according to the first
embodiment described earlier, the first transistor TR.sub.1
functioning as the first switch circuit SW.sub.1 is controlled by a
signal asserted on the scan line SCL.sub.m. In the case of this
second embodiment, on the other hand, the gate electrode of the
first transistor TR.sub.1 is connected to a first-transistor
control line CL1.sub.m. The first-transistor controlling circuit
121 supplies a signal to the gate electrode of the first transistor
TR.sub.1 by way of the first-transistor control line CL1.sub.m in
order to put the first transistor TR.sub.1 in a turned-on or
turned-off state.
[0159] In the case of the first embodiment, each of the gate
electrode of the third transistor TR.sub.3 serving as the third
switch circuit SW.sub.3 and the gate electrode of the fourth
transistor TR.sub.4 serving as the fourth switch circuit SW.sub.4
is connected to the control line CL.sub.m common to the third
switch circuit SW.sub.3 and the fourth switch circuit SW.sub.4 so
that the third switch circuit SW.sub.3 and the fourth switch
circuit SW.sub.4 are control to enter a turned-on or turned-off
state by the same control signal asserted on the control line
CL.sub.m. In the case of the second embodiment, on the other hand,
the gate electrode of the third transistor TR.sub.3 is connected to
the third-transistor control line CL3.sub.m whereas the gate
electrode of the fourth transistor TR.sub.4 is connected to the
fourth-transistor control line CL4.sub.m.
[0160] In the case of the second embodiment, the third-transistor
controlling circuit 123 supplies a signal to the gate electrode of
the third transistor TR.sub.3 by way of the third-transistor
control line CL3.sub.m in order to control transitions of the third
transistor TR.sub.3 from a turned-on state to a turned-off state
and vice versa. By the same token, the fourth-transistor
controlling circuit 124 supplies a signal to the gate electrode of
the fourth transistor TR.sub.4 by way of the fourth-transistor
control line CL4.sub.m in order to control transitions of the
fourth transistor TR.sub.4 from a turned-on state to a turned-off
state and vice versa.
[0161] A commonly known configuration and a commonly known
structure can be used respectively as the configuration and
structure of each of the first-transistor controlling circuit 121,
the third-transistor controlling circuit 123 and the
fourth-transistor controlling circuit 124. By the same token, a
commonly known configuration and a commonly known structure can be
used respectively as the configuration and structure of each of the
first-transistor control line CL1, the third-transistor control
line CL3 and the fourth-transistor control line CL4.
[0162] In the same way as the description of the first embodiment,
the following description explains driving operations carried out
by the display apparatus on the light emitting unit 10 located at
the intersection of the mth matrix row and the nth matrix
column.
[0163] A model of timing charts of signals involved in the driving
operations carried out by the display apparatus is shown in the
timing diagram of FIG. 8. FIGS. 9A and 9B are a plurality of model
circuit diagrams referred to in description of driving operations
carried out by the display apparatus. To be more specific, FIGS. 9A
and 9B are model circuit diagrams showing turned-on and turned-off
states of transistors in the driving circuit 11.
[0164] In the second embodiment, between the signal writing process
and the light emission process, a second-node electric-potential
correction process is carried out so as to change an electric
potential appearing on the second node ND.sub.2 by applying a
voltage with a magnitude determined in advance to the first node
ND.sub.1 for a period determined in advance with the first switch
circuit SW.sub.1 already put in a turned-on state in order to put
the second node ND.sub.2 in a state of being electrically connected
to the other one of the source and drain areas of the device
driving transistor TR.sub.D. To put it more concretely, the signal
writing process is carried out during a period TP(2).sub.1 shown in
the timing diagram of FIG. 8, the second-node electric-potential
correction process is executed during a period TP(2).sub.2 lagging
behind the period TP(2).sub.4 as shown in the same timing diagram
whereas the light emission process is performed during a period
TP(2).sub.3 lagging behind the period TP(2).sub.2 as shown in the
same timing diagram. The following description explains details of
an operation carried out in every period shown in the timing
diagram of FIG. 8.
Period TP(2).sub.-1 (with Reference to FIG. 8)
[0165] As is the case with the period TP(1).sub.-1 shown in the
timing diagram of FIG. 4, the period TP(2).sub.-1 serving as the
period of a light emission process is the period in which the light
emitting unit 10 serving as the (n, m)th sub-pixel circuit is in an
immediately preceding light emission state of emitting light at a
luminance according to a video signal V'.sub.Sig written right
before. Each of the third transistor TR.sub.3 and the fourth
transistor TR.sub.4 is put in a turned-on state whereas each of the
signal writing transistor TR.sub.W, the first transistor TR.sub.1
and the second transistor TR.sub.2 is conversely put in a
turned-off state. The turned-on and turned-off states of the
transistors composing the driving circuit 11 are the same as those
explained earlier by referring to the circuit diagram of FIG. 5A as
the turned-on and turned-off states for the first embodiment.
Through the light emitting device ELP employed in the light
emitting unit 10 serving as the (n, m)th sub-pixel circuit, the
source-to-drain current I'.sub.ds expressed by Eq. (7) to be
described later is flowing. Thus, the light emitting device ELP
employed in the light emitting unit 10 serving as the (n, m)th
sub-pixel circuit is emitting light with a luminance determined by
the source-to-drain current I'.sub.ds.
Period TP(2).sub.0 (with Reference to FIG. 8)
[0166] Much like the period TP(1).sub.0 shown in the timing diagram
of FIG. 4, the period TP(2).sub.0 is the first half of the mth
horizontal scan period of the currently displayed frame. The
turned-on and turned-off states of transistors employed in the
driving circuit 11 are shown in the circuit diagram of FIG. 5B
referred to earlier in the description of the first embodiment.
However, the display apparatus according to the second embodiment
is different from the display apparatus according to the first
embodiment in that, in the case of the configuration of the display
apparatus according to the second embodiment, the first transistor
TR.sub.1, the third transistor TR.sub.3 and the fourth transistor
TR.sub.4 are controlled by a first-transistor controlling circuit
121, a third-transistor controlling circuit 123 and a
fourth-transistor controlling circuit 124 respectively. Otherwise,
operations carried out in the period TP(2).sub.0 are identical with
the operations carried out in the period TP(1).sub.0 of the first
embodiment. Thus, the operations carried out in the period
TP(2).sub.0 are not explained. As explained earlier in the
description of the first embodiment, the initialization voltage
V.sub.Ini is used to set the electric potential appearing on the
second node ND.sub.2 at a predetermined reference electric
potential of -4 volts.
Period TP(2).sub.1 (with Reference to FIG. 8)
[0167] Much like the period (1).sub.1 shown in the timing diagram
of FIG. 4, the period TP(2).sub.1 serving as the period of the
signal writing process is the second half of the mth horizontal
scan period of the currently displayed frame. The turned-on and
turned-off states of the transistors composing the driving circuit
11 are the same as those explained earlier by referring to the
circuit diagram of FIG. 5C as the turned-on and turned-off states
for the first embodiment.
[0168] Operations carried out in the period TP(2).sub.1 are
basically identical with the operations carried out in the period
TP(1).sub.1 of the first embodiment. In the case of the first
embodiment, however, before the (m+1) th horizontal scan period is
started, a signal asserted on the scan line SCL.sub.m puts the
first transistor TR.sub.1 in a turned-off state. The display
apparatus according to the second embodiment is different from the
display apparatus according to the first embodiment in that, in the
case of the display apparatus according to the second embodiment,
the first transistor TR.sub.1 is sustained in a turned-on state
till the end of a period TP(2).sub.2 which will be described later.
As explained earlier in the description of the first embodiment,
the electric potential V.sub.ND2 appearing on the second node
ND.sub.2 is expressed by Eq. (2) given as follows.
V.sub.ND2.apprxeq.(V.sub.Sig.sub.--.sub.m-V.sub.th) (2)
Period TP(2).sub.2 (with Reference to FIGS. 8 and 9A)
[0169] The period TP(2).sub.2 is the period of the second-node
electric-potential correction process of changing an electric
potential appearing on the second node ND.sub.2 by applying a
voltage having a magnitude determined in advance to the first node
ND.sub.1 for a time period determined in advance with the first
switch circuit SW.sub.1 already put in a turned-on state in order
to put the second node ND.sub.2 in a state of being electrically
connected to the other one of the source and drain areas of the
device driving transistor TR.sub.D. In the case of the second
embodiment, the second-node electric-potential correction process
is carried out by applying the driving voltage V.sub.CC to the
first node ND.sub.1 as the voltage having a magnitude determined in
advance.
[0170] To put it concretely, the first transistor TR.sub.1 is
sustained in a turned-on state whereas the third transistor
TR.sub.3 is put in a turned-on state in order to apply the driving
voltage V.sub.CC to the first node ND.sub.1 as the voltage having a
magnitude determined in advance for the period TP(2).sub.2. It is
to be noted that each of the second transistor TR.sub.2 and the
fourth transistor TR.sub.4 is sustained in a turned-off state. As a
result, if the mobility .mu. of the device driving transistor
TR.sub.D is large, the source-to-drain current flowing through the
device driving transistor TR.sub.D is also large, resulting in a
large electric-potential change .DELTA.V or a large
electric-potential correction value .DELTA.V. If the mobility .mu.
of the device driving transistor TR.sub.D is small, on the other
hand, the source-to-drain current flowing through the device
driving transistor TR.sub.D is also small, resulting in a small
electric-potential change .DELTA.V or a small electric-potential
correction value .DELTA.V. Since the second node ND.sub.2 is
electrically connected to the drain area of the device driving
transistor TR.sub.D, the electric potential V.sub.ND2 appearing on
the second node ND.sub.2 also rises by the electric-potential
change .DELTA.V or the electric-potential correction value
.DELTA.V. The equation for expressing the electric potential
V.sub.ND2 appearing on the second node ND.sub.2 is changed from Eq.
(2) to Eq. (5) given as follows.
V.sub.ND2.apprxeq.(V.sub.Sig.sub.--.sub.m-V.sub.th)+.DELTA.V
(5)
[0171] It is to be noted that the entire length t.sub.0 of the
period TP(2).sub.2 during which the second-node electric-potential
correction process is carried out is determined in advance as a
design value at the stage of designing the display apparatus. In
addition, by carrying out the second-node electric-potential
correction process, the source-to-drain current I.sub.ds is also
compensated at the same time for variations in coefficient k which
is expressed as follows: k.ident.(1/2)*(W/L)*C.sub.0X.
Period TP.sub.2(3) (with Reference to FIGS. 8 and 9B)
[0172] The period TP(2).sub.3 is the period of the next light
emission process of driving the light emitting device ELP to emit
light.
[0173] To put it more concretely, at the beginning of the period
TP(2).sub.3, the first transistor TR.sub.1 is put in a turned-off
state whereas the fourth transistor TR.sub.4 is put in a turned-on
state. The second transistor TR.sub.2 is sustained in a turned-off
state whereas the third transistor TR.sub.3 is sustained in a
turned-on state. The driving voltage V.sub.CC determined in advance
is applied to the first node ND.sub.1 by way of the third switch
circuit SW.sub.3 sustained in the turned-on state whereas the
fourth switch circuit SW.sub.4 put in a turned-on state puts the
other one of the source and drain areas of the device driving
transistor TR.sub.D in a state of being electrically connected to a
specific one of the electrodes of the light emitting device ELP. In
these states, a driving current generated by the device driving
transistor TR.sub.D is flowing to the light emitting device ELP and
driving the light emitting device ELP to emit light.
[0174] Following Eq. (6) is derived from Eq. (5).
V.sub.gs.apprxeq.V.sub.CC((V.sub.Sig.sub.--.sub.m-V.sub.th)+.DELTA.V)
(6)
[0175] Thus, Eq. (1) can be changed to following Eq. (7).
I ds = k * .mu. * ( V gs - V th ) 2 = k * .mu. * ( ( V CC - V Sig _
m ) - .DELTA. V ) 2 ( 7 ) ##EQU00003##
[0176] As is obvious from Eq. (7) given above, the source-to-drain
current I.sub.ds flowing to the light emitting device ELP is
proportional to the square of a difference between an
electric-potential difference (V.sub.CC-V.sub.Sig.sub.--.sub.m) and
the electric-potential correction value .DELTA.V which is
determined by the mobility .mu. of the device driving transistor
TR.sub.D. In other words, the source-to-drain current I.sub.ds
flowing to the light emitting device ELP is not dependent on the
threshold voltage V.sub.th of the device driving transistor
TR.sub.D. That is to say, the luminance (or the light quantity) of
light emitted by the light emitting device ELP is not affected by
the threshold voltage V.sub.th of the device driving transistor
TR.sub.D. The luminance of light emitted by the light emitting
device ELP employed in the (n, m) light emitting unit 10 is a value
determined by the source-to-drain current I.sub.ds flowing to the
light emitting device ELP.
[0177] In addition, the larger the mobility .mu. of the device
driving transistor TR.sub.D, the larger the electric-potential
correction value .DELTA.V. Thus, the larger the mobility .mu. of
the device driving transistor TR.sub.D, the smaller the value of
the expression ((V.sub.CC-V.sub.Sig.sub.--m)-.DELTA.V).sup.2
included in Eq. (7) or the smaller the magnitude of the
source-to-drain current I.sub.ds. As a result, the source-to-drain
current I.sub.ds can be compensated for variations in mobility .mu.
from transistor to transistor. That is to say, if a video signal
V.sub.Sig.sub.--.sub.m having the same value is applied to
different light emitting units 10 employing device driving
transistors TR.sub.D having different values of the mobility p, the
source-to-drain currents I.sub.ds generated by the device driving
transistors TR.sub.D have magnitudes about equal to each other. As
a result, the source-to-drain current I.sub.ds flowing to the light
emitting device ELP as a driving current for controlling the
luminance of light emitted by the light emitting device ELP can be
made uniform. Thus, it is possible to eliminate the effects of
variations in mobility .mu. or the effects of variations in
coefficient k, and it is therefore possible to eliminate the
effects of variations of the luminance of light emitted by the
light emitting device ELP.
[0178] The light emission state of the light emitting device ELP is
sustained till the (m-1) th horizontal scan period of the
immediately following frame. That is to say, the light emission
state of the light emitting device ELP is sustained till the end of
the period TP(2).sub.-1 of the immediately following frame.
[0179] At the end of the light emission state of the light emitting
device ELP, the series of processes of driving the light emitting
unit 10 serving as the (n, m)th sub-pixel circuit as described
above is completed.
Third Embodiment
[0180] A third embodiment also implements a display apparatus and a
driving method for driving the display apparatus. The third
embodiment is also obtained by modifying the first embodiment. In
the case of the first embodiment, a voltage with a fixed magnitude
is used as the initialization voltage. In the case of the third
embodiment, on the other hand, a voltage with a magnitude varying
in accordance with the video signal is used as the initialization
voltage. Thus, the display apparatus according to the third
embodiment is provided with a voltage conversion circuit 131 having
a voltage reduction circuit 132. The third embodiment is different
from the first embodiment in these points.
[0181] The display apparatus according to the third embodiment is
also an organic EL (Electro Luminescence) display apparatus defined
as a display apparatus employing light emitting units which each
have an organic EL light emitting device and a driving circuit for
driving the organic EL device. First of all, an outline of the
display apparatus is explained. FIG. 10 is a diagram showing an
equivalent circuit of the driving circuit 11 employed in the light
emitting unit 10 at an intersection of the nth matrix column and
the mth matrix row in a two-dimensional matrix of the display
apparatus according to the third embodiment in which light emitting
units are laid out to form the two-dimensional matrix. FIG. 11 is a
conceptual diagram showing the display apparatus. The structure of
the light emitting unit 10 employed in the second embodiment is
identical with the structure of the light emitting unit 10 employed
in the first embodiment.
[0182] As described above, the display apparatus according to the
third embodiment is provided with a voltage conversion circuit 131
having a voltage reduction circuit 132. The input side of the
voltage conversion circuit 131 is connected to the signal
outputting circuit 102 and the output side of the voltage
conversion circuit 131 is connected to the data line DTL. The third
embodiment is much different from the first embodiment in that, in
the case of the third embodiment, the signal outputting circuit 102
outputs only a video signal V.sub.Sig in both the first and second
halves of the horizontal scan period. Except for the differences
described above, the third embodiment otherwise has a configuration
basically identical with the configuration of the first embodiment.
Configuration elements employed in the third embodiment as elements
identical with their respective counterparts included in the first
embodiment are denoted by the same reference notations and the same
reference numerals as the counterparts, and the explanation of the
configuration elements identical with the counterparts is not
repeated in order to avoid duplications of descriptions.
[0183] In the same way as the first embodiment, the display
apparatus according to the third embodiment employs:
[0184] (1): N.times.M light emitting units 10 laid out to form a
two-dimensional matrix composed of N matrix columns oriented in a
first direction and M matrix rows oriented in a second
direction;
[0185] (2): M scan lines SCL each stretched in the first direction;
and
[0186] (3): N data lines DTL each stretched in the second
direction.
[0187] The scan line SCL is connected to the scan circuit 101. As
described above, the display apparatus according to the third
embodiment is provided with a voltage conversion circuit 131 having
a voltage reduction circuit 132. The input side of the voltage
conversion circuit 131 is used for receiving a video signal
V.sub.Sig from the signal outputting circuit 102 and the output
side of the voltage conversion circuit 131 is connected to the data
line DTL. The conceptual diagram of FIG. 11 shows 3.times.3 light
emitting units 10 centered at a light emitting unit 10 located at
the intersection of the mth matrix row and the nth matrix column.
It is to be noted, however, that the configuration shown in the
conceptual diagram of FIG. 11 is also no more than a typical
configuration. In addition, the conceptual diagram of FIG. 11 does
not show the first power-supply line PS.sub.1 and the second
power-supply line PS.sub.2 which are shown in the diagram of FIG.
10 to serve as power-supply lines for conveying the driving voltage
V.sub.CC and the cathode voltage V.sub.Cat respectively.
[0188] As described above, the input side of the voltage conversion
circuit 131 is used for receiving a video signal V.sub.Sig from the
signal outputting circuit 102. In addition, in the second-node
electric-potential initialization process, the voltage reduction
circuit 132 employed in the voltage conversion circuit 131 asserts
a voltage obtained as a result of subtracting a voltage having a
fixed magnitude from the voltage of the video signal V.sub.Sig to
the data line DTL as the initialization voltage. Except for the
differences described above, operations of processes carried out in
accordance with the driving method for driving the display
apparatus according to the third embodiment are otherwise basically
identical with the operations of the processes carried out in
accordance with the driving method for driving the display
apparatus according to the first embodiment and the explanation of
the operations of the processes carried out in accordance with the
driving method for driving the display apparatus according to the
third embodiment is not repeated.
[0189] As shown in a diagram of FIG. 10, the voltage conversion
circuit 131 is provided with a voltage reduction circuit 132 as
well as signal switching sections 133A and 133B for every data line
DTL. The voltage reduction circuit 132 as well as the signal
switching sections 133A and 133B are configured as transistors
which are provided on the support body 20 by carrying out the same
manufacturing process as the driving circuit 11. The signal
switching sections 133A and 133B are properly subjected to
switching control to put the switching sections 133A and 133B
alternately in turned-on and turned-off states with timings which
are determined by a control clock signal not shown in the diagram
of FIG. 10 as will be described later. The input side of the
voltage reduction circuit 132 receives the video signal V.sub.Sig
from the signal outputting circuit 102 whereas the output side of
the voltage reduction circuit 132 asserts a voltage obtained as a
result of subtracting a voltage V.sub.D having a fixed magnitude
from the voltage of the video signal V.sub.Sig to the data line DTL
as the initialization voltage V.sub.Ini to be described later.
[0190] As described above, in the case of the third embodiment, a
voltage with a magnitude varying in accordance with the video
signal V.sub.Sig is used as the initialization voltage V.sub.Ini.
To put it more concretely, the initialization voltage V.sub.Ini is
a voltage expressed by (V.sub.Sig-V.sub.D).
[0191] Next, the configuration of the voltage reduction circuit 132
is explained. FIG. 12 is a circuit diagram showing a model of the
voltage conversion circuit 131. As shown in the circuit diagram,
the voltage reduction circuit 132 employed in the third embodiment
is configured to include diode-wired transistors. To put it more
concretely, the voltage reduction circuit 132 has two diode-wired
transistors 132A and 132B which are connected to each other to form
a series circuit. In this case, each of the diode-wired transistors
132A and 132B and the device driving transistor TR.sub.D can be
designed as transistors of the same configuration. To put it more
concretely, each of the diode-wired transistors 132A and 132B and
the device driving transistor TR.sub.D is a TFT of the p-channel
type. Thus, from the design point of view, each of the diode-wired
transistors 132A and 132B has a threshold voltage equal to the
threshold voltage V.sub.th of the device driving transistor
TR.sub.D. Therefore, in the voltage reduction circuit 132 shown in
the diagram of FIG. 12, from the design point of view, the voltage
V.sub.D is equal to 2.times.V.sub.th (that is,
V.sub.D=2.times.V.sub.th). That is to say, in the third embodiment,
since threshold voltage V.sub.th of the device driving transistor
TR.sub.D is 2 volts, the voltage V.sub.D is 4 volts.
[0192] FIG. 13 is a model timing diagram showing timing charts
referred to in explanation of operations carried out by the voltage
conversion circuit 131. The timing diagram shows timing charts of
turned-on and turned-off states of the signal switching sections
133A and 133B as well as turned-on and turned-off states of the
first and second transistors TR.sub.1 and TR.sub.2.
[0193] As shown in the timing diagram of FIG. 13, the signal
switching section 133A is controlled to sustain the signal
switching section 133A in a turned-on state during the first half
of every horizontal scan period and a turned-off state during the
second half of every horizontal scan period. On the other hand, the
signal switching section 133B is controlled to conversely sustain
the signal switching section 133B in a turned-off state during the
first half of every horizontal scan period and a turned-on state
during the second half of every horizontal scan period. Typically,
each of the signal switching sections 133A and 133B is controlled
by properly making use of a clock signal for generating a scan
signal in the scan circuit 101.
[0194] During the first half of the mth horizontal scan period, the
signal switching section 133A is sustained in a turned-on state but
the signal switching section 133B is conversely sustained in a
turned-off state. The first half of the mth horizontal scan period
is a period TP(1).sub.0 which has been explained earlier in the
description of the first embodiment. Thus, the initialization
voltage V.sub.Ini.sub.--m asserted on the data line DTL.sub.n in
the mth horizontal scan period is expressed as follows:
V.sub.Ini.sub.--.sub.m=V.sub.Sig.sub.--.sub.m-V.sub.D
To put it more concretely, the initialization voltage
V.sub.Ini.sub.--.sub.m asserted on the data line DTL.sub.n in the
mth horizontal scan period is expressed as follows:
V.sub.Ini.sub.--.sub.m=V.sub.Sig.sub.--.sub.m-2.times.V.sub.th
where reference notation V.sub.Sig.sub.--.sub.m denotes the video
signal V.sub.Sig supplied to the voltage conversion circuit 131 in
the mth horizontal scan period.
[0195] The initialization voltage V.sub.Ini.sub.--.sub.m asserted
on the data line DTL.sub.n in the first half of each of periods
other than the mth horizontal scan period is the same as that
asserted on the data line DTL.sub.n in the first half of the mth
horizontal scan period.
[0196] During the second half of the mth horizontal scan period, on
the other hand, the signal switching section 133A is sustained in a
turned-off state but the signal switching section 133B is
conversely sustained in a turned-on state. The second half of the
mth horizontal scan period is a period TP(1).sub.1 which has been
explained earlier in the description of the first embodiment. Thus,
the video signal V.sub.Sig.sub.--.sub.m is asserted on the data
line DTL.sub.n in the mth horizontal scan period is as it is. The
video signal V.sub.Sig.sub.--.sub.m is asserted on the data line
DTL.sub.n as it is in the second half of each of periods other than
the mth horizontal scan period.
[0197] FIG. 14 is a model timing diagram showing timing charts of
driving operations carried out by the display apparatus as timing
charts to be referred to in explanation of a driving method
according to the third embodiment. The timing diagram of FIG. 14
corresponds to the timing diagram of FIG. 4 referred to in the
description of the first embodiment. If the video signal
V.sub.Sig.sub.--.sub.m has a typical voltage of 6 volts for
example, the initialization voltage V.sub.Ini.sub.--.sub.m
(=V.sub.Sig.sub.--.sub.m-2.times.V.sub.th) is 2 volts in the third
embodiment since the threshold voltage V.sub.th of the device
driving transistor TR.sub.D (or the diode-wired transistors 132A
and 132B) is 2 volts. As explained earlier in the description of
the first embodiment, during the period TP(1).sub.1, the signal
writing process is carried out.
[0198] In the timing diagram of FIG. 4 referred to in the
description of the first embodiment, the initialization voltage
V.sub.Ini is -4 volts. If the video signal V.sub.Sig.sub.--.sub.m
has a typical voltage of 6 volts for example, during the period
TP(1).sub.1, the electric potential appearing on the second node
ND.sub.2 must rise from -4 volts to 4 volts
(=V.sub.Sig.sub.--.sub.m-V.sub.th=6 volts -2 volts). Otherwise, the
signal writing process is not completed normally. In accordance
with specifications of the display apparatus, however, the period
TP(1).sub.1 must be shortened in some cases, raising a problem that
the period TP(1).sub.1 is undesirably ended before the electric
potential appearing on the second node ND.sub.2 attains the level
of 4 volts (=V.sub.Sig.sub.--.sub.m-V.sub.th=6 volts -2 volts).
[0199] In the case of the driving method according to the third
embodiment, on the other hand, if the video signal
V.sub.Sig.sub.--.sub.m has a typical voltage of 6 volts for
example, the initialization voltage V.sub.Ini.sub.--.sub.m
(=V.sub.Sig.sub.--.sub.m-2.times.V.sub.th) in the third embodiment
is 2 volts as described above. Thus, in the case of the third
embodiment, the electric potential appearing on the second node
ND.sub.2 needs to be raised by only an increase equal to the
threshold voltage V.sub.th of 2 volts during the period
TP(1).sub.1. If the electric potential appearing on the second node
ND.sub.2 can be raised by 2 volts, the signal writing process can
be completed normally. The increase of 2 volts is equal to the
threshold voltage V.sub.th of the device driving transistor
TR.sub.D and independent of the magnitude of the video signal
V.sub.Sig.sub.--.sub.m. Thus, the driving method according to the
third embodiment of the present invention has a merit that the
length of the period TP(1).sub.1 required for completing the signal
writing process normally can be reduced.
[0200] The present invention has been exemplified above by taking
each of the preferred embodiments as a typical example. However,
implementations of the present invention are by no means limited to
this preferred embodiment. That is to say, the configuration and
structure of each component employed in the driving circuit and the
light emitting device which are included in the light emitting unit
of the display apparatus according to the preferred embodiment as
well as the processes of the method for driving the light emitting
device are typical examples and can thus be changed properly.
[0201] For example, the display apparatus according to the second
embodiment can be changed to a display apparatus having a
configuration in which the initialization voltage has a magnitude
varying in accordance with the voltage of the video signal, that
is, a configuration further provided with the voltage conversion
circuit having the voltage reduction circuit as is the case with
the third embodiment described above.
[0202] The present application contains subject matter related to
that disclosed in Japanese Priority Patent Application JP
2008-119839 filed in the Japan Patent Office on May 1, 2008 and
Japanese Priority Patent Application JP 2008-319828 filed in the
Japan Patent Office on Dec. 16, 2008, the entire contents of which
are hereby incorporated by reference.
[0203] It should be understood by those skilled in the art that a
variety of modifications, combinations, sub-combinations and
alterations may occur, depending on design requirements and other
factors as far as they are within the scope of the appended claims
or the equivalents thereof.
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