U.S. patent application number 13/555831 was filed with the patent office on 2012-11-15 for metal-insulator-metal structure for system-on-chip technology.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Chun-Yao Chen, Kuo-Cheng Ching, Kuo-Chi Tu.
Application Number | 20120289021 13/555831 |
Document ID | / |
Family ID | 42677459 |
Filed Date | 2012-11-15 |
United States Patent
Application |
20120289021 |
Kind Code |
A1 |
Ching; Kuo-Cheng ; et
al. |
November 15, 2012 |
METAL-INSULATOR-METAL STRUCTURE FOR SYSTEM-ON-CHIP TECHNOLOGY
Abstract
The present disclosure provides a semiconductor device that
includes a semiconductor substrate, an isolation structure formed
in the semiconductor substrate, a conductive layer formed over the
isolation structure, and a metal-insulator-metal (MIM) capacitor
formed over the isolation structure. The MIM capacitor has a crown
shape that includes a top electrode, a first bottom electrode, and
a dielectric disposed between the top electrode and the first
bottom electrode, the first bottom electrode extending at least to
a top surface of the conductive layer.
Inventors: |
Ching; Kuo-Cheng; (Zhubei
City, TW) ; Tu; Kuo-Chi; (Hsin-Chu, TW) ;
Chen; Chun-Yao; (Hsin-Chu, TW) |
Assignee: |
Taiwan Semiconductor Manufacturing
Company, Ltd.
Hsin-Chu
TW
|
Family ID: |
42677459 |
Appl. No.: |
13/555831 |
Filed: |
July 23, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12397948 |
Mar 4, 2009 |
8242551 |
|
|
13555831 |
|
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Current U.S.
Class: |
438/386 ;
257/E21.008 |
Current CPC
Class: |
H01L 28/91 20130101;
H01L 27/0629 20130101; H01L 27/0805 20130101; H01L 27/10852
20130101; H01L 27/10894 20130101 |
Class at
Publication: |
438/386 ;
257/E21.008 |
International
Class: |
H01L 21/02 20060101
H01L021/02 |
Claims
1-14. (canceled)
15. A method of fabricating a semiconductor device that includes a
semiconductor substrate including a first region and a second
region, the first region including an isolation structure and a
conductive layer disposed over the isolation structure, the second
region including a memory cell that includes a transistor having a
doped feature, the method comprising: forming a first interlayer
dielectric (ILD) layer over the conductive layer in the first
region and over the memory cell in the second region; forming a
contact feature within the first ILD layer in the first region, the
contact feature being coupled to the doped feature of the
transistor; and forming a second ILD layer over the first ILD layer
in first and second regions; forming a first trench that extends at
least to the conductive layer in the first region and a second
trench that extends to the contact feature in the second region;
forming a bottom metal layer over the second ILD partially filling
in the first and second trenches; removing portions of the bottom
metal layer outside of the first and second trenches; forming a
dielectric layer over the second ILD layer partially filling in the
first and second trenches; and forming a top metal layer over the
dielectric layer partially filling in the first and second
trenches.
16. The method of claim 15, further comprising: forming an etch
stop layer over the first ILD layer in the first and second regions
after forming the contact feature; and removing the etch stop layer
in the first region; wherein forming the first trench and the
second trench includes: performing a dry etching process that stops
at least at the conductive layer in the first region thereby
forming the first trench and that stops at the etch stop layer in
second region thereby forming the second trench; and removing the
exposed etch stop layer in the second trench.
17. The method of claim 15, further comprising: forming an etch
stop layer over the first ILD layer in the first and second regions
after forming the contact feature; wherein forming the first trench
and the second trench includes: performing a first dry etching that
stops at the etch stop layer thereby forming a portion of the first
trench and a portion of the second trench; removing the exposed
etch stop layer in the portion of the first trench and in the
portion of the second trench, respectively; forming a protection
layer filling in the second trench; performing a second dry etching
that stops at least at the conductive layer in the first region
thereby extending the portion of the first trench.
18. The method of claim 15, wherein the first trench extends
through the conductive layer and at least to the isolation
structure.
19. The method of claim 15, wherein the first trench extends
through the conductive layer and through a portion of the isolation
structure.
20. The method of claim 15, wherein forming the first trench
includes: performing a dry etching process that stops at least at
the conductive layer; and performing a wet etching process that
modifies a corner profile of the first trench.
21. A method comprising: providing a semiconductor substrate having
an isolation structure disposed in the semiconductor substrate;
forming a conductive layer over the isolation structure; forming an
interlayer dielectric layer over the conductive layer; forming a
first trench extending through the interlayer dielectric layer,
conductive layer, and to the isolation structure; forming a bottom
metal layer within the first trench, wherein the bottom metal layer
contacts the isolation structure; forming a dielectric layer over
the bottom metal layer within the first trench; and forming a top
metal layer over the dielectric layer within the first trench.
22. The method of claim 21, further comprising forming an etch stop
layer over the semiconductor substrate prior to forming the
interlayer dielectric layer over the conductive layer.
23. The method of claim 21, further comprising forming an etch stop
layer over the interlayer dielectric layer.
24. The method of claim 23, further comprising forming another
interlayer dielectric layer over the etch stop layer.
25. The method of claim 24, further comprising performing a first
etching process that stops at the etch stop layer to form a second
trench.
26. The method of 27, wherein forming the first trench extending
through the interlayer dielectric layer, conductive layer, and to
the isolation structure occurs after performing the first etching
process.
27. The method of claim 21, wherein forming the first trench
extending through the interlayer dielectric layer, conductive
layer, and to the isolation structure includes the first trench
extending through a portion of the isolation structure.
28. A method comprising: providing a semiconductor substrate having
an isolation structure disposed in the semiconductor substrate;
forming a conductive layer over the isolation structure; forming a
trench extending through the conductive layer and to a top surface
of the isolation structure; forming a bottom metal layer within the
trench; forming a dielectric layer over the bottom metal layer
within the trench; and forming a top metal layer over the
dielectric layer within the trench.
29. The method of claim 28, further comprising forming a silicide
layer over the conductive layer prior to forming the trench
extending through the conductive layer and to the top surface of
the isolation structure.
30. The method of claim 28, wherein the conductive layer includes a
doped polysilicon layer and the bottom electrode physically
contacts the doped polysilicon layer.
31. The method of claim 28, further comprising: forming a first
interlayer dielectric layer over the conductive layer; forming an
etch stop layer over the first interlayer dielectric layer; and
forming a second interlayer dielectric layer over the etch stop
layer.
32. The method of claim 31, further comprising performing a first
etch process through the second interlayer dielectric layer that
stops on the etch stop layer to form a first portion of the trench,
and wherein forming the trench extending through the conductive
layer and to the top surface of the isolation structure includes
performing a second etch process through the first interlayer
dielectric layer to form a second portion of the trench.
33. The method of claim 28, further comprising after forming the
trench, performing an etching process that modifies a corner
profile of the trench.
34. The method of claim 28, wherein the isolation structure is a
shallow trench isolation structure.
Description
PRIORITY DATA
[0001] The present application is a divisional application of U.S.
patent application Ser. No. 12/397,948, filed Mar. 4, 2009, which
is incorporated herein by reference in its entirety.
BACKGROUND
[0002] The present disclosure is related generally to the
fabrication of semiconductor devices, and, more particularly, to a
metal-insulator-metal (MIM) structure, a method of manufacturing
the structure, and a semiconductor device incorporating the
structure.
[0003] Capacitors are critical components for many data
manipulation and data storage applications. In general, capacitors
include two conductive electrodes on opposing sides of a dielectric
or other insulating layer, and they may be categorized based on the
materials employed to form the electrodes. For example, in a
metal-insulator-metal (MIM) capacitor, the electrodes substantially
comprise metal. MIM capacitors offer the advantage of a relatively
constant value of capacitance over a relatively wide range of
voltages applied thereto. MIM capacitors also exhibit a relatively
small parasitic resistance.
[0004] Generally, it is desirable that MIM capacitors (and others)
consume as little surface area as possible to increase packing
density. At the same time, capacitance values should be maximized
to obtain optimum device performance, such as when employed for
data retention in dynamic random access memory (DRAM) applications
or for decoupling in mixed-signal and microprocessor applications.
However, capacitance values for a single capacitor generally
decrease as the surface area of the capacitor decreases. Various
structures have been proposed in attempt to overcome this dichotomy
between minimizing capacitor structure size and maximizing
capacitance values. One such example is a crown-shaped capacitor,
which resembles a folded structure in which a trench is lined with
a first electrode and filled with an annular shaped insulating
element and an inner core electrode, thereby increasing the
effective electrode contact area relative to conventional planar
capacitors. Although crown capacitors have been satisfactory for
its intended purpose, they have not been satisfactory in all
respects.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1 illustrates a sectional view of a semiconductor
device including a metal-insulator-metal (MIM) capacitor;
[0006] FIG. 2 illustrates a sectional view of a semiconductor
device including an alternative MIM capacitor;
[0007] FIG. 3 illustrates a sectional view of a semiconductor
device including another alternative MIM capacitor;
[0008] FIG. 4 illustrates a flowchart of a method for fabricating a
semiconductor device including an MIM capacitor;
[0009] FIGS. 5A-5E illustrate sectional views of a semiconductor
device at various stages of fabrication according to the method of
FIG. 4;
[0010] FIG. 6 illustrates a flowchart of an alternative method for
fabricating a semiconductor device including an MIM capacitor;
[0011] FIGS. 7A-7G illustrate sectional views of a semiconductor
device at various stages of fabrication according to the method of
FIG. 6; and
[0012] FIG. 8 illustrates a rounded corner profile of a MIM
capacitor according to various aspects of the present
disclosure.
DETAILED DESCRIPTION
[0013] The present disclosure is related generally to the
fabrication of semiconductor devices, and, more particularly, to a
capacitor structure having a high unit capacitance, a method of
manufacturing the structure and a semiconductor device
incorporating the structure. It is understood, however, that the
following disclosure provides many different embodiments, or
examples, for implementing different features of the invention.
Specific examples of components and arrangements are described
below to simplify the present disclosure. These are, of course,
merely examples and are not intended to be limiting. In addition,
the present disclosure may repeat reference numerals and/or letters
in the various examples. This repetition is for the purpose of
simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
discussed. Moreover, the formation of a first feature over or on a
second feature in the description that follows may include
embodiments in which the first and second features are formed in
direct contact, and may also include embodiments in which
additional features may be formed interposing the first and second
features, such that the first and second features may not be in
direct contact.
[0014] Referring to FIG. 1, illustrated is a sectional view of a
semiconductor device 100 including one embodiment of a
metal-insulator-metal (MIM) capacitor. The semiconductor device 100
is configured as a system-on-chip (SoC) device that integrates
various functions on a single chip. In the present embodiment, the
semiconductor device 100 includes regions 102, 104, 106 that are
each configured for a different function. The region 102 may
include a plurality of transistors 110, such as metal oxide
semiconductor field effect transistors (MOSFET) or complementary
MOS (CMOS) transistors, and resistors that form a logic circuit,
static random access memory (SRAM) circuit, processor circuit, or
other suitable circuit. The region 104 may include a plurality of
transistors 112 and capacitors 114 that form a dynamic random
access memory (DRAM) array for memory storage. The region 106 may
include a plurality of metal-insulator-metal (MIM) capacitors 120.
The MIM capacitors 120 can be used for various functions such as
for decoupling capacitance and high-frequency noise filters in
mixed-signal applications, for decoupling capacitance in
microprocessor applications, for storage retention in memory
applications, and for oscillators, phase-shift networks, bypass
filters, and coupling capacitance in radio frequency (RF)
applications. It is understood that the semiconductor device 100
includes other features and structures such as eFuses, inductors,
passivation layers, bonding pads, and packaging, but is simplified
for the sake of simplicity and clarity.
[0015] The semiconductor device 100 may include a semiconductor
substrate 124. In the present embodiment, the substrate 124
includes a silicon substrate (e.g., wafer) in a crystalline
structure. The substrate 124 may include various doping
configurations depending on design requirements as is known in the
art (e.g., p-type substrate or n-type substrate). Additionally, the
substrate 124 may include various doped regions such as p-type
wells (p-wells or PW) or n-type wells (n-wells or NW). The
substrate 124 may also include other elementary semiconductors such
as germanium and diamond. Alternatively, the substrate 124 may
include a compound semiconductor such as, silicon carbide, gallium
arsenide, indium arsenide, or indium phosphide. Further, the
substrate 124 may optionally include an epitaxial layer (epi
layer), may be strained for performance enhancement, and may
include a silicon-on-insulator (SOI) structure.
[0016] The semiconductor device 100 further includes isolation
structures such as shallow trench isolation (STI) features 126
formed in the substrate 124 to isolate one or more devices. The STI
features 126 may include silicon oxide, silicon nitride, silicon
oxynitride, fluoride-doped silicate (FSG), and/or a low-k
dielectric material known in the art. Other isolation methods
and/or features are possible in lieu of or in addition to STI. The
STI features 126 may be formed using processes such as reactive ion
etch (RIE) of the substrate 124 to form trenches which are then
filled with an insulator material using deposition processes
followed by a chemical-mechanical-polishing (CMP) process.
[0017] It is understood that formation of the transistors 110 in
the region 102 and transistors 114 in the region 104 includes
various processes known in the art, and thus are not described in
detail herein. For example, various material layers, such as an
oxide layer (e.g., gate dielectric) and polysilicon layer 130
(e.g., gate electrode) are formed, and then patterned to form gate
structures. The processing continues with forming lightly doped
drain (LDD) regions, forming gate spacers, forming heavy doped
source/drain regions, forming self-aligned silicide features 132,
forming a contact etch stop layer (CESL) 134, and forming an
inter-level (or inter-layer) dielectric (ILD) layer 140. It should
be noted that the region 106 may be protected during some of these
processes. Accordingly, the region 106 may include the oxide layer,
polysilicon layer 130, the silicide layer 132, CESL 134, and ILD
layer 140. The CESL 134 may be formed of silicon nitride, silicon
oxynitride, and/or other suitable materials. The ILD layer 140 may
be formed of silicon oxide or a low-k dielectric material. The ILD
layer 140 may be formed by chemical vapor deposition (CVD), high
density plasma CVD, spin-on, PVD (or sputtering), or other suitable
methods. A plurality of first contacts 142 are formed in the ILD
layer 140 to provide electrical connections to the doped features
(e.g., source/drain and poly gate electrode) of the transistors
110, 114 in the regions 102, 104, respectively, as well as other
devices such as resistors. An ILD layer 144 is formed over the ILD
layer 140 following the formation of the contacts 142. The ILD
layer 144 may be formed of a similar material as the ILD layer
140.
[0018] The MIM capacitors 114 in the region 104 include a bottom
electrode 150, a top electrode 152, and a high-k dielectric 154
disposed between the bottom electrode 150 and top electrode 152.
The MIM capacitors 114 are formed in the ILD layer 144 such that
the bottom electrode 150 is coupled to the doped feature of the
transistor 112 via the contact 142.
[0019] The MIM capacitor 120 in the region 106 may be considered as
two capacitors 120a, 120b connected in parallel. The capacitors
120a, 120b each includes a bottom electrode 160a, 160b,
respectively, a same top electrode 162, and a high-k dielectric 164
disposed between the bottom electrodes 160a, 160b and the top
electrode 162. The capacitors 120a, 120b are formed in the ILD
layers 140, 144 and the bottom electrodes 160a, 160b may extend to
a top surface of the polysilicon layer 130. Accordingly, the bottom
electrodes 160a, 160b of the capacitors 120a, 120b, respectively,
are in contact with the silicide layer 132 and the polysicon layer
130, and thus are electrically coupled to each other. As such, the
total capacitance value is the sum of the capacitance values of the
capacitors 120a, 120b. Further, electrical connections may be
provided to interconnect the capacitor 120 with other devices in
the regions 102, 104. The STI 126 isolates the capacitor 120 from
the substrate noise.
[0020] Although only two capacitors 120a, 120b (two crown features)
are illustrated, it is understood that the number of capacitors
(multiple crown features) may vary depending on design
requirements. It should also be noted that the capacitance value of
the capacitors 120a, 120b are increased due to an increase of the
surface area of the electrodes. The increase of the surface area
can be achieved by extending the bottom electrodes 160a, 160b to
the polysilicon layer 130. Further, the surface area of the
capacitor 120 can be increased in this manner without adversely
effecting the performance of the other regions 102, 104. For
example, the surface area of the capacitors 120 may be increased by
increasing the thickness of the ILD layer 144 (thereby increasing
the surface are of the top and bottom electrodes) but this causes
an increase of a parasitic capacitance between metal structures
(interconnection structures) formed in the ILD layer 144. Moreover,
the formation of the capacitors 120 is easily integrated within the
process flow that forms the other devices and features of the
regions 102, 104 as will be explained below in FIGS. 4-7.
[0021] The semiconductor device 100 further includes an ILD layer
168 formed over the capacitors 114, 120 in the regions 104, 106,
respectively, and over the ILD layer 144 in the region 102. The
semiconductor device 100 further includes a plurality of contacts
170 formed in the ILD layers 144, 168 to electrically couple the
contacts 142 to a first metal layer 172 of an interconnect
structure. The interconnect structure may include a plurality of
metal layers for interconnecting the various devices and features
in the regions 102, 104, 106 as is known in the art. It is
understood that the present disclosure does not limit the specific
interconnection of the logic devices to each other or to a
capacitor device or to the DRAM array. Those skilled in the art
will recognize that there are myriad applications, structures,
device layouts and interconnection schemes in which an embodiment
of a capacitor device of the present disclosure may be implemented.
Accordingly, for the sake of simplicity and clarity, additional
details of the logic devices, DRAM array, and the interconnection
between and among the various devices are not illustrated or
further described herein.
[0022] Referring to FIG. 2, illustrated is a sectional view of a
semiconductor device 200 including an alternative embodiment of an
MIM capacitor. The semiconductor device 200 is similar to the
semiconductor device 100 of FIG. 1 except for the differences
discussed below. Accordingly, similar features in FIGS. 1 and 2 are
numbered the same for the sake of simplicity and clarity. The MIM
capacitor 210 in the region 106 may be considered as two capacitors
210a, 210b as was discussed above. The MIM capacitor 210 includes
bottom electrodes 212a, 212b, a top electrode 214, and a high-k
dielectric 216 disposed between the bottom electrodes 212a, 212b
and top electrode 214. The bottom electrodes 212a, 212b extend
through the polysilicon layer 130 and to a top surface of the STI
126. Accordingly, the bottom electrodes 212a, 212b are in contact
with the silicide layer 132 and polysilicon layer 130 and may be
electrically coupled to each other. It should be noted that the
capacitance value of the capacitor 210 is larger than the capacitor
120 in FIG. 1 due to an increase of the surface area of the
capacitor 210. The increase of the surface area is achieved by
extending the bottom electrodes 212a, 212b to the top surface of
the STI 126. Further, the advantages discussed above with respect
to the capacitor 120 in FIG. 1 are also applicable in this
embodiment.
[0023] Referring to FIG. 3, illustrated is a sectional view of a
semiconductor device 300 including another alternative embodiment
of an embedded MIM capacitor. The semiconductor device 300 is
similar to the semiconductor device 100 of FIG. 1 except for the
differences discussed below. Accordingly, similar features in FIGS.
1 and 3 are numbered the same for the sake of simplicity and
clarity. The MIM capacitor 310 in the region 106 may be considered
as two capacitors 310a, 310b as was discussed above. The MIM
capacitor 310 includes bottom electrodes 312a, 312b, a top
electrode 314, and a high-k dielectric 316 disposed between the
bottom electrodes 312a, 312b and top electrode 314. The bottom
electrodes 312a, 312b extend through the polysilicon layer 130 and
through a portion of the STI 126. Accordingly, the bottom
electrodes 312 are in contact with the silicide layer 132 and
polysilicon layer 130 and may be electrically coupled to each
other. It should be noted that the capacitance value of the
capacitor 310 is larger than the capacitors 120, 210 in FIGS. 1 and
2, respectively, due to an increase of the surface area of the
capacitor 310. The increase of the surface area is achieved by
extending the bottom electrodes 312a, 312b through a portion of the
STI 126. Additionally, the amount of extension of the bottom
electrodes 312a, 312b in the STI 126 may depend on design
requirements and the function of the STI 126 to isolate the
capacitor 310 from substrate noise. Further, the advantages
discussed above with respect to the capacitors 120, 210 in FIGS. 1
and 2, respectively, are also applicable in this embodiment.
[0024] Referring to FIG. 4, illustrated is a flowchart of a method
400 of fabricating a semiconductor device with an embedded MIM
capacitor according to various aspects of the present disclosure.
Referring also to FIGS. 5A-5E, illustrated are sectional views of a
semiconductor device 500 at various stages of fabrication according
to the method 400 of FIG. 4. The semiconductor device 500 is
similar to the semiconductor devices 100, 200, 300 in FIGS. 1-3,
respectively. Accordingly, similar features in FIGS. 1-3 and 5 are
numbered the same for the sake of simplicity and clarity. The
method 400 begins with block 402 in which a semiconductor substrate
including a first region and a second region is provided. The first
region includes an isolation structure formed in the substrate, a
conductive layer formed over the isolation structure, and a first
inter-layer dielectric (ILD) formed over the conductive layer. The
second region includes a transistor having a doped feature formed
in the substrate, the first ILD formed over the transistor, and a
contact feature formed in the first ILD and coupled to the doped
feature of the transistor.
[0025] In FIG. 5A, the semiconductor device 500 is illustrated
following the formation of a plurality of first contacts 142 in the
ILD layer 140 of the region 104. The first contacts 142 are coupled
to the doped features of the transistors 112 in the region 104, and
are coupled to the doped features (e.g., source/drain and poly gate
electrode) of the transistors 120 in the region 102 (not shown).
The first contacts 142 are formed by etching trenches in the ILD
layer 140, filling the trenches with seed layers, barrier layers,
and/or metal layers, followed by a planarizing process, such as
chemical-mechanical-polishing (CMP) or a etch-back process. It
should be noted that the first contacts 142 are not formed in the
region 106. As previously discussed, the region 104 is configured
for a DRAM or embedded DRAM array, and the region 106 is configured
for a MIM capacitor. The region 106 includes an STI 126 formed in
the substrate 124. The region 106 further includes an oxide layer
formed on the substrate 124, a doped polysilicon layer 130 formed
on the oxide layer, a silicide layer 132 formed on the polysilicon
layer 130, a contact etch stop layer (CESL) 134 formed on the
silicide layer 132, and the ILD layer 140 formed on the CESL 134.
It is understood that the various material layers in the region 106
may be formed concurrently when forming the transistors 112 and
other features in the region 104.
[0026] The method 400 continues with block 404 in which an etch
stop layer is formed over the first ILD in the second region. The
semiconductor device 500 includes an etch stop layer 502 formed
over the ILD layer 140. A photoresist mask may be formed and
patterned to protect the etch stop layer 502 in the region 104. The
photoresist mask may be formed and patterned by photolithography.
For example, the photolithography process includes spin coating,
soft-baking, exposure, post-exposure baking, developing, rinsing,
drying, and other suitable process. Accordingly, the etch stop
layer in the region 106 may be removed by a wet etching process, a
dry etching process, or other suitable process.
[0027] The etch stop layer 502 may function as an end point of
subsequent etching processes as discussed below. Although not
limited by the present disclosure, the etch stop layer 502 may
comprise silicon carbide, silicon nitride, or silicon oxynitride,
may be formed by CVD, plasma enhanced chemical vapor deposition
(PECVD), or low pressure chemical vapor deposition (LPCVD). The
etch stop layer may have a thickness ranging from about 500 to
about 1500 angstrom (A). For example, in an embodiment in which the
etch stop layer 502 comprises silicon carbide, the etch stop layer
502 may be formed by PECVD employing a process chemistry comprising
trimethylsilane.
[0028] The method 400 continues with block 406 in which a second
ILD is formed over the first ILD in the first region and over the
etch stop layer in the second region. In FIG. 5B, the semiconductor
device 500 further includes an ILD layer 144 formed over the ILD
layer 140 in the region 106 and over the etch stop layer 502 in the
region 104. The ILD layer 144 may be formed of a similar material
as the ILD layer 140. The ILD layer 144 may be formed of silicon
oxide or a low-k dielectric material. The ILD layer 144 may be
formed by chemical vapor deposition (CVD), high density plasma CVD,
spin-on, PVD (or sputtering), or other suitable methods. The ILD
layer 144 may have a thickness ranging from about 5000 to about
12000 angstrom (A).
[0029] The method 400 continues with block 408 in which an etching
process is performed that stops at least at the conductive layer in
the first region thereby forming a first trench and that stops at
the etch stop layer in the second region thereby forming a second
trench. In FIG. 5C, a photoresist 504 is formed to define openings
for the capacitors in the regions 104 and 106. The photoresist 504
may be employed as a mask during an etching process 510 and
subsequently stripped, such as by wet stripping or plasma ashing.
The etching process 510 may include a dry etch, a wet etch, a
reactive ion etch (RIE), or combination dry and wet etch process.
In the present embodiment, the etching process 510 includes a dry
etch that passes through the silicide layer 132, polysilicon layer
130, and a portion of the STI 126 in the region 106, and that stops
at the etch stop layer 502 in the region 104. It should be noted
the dry etch may stop at a top surface of the polysilicon layer 130
in some embodiments (similar to FIG. 1), or may stop at a top
surface of the STI 126 in some other embodiments (similar to FIG.
2). As such, trenches 512 are formed in the region 106 and trenches
514 are formed in the region 104. The trenches 512 may have
vertical sidewalls and substantially square corners due to the
anisotropic dry etch process. Accordingly, the etching process 510
further includes an isotropic etch process that modifies a corner
profile of the trenches 512 in the region 106. In some embodiments,
the corner profile of the trenches 512 are rounded and smoothed by
an isotropic wet etch process (e.g., wet dip) as illustrated by 800
of FIG. 8. It has been observed that the capacitance value can be
increased and the reliability of the MIM structure (e.g., time
dependent dielectric breakdown (TDDB)) can be improved due to
corner rounding and smoothing.
[0030] The method 400 continues with block 410 in which the etch
stop layer in the second trench is removed thereby exposing the
contact feature. In FIG. 5D, an etching process 520 is performed to
selectively remove portions of the etch stop layer 502 that are
exposed in the trenches 514 in the region 106. The etching process
520 may include a dry etch, dry etch, or combination wet and dry
etch process. For example, the etching process 520 includes a dry
etch process that has a high etching selectivity of silicon carbide
to remove the exposed etch stop layer 502. Accordingly, the first
contacts 142 are exposed in the trenches 514.
[0031] The method 400 continues with block 412 in which a bottom
electrode layer is formed to partially fill in the first and second
trenches. In FIG. 5E, a metal layer is formed over the ILD layer
144 to partially fill in the trenches 512, 514. The metal layer may
function as a bottom electrode layer for the capacitors in the
regions 104 and 106. The metal layer includes titanium nitride
(TiN). Although not limited by the present disclosure, the metal
layer may have a thickness ranging from about 100 to about 500
angstrom (A). The metal layer may be formed by atomic layer
deposition (ALD), PVD, CVD, or other suitable technique.
Alternatively, the metal layer may optionally include may tantalum
nitride (TaN), tungsten nitride (WN), ruthenium (Ru), iridium (Ir),
platinum (Pt), and combinations thereof. In other embodiments, the
metal layer may include a stack of two or more layers, such as a
titanium nitride/titanium or titanium nitride/tungsten.
[0032] The method 400 continues with block 414 in which portions of
the bottom electrode layer outside the first and second trenches
are removed. The semiconductor device 500 is planarized to remove
portions of the metal layer outside of the trenches 512, 514. For
example, a CMP or etch back process may be performed on the metal
layer and substantially stops at the ILD layer 144. Accordingly, a
bottom electrode 150 of a capacitor 114 is formed in the trenches
514 of the region 104, and bottom electrodes 312a, 312b of
capacitor 530a, 530b are formed in the trenches 512 of the region
106. The bottom electrode 150 of the capacitor 114 is electrically
coupled to the doped feature of the transistor 112 via the first
contact 142 in the region 104. As previously discussed, the
capacitor 530 in the region 106 may be considered as two capacitors
530a, 530b connected in parallel. Accordingly, the bottom
electrodes 312a, 312b are electrically coupled to the silicide
layer 132 and polysilicon layer 130 in the region 106, and thus are
electrically coupled to each other.
[0033] The method 400 continues with block 416 in which a
dielectric layer is formed to partially fill in the first and
second trenches. A dielectric layer 154, 316 is formed in the
regions 104, 106, respectively, partially filling in the trenches
514, 512. Although, referenced as different numbers 154, 316, it is
understood that the dielectric layer 154, 316 illustrated in the
regions 104, 106 are formed of the same material and process. The
dielectric layer 154, 316 includes a high-k dielectric material
such as zirconium oxide (ZrO.sub.2). Alternatively, the dielectric
layer 154, 316 may optionally include one or more layers of silicon
oxide (SiO.sub.2), silicon nitride (Si.sub.3N.sub.4), silicon
oxynitride (SiON), aluminum oxide (Al.sub.2O.sub.3), hafnium
silicates (HfSiON), tantalum oxide (Ta.sub.2O.sub.5), hafnium oxide
(HfO.sub.2), titanium oxide (TiO.sub.2), barium strontium titanate
(BST), strontium titanate oxide (STO), or combinations thereof. The
dielectric layer 154, 316 may have a thickness ranging between
about 50 to about 400 angstrom (A). The dielectric layer 154, 316
may be formed by ALD, CVD, PVD, or other suitable technique.
[0034] The method 400 continues with block 418 in which a top
electrode layer is formed over the dielectric layer to partially
fill in the first and second trenches. Another metal layer may be
formed over the dielectric layer 154, 316 that partially fills in
the trenches 512, 514. The metal layer functions as a top electrode
layer 152, 314 for the capacitors 114, 530, respectively. The metal
layer includes titanium nitride (TiN). Although not limited by the
present disclosure, the metal layer may have a thickness ranging
from about 100 to about 500 angstrom (A). The metal layer may be
formed by atomic layer deposition (ALD), PVD, CVD, or other
suitable technique. Alternatively, the metal layer may optionally
include may tantalum nitride (TaN), tungsten nitride (WN),
ruthenium (Ru), iridium (Ir), platinum (Pt), and combinations
thereof. In other embodiments, the metal layer may include a stack
of two or more layers, such as a titanium nitride/titanium or
titanium nitride/tungsten.
[0035] The method 400 continues with block 420 in which a third ILD
is formed over the top electrode layer and filling in the remainder
of the first and second trenches. The semiconductor device 500
further includes an ILD layer 168 formed over the capacitors 114,
530 substantially filling in the remainder of the trenches 512,
514. The ILD layer 168 may be similar to the ILD layer 144. The
method 400 continues with block 4222 in which an interconnect
structure is formed over the third ILD. The semiconductor device
500 includes an interconnect structure formed over the ILD layer
168 for interconnecting the various devices in the regions 102 (not
shown), 104, 106 to form an integrated circuit or system-on-chip
(SoC) device. The interconnect structure includes a plurality of
metal layers (a first level metal layer 172 is illustrated) and
intermetal dielectric for insulating each of the metal layers.
Further, the interconnect structure includes vertical connections
(vias/contacts) and horizontal connections (lines). It should be
noted that etch stop layer 502 in the region 104 may be an extra
loading for the etching process that forms the second level
contacts. For example, a plurality of contacts 170 may be formed in
the ILD layers 144, 168 for coupling the contacts 142 to the first
metal layer 172.
[0036] Referring to FIG. 6, illustrated is a flowchart of an
alternative method 600 of fabricating a semiconductor device with a
MIM capacitor according to various aspects of the present
disclosure. The method 600 implements some of the same processes as
the method 400 of FIG. 4. Referring also to FIGS. 7A-7G,
illustrated are sectional views of a semiconductor device 700 at
various stages of fabrication according to the method of FIG. 4.
The semiconductor device 700 is similar to the semiconductor
devices 100, 200, 300 in FIGS. 1-3, respectively. Accordingly,
similar features in FIGS. 1-3 and 7 are numbered the same for the
sake of simplicity and clarity. The method 600 begins with block
602 (similar to block 402 of FIG. 4) in which a semiconductor
substrate including a first region and a second region is provided.
The first region includes an isolation structure formed in the
substrate, a conductive layer formed over the isolation structure,
and a first inter-layer dielectric (ILD) formed over the conductive
layer. The second region includes a transistor having a doped
feature formed in the substrate, the first ILD formed over the
transistor, and a contact feature formed in the first ILD and
coupled to the doped feature of the transistor.
[0037] In FIG. 7A, the semiconductor device 700 is illustrated
following the formation of a plurality of first contacts 142 in the
ILD layer 140 of the region 104. The first contacts 142 are coupled
to the doped features of the transistors 112 in the region 104, and
are coupled to the doped features (e.g., source/drain and poly gate
electrode) of the transistors 120 in the region 102 (not shown).
The first contacts 142 are formed by etching trenches in the ILD
layer 140, filling the trenches with seed layers, barrier layers,
and/or metal layers, followed by a planarizing process, such as
chemical-mechanical-polishing (CMP) or a etch-back process. It
should be noted that the first contacts 142 are not formed in the
region 106. As previously discussed, the region 104 is configured
for a DRAM or embedded DRAM array, and the region 106 is configured
for a MIM capacitor. The region 106 include an STI 126 formed in
the substrate 124. The region 106 further includes an oxide layer
formed on the substrate 124, a doped polysilicon layer 130 formed
on the oxide layer, a silicide layer 132 formed on the polysilicon
layer 130, a contact etch stop layer (CESL) 134 formed on the
silicide layer 132, and the ILD layer 140 formed on the CESL 134.
It is understood that the various material layers in the region 106
may be formed concurrently when forming the transistors 112 and
other features in the region 104.
[0038] The method 600 continues with block 604 in which an etch
stop layer is formed over the first ILD. The semiconductor device
700 includes an etch stop layer 702 formed over the ILD layer 140.
The etch stop layer 702 may function as an end point of subsequent
etching processes as discussed below. Although not limited by the
present disclosure, the etch stop layer 702 may comprise silicon
carbide, silicon nitride, or silicon oxynitride, may be formed by
CVD, plasma enhanced chemical vapor deposition (PECVD), or low
pressure chemical vapor deposition (LPCVD). The etch stop layer may
have a thickness ranging from about 500 to about 1500 angstrom (A).
For example, in an embodiment in which the etch stop layer 702
comprises silicon carbide, the etch stop layer 702 may be formed by
PECVD employing a process chemistry comprising trimethylsilane.
[0039] The method 600 continues with block 606 in which a second
ILD is formed over the etch stop layer. In FIG. 7B, the
semiconductor device 700 further includes an ILD layer 144 formed
over the etch stop layer 702. The ILD layer 144 may be formed of a
similar material as the ILD layer 140. The ILD layer 144 may be
formed of silicon oxide or a low-k dielectric material. The ILD
layer 144 may be formed by chemical vapor deposition (CVD), high
density plasma CVD, spin-on, PVD (or sputtering), or other suitable
methods. The ILD layer 144 may have a thickness ranging from about
5000 to about 12000 angstrom (A).
[0040] The method 600 continues with block 608 in which a first
etching process is performed that stops at the etch stop layer
thereby forming a first trench in the first region and a second
trench in the second region. In FIG. 7C, a photoresist 704 is
formed to define openings for the capacitors in the regions 104 and
106. The photoresist 704 may be employed as a mask during an
etching process 710 and subsequently stripped, such as by wet
stripping or plasma ashing. The etching process 710 may include a
dry etch, a wet etch, a reactive ion etch (RIE), or combination dry
and wet etch process. In the present embodiment, the etching
process 710 may include a dry etch that passes through the ILD
layer 144 and substantially stops at the etch stop layer 702.
Accordingly, trenches 712 may be formed in the region 106 and
trenches 714 may be formed in the region 104.
[0041] The method 600 continues with block 610 in which the etch
stop layer in the first and second trenches are removed. In FIG.
7D, an etching process 720 is performed to selectively remove
portions of the etch stop layer 702 that are exposed in the
trenches 712, 714 in the regions 106, 104, respectively. The
etching process 720 may include a dry etch, dry etch, or
combination wet and dry etch process. For example, the etching
process 720 includes a dry etch process that has a high etching
selectivity of silicon carbide to remove the exposed etch stop
layer 702. Accordingly, the first contacts 142 may be exposed in
the trenches 714.
[0042] The method 600 continues with block 612 in which a
protection layer is formed to protect the second region. In FIG.
7E, a protection layer, such as a photoresist mask 730, is formed
to the protect the region 104 and fills in the trenches 714. The
photoresist mask 730 may be formed by a photolithography process as
was discussed above.
[0043] The method 600 continues with block 614 in which a second
etching process is performed that stops at least at the conductive
layer in the first region thereby extending the first trench. In
FIG. 7F, an etching process 740 is performed to extend the trenches
712 through the silicide layer 132, polysilicon layer 130, and a
portion of the STI 126. The etching process may 740 include a dry
etch, a wet etch, a reactive ion etch (RIE), or combination dry and
wet etch process. In the present embodiment, the etching process
740 includes a dry etch process that extends the trenches 712 into
the STI 126. It should be noted the dry etch may stop at a top
surface of the polysilicon layer 130 in some embodiments (similar
to FIG. 1), or may stop at a top surface of the STI 126 in some
other embodiments (similar to FIG. 2). The trenches 712 have
vertical sidewalls and substantially square corners due to the
anisotropic dry etch process. Accordingly, the etching process 740
further includes an isotropic etch process that modifies a corner
profile of the trenches 712 in the region 106. In some embodiments,
the corner profile of the trenches 712 may be rounded and smoothed
by an isotropic wet etch process (e.g., wet dip) as illustrated by
800 of FIG. 8. It has been observed that the capacitance value can
be increased and the reliability of the MIM structure (e.g., time
dependent dielectric breakdown (TDDB)) can be improved due to
corner rounding and smoothing.
[0044] The method 600 continues with block 616 in which the
protection layer is removed. In FIG. 7G, the photoresist mask 730
is removed from the region 106 by wet stripping or plasma ashing
after the etching process 740. The method 600 continues with blocks
412-422 of FIG. 4 to complete fabrication of the capacitors in the
trenches 712, 714, and the interconnection structure for
interconnecting the various devices and features of the regions 102
(not shown), 104, and 106.
[0045] In summary, the methods and devices disclosed herein provide
a compact MIM capacitor design with increased capacitance which may
be implemented to reduce the chip size. Accordingly, the capacitor
design may be implemented in current and advance technology node
processes (e.g., 90 nm, 65 nm, 40 nm, and beyond). The MIM
capacitor designs disclosed herein may provide various functions
and may be integrated in various applications to provide a system
on chip (SoC) device. The methods and devices disclosed herein
increase the surface area of the capacitor (e.g., capacitor
density) by extending the crown-shaped structure at least to a
conductive layer formed over an isolation structure.
[0046] In some embodiments, the MIM structure may be extended
through the conductive layer and to a top surface of the isolation
structure. In some other embodiments, the MIM structure may be
extended through the conductive layer and a portion of an isolation
structure. Further, multiple crown structures may be coupled to
each other using the conductive layer formed over the isolation
structure. Accordingly, the capacitance values may be increased
without adversely effecting the performance (e.g., increased
parasitic capacitance) in other regions of the semiconductor
device. Moreover, aspects of the present disclosure may be readily
implemented into existing device fabrication with little or no
complexity, and with little impact to fabrication time and
costs.
[0047] The present invention has been described relative to a
preferred embodiment. Improvements or modifications that become
apparent to persons of ordinary skill in the art only after reading
this disclosure are deemed within the spirit and scope of the
application. It is understood that several modifications, changes
and substitutions are intended in the foregoing disclosure and in
some instances some features of the invention will be employed
without a corresponding use of other features. For example,
although the methods and devices disclosed herein utilize a
polysilicon layer and silicide layer to couple the bottom
electrodes of the MIM capacitor, it is contemplated other types of
conductive layers may be used. For high-k metal gate technology,
the conductive layer may include a metal layer that is used to form
the metal gate of the transistors in the other regions of the
semiconductor device. Accordingly, it is appropriate that the
appended claims be construed broadly and in a manner consistent
with the scope of the invention.
* * * * *