U.S. patent application number 13/466160 was filed with the patent office on 2012-11-15 for formation of through-silicon via (tsv) in silicon substrate.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Katsuyuki Sakuma.
Application Number | 20120286428 13/466160 |
Document ID | / |
Family ID | 47141348 |
Filed Date | 2012-11-15 |
United States Patent
Application |
20120286428 |
Kind Code |
A1 |
Sakuma; Katsuyuki |
November 15, 2012 |
FORMATION OF THROUGH-SILICON VIA (TSV) IN SILICON SUBSTRATE
Abstract
To form a through-silicon via (TSV) in a silicon substrate
without using plating equipment or using sputtering equipment or
small metal particles, and form an interlayer connection by
stacking a plurality of such silicon substrates, a through hole of
a silicon substrate is filled using molten solder itself. In
detail, solid solder placed above the through hole of the silicon
substrate is molten and the molten solder is guided to and filled
in the internal space. A metal layer can be deposited on an
internal surface of the through hole beforehand, and also an
intermetallic compound (IMC) can be formed in a portion other than
the metal layer.
Inventors: |
Sakuma; Katsuyuki;
(Fishkill, NY) |
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
47141348 |
Appl. No.: |
13/466160 |
Filed: |
May 8, 2012 |
Current U.S.
Class: |
257/774 ;
257/E21.499; 257/E21.597; 257/E23.011; 438/107; 438/667 |
Current CPC
Class: |
H01L 2224/16146
20130101; H01L 2224/0401 20130101; H01L 24/16 20130101; H01L
2924/15311 20130101; H01L 2224/17181 20130101; H01L 23/147
20130101; H01L 2924/10253 20130101; H01L 2924/00014 20130101; H01L
2224/131 20130101; H01L 2924/01327 20130101; H01L 2225/06541
20130101; H01L 2224/81815 20130101; H01L 2924/01327 20130101; H01L
21/486 20130101; H01L 2224/131 20130101; H01L 2224/9202 20130101;
H01L 24/11 20130101; H01L 21/76898 20130101; H01L 23/3128 20130101;
H01L 2224/73204 20130101; H01L 2225/06565 20130101; H01L 2224/81815
20130101; H01L 2924/10253 20130101; H01L 24/81 20130101; H01L
2224/13025 20130101; H01L 2224/16227 20130101; H01L 23/49827
20130101; H01L 2224/05552 20130101; H01L 2924/00 20130101; H01L
2924/00 20130101; H01L 2924/00014 20130101; H01L 25/0657 20130101;
H01L 2224/0557 20130101; H01L 2224/171 20130101; H01L 2225/06517
20130101; H01L 23/481 20130101; H01L 2924/00014 20130101; H01L
2224/16225 20130101; H01L 24/17 20130101; H01L 2225/06513 20130101;
H01L 2924/014 20130101 |
Class at
Publication: |
257/774 ;
438/667; 438/107; 257/E21.597; 257/E23.011; 257/E21.499 |
International
Class: |
H01L 23/48 20060101
H01L023/48; H01L 21/50 20060101 H01L021/50; H01L 21/768 20060101
H01L021/768 |
Foreign Application Data
Date |
Code |
Application Number |
May 12, 2011 |
JP |
2011-107280 |
Claims
1. A method of forming a through-silicon via (TSV) in a through
hole of a silicon substrate, the method comprising: blocking a
lower end of the through hole of the silicon substrate, thereby
keeping gas from flowing from the lower end of the through hole
into an internal space of the through hole; placing solid solder
above the through hole of the silicon substrate for subsequently
filling in the through hole; evacuating a space that includes both
the internal space and an external space of the through hole;
melting the placed solid solder to block an upper end of the
through hole of the silicon substrate by the molten solder, thereby
keeping gas from flowing from the upper end of the through hole
into the internal space of the through hole; and changing an
evacuated state back to a previous state to cause a pressure
difference between the external space and the internal space of the
through hole so that the molten solder is guided to the internal
space of the through hole and the internal space of the through
hole is filled with the molten solder.
2. The method according to claim 1, further comprising: depositing
a metal layer on an internal surface of the through hole.
3. The method of claim 2, wherein the metal layer is a thin film of
Au.
4. The method of claim 2, wherein the metal layer is a thin film of
Cu.
5. The method according to claim 2, wherein a thickness of the
metal layer that is deposited on the internal surface of the
through hole is a specified thickness at which substantial electric
conduction occurs.
6. The method according to claim 5, wherein the thickness of the
metal layer is in a range of 0.64 .mu.m to 0.84 .mu.m, and ranges
therebetween, a diameter of the through hole is 50 .mu.m or less,
and a depth of the through hole is 400 .mu.m or less.
7. The method according to claim 2, further comprising: forming an
intermetallic compound (IMC) in a portion other than the metal
layer in the filled internal space of the through hole.
8. The method according to claim 7, further comprising: adding a
fine powder of metal which is Cu into the through hole before the
step of melting.
9. The method according to claim 8, wherein the metal layer has a
thickness in a range of 1 .mu.m to 9 .mu.m, and ranges
therebetween.
8-10. (canceled)
11. A method of joining a plurality of silicon substrates which are
each the silicon substrate according to claim 8, the method
comprising: providing a plurality of solder bumps on a first
silicon substrate; providing a second silicon substrate on the
plurality of solder bumps; and melting the solder bumps by
generating a specific temperature higher than a melting temperature
of the placed solid solder.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims priority under 35 U.S.C. .sctn.119
from Japanese Patent Application No. 2011-107280 filed May 12,
2011, the entire contents of which are incorporated herein by
reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a method for forming a
through-silicon via (TSV) in a through hole of a silicon substrate
in a 3D integration technique, and more specifically relates to a
technique of filling an internal space of a through hole of a small
diameter provided in a silicon substrate with molten solder. The
present invention also relates to an interlayer connection
technique whereby a plurality of silicon substrates are stacked and
joined to each other.
[0004] 2. Description of Related Art
[0005] A through-silicon via (TSV) technique is one of the 3D
integration techniques. An optimal fabrication method and material
need to be selected for the TSV, according to specifications,
architecture, silicon (substrate) thickness, and overall
fabrication process of a product that requires this integration
technique. A "through hole" filled with a conductive material
becomes wiring that functions as a conductive path after the
filling, and is also referred to as a "via".
[0006] In a commonly known TSV fabrication method, a TSV is
fabricated in a sequence of (1) etching silicon (substrate) to form
a through hole in the silicon substrate, (2) forming an insulation
film on an internal surface of the through hole, and (3) filling a
remaining internal space of the through hole with a conductive
material.
[0007] As a conventional technique for (3) in this sequence of the
fabrication method, a process of filling with the conductive
material (e.g. Cu) by plating is known. However, not only this
process requires dedicated plating equipment, but also depositing
the metal on the surface by plating takes time. Hence, this process
has low yields.
[0008] FIG. 6 shows an example of a plating process in the
conventional technique
[0009] FIG. 6(a) shows an example of plating equipment in the
conventional technique. An object to be plated is placed at a
position of a sample between a cathode and an anode. A plating
solution contains ions of metal for plating.
[0010] FIG. 6(b) shows a situation where a void occurs in the
through hole of the silicon substrate in the conventional
technique. When there is such a portion that is not filled with the
conductive material, the function as the conductive path cannot be
sufficiently achieved. Even though the TSV conducts immediately
after fabrication, there is a possibility that a conduction failure
occurs as a result of deterioration with age. Thus, the
conventional technique lacks reliability.
[0011] FIG. 6(c) shows a situation where the plating is not
deposited (not distributed) throughout the internal space of the
through hole. This is probably because, in the plating process, the
metal ions contained in the solution are grown and deposited with
time, and so there is a tendency that the metal deposits near an
entrance between the internal space and an external space of the
through hole before it reaches the internal space. In the
experimental example shown in FIG. 6(c), a diameter of the through
hole is .phi.=50 .mu.m, and a depth of the through hole (a
thickness of the silicon substrate) is t=400 .mu.m. Under
conditions of smaller scales than this, a further technique is
needed to prevent such a situation.
[0012] Patent Document 1 discloses a technique of small metal
particles having a nanocomposite structure. Such a technique can be
applied to distribute metal particles of a small diameter
throughout a through hole of a small diameter to thereby form a
TSV. However, even if the metal particles can be supplied in a
closest packing manner, still it does not mean that the metal
particles are supplied as a gap-free continuous body. Therefore,
perfect filling cannot be ensured. FIG. 7 is a diagram for
describing such a conventional technique that uses small metal
particles.
[0013] Patent Document 2 discloses a technique whereby, for an
insulation substrate made of a thermoplastic resin, a semi-molten
metal mixture is formed by mixing a binder resin in metal
particles, to improve interlayer connection reliability of a
multilayer substrate. However, required specifications and
architecture are different between the insulation substrate and the
silicon substrate, and the diameter of the through hole relating to
the present invention is of a much smaller order than the diameter
of the via hole (through hole) in Patent Document 2.
[0014] Although the binder resin is mixed in expectation of its gap
reduction effect, the use of the binder resin causes generation of
gas during melting and so rather raises a possibility of a void
occurrence.
SUMMARY OF THE INVENTION
[0015] One aspect of the present invention provides a method of
forming a through-silicon via (TSV) in a through hole of a silicon
substrate, the method including: blocking a lower end of the
through hole of the silicon substrate, thereby keeping gas from
flowing from the lower end of the through hole into an internal
space of the through hole; placing solid solder above the through
hole of the silicon substrate for subsequently filling in the
through hole; evacuating a space that includes both the internal
space and an external space of the through hole; melting the placed
solid solder to block an upper end of the through hole of the
silicon substrate by the molten solder, thereby keeping gas from
flowing from the upper end of the through hole into the internal
space of the through hole; and changing an evacuated state back to
a previous state to cause a pressure difference between the
external space and the internal space of the through hole so that
the molten solder is guided to the internal space of the through
hole and the internal space of the through hole is filled with the
molten solder.
[0016] Another aspect of the present invention provides a silicon
substrate in which a through-silicon via (TSV) is formed in a
through hole by the method of forming a through-silicon via (TSV)
as described above.
[0017] Another aspect of the present invention provides a method of
joining a plurality of silicon substrates which are each the
silicon substrate described above, the method further including:
providing a plurality of solder bumps on a first silicon substrate;
providing a second silicon substrate on the plurality of solder
bumps; and melting the solder bumps by generating a specific
temperature higher than a melting temperature of the placed solid
solder. Also provided is a 3D chip where the chip includes a
plurality of silicon substrates joined by this method.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The invention and its preferred embodiments, additional
objects, features and advantages will be better understood by
referring to the detailed description of the exemplary embodiments
when read in conjunction with the attached drawings, in which:
[0019] FIG. 1 illustrates a section diagram showing a 3D chips in
which a plurality of silicon substrates are joined to each other
according to an embodiment of the present invention.
[0020] FIG. 2 illustrates a schematic diagram showing a method for
forming a through-silicon via (TSV) in a through hole of a silicon
substrate using molten solder itself, according to an embodiment of
the present invention.
[0021] FIG. 3 illustrates a diagram for describing a structure in
which a metal layer is deposited on an internal surface of the
through hole of the silicon substrate and a structure in which an
intermetallic compound (IMC) is formed in a portion other than the
metal layer, according an embodiment of the present invention.
[0022] FIG. 4 illustrates a diagram for describing a skin effect of
the metal layer according to an embodiment of the present
invention.
[0023] FIG. 5 illustrates a conceptual diagram for describing a
process of adding a fine powder of metal (Cu) into the through hole
according to an embodiment of the present invention.
[0024] FIG. 6 illustrates a diagram showing an example of a plating
process in a conventional technique according to an embodiment of
the present invention.
[0025] FIG. 7 illustrates a diagram for describing a conventional
technique that uses small metal particles according to an
embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0026] The present invention has an object of forming a
through-silicon via (TSV) in a silicon substrate without using
plating equipment or small metal particles, and forming an
interlayer connection by stacking and joining a plurality of such
silicon substrates.
[0027] In one aspect of the present invention, a through hole of a
silicon substrate is filled using molten solder itself. In more
detail, a lower end of the through hole of the silicon substrate is
blocked, solid solder placed above the through hole (directly above
or above and to the side of the through hole) of the silicon
substrate is molten, and the molten solder is guided to and filled
in the internal space of the through hole by a pressure difference
between the external space and the internal space of the through
hole.
[0028] A through-silicon via (TSV) that has no conduction failure
caused by a void occurrence can be formed without a time-consuming
process of depositing metal on an internal surface of a through
hole by plating.
[0029] The metal layer deposited beforehand contributes to improved
wettability of the internal surface of the through hole, which
facilitates passage of a high frequency signal.
[0030] By forming the intermetallic compound (IMC) so as to prevent
remelting in a subsequent process, a high resistance to
electromigration can be attained.
[0031] FIG. 1 illustrates a section diagram showing a 3D stacked
body in which a plurality of silicon substrates are joined to each
other.
[0032] In this specification, the term "silicon substrate" has a
broad concept including a silicon interposer and a silicon chip
typically with a substrate shape so long as a through-silicon via
(TSV) can be formed. The silicon chip is usually much thinner than
the silicon interposer.
[0033] The plurality of silicon substrates are electrically and
mechanically joined through fine-pitch solder bumps. The solder
bumps solidified as a result of melting are shown in the drawing.
The plurality of silicon substrates are joined by a process of
providing a first silicon substrate, providing a plurality of
solder bumps on the first silicon substrate, providing a second
silicon substrate on the plurality of solder bumps, and melting the
placed solid solder.
[0034] In the case where a required series of fabrication process
(overall fabrication process) is such a type that stacks silicon
substrates one by one in a laminated structure, it is preferable to
prevent remelting even when a specific temperature equal to or
higher than a temperature generated in a previous process to melt
solid solder is generated in a subsequent process. This is because
there is a possibility that remelting causes an already joined
silicon substrate situated below to be displaced. A structure
having such a resistance is referred to as a structure highly
resistant to electromigration.
[0035] A metal layer can be deposited on an internal surface of the
through hole beforehand, and also an intermetallic compound (IMC)
can be formed in a portion other than the metal layer.
[0036] FIG. 2 is a schematic diagram showing a method for forming a
through-silicon via (TSV) in a through hole of a silicon substrate
using molten solder itself, according to an embodiment of the
present invention.
[0037] First, a lower end of each through hole of the silicon
substrate is blocked, as shown in FIG. 2(a). The blocking can be
made with a molten solder bump or an I/O pad shown in FIG. 1, as
long as gas is kept from flowing from the lower end of the through
hole into its internal space.
[0038] In addition, sold solder prepared for subsequently filling
the through hole is placed above the through hole (directly above
or above and to the side of the through hole) of the silicon
substrate, as shown in FIG. 2(a). The solid solder can be platelike
or spherical in shape.
[0039] In this state, a space including both the internal space and
the external space of the through hole is evacuated, as shown in
FIG. 2(a). There is no need to fear that the internal space of the
through hole can not be evacuated when the solid solder lies
directly above the through hole, because the actual solid solder
has innumerable projections and depressions on its surface and so
there is a clearance between the internal space and the external
space of the through hole.
[0040] Various techniques for evacuating both the internal space
and the external space of the through hole can be conceivable by a
person skilled in the art. The term "evacuation" should be broadly
interpreted so long as it is a process of causing a pressure
difference between the external space and the internal space of the
through hole.
[0041] Next, the solder is molten in the state where the space is
evacuated, as shown in FIG. 2(b). For example, heating is performed
at 260.degree. C. or higher, which is a melting point of solid
solder (the melting point can be 300.degree. C. or higher depending
on solder composition). The heating method can be a method for
heating the entire atmosphere or a method for heating only the
solid solder (as intensively as technically possible). As a result,
the placed solid solder melts and flows as a gap-free continuous
body, so that the upper end of the through hole of the silicon
substrate is blocked by the molten solder. This keeps gas from
flowing from the upper end of the through hole into the internal
space.
[0042] Lastly, the evacuated state is changed back to the previous
state (i.e. FIG. 2(a)), as shown in FIG. 2(c). In other words, the
vacuum is released. As a result, the external space of the through
hole is brought back to the same ambient pressure as in the
previous state, causing a pressure difference between the external
space and the internal space of the through hole. Due to this
pressure difference, the molten solder, flowing as a gap-free
continuous body, is guided to the internal space of the through
hole. Thus, the internal space of the through hole is filled with
the molten solder.
[0043] FIG. 3 is a diagram for describing a structure in which a
metal layer is deposited on an internal surface of the through hole
of the silicon substrate and a structure in which an intermetallic
compound (IMC) is formed in a portion other than the metal layer,
according to the present invention.
[0044] FIG. 3(a) schematically shows a process of forming the
intermetallic compound (IMC) in the internal space of the through
hole.
[0045] First, in FIG. 3(a1), the metal layer is deposited on the
internal surface of the through hole. The deposition method can be
plating (of the conventional technique shown in FIG. 6) or the
like. A thin film of gold (Au), for example, is a favorable
material when wettability (affinity with other metal) in the next
process and the like are taken into consideration. A thin film of
copper (Cu) is also applicable.
[0046] Next, in FIG. 3(a2), a different kind of metal (e.g. solder)
is filled in the portion other than the metal layer deposited on
the internal surface of the through hole. In FIG. 3(a3), the
intermetallic compound (IMC) is formed in the internal space of the
through hole.
[0047] FIG. 3(b) is a diagram showing a distribution of the
intermetallic compound (IMC) formed in the case where Cu is used in
the metal layer and solder (whose composition has Cu and Sn as main
components) is used in the other portion. A pure metal layer is
formed at Pt1, while solder of Cu and Sn is filled at Pt2 in the
other portion, creating a boundary.
[0048] Moreover, a metal composition of Ni and Au is contained
further inside at Pt3 and Pt4. This is probably because, in the
process where the solid solder placed above the through hole
(directly above or above and to the side of the through hole) of
the silicon substrate is molten and guided to the internal space of
the through hole so as to be filled in the through hole as shown in
FIG. 2, wiring metal and the like mounted above the through hole
(directly above or above and to the side of the through hole) of
the silicon substrate diffuse into the solder.
[0049] FIG. 3(c) is a Cu--Sn system phase diagram showing a change
in melting point of the intermetallic compound (IMC). It can be
expected that a phase according to this equilibrium state appears
as long as Cu and Sn are the main components of the composition. In
two phases of composition ratio at two positions indicated by
arrows, the intermetallic compound (IMC) with an increased melting
point is formed to thereby prevent remelting in a subsequent
process.
[0050] In the experimental condition in FIG. 3(b), the through hole
is 5 .mu.m or less in diameter. This demonstrates that the present
invention is applicable even in such a case. The method for the
present invention seems to be more advantageous when the diameter
of the through hole is smaller.
[0051] FIG. 4 is a diagram for describing a skin effect of the
metal layer according to the present invention.
[0052] A cross section of the through-silicon via (TSV) (as viewed
from above in FIGS. 1 to 3) is schematically shown in FIG. 4. A
pure metal layer is formed in a thickness portion close to the
internal surface of the through hole (the periphery of the through
hole), while an intermetallic compound (IMC) state (or a similar
state) is formed in a portion other than the metal layer. It is
commonly known that an intermetallic compound (IMC) has lower
electric conductivity than pure metal.
[0053] On the other hand, metal having favorable electric
conductivity is scarce in many cases, and Au, for example, is
expensive metal. In view of this, it is important to take a skin
depth where a skin effect appears, into consideration. Throughout
the filled internal space of the through hole, substantial electric
conduction occurs only in this thickness. Based on such an aspect,
an appropriate thickness of the metal layer to be deposited
beforehand can be determined. This eliminates waste of using
redundant material, exceeding the required product specifications
and architecture (overdesigned).
[0054] It is known that the skin depth by the skin effect is
smaller when the frequency is higher. In copper, silver, gold, and
aluminum which are typical materials having favorable electric
conductivity, the skin depth is in a range of 0.64 .mu.m to 0.84
.mu.m when the frequency is as high as 10 GHz.
[0055] FIG. 5 is a conceptual diagram for describing a process of
adding a fine powder of metal (Cu) into the through hole. This
process is effective in the case of forming the intermetallic
compound (IMC) as widely and reliably as possible. In the case
where the metal layer deposited beforehand is made of Cu and is
thick, for example, in a range of 1 .mu.m to 9 .mu.m, Cu can be
effectively mixed in the through hole.
[0056] By adding the fine powder of metal (Cu) into the internal
space of the through hole before the solder melting process, it can
be expected that the intermetallic compound (IMC) is effectively
formed especially by a synergic effect that the fine powder and the
metal layer are made of the same metal (e.g. Cu), since the metal
layer deposited beforehand is thick. The small metal particles in
the conventional technique shown in FIG. 7 can be used in such a
manner.
* * * * *