U.S. patent application number 13/457825 was filed with the patent office on 2012-11-01 for liquid crystal display and array substrate.
This patent application is currently assigned to BOE TECHNOLOGY GROUP CO., LTD. Invention is credited to Seungjin CHOI, Guanboa HUI, Feng ZHANG.
Application Number | 20120273789 13/457825 |
Document ID | / |
Family ID | 44895853 |
Filed Date | 2012-11-01 |
United States Patent
Application |
20120273789 |
Kind Code |
A1 |
HUI; Guanboa ; et
al. |
November 1, 2012 |
LIQUID CRYSTAL DISPLAY AND ARRAY SUBSTRATE
Abstract
An embodiment of the disclosed technology discloses an array
substrate comprising: a base substrate; a first layer transparent
common electrode formed on the base substrate; a gate metal common
electrode formed on the first layer transparent common electrode;
an insulation layer formed on the gate metal common electrode, with
via holes being formed in the insulation layer; and a second layer
transparent common electrode formed on the insulation layer. A side
portion of via holes is in contact with the gate metal common
electrode, another side portion is in contact with the first layer
transparent common electrode, such that the second layer
transparent common electrode is connected electrically with the
first layer transparent common electrode and the gate metal common
electrode in the via holes.
Inventors: |
HUI; Guanboa; (Beijing,
CN) ; CHOI; Seungjin; (Beijing, CN) ; ZHANG;
Feng; (Beijing, CN) |
Assignee: |
BOE TECHNOLOGY GROUP CO.,
LTD
Beijing
CN
|
Family ID: |
44895853 |
Appl. No.: |
13/457825 |
Filed: |
April 27, 2012 |
Current U.S.
Class: |
257/59 ;
257/E29.273 |
Current CPC
Class: |
H01L 29/4908 20130101;
H01L 27/124 20130101; G02F 1/136227 20130101; G02F 2001/134381
20130101 |
Class at
Publication: |
257/59 ;
257/E29.273 |
International
Class: |
H01L 29/786 20060101
H01L029/786 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 29, 2011 |
CN |
201120136037.9 |
Claims
1. An array substrate comprising: a base substrate; a first layer
transparent common electrode formed on the base substrate; a gate
metal common electrode formed on the first layer transparent common
electrode; an insulation layer formed on the gate metal common
electrode, with via holes being formed in the insulation layer; and
a second layer transparent common electrode formed on the
insulation layer; wherein a side portion of the via holes is in
contact with the gate metal common electrode, another side portion
is in contact with the first layer transparent common electrode,
such that the second layer transparent common electrode is
connected electrically with the first layer transparent common
electrode and the gate metal common electrode in the via holes.
2. The array substrate according to claim 1, wherein the insulation
layer comprises: a gate insulation layer formed on the gate metal
common electrode and a passivation insulation layer formed on the
gate insulation layer.
3. The array substrate according to claim 1, wherein the bottom of
at least one of the via holes is formed in a step-like shape.
4. The array substrate according to claim 2, wherein the bottom of
at least one of the via holes is formed in a step-like shape.
5. The array substrate according to claim 1, wherein the gate metal
common electrode is in contact with a side portion and a part of
the bottom of the corresponding via hole, and the first layer
transparent common electrode is in contact with the other part of
the bottom of the via hole.
6. The array substrate according to claim 2, wherein the gate metal
common electrode is in contact with a side portion and a part of
the bottom of the corresponding via hole, and the first layer
transparent common electrode is in contact with the other part of
the bottom of the via hole.
7. The array substrate according to claim 3, wherein the gate metal
common electrode is in contact with a side portion and a part of
the bottom of the corresponding via hole, and the first layer
transparent common electrode is in contact with the other part of
the bottom of the via hole.
8. The array substrate according to claim 1,wherein the gate metal
common electrode is in contact with a side portion of the
corresponding via hole, and the first layer transparent common
electrode is in contact with the bottom of the via hole.
9. The array substrate according to claim 2,wherein the gate metal
common electrode is in contact with a side portion of the
corresponding via hole, and the first layer transparent common
electrode is in contact with the bottom of the via hole.
10. The array substrate according to claim 1, wherein the gate
insulation layer includes one via hole at the either side of each
gate metal line.
11. The array substrate according to claim 2, wherein the gate
insulation layer has one via hole at the either side of each gate
metal line.
12. The array substrate according to claim 3, wherein the gate
insulation layer has one via hole at the either side of each gate
metal line.
13. The array substrate according to claim 3, wherein the bottoms
of both via holes in two adjacent rows are formed in a step-like
shape.
14. A liquid crystal display, comprising an array substrate which
comprises: a base substrate; a first layer transparent common
electrode formed on the base substrate; a gate metal common
electrode formed on the first layer transparent common electrode;
an insulation layer formed on the gate metal common electrode, with
via holes being formed in the insulation layer; and a second layer
transparent common electrode formed on the insulation layer;
wherein a side portion of the via holes is in contact with the gate
metal common electrode, another side portion is in contact with the
first layer transparent common electrode, such that the second
layer transparent common electrode is connected electrically with
the first layer transparent common electrode and the gate metal
common electrode in the via holes.
Description
BACKGROUND
[0001] Embodiments of the disclosed technology relate to a liquid
crystal display (LCD) and an array substrate.
[0002] Thin film transistor liquid crystal displays (TFT-LCDs) have
the characteristics of small volume, low power consumption, no
radiation and so on, and have prevailed in the present market of
flat displays. However, liquid crystal displays have the
disadvantage of relatively narrow viewing angle, thus the
manufacturers developed various wide viewing angle technologies.
Among the wide viewing angle technologies, advanced-super
dimensional switching technology (AD-SDS) forms a multi-dimensional
electric field including a parallel electric field generated
between the sides (edge portions) of the pixel electrodes within a
same plane and a longitudinal electric field generated between the
pixel electrode layer and the common electrode layer on different
layers, which enables all liquid crystal molecules between the
pixel electrode and above the electrodes within the liquid crystal
cell to rotate so as to enhance the work efficiency of the plane
orientation liquid crystal and increase light transmittance. AD-SDS
technology can be used to improve the display quality of TFT-LCDs,
and has the advantages of high transmittance, wide viewing angle,
high aperture ratio, low color aberration, small response time, no
push Mura, etc.
[0003] In order to reduce production cost, the number of mask
processes (i.e., the number of the mask used or the number of
photolithography process) was reduced during the preparation
process of the TFT-LCD array substrates of the AD-SDS type.
Presently, manufacturers are actively developing 4-mask process to
prepare the TFT-LCD array substrates of the AD-SDS type. As shown
in FIGS. 1, 2 and 3, a conventional method comprises the following
processes. The first mask process: a first transparent electrode
layer and a gate metal layer are deposited on a glass substrate 1,
exposure is conducted with a gray scale mask plate in a gray scale
mask process, and etching, ashing, and removing processes are
conducted to form the first layer transparent common electrode 2, a
gate metal line 3 (including gate electrode (Gate)), two gate metal
common electrodes (the gate metal common electrode 11' in one row
and the gate metal common electrode 12' in a previous row). The
second mask process: on the formed pattern described above, a gate
insulation layer, a semiconductor layer, a doped semiconductor
layer and a source/drain metal layer are sequentially deposited,
then exposure is conducted with a gray scale mask plate in using a
gray scale mask process, and etching, ashing, and removing
processes are conducted to form a gate insulation layer 4, a
semiconductor layer 5 (semiconductor active silicon island), a
doped semiconductor layer 6 and a source/drain metal layer 7
(including source electrodes, drain electrodes, and data lines).
The third mask process: a passivation insulation layer 8 (via hole
layer) is deposited on the source/drain metal layer 7 and covers
the entire glass substrate 1, and then via holes 10' and 14' are
formed in the passivation insulation layer 8 by the process of
exposure and etching. The fourth mask process: a transparent
electrode layer is deposited on the substrate, a second layer of
transparent pixel electrode 9 and a second layer transparent common
electrode 13 are formed by the process of exposure and etching with
a gray scale mask process. The pixel electrode 9 is connected with
one of the source and drain electrodes by the via hole 10'; the
second layer transparent common electrode 13 is connected with both
the common electrodes 11' and 12' in two adjacent pixel rows by via
holes 14'. In the area connecting the common voltage signals of the
pixels in the present and previous lines (as shown in FIG. 3), the
cross-section of via holes 14' is U-shaped or square-shaped, the
bottom side is in contact with the gate metal common electrodes
11', 12', under which the first layer transparent common electrode
2 is formed and not in contact with the via hole 14'.
[0004] The conventional technology employs amorphous indium tin
oxide (a-ITO) thin film in preparing the first layer transparent
common electrode with a gray scale mask plate; when the film for
forming the next gate insulation layer 4 is deposited, the
temperature is typically of above 300 degree Celsius. The a-ITO
thin film will undergo a crystallization reaction under such a high
temperature and be converted into polycrystalline indium tin oxide
(p-ITO) thin film. Since the crystal grains of p-ITO are different
in size from those of the gate metal common electrode 11', 12', it
will result in strip and delamination between the first layer
transparent common electrode 2 and the gate metal common electrode
11', 12' during the course of a-ITO being converted into p-ITO (as
shown in FIG. 4), and cracks or gaps 15 appear. Such gaps 15 can
cause poor contact, thus the voltage signals over the gate metal
common electrode 11', 12' can not be transferred to the first layer
transparent common electrode 2 effectively, such that in the
adjacent pixel rows, the first layer transparent common electrode
of the previous pixel row and the first layer transparent common
electrode of the present pixel row can not work normally, which
results in the abnormality of the pixel operation and affects the
display effect and display quality.
SUMMARY
[0005] An embodiment of the disclosed technology provides an array
substrate comprising: a base substrate; a first layer transparent
common electrode formed on the base substrate; a gate metal common
electrode formed on the first layer transparent common electrode;
an insulation layer formed on the gate metal common electrode, with
via holes being formed in the insulation layer; and a second layer
transparent common electrode formed on the insulation layer;
wherein a side portion of via holes is in contact with the gate
metal common electrode, another side portion is in contact with the
first layer transparent common electrode, such that the second
layer transparent common electrode is connected electrically with
the first layer transparent common electrode and the gate metal
common electrode in the via holes.
[0006] Another embodiment of the disclosed technology provides a
liquid crystal display which comprises the above-mentioned array
substrate.
[0007] In the above embodiments, the gate metal common electrode is
shorten on one side to be located below the via holes; a portion of
the bottom of each via hole after photolithography is in contact
with the gate metal common electrode, and another portion is in
contact with the first layer transparent common electrode.
Therefore, the voltage signals over the gate metal common electrode
can be transferred to the first layer transparent common electrode
through the second layer transparent common electrode, which is in
contact with the first layer transparent common electrode, in the
bottom of the via holes, even if strip and delamination occur
between the first layer transparent common electrode and the gate
metal common electrode, so as to ensure the common electrode
signals of the pixels in adjacent two rows can be transferred
normally and the pixels are able to be displayed normally, which
ensures the display effect of the liquid crystal display and
improve the display quality.
[0008] Further scope of applicability of the disclosed technology
will become apparent from the detailed description given
hereinafter. However, it should be understood that the detailed
description and specific examples, while indicating preferred
embodiments of the disclosed technology, are given by way of
illustration only, since various changes and modifications within
the spirit and scope of the disclosed technology will become
apparent to those skilled in the art from the following detailed
description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The disclosed technology will become more fully understood
from the detailed description given hereinafter and the
accompanying drawings which are given by way of illustration only,
and thus are not limitative of the disclosed technology and
wherein:
[0010] FIG. 1 is a top view of a liquid crystal display array
substrate in conventional technology;
[0011] FIG. 2 is a cross-sectional view of FIG. 1 taken from
A'-A;
[0012] FIG. 3 is a cross-sectional view of FIG. 1 taken from
B'-B;
[0013] FIG. 4 is a cross-sectional view of FIG. 1 taken from B'-B,
which shows appearance of abnormality;
[0014] FIG. 5 is a top view of a liquid crystal display array
substrate according to an embodiment of the disclosed technology;
and
[0015] FIG. 6 is a cross-sectional view of FIG. 5 taken from
B'-B.
DETAILED DESCRIPTION
[0016] The specific implementation of the disclosed technology will
be further described below in detail in conjunction with the
drawings and embodiments. The following embodiments are used to
illustrate the technical solution of the disclosed technology, but
not limiting the scope of the disclosed technology.
[0017] FIG. 5 and FIG. 6 are respectively the top view and the
cross-sectional view of a liquid crystal display array substrate of
an embodiment of the disclosed technology. This array substrate 100
comprises: a base substrate 1 which is a glass substrate 1 in this
embodiment, a first layer transparent common electrode 2 is formed
on the glass substrate 1, and gate metal common electrodes 11, 12
are formed on the first layer transparent common electrode 2. The
gate metal common electrode 11 is located in one pixel line, while
the gate metal common electrode 12 is located in the upper adjacent
pixel line. An insulation layer 4, 8 is formed on the gate metal
common electrode 11, 12, and the insulation layer is provided with
via holes 14 therein. One side portion of at least one via hole 14
is in contact with the gate metal common electrode (11 or 12), and
the other side portion is in contact with the first layer
transparent common electrode 2. One side of the gate metal common
electrode 11 is aligned and overlapped with the first layer
transparent common electrode 2, the other side extends to under the
lower side of the via hole 14 at the common electrode; one side of
the gate metal common electrode 12 in the upper adjacent row is
aligned and overlapped with the first layer transparent common
electrode 2, and the other side extends to under the lower side of
another via hole 14 at the common electrode. A second layer
transparent common electrode 13 is formed on the insulation layer,
the second layer transparent common electrode 13 is in contact with
the gate metal common electrodes 11, 12 through side portions of
via holes14, and another side portion of the common electrode 13 is
in contact with the first layer transparent common electrode 2,
thus electrically connecting the gate metal common electrode 11 and
12.
[0018] The insulation layer above the gate metal common electrode
11, 12 comprises a gate insulation layer 4 which is formed on the
gate metal common electrode 11 and a passivation insulation layer 8
which is formed on the gate insulation layer 4. The via holes 14
are formed through the passivation insulation layer 8 and the gate
insulation layer 4.
[0019] On each side of the gate metal line 3 one via hole 14 is
formed. These two via holes 14, for example, are provided
symmetrically on both sides of the gate metal line 3. The bottom of
the at least one via hole14 is formed in a step-like shape as shown
in FIG. 5.
[0020] For one via hole14, as shown in FIG. 5, a side portion and a
part of the bottom of the via hole are in contact with the gate
metal common electrode 11, and the other part of the bottom is in
contact with the first layer transparent common electrode 2. A side
portion and a part of the bottom of another via hole 4 are in
contact with the gate metal common electrode 12 in the upper row,
and the other part of the bottom is in contact with the first layer
transparent common electrode 2.
[0021] Or, for one via hole14, a side portion of the via hole is in
contact with the gate metal common electrode 11, and the bottom of
it is in contact with the first layer transparent common electrode
2; for the other via hole 14, a side portion of the via hole is in
contact with the gate metal common electrode 12 in the upper row,
and the bottom of it is in contact with the first layer transparent
common electrode 2.
[0022] In preparing the above array substrate, taking the via
hole14 as an example, in the first-time gray scale mask process,
the transparent common electrode layer and the gate metal layer are
deposited sequentially on the glass substrate 1, and the stacked
layers of the transparent common electrode layer and the gate metal
layer described above are patterned with the process of
photolithography to form the first layer transparent common
electrode 2 and the gate metal common electrodes 11, 12 on the
first layer transparent common electrode 2. In the area connecting
the common voltage signals of the pixels in the upper and lower
adjacent lines, the gate metal common electrodes 11, 12 are formed
to extend to under the lower side corresponding to the positions of
the via holes 14 in the subsequent photolithography progress with a
gray scale mask. The via holes 14 are formed by etching through the
insulation layers 4, 8 till the first layer transparent common
electrode 2. In this way, even if the strip and delamination occur
between the first layer transparent common electrode 2 and the gate
metal common electrodes 11, 12, the voltage signals over the gate
metal common electrodes 11,12 can be transferred to the first layer
transparent common electrode 2 through the second layer transparent
common electrode 13 at the bottom of the via holes 14, which is in
contact with the first layer transparent common electrode 2, so as
to ensure the first layer transparent common electrodes 2 of the
adjacent pixels to work normally and the pixels can display
normally, which ensures the display effect of the liquid crystal
display and improve the display quality.
[0023] The liquid crystal display according to the embodiment of
the disclosed technology comprises an array substrate according to
any one of the above-described array substrates of the disclosed
technology, and may further comprise other components such as a
color filter substrate, a backlight module, driving circuits, etc.
The liquid crystal display can be applied to TV sets, mobile
phones, computers, and the like.
[0024] The embodiment of the disclosed technology being thus
described, it will be obvious that the same may be varied in many
ways. Such variations are not to be regarded as a departure from
the spirit and scope of the disclosed technology, and all such
modifications as would be obvious to those skilled in the art are
intended to be included within the scope of the following
claims.
* * * * *