U.S. patent application number 13/526062 was filed with the patent office on 2012-10-04 for reliable and efficient computation of modal interval arithmetic operations.
This patent application is currently assigned to Sunfish Studio, LLC. Invention is credited to Nathan T. Hayes.
Application Number | 20120254275 13/526062 |
Document ID | / |
Family ID | 37906825 |
Filed Date | 2012-10-04 |
United States Patent
Application |
20120254275 |
Kind Code |
A1 |
Hayes; Nathan T. |
October 4, 2012 |
RELIABLE AND EFFICIENT COMPUTATION OF MODAL INTERVAL ARITHMETIC
OPERATIONS
Abstract
A computer executable method of performing a modal interval
operation, and system for performing same is provided. The method
includes providing representations of first and second modal
interval operands. Each modal interval operand of the operands is
delimited by first and second marks of a digital scale, each mark
of the marks comprises a bit-pattern. Each bit-pattern of the
bit-patterns of the marks of each of the modal interval operands
are examined, and conditions of a set of status flags corresponding
to each bit-pattern of the bit-patterns of the marks are set. A
bit-mask is computed wherein the mask is based upon the set
condition of the status flag sets and a presence/absence of an
exceptional arithmetic condition, and a presence/absence of an
indefinite operand are each represented by a bit of said bits of
said bit mask.
Inventors: |
Hayes; Nathan T.;
(Minneapolis, MN) |
Assignee: |
Sunfish Studio, LLC
|
Family ID: |
37906825 |
Appl. No.: |
13/526062 |
Filed: |
June 18, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12088374 |
Mar 27, 2008 |
8204926 |
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PCT/US06/38578 |
Oct 2, 2006 |
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13526062 |
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60723059 |
Oct 3, 2005 |
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60723249 |
Oct 3, 2005 |
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Current U.S.
Class: |
708/490 |
Current CPC
Class: |
G06F 7/49989
20130101 |
Class at
Publication: |
708/490 |
International
Class: |
G06F 7/483 20060101
G06F007/483 |
Claims
1-47. (canceled)
48. A method of performing a modal interval operation comprising:
a. providing representations of first and second modal interval
operands such that each modal interval operand of the modal
interval operands is delimited by first and second marks of a
digital scale, each mark of the marks comprising a bit-pattern; b.
constructing a bit-mask based upon each bit-pattern of the marks of
the first and second marks, a presence or absence of an exceptional
arithmetic condition and a presence or absence of an indefinite
operand, or division by zero, each represented by a bit of bits of
said bit mask; and, c. ascertaining said exceptional arithmetic
condition in advance of ascertaining said presence or absence of an
indefinite operand or division by zero, and subsequently,
separately and selectively treating said exceptional arithmetic
condition.
Description
[0001] This is an international application filed under 35 USC
.sctn.363 claiming priority under 35 U.S.C. .sctn.119(e) (1), of
U.S. provisional application Ser. Nos. 60/723,059 and 60/723,249,
each having a filing date of Oct. 3, 2005, said applications
incorporated herein by reference in their entireties.
TECHNICAL FIELD
[0002] The present invention generally relates to methods
associated with the execution of arithmetic operations on modal
intervals within a computing/processing environment, more
particularly, the present invention relates to a system and method
of performing a modal interval arithmetic operation that is both
mathematically reliable and computationally efficient.
BACKGROUND OF THE INVENTION
[0003] The common and popular notion of interval arithmetic is
based on the fundamental premise that intervals are sets of numbers
and that arithmetic operations can be performed on these sets. Such
interpretation of interval arithmetic was initially advanced by
Ramon Moore in 1957, and has been recently promoted and developed
by interval researchers such as Eldon Hansen, William Walster, Guy
Steele and Luc Jaulin. This is the so-called "classical" interval
arithmetic, and it is purely set-theoretical in nature.
[0004] A set-theoretical interval is a compact set of real numbers
[a,b] such that a.ltoreq.b. The classical interval arithmetic
operations of addition, subtraction, multiplication and division
combine two interval operands to produce an interval result such
that every arithmetical combination of numbers belonging to the
operands is contained in the interval result. This leads to
programming formulas made famous by classical interval analysis,
and which are discussed at length in the interval literature.
[0005] Translating interval programming formulas into practical
computational methods that can be performed within a computer
remains a topic of research in the interval community. The
Institute of Electrical and Electronics Engineers Standard for
Binary Floating-Point Arithmetic (i.e., IEEE standard 754), which
specifies exceptionally particular semantics for binary
floating-point arithmetic, enjoys pervasive and worldwide use in
modern computer hardware. As a result, efforts have been focused on
creating practical interval arithmetic implementations that build
on the reputation and legacy of this standard.
[0006] Creating practical implementations, however, is not without
its perils. The problems begin with choosing a suitable
representation in a computer for the intervals. An obvious choice
is to use two floating-point numbers to represent the endpoints of
an interval. What is not obvious is how to handle complications
which arise in conditions such as overflow, underflow and
exceptional combinations of operands.
[0007] IEEE standard 754 specifies bit-patterns to represent real
floating-point numbers as well as -.infin., +.infin., -0, +0 and
the pseudo-numbers, which are called NaNs (i.e., Not-a-Number).
Although the standard defines precise rules for the arithmetical
combination of all permutations of bit-patterns of two
floating-point values, the translation of these rules into
arithmetical combinations of intervals is unclear. As is widely
held, mapping the interval endpoints onto the set of IEEE
floating-point representations is both desirable and
challenging.
[0008] With great debate, and various levels of success,
set-theoretical interval researchers have developed different
representation methods for intervals. In the paper "Interval
Arithmetic: from Principles to Implementation," Hickey, et. al.,
Journal of the ACM, Vol. 48.5, 2001, p. 1038-1068, incorporated
herein by references, the authors discuss and summarize the many
different implementations and viewpoints of the interval community
on this subject. In another example, Walster defines a
sophisticated mapping of set-theoretical intervals to IEEE standard
754 in U.S. Pat. No. 6,658,443, which is also incorporated herein
by reference.
[0009] Consensus in the interval community remains divided. As an
example, the methods of both Walster and Hickey require special
treatment of -0 and +0 as distinct values. However, others, like
Jorge Stolfi, reject such special treatments of -0, and generally
comment that while it is possible to concoct examples where such
special treatment saves an instruction or two, in the vast majority
of applications doing so is an annoying distraction, and a source
of subtle bugs.
[0010] This observation is closely related to a problem that
plagues representations of intervals in the prior art: a lack of
closure or completeness. Such representations do not specify
semantics for all possible bit-patterns of intervals represented by
the set of IEEE floating-point numbers.
[0011] For example, in the 1997 monograph "Self-Validated Numerical
Methods and Applications," Stolfi describes a system and method for
representing set-theoretical intervals within a computer, but not
all possible bit-patterns are accounted for. The computational
programs therein assume such bit-patterns will not appear as an
operand. If the user does not take great care to submit only the
valid subset of operands to the computational program, unreliable
results are the inevitable and unfortunate consequence.
[0012] The same problem or shortcoming is found in the
representations of Walster and Hickey. In both cases, true
mathematical zero must be represented as the interval [-0, +0]. By
construction, the intervals [0013] [-0,-0] [+0,+0] [+0,-0] are
invalid and have no semantical meaning. If great care is not taken
to ensure these intervals do not appear in a computation,
unreliable results occur.
[0014] Similarly, semantics do not exist, or are unclear for some
intervals involving infinities. As an example, Walster's method is
ambiguous on the treatment of the intervals [0015]
[-.infin.,-.infin.] [+.infin.,+.infin.], whereas Stolfi
unequivocally identifies such intervals as invalid.
[0016] Last but hardly least, computational simplicity is another
goal that has so far been elusive. For example, the method of
Walster requires significant amounts of special software
instruction to create an implementation that works properly with
existing hardware, with such requirement no doubt an obstacle to
creating a practical implementation and/or commercial product
embodying same.
[0017] In 2001, Miguel Sainz and other members of the SIGLA/X group
at the University of Girona, Spain, introduced a new branch of
interval mathematics known as "modal intervals." Unlike the
classical view of an interval as a compact set of real numbers, the
new modal mathematics considers an interval to be a quantified set
of real numbers.
[0018] As a practical consequence, a modal interval is comprised of
a binary quantifier and a set-theoretical interval. In the modal
interval literature, an apostrophe is used to distinguish a
set-theoretical interval from a modal interval, so if Q is a
quantifier and X' is a purely set-theoretical interval, then X=(Q,
X') is a modal interval. For this reason, it is easy to see that
modal intervals are a true superset of the classical
set-theoretical intervals. At the same time, the quantified nature
of a modal interval provides an extra dimension of symmetry not
present in the classical set-theoretical framework.
[0019] This difference allows the modal intervals to solve problems
out of the reach of their classical counterparts. Just as the real
expression 3+x=0 has no meaning without negative numbers, it can be
shown that the interval expression [1,2]+X=[0,0] has no meaning
without quantified (i.e., modal) intervals.
[0020] The quantified nature of a modal interval comes from
predicate logic, and the value of a quantifier may be one of the
fundamental constructions .E-backward. or .A-inverted., that is,
"existential" or "universal." The symbols .E-backward. and
.A-inverted. are commonly read or interpreted as "there exists" and
"for all," respectively.
[0021] The article "Modal Intervals," M. Sainz, et. al., Reliable
Computing, Vol. 7.2, 2001, pp. 77-111, provides an in-depth
introduction to the notion of modal intervals, how they differ from
the classical set-theoretical intervals, and upon what mathematical
framework they operate; the article is also incorporated herein by
reference.
[0022] Considering that modal intervals are a new mathematical
construct, a new and improved set of arithmetical operations is
needed. The large body of work dealing with arithmetical operations
on set-theoretical intervals is largely unhelpful due to the fact
that modal intervals are mathematically more complex.
[0023] A software program for modal intervals available from the
University of Girona provides a starting point or benchmark. The
designers of that system avoid several implementation complexities
by limiting modal intervals to those comprised only of finite and
bounded endpoints. Such a representation is relatively simple to
implement in a computer, but it lacks reliable overflow tracking,
which can lead to pessimism and even unreliable results. This is
particularly true when computations are performed in a mixed-mode
environment, that is, when calculations on numbers represented by
different digital scales are mixed within a lengthy computation.
This occurs, for example, when some intervals in a computation are
represented by 32-bit floating-point values while others have
64-bit representations.
[0024] For this reason, the previously discussed pitfalls which
plague the set-theoretical operations apply to modal intervals.
When considering a set of improved arithmetical operations for
modal intervals, there is also the burden of supporting
mathematical semantics required by modal intervals which are- not
present in a set-theoretical interval system, or vice-versa. Hickey
defines [0,1]/[0,1]=[0,+.infin.] as a valid example of an
expression which represents the division of two set-theoretical
intervals containing zero. Such semantics do not exist in the
context of modal intervals and are therefore unsuitable for, and
hardly compatible with, a modal interval operation.
[0025] More recently, invalid operations of IEEE arithmetic in
relation to the classical set-theoretical interval arithmetic have
been addressed by Steele, Jr. in U.S. Pat. No. 7,069,288,
incorporated herein by reference. In-as-much as improved results
are arguably provided, the improved result values are not
compatible with an unbounded modal interval framework, more
particularly, Steele does not consider existential or universal
quantifiers. Furthermore, and also of significance, the improved
results identified by Steele depend on a rounding mode. For
example, Steele defines [0026] (+.infin.)+(-.infin.)=+.infin. when
rounding towards positive infinity and [0027]
(+.infin.)+(-.infin.)=-.infin. when rounding in the opposite
direction.
[0028] The focus of the present invention is the reliable and
efficient computation of modal interval arithmetic operations. By
definition, this includes modal interval addition, subtraction,
multiplication and division.
[0029] In the case of the present invention, an implementation is
"reliable" if it generates a mathematically correct result for any
combination of operands; and the implementation is "efficient" if
it requires minimal computational effort.
[0030] The prior art is filled with examples of implementations of
arithmetical operations on set-theoretical intervals. Some of the
examples are efficient, but none are completely reliable. In most
cases, they are neither reliable nor efficient.
[0031] As a point of reference, Walster et al. describe a
mask-driven division operation for set-theoretical intervals in
U.S. Pat. No. 6,658,444, which is incorporated herein by reference.
The basic idea of the disclosed method is to condense the complex
branching logic required by the division operation into a mask,
which can then be used as a switch to efficiently direct control of
the software to the relevant case. Little attention is given,
however, to the most crucial and important function: the actual
creation of the mask. The disclosed methodology requires as much
branching logic to compute the value of the mask as an
implementation that is not mask-driven. As a result, the efficiency
of such an implementation is questionable.
[0032] A further shortcoming of the disclosed methodology is that
all cases of input are not properly considered. This can lead to
unreliable computations for certain combinations of operands. As in
Stolfi's "Self Validated Numerical Methods and Applications"
monograph discussed earlier, Walster et al.'s method is similarly
reliable only to the extent that great care is taken to submit a
valid combination of operands to the division operation.
[0033] As an example, if the operands X=[+.infin.,+.infin.] and
Y=[6,+.infin.] are submitted to Walster et al.'s TABLE 1 division
operation, the operation will not properly detect the invalid IEEE
arithmetic operation +.infin./+.infin. which occurs in the first
endpoint of the result. Instead, the computational program will
improperly create a mask representing case 10, and compute
[+.infin./+.infin.,+.infin./6]=[NaN, +.infin.].
[0034] Similarly, if an invalid set-theoretical interval is
submitted as an operand, Walster et al.'s TABLE 1 division
operation will not detect the error in all cases. If X=[5,3] and
Y=[6,9], a mask for case 10 is computed and the result [5/9,1/2] is
returned. In this case, X is not a valid set-theoretical interval,
nor is the result.
[0035] The methodology of Walster et al. is set primarily in the
context of a software system which is under control of a compiler.
As such, it is reasonable to assume that the compiler will do
syntactical verification of the operands and detect such errors.
But this is only true to the extent that the operands are
compile-time constants in the original software source code. For
example, if the operands to the interval division operation are
input selectively by a user at runtime, then the compiler has no
opportunity to detect that invalid operands are being submitted to
the interval division operation. In such case, the inevitable
result will be unreliable computations.
[0036] Similar shortcomings are likewise present in the mask-driven
multiplication operation for set-theoretical intervals described in
U.S. Pat. No. 6,629,120 (Walster et al.), incorporated herein by
reference, as well as with the computational programs in Stolfi's
previously cited monograph. The point to be made by all these
examples is not to depreciate the work and contributions of prior
artisans, but to illustrate the critical issue that remains: that
computing reliable and efficient arithmetical operations on
intervals is an exceptionally challenging problem, a problem yet to
be solved.
SUMMARY OF THE INVENTION
[0037] The present invention provides a novel set of modal interval
arithmetical operations that are both reliable and efficient. The
preferred embodiment of each arithmetical operation in the present
invention is an Arithmetic Functional Unit (AFU) of a modal
interval processor, such as the processor described in applicant's
pending international application ser. no. PCT/US06/12547 filed
Apr. 5, 2006 entitled MODAL INTERVAL PROCESSOR, and incorporated
herein by reference. Representations for modal intervals within a
computer, consistent and/or compatible with the teaching associated
with applicant's copending international application ser. no.
______, entitled REPRESENTATION OF MODAL INTERVALS WITHIN A
COMPUTER, filed Oct. 2, 2006 and which is incorporated herein by
reference, are utilized.
[0038] The AFU receives a representation of a first and a second
modal interval, performs a modal interval arithmetic operation, and
returns a modal interval result. To perform the arithmetic
operation, the present invention examines the bit-pattern of each
of the four numbers which represent the endpoints of the two modal
interval operands. For each bit-pattern of each number, a
corresponding S (sign), N (not-a-number), I (infinity), and Z
(zero) flag is set to a state which characterizes the number.
[0039] Once each bit-pattern is examined, the signal of each S, N,
I and Z flag of each number is processed by a series of logic gates
to construct a 6-bit mask such that four consecutive bits in the
mask represent an ordered arrangement of the signs of the four
original numbers; that a fifth bit in the mask represents the
presence or absence of an exceptional arithmetic condition; and
that a sixth bit in the mask represents the presence or absence of
an indefinite operand or division by zero.
[0040] The 6-bit mask is then used to transfer control of the
arithmetic operation to one of several different cases. The number
of cases depends on the arithmetical operation, but there always
exists three general conditions of cases: unexceptional,
exceptional, and indefinite.
[0041] An unexceptional condition occurs when the fifth and sixth
bit of the 6-bit mask are zero. An exceptional condition occurs
when the fifth bit is one and the sixth bit is zero. An indefinite
condition occurs when the sixth bit is one, regardless of the fifth
bit. For the exceptional conditions of a modal interval arithmetic
operation, the S, I and Z flags of the original numbers are further
processed by a second series of logic gates to further transfer
control of the arithmetical operation to an appropriate
handler.
[0042] In another embodiment of the present invention, special
instruction is provided to a floating-point processor, thereby
emulating the aforementioned function of the AFU circuit.
[0043] By combination of these parts and methods, the present
invention produces, among other things, the following novelties: a
closed mapping of modal interval arithmetical operations to IEEE
standard 754; reliable and efficient arithmetical operations for
modal intervals; reliable mixed-mode computing for modal intervals;
complete support for arithmetical operations on unbounded modal
intervals; and, reliable overflow tracking for arithmetical
operations on modal intervals.
BRIEF DESCRIPTION OF THE DRAWINGS
[0044] FIG. 1 schematically depicts a procedure to set the status
or status flags which characterize a floating-point number;
[0045] FIG. 2 depicts logic operations in furtherance of computing
a 6-bit mask for modal interval addition and subtraction;
[0046] FIG. 3 depicts logic operations in furtherance of computing
a 6-bit mask for modal interval multiplication;
[0047] FIG. 4 depicts logic operations in furtherance of computing
a 6-bit mask for modal interval division;
[0048] FIG. 5 presents tabulated conditions for a mask-driven modal
interval arithmetical operation;
[0049] FIG. 6 presents tabulated conditions for a mask-driven modal
interval multiplication operation;
[0050] FIG. 7 presents tabulated conditions for a mask-driven modal
interval division operation;
[0051] FIG. 8 depicts logic operations in furtherance of computing
special instruction for unbounded addition;
[0052] FIG. 9 depicts logic operations in furtherance of computing
special instruction for unbounded subtraction;
[0053] FIG. 10 depicts logic operations in furtherance of computing
special instruction for unbounded multiplication;
[0054] FIG. 11 depicts logic operations in furtherance of computing
special instruction for unbounded division;
[0055] FIG. 12 is an illustrative example of code, i.e., a software
program, which emulates the procedure depicted in FIG. 1;
[0056] FIG. 13 is an illustrative example of code, i.e., a software
program which emulates the logic diagram depicted in FIG. 3;
[0057] FIG. 14 is an illustrative example of code, i.e., a software
program which emulates the logic diagram depicted in FIG. 4;
[0058] FIG. 15 depicts logic operations in furtherance of computing
a 6-bit mask for "simple" modal interval addition, subtraction and
multiplication; and,
[0059] FIG. 16 depicts logic operations in furtherance of computing
a 6-bit mask for "simple" modal interval division.
DETAILED DESCRIPTION OF THE INVENTION
[0060] As a preliminary matter, there exists a relatedness and/or
synergy between and among the subject invention and other
inventions of applicant which are subject of one or more pending
patent applications. The arithmetical operations of the present
invention are advantageously embodied in an Arithmetic Functional
Unit (AFU) of a modal interval processor or the like, more
particularly, a modal interval processor as disclosed in
applicant's copending, and previously cited application entitled
MODAL INTERVAL PROCESSOR.
[0061] Throughout the subject disclosure, the term "mark" is
intended to have the same definition as that provided in
applicant's copending, and previously cited application entitled
REPRESENTATION OF MODAL INTERVALS WITHIN A COMPUTER. Furthermore,
the term mark is an alias for the term "set-theoretical number" as
defined in applicant's copending, and previously cited application
entitled MODAL INTERVAL PROCESSOR.
Classifying Numbers
[0062] The AFU in a modal interval processor generally receives a
representation of a first and a second modal interval as operands.
The AFU then performs a modal interval arithmetical operation on
the operands and returns a modal interval result.
[0063] To perform the operation, the present invention examines the
bit-pattern of a first and a second mark which represent the
endpoints of the first and second modal interval operands,
respectively. For each bit-pattern of each mark, a set of status
flags are set to a state which characterize the mark. The set of
status flags is comprised of an S (sign), N (not-a-number), I
(infinity), and Z (zero) flag.
[0064] In the preferred embodiment of the invention, the allocation
of bits which represent a mark is specified by IEEE standard 754.
Specifically, the bits of a mark are grouped into three fields:
sign, exponent, and fraction. It is always the case that the sign
field is comprised of a single bit. The exponent field is typically
comprised of 8 or 11 bits, the fraction field being respectively
comprised of 23 or 52 bits. Other allocations of bits are possible,
and the present invention extends to and contemplates such
cases.
[0065] IEEE standard 754 specifies that the magnitude of a mark is
infinity if the exponent field is comprised of all ones and the
fraction field is comprised of all zeros. Similarly, such a mark is
a pseudo-number (i.e., NaN) if the exponent field is comprised of
all ones, and the fraction field is comprised of any combination of
ones and zeros such that all bits are not zero.
[0066] FIG. 1 represents a procedure to set the state of the status
flags. First, the sign bit (S) of the mark is copied to the S flag.
Next, the exponent (E) and fraction (F) fields of the mark are
considered as a single unsigned integer, as a logical unit; the
exponent field representing the highest-order bits of the unit. The
Z flag is set to one (true) if all bits of the unit are zero;
otherwise the Z flag is set to zero (false). The I flag is set to
one (true) if all bits of the unit are equal to the bit-pattern of
infinity; otherwise the I flag is set to zero (false). The N flag
is set to one (true) if the magnitude of all bits in the unit are
above (greater-than) the bit-pattern of infinity; otherwise the N
flag is set to zero (false).
Creating a Mask
[0067] An AFU in a modal interval processor generally receives as
operands a representation of a first modal interval X and a second
modal interval Y. Operand X is comprised of a first mark X1 and a
second mark X2, and operand Y is comprised of a first mark Y1 and a
second mark Y2.
[0068] First, the AFU computes a proper state for an S, N, I and Z
status flag that exists for each of the X1, X2, Y1 and Y2 marks.
Then the AFU passes the signals of or associated with these states
through a series of logic gates to compute a 6-bit mask.
[0069] The S flag of each X1, X2, Y1 and Y2 is copied into a
consecutive and ordered arrangement within the mask to bit
positions 3, 2, 1 and 0, respectively.
[0070] The mask at bit position 4 and 5 depends on the arithmetical
operation, that is, each AFU has a different logic which is used to
compute the final result of the mask at bit position 4 and 5.
[0071] FIG. 2 depicts the creation of a mask for addition and
subtraction. The I flags of X1 and X2 pass through an OR gate to
produce a first intermediate result. The I flags of Y1 and Y2 pass
through an OR gate to produce a second intermediate result. The
signals of the first and second intermediate results pass through
an AND gate to produce a final result within the mask at bit
position 4. The N flag of each X1, X2, Y1 and Y2 pass through a
four-way OR gate to produce a final result within the mask at bit
position 5.
[0072] FIG. 3 depicts the creation of a mask for multiplication.
The I flags of X1 and X2 pass through an OR gate to produce a first
intermediate result. The Z flags of Y1 and Y2 pass through an OR
gate to produce a second intermediate result. The signals of the
first and second intermediate results pass through an AND gate to
produce a third intermediate result. The I flags of Y1 and Y2 pass
through an OR gate to produce a fourth intermediate result. The Z
flags of X1 and X2 pass through an OR gate to produce a fifth
intermediate result. The signals of the fourth and fifth
intermediate results pass through an AND gate to produce a sixth
intermediate result. The signals of the third and sixth
intermediate results pass through an OR gate to produce a final
result within the mask at bit position 4. The N flag of each X1,
X2, Y1 and Y2 pass through a four-way OR gate to product a final
result within the mask at bit position 5.
[0073] FIG. 4 depicts the creation of a mask for division. The I
flags of X1 and X2 pass through an OR gate to produce a first
intermediate result. The I flags of Y1 and Y2 pass through an OR
gate to produce a second intermediate result. The signals of the
first and second intermediate results pass through an AND gate to
produce a final result within the mask at bit position 4. The Z
flags of Y1 and Y2 pass through an OR gate to produce a third
intermediate result. The N flag of each X1, X2, Y1 and Y2 pass
through a four-way OR gate to produce a fourth intermediate result.
The signals of the third and fourth intermediate results pass
through an OR gate to produce a final result within the mask at bit
position 5.
[0074] By combination of these parts and methods, the present
invention creates a 6-bit mask for modal interval addition,
subtraction, multiplication and division such that bits 0 to 3
represent an ordered arrangement of the signs of the marks X1, X2,
Y1 and Y2; that bit 4 represents the presence (one) or absence
(zero) of an exceptional arithmetic condition; and that bit 5
represents the presence (one) or absence (zero) of an indefinite
operand or division by zero.
[0075] The 6-bit mask is then used to transfer control of the
arithmetic operation to one of several different cases. The number
of cases depends on the arithmetical operation, but there always
exists three general conditions of cases: unexceptional,
exceptional, and indefinite, see generally FIG. 5. An unexceptional
condition occurs when bits 4 and 5 are zero. An exceptional
condition occurs when bit 4 is one and bit 5 is zero. An indefinite
condition occurs when bit 5 is one, regardless of bit 4.
Unexceptional Condition
[0076] If bits 4 and 5 are zero, an unexceptional arithmetical
operation occurs; the ordered arrangement of bits 0 to 3 forms a
binary representation of a number which represents one of a sixteen
possible cases of the unexceptional arithmetical operation.
[0077] For each unexceptional case, a modal interval result
comprised of a first mark, Z1, and a second mark, Z2, is defined.
If an arithmetic operation is performed to compute Z1, the exact
result of the arithmetic operation is rounded towards negative
infinity; if an arithmetic operation is performed to compute Z2,
the exact result of the arithmetic operation is rounded towards
positive infinity.
[0078] The symbols ".dwnarw." and ".uparw." are used to represent a
rounding of an exact arithmetical result to the nearest mark
towards negative and positive infinity, respectively.
[0079] For modal interval addition, the computation of Z1 and Z2
does not depend on bits 0 to 3. In all cases, Z1 is the result of
arithmetic operation .dwnarw.(X1+Y1) and Z2 is the result of
arithmetic operation .uparw.(X2+Y2).
[0080] For modal interval subtraction, the computation of Z1 and Z2
does not depend on bits 0 to 3. In all cases, Z1 is the result of
arithmetic operation .dwnarw.(X1-Y2) and Z2 is the result of
arithmetic operation .uparw.(X2-Y1).
[0081] FIG. 6 is a table for a mask-driven modal interval
multiplication operation. The computation of Z1 and Z2 depends on
bits 0 to 3, a total of sixteen cases in all.
[0082] For case 0, Z1 is the result of arithmetic operation
.dwnarw.(X1Y1) and Z2 is the result of arithmetic operation
.uparw.(X2Y2).
[0083] For case 1, Z1 is the result of arithmetic operation
.dwnarw.(X1Y1) and Z2 is the result of arithmetic operation
.uparw.(X1Y2).
[0084] For case 2, Z1 is the result of arithmetic operation
.dwnarw.(X2Y1) and Z2 is the result of arithmetic operation
.uparw.(X2Y2).
[0085] For case 3, Z1 is the result of arithmetic operation
.dwnarw.(X2Y1) and Z2 is the result of arithmetic operation
.uparw.(X1Y2).
[0086] For case 4, Z1 is the result of arithmetic operation
.dwnarw.(X1Y1) and Z2 is the result of arithmetic operation
.uparw.(X2Y1).
[0087] For case 5, Z1 is the result of arithmetic operation
max(.dwnarw.(X2Y2), .dwnarw.(X1Y1)) and Z2 is the result of
arithmetic operation min(.uparw.(X2Y1, .uparw.(X1Y2)).
[0088] For case 6, Z1 is +0 and Z2 is -0.
[0089] For case 7, Z1 is the result of arithmetic operation
.dwnarw.(X2Y2) and Z2 is the result of arithmetic operation
.uparw.(X1Y2).
[0090] For case 8, Z1 is the result of arithmetic operation
.dwnarw.(X1Y2) and Z2 is the result of arithmetic operation
.uparw.(X2Y2).
[0091] For case 9, Z1 is -0 and Z2 is +0.
[0092] For case 10, Z1 is the result of arithmetic operation
min(.dwnarw.(X1Y2),.dwnarw.(X2Y1)) and Z2 is the result of
arithmetic operation max(.uparw.(X1Y1),.uparw.(X2Y2)).
[0093] For case 11, Z1 is the result of arithmetic operation
.dwnarw.(X2Y1) and Z2 is the result of arithmetic operation
.uparw.(X1Y1).
[0094] For case 12, Z1 is the result of arithmetic operation
.dwnarw.(X1Y2) and Z2 is the result of arithmetic operation
.uparw.(X2Y1).
[0095] For case 13, Z1 is the result of arithmetic operation
.dwnarw.(X2Y2) and Z2 is the result of arithmetic operation
.uparw.(X2Y1).
[0096] For case 14, Z1 the result of arithmetic operation
.dwnarw.(X1Y2) and Z2 is the result of arithmetic operation
[0097] For case 15, Z1 is the result of arithmetic operation
.dwnarw.(X2Y2) and Z2 is the result of arithmetic operation
.uparw.(X1Y1).
[0098] FIG. 7 is a table for a mask-driven modal interval division
operation. The computation of Z1 and Z2 depends on bits 0 to 3, a
total of sixteen cases in all.
[0099] For case 0, Z1 is the result of arithmetic operation
.dwnarw.(X1/Y2) and Z2 is the result of arithmetic operation
.uparw.(X2/Y1).
[0100] For case 3, Z1 is the result of arithmetic operation
.dwnarw.(X2/Y2) and Z2 is the result of arithmetic operation
.uparw.(X1/Y1).
[0101] For case 4, Z1 is the result of arithmetic operation
.dwnarw.(X1/Y2) and Z2 is the result of arithmetic operation
.uparw.(X2/Y2).
[0102] For case 7, Z1 is the result of arithmetic operation
.dwnarw.(X2/Y1) and Z2 is the result of arithmetic operation
.uparw.(X1/Y1).
[0103] For case 8, Z1 is the result of arithmetic operation
.dwnarw.(X1/Y1) and Z2 is the result of arithmetic operation
.uparw.(X2/Y1).
[0104] For case 11, Z1 is the result of arithmetic operation
.dwnarw.(X2/Y2) and Z2 is the result of arithmetic operation
.uparw.(X1/Y2).
[0105] For case 12, Z1 is the result of arithmetic operation
.dwnarw.(X1/Y1) and Z2 is the result of arithmetic operation
.uparw.(X2/Y2).
[0106] For case 15, Z1 is the result of arithmetic operation
.dwnarw.(X2/Y1) and Z2 is the result of arithmetic operation
.uparw.(X1/Y2).
[0107] For cases 1, 2, 5, 6, 9, 10, 13 and 14, Z1 and Z2 are both
NaN.
Exceptional Condition
[0108] If bit 4 is one and bit 5 is zero, an exceptional
arithmetical operation occurs; the ordered arrangement of bits 0 to
3 forms a binary representation of a number which represents one of
sixteen possible cases of the exceptional arithmetical
operation.
[0109] For each case of the exceptional condition, a modal interval
result comprised of a first mark, Z1, and a second mark, Z2, is
defined. All cases are analogous to the unexceptional cases of each
arithmetical operation, but with the following exceptions.
[0110] As described in applicant's copending application entitled
REPRESENTATION OF MODAL INTERVALS WITHIN A COMPUTER, it is a
fortunate coincidence that arithmetical operations on the endpoints
of unbounded modal intervals can be calculated properly using the
IEEE arithmetic for any combination of marks that is not an invalid
operation. In all other cases, hardware conforming to IEEE standard
754 will return a NaN. To avoid such an invalid operation, special
instruction must return the proper result and not the NaN returned
by the IEEE arithmetic. The present invention considers the correct
handling of these semantics so as to avoid generating an unwanted
NaN in the final result.
[0111] If bit 4 is one, the potential for such an exceptional
condition has been detected, that is, the modal interval operands X
and Y contain a combination of marks that may cause an invalid
operation.
[0112] Using a division operation as an example, the mask 010000
represents exceptional condition, case 0. The modal interval result
of this case is a Z1 of .dwnarw.(X1/Y2) and a Z2 of .uparw.(X2/Y1).
If X=[+.infin.,3] and Y=[+.infin.,7], then the arithmetical
operations .dwnarw.(+.infin./7) and .uparw.(3/+.infin.) are not
invalid, and special instruction is not needed. However, if
Y=[7,+.infin.], the arithmetical operations
.dwnarw.(+.infin./+.infin.) and .uparw.(3/7) contain an invalid
operation, namely .dwnarw.(+.infin./+.infin.). In this case,
special instruction must return the result +1 for the invalid
operation.
[0113] Using a multiplication operation as a second example, the
mask 010000 represents exceptional condition, case 0. The modal
interval result of this case is a Z1 of .dwnarw.(X1Y1) and a Z2 of
.uparw.(X2Y2). If X=[+.infin.,3] and Y=[+.infin.,+0], then the
arithmetical operations .dwnarw.((+.infin.)(+.infin.)) and
.uparw.((3)(+0)) are not invalid, and special instruction is not
needed. However, if Y=[+0,+.infin.], the arithmetical operations
.dwnarw.((+.infin.)(+0)) and .uparw.((3)(+.infin.)) contain an
invalid operation, namely .dwnarw.((+.infin.)(+0)). In this case,
special instruction must return the result +0 for the invalid
operation.
[0114] Using an addition operation as a third example, the mask
010011 represents exceptional condition, case 3. The modal interval
result of this case is a Z1 of .dwnarw.(X1+Y1) and a Z2 of
.uparw.(X2+Y2). If X=[+.infin.,3] and Y=[-2,-.infin.], then the
arithmetical operations .dwnarw.((+.infin.)+(-2)) and
.uparw.(3+(-.infin.)) are not invalid, and special instruction is
not needed. However, if Y=[-.infin.,-2], the arithmetical
operations .dwnarw.((+.infin.)+(-.infin.)) and .uparw.(3+(-2))
contain an invalid operation, namely
.dwnarw.((+.infin.)+(-.infin.)). In this case, special instruction
must return the result +0 for the invalid operation.
[0115] A complete list of all possible invalid operations is given
in applicant's copending application entitled REPRESENTATION OF
MODAL INTERVALS WITHIN A COMPUTER, as is the correct result that a
special instruction must return. When creating the 6-bit mask for
each arithmetical operation, the present invention, as described,
ensures that no combination of operands which might possibly
generate an invalid operation will be missed (by setting bit 4 to
one). This is, however, a conservative guarantee. As the previous
examples show, special instruction may not always be needed.
[0116] As such, when the presence of an exceptional condition is
detected via bit 4, and when Z1 and Z2 are computed, each
arithmetic operation performed on the operands of Z1 and Z2 is
examined. If an invalid operation is detected, special instruction
is given; otherwise the arithmetical operation is computed as
usual.
[0117] FIG. 8 represents a procedure to determine if special
instruction must be performed for addition. A and B are aliases for
two marks that are operands of Z1 or Z2. If the I flags of A and B
pass through an AND gate to result in a signal of zero, the
arithmetical operation A+B will not result in an invalid operation
and the result can be properly computed with IEEE arithmetic;
otherwise special instruction might still be necessary. If the S
flags of A and B pass through an XOR gate to result in a signal of
zero, the arithmetical operation A+B represents addition of two
same-signed infinities, which will not result in an invalid
operation. In this case, again, the result can be properly computed
with IEEE arithmetic; otherwise special instruction must return +0,
as the arithmetical operation A+B represents addition of two
opposite-signed infinites, which is an invalid operation.
[0118] FIG. 9 represents a procedure to determine if special
instruction must be performed for subtraction. A and B are aliases
for two marks that are operands of Z1 or Z2. If the I flags of A
and B pass through an AND gate to result in a signal of zero, the
arithmetical operation A-B will not result in an invalid operation
and the result can be properly computed with IEEE arithmetic;
otherwise special instruction might still be necessary. If the S
flags of A and B pass through an XOR gate to result in a signal of
one, the arithmetical operation A-B represents subtraction of two
opposite-signed infinities, which will not result in an invalid
operation. In this case, again, the result can be properly computed
with IEEE arithmetic; otherwise special instruction must return +0,
as the arithmetical operation A-B represents subtraction of two
same-signed infinites, which is an invalid operation.
[0119] FIG. 10 represents a procedure to determine if special
instruction must be performed for multiplication. A and B are
aliases for any two marks that are operands of Z1 or Z2. The I flag
of A and the Z flag of B pass through an AND gate to produce a
first intermediate result. The I flag of B and the Z flag of A pass
through an AND gate to produce a second intermediate result. The
signals of the first and second intermediate results pass through
an OR gate to produce a final result. If the signal of the final
result is zero, the arithmetical operation (A)(B) will not result
in an invalid operation and the result can be properly computed
with IEEE arithmetic; otherwise special instruction must return
.+-.0. The sign of the result is computed as the XOR of the S flag
of A and B, that is, the result is positive if the signal of the
XOR is zero; otherwise the result is negative.
[0120] FIG. 11 represents a procedure to determine if special
instruction must be performed for division. A and B are aliases for
two marks that are operands of Z1 or Z2. If the I flags of A and B
pass through an AND gate to result in a signal of zero, the
arithmetical operation A/B will not result in an invalid operation
and the result can be properly computed with IEEE arithmetic;
otherwise special instruction must return .+-.1. The sign of the
result is computed as the XOR of the S flag of A and B, that is,
the result is positive if the signal of the XOR is zero; otherwise
the result is negative.
[0121] In summary, since the vast majority of modal interval
arithmetical operations performed in typical calculations result in
an unexceptional condition, it is undesirable to waste
computational time and resources to test for invalid operations all
the time. The present invention avoids this undesirable situation
by conservatively detecting the presence of an exceptional
condition in bit 4 of the 6-bit mask. This allows the
implementation to perform the extra computational effort associated
with special instruction only in the few cases where it may
actually be required.
Indefinite Condition
[0122] If bit 5 is one (regardless of bit 4), an indefinite
arithmetical operation occurs. This happens when at least one of
the modal interval operands X or Y is indefinite, or when Y
contains a zero and the arithmetical operation is division. For any
indefinite arithmetical operation, the result is always an
indefinite modal interval, that is, both Z1 and Z2 are NaN. An
indefinite condition always exists if bit 5 is one, regardless of
whether bit 4 is zero or one.
Conclusion
[0123] In-as-much as the preferred embodiment of each arithmetical
operation in the present invention is an AFU in a modal interval
processor, that is, an integrated circuit, it need not be so
limited. For example, and without limitation, the present invention
lends itself conveniently to a software implementation which uses
existing computing devices, particularly a processor that supports
or emulates IEEE floating-point arithmetic.
[0124] As an example, FIG. 12 is a software program to efficiently
compute the S, N, I and Z flags of a 32-bit IEEE floating-point
number on a general-purpose Intel processor; the software emulates
the procedure described in FIG. 1.
[0125] As a second example, FIG. 13 is a software program to
efficiently compute a 6-bit mask for a modal interval
multiplication operation on a general-purpose Intel processor; the
software emulates the logic gates depicted in FIG. 3.
[0126] As a third example, FIG. 14 is a software program to
efficiently compute a 6-bit mask for a modal interval division
operation on a general-purpose Intel processor; the software
emulates the logic gates depicted in FIG. 4.
[0127] The present invention can also be "simplified" to provide
backwards compatibility with existing modal interval
representations that do not support unbounded modal intervals. As
an example, FIG. 15 is a simplified logic diagram for creating a
6-bit mask for addition, subtraction and multiplication, and FIG.
16 is a simplified logic diagram for creating a 6-bit mask for
division. In both figures, all logic gates relating to the
computation of bit are eliminated and the computation of bit 5
treats infinity as a special case of NaN. The result is a 6-bit
mask which will operate properly with the present invention on a
modal interval representation that supports only the bounded modal
intervals.
[0128] There are other variations of this invention which will
become obvious to those skilled in the art. It will be understood
that this disclosure, in many respects, is only illustrative.
Although the various aspects of the present invention have been
described with respect to various preferred embodiments thereof, it
will be understood that the invention is entitled to protection
within the full scope of the appended claims.
* * * * *