U.S. patent application number 13/308826 was filed with the patent office on 2012-10-04 for semiconductor device and manufacturing method thereof.
This patent application is currently assigned to KABUSHIKI KAISHA TOSHIBA. Invention is credited to Mitsuyoshi Endo.
Application Number | 20120248624 13/308826 |
Document ID | / |
Family ID | 46926100 |
Filed Date | 2012-10-04 |
United States Patent
Application |
20120248624 |
Kind Code |
A1 |
Endo; Mitsuyoshi |
October 4, 2012 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Abstract
According to one embodiment, a first back surface of a first
substrate and a second front surface of a second substrate are
jointed together so as to connect a first conductor with a second
conductor. The first conductor includes a portion having a diameter
equal to that of a first gap formed above a first metal layer in a
range between the first metal layer and a first front surface, and
a portion having a diameter greater than that of the first gap and
smaller than an outer diameter of the first metal layer in a range
between the first metal layer and the first back surface. A first
insulating layer has a gap formed above the first metal layer, the
gap being greater than the first gap and smaller than the outer
diameter of the first metal layer.
Inventors: |
Endo; Mitsuyoshi; (Kanagawa,
JP) |
Assignee: |
KABUSHIKI KAISHA TOSHIBA
Tokyo
JP
|
Family ID: |
46926100 |
Appl. No.: |
13/308826 |
Filed: |
December 1, 2011 |
Current U.S.
Class: |
257/774 ;
257/E21.214; 257/E23.011; 438/459 |
Current CPC
Class: |
H01L 2224/0401 20130101;
H01L 2224/92132 20130101; H01L 2924/00014 20130101; H01L 2224/13025
20130101; H01L 2225/06544 20130101; H01L 24/82 20130101; H01L
2224/32145 20130101; H01L 2924/00014 20130101; H01L 2224/03002
20130101; H01L 2224/94 20130101; H01L 2224/05571 20130101; H01L
2224/16146 20130101; H01L 24/06 20130101; H01L 2224/94 20130101;
H01L 24/03 20130101; H01L 25/50 20130101; H01L 2224/0557 20130101;
H01L 2224/05647 20130101; H01L 2924/00014 20130101; H01L 2224/94
20130101; H01L 2224/80 20130101; H01L 2224/05552 20130101; H01L
2924/00012 20130101; H01L 2224/03 20130101; H01L 2924/00 20130101;
H01L 2924/12042 20130101; H01L 21/6836 20130101; H01L 2221/68372
20130101; H01L 2224/24146 20130101; H01L 2224/83005 20130101; H01L
2224/94 20130101; H01L 24/24 20130101; H01L 2225/06513 20130101;
H01L 24/16 20130101; H01L 2224/82031 20130101; H01L 2224/9202
20130101; H01L 2224/05571 20130101; H01L 25/0657 20130101; H01L
2224/16145 20130101; H01L 24/05 20130101; H01L 21/76898 20130101;
H01L 2224/05647 20130101; H01L 24/83 20130101; H01L 2224/82005
20130101; H01L 22/22 20130101; H01L 2924/12042 20130101; H01L 24/92
20130101; H01L 2224/83 20130101 |
Class at
Publication: |
257/774 ;
438/459; 257/E23.011; 257/E21.214 |
International
Class: |
H01L 23/48 20060101
H01L023/48; H01L 21/302 20060101 H01L021/302 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 4, 2011 |
JP |
2011-082951 |
Claims
1. A semiconductor device comprising: a first substrate including:
a first semiconductor element provided above a first front surface
of the first substrate; a first metal layer electrically connected
to the first semiconductor element and having a first gap above the
first front surface of the first substrate; a first insulating
layer formed above each of the first metal layer and the first
front surface; and a first conductor embedded in a first via hole
at a forming position of the first metal layer, the first via hole
penetrating the first substrate in a thickness direction thereof;
and a second substrate including: a second semiconductor element
formed above a second front surface of the second substrate; and a
second conductor embedded in a second via hole penetrating the
second substrate in a thickness direction thereof, wherein a first
back surface opposed to the first front surface of the first
substrate and the second front surface of the second substrate are
joined together so as to connect the first conductor with the
second conductor, the first conductor includes a first portion
having a diameter equal to that of the first gap in a range between
the first metal layer and the first front surface, and a second
portion having a diameter greater than that of the first gap and
smaller than an outer diameter of the first metal layer in a range
between the first metal layer and the first back surface, and the
first insulating layer has a gap formed above the first metal
layer, the gap being greater than the first gap and smaller than
the outer diameter of the first metal layer.
2. The semiconductor device according to claim 1, wherein the
second substrate further includes: a second metal layer formed
above the second front surface and electrically connected to the
second semiconductor element, the second metal layer having a
second gap; and a second insulating layer formed above each of the
second metal layer and the second front surface, the second
conductor includes a third portion having a diameter equal to that
of the second gap in a range between the second metal layer and the
second front surface, and a fourth portion having a diameter
greater than that of the second gap and smaller than an outer
diameter of the second metal layer in a range between the second
metal layer and a second back surface of the second substrate, the
second back surface being opposed to the second front surface, and
the second insulating layer has a gap formed above the second metal
layer, the gap being greater than the second gap and smaller than
the outer diameter of the second metal layer.
3. The semiconductor device according to claim 1, wherein the
second substrate further includes: a second metal layer formed
above the second front surface and electrically connected to the
second semiconductor element, the second metal layer having a
second gap; and a second insulating layer formed above each of the
second metal layer and the second front surface and having a third
gap, the second conductor is disposed in the second via hole in a
range between the second front surface and a second back surface of
the second substrate, the second via hole having a diameter
substantially equal to that of the first via hole, the second back
surface being opposed to the second front surface, and the third
gap of the second insulating layer and the second gap of the second
metal layer have a diameter greater than or equal to that of the
second via hole, and the second metal layer and the second
conductor are electrically disconnected.
4. The semiconductor device according to claim 3, wherein the
second substrate is a defective chip.
5. The semiconductor device according to claim 1, wherein the first
substrate is thinned by polishing the first back surface and is
then connected to the second substrate, and the second substrate is
thinned by polishing the second back surface.
6. The semiconductor device according to claim 1, wherein the first
and second substrates each have a thickness of 50 .mu.m or
less.
7. The semiconductor device according to claim 1, wherein the first
substrate further includes an electrode formed above a forming
position of the first conductor of the first front surface.
8. The semiconductor device according to claim 7, wherein a contact
area between the electrode and the first portion the first
conductor is substantially equal to a contact area between the
first metal layer and the second portion of the first
conductor.
9. A semiconductor device comprising: a first substrate including:
a first semiconductor element provided above a first front surface
of the first substrate; a first metal layer electrically connected
to the first semiconductor element provided above the first front
surface of the first substrate; a first insulating layer formed
above each of the first metal layer and the first front surface; a
first conductor embedded in a first via hole at a forming position
of the first metal layer, the first via hole penetrating the first
substrate in a thickness direction thereof; and a second substrate
including: a second semiconductor element provided above a second
front surface of the second substrate; and a second conductor
embedded in a second via hole penetrating the second substrate in a
thickness direction thereof, wherein a first back surface opposed
to the first front surface of the first substrate and the second
front surface of the second substrate are joined together so as to
connect the first conductor with the second conductor, and the
first conductor has substantially the same diameter in a range
between the first front surface and the first back surface.
10. The semiconductor device according to claim 9, wherein the
second substrate further includes: a second metal layer formed
above the second front surface and electrically connected to the
second semiconductor element, the second metal layer having a
second gap; and a second insulating layer formed above each of the
second metal layer and the second front surface, the second
conductor includes a first portion having a diameter equal to that
of the second gap in a range between the second metal layer and the
second front surface, and a second portion having a diameter
greater than that of the second gap and smaller than an outer
diameter of the second metal layer in a range between the second
metal layer and a second back surface of the second substrate, the
second back surface being opposed to the second front surface, and
the second insulating layer has a gap formed above the second metal
layer, the gap being greater than the second gap and smaller than
the outer diameter of the second metal layer.
11. The semiconductor device according to claim 9, wherein the
second substrate further includes: a second metal layer formed
above the second front surface and electrically connected to the
second semiconductor element, the second metal layer having a
second gap; and a second insulating layer formed above each of the
second metal layer and the second front surface and having a third
gap, the second conductor is disposed in the second via hole in a
range between the second front surface and a second back surface of
the second substrate, the second via hole having a diameter
substantially equal to that of the first via hole, the second back
surface being opposed to the second front surface, and the third
gap of the second insulating layer and the second gap of the second
metal layer have a diameter greater than or equal to that of the
second via hole, and the second metal layer and the second
conductor are electrically disconnected.
12. The semiconductor device according to claim 11, wherein the
second substrate is a defective chip.
13. The semiconductor device according to claim 9, wherein the
first substrate is thinned by polishing the first back surface and
is then connected to the second substrate, and the second substrate
is thinned by polishing the second back surface.
14. A manufacturing method of a semiconductor device comprising:
forming a first semiconductor element above a first front surface
of a first substrate and forming a first metal layer electrically
connected to the first semiconductor element above the first front
surface of the first substrate; bonding the first front surface of
the first substrate with a base substrate; polishing a first back
surface of the first substrate, the first back surface being
opposed to the first front surface; forming a first via hole having
a predetermined diameter in the first back surface; forming a first
conductor in the first via hole so as to electrically connect the
first metal layer with the first conductor; forming a second
semiconductor element above a second front surface of a second
substrate and forming a second metal layer having a first gap
electrically connected to the second semiconductor element above
the second front surface of the second substrate; bonding the
second front surface of the second substrate with the first back
surface of the first substrate; polishing a second back surface of
the second substrate, the second back surface being opposed to the
second front surface; forming a second via hole in the second
substrate so as to communicate with a forming position of the first
conductor; forming a second conductor in the second via hole;
removing a part of the base substrate; and dividing a structure
including at least the first substrate and the second substrate
joined together.
15. The manufacturing method of a semiconductor device according to
claim 14, wherein in the formation of the second via hole, the
second substrate is etched using the second metal layer as a mask,
the second metal layer having a diameter greater than that of the
first gap in a range between the second back surface and the second
metal layer and having the first gap in a range between the second
metal layer and the second front surface, and in the formation of
the second conductor, the second conductor is connected to the
second metal layer.
16. The manufacturing method of a semiconductor device according to
claim 14, wherein the second via hole has a diameter substantially
equal to the diameter of the first via hole, after the formation of
the second metal layer, an insulating layer having a second gap
smaller than an outer diameter of the second metal layer and
greater than the first gap is formed above the second front surface
of the second substrate having the second metal layer formed
thereon, when the second semiconductor element is defective, the
second metal layer is etched using the insulating layer as a mask
so that the first gap of the second metal layer and the second gap
of the insulating layer have the same diameter, after the formation
of the second metal layer and before the bonding of the first and
second substrates, and in the formation of the second conductor,
the second conductor and the second metal layer are
disconnected.
17. The manufacturing method of a semiconductor device according to
claim 14, further comprising repeating a process from the formation
of the second semiconductor element and the second metal layer
above the second substrate to the formation of the second
conductor, until the number of substrates to be stacked reaches a
predetermined number.
18. The manufacturing method of a semiconductor device according to
claim 14, wherein the base substrate is a transparent substrate,
and in the removal of the base substrate, the transparent substrate
is separated from the structure.
19. The manufacturing method of a semiconductor device according to
claim 14, wherein the first base substrate is one of a
semiconductor substrate and a conductor substrate, and in the
formation of the first conductor, the first conductor is filled in
the first via hole by plating using the base substrate as a plating
electrode.
20. The manufacturing method of a semiconductor device according to
claim 14, wherein the first and second back surfaces are polished
to polish each of the first and second substrates to a thickness of
50 .mu.m or less.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from Japanese Patent Application No. 2011-82951, filed on
Apr. 4, 2011; the entire contents of which are incorporated herein
by reference.
FIELD
[0002] Embodiments described herein relate generally to a
semiconductor device and a manufacturing method thereof.
BACKGROUND
[0003] Along with the recent demand for miniaturization of personal
digital assistances, storage devices, and the like, there has been
an increasing demand for mounting of a plurality of semiconductor
chips with high density. Under such circumstances, a structure
having a plurality of semiconductor chips stacked therein has been
studied. For example, a semiconductor module is manufactured in
such a manner that an operational test is performed on each
semiconductor chip in the state of a semiconductor wafer so as to
select non-defective chips, and the non-defective chips are
stacked. Typically, each chip has a through via hole, connecting
pads formed on the top surface of the chip, and connecting bumps
formed on the bottom surface of the chip. The bumps formed on an
upper chip are connected to the pads formed on a lower chip,
thereby electrically connecting the upper and lower chips.
[0004] However, the use of bumps to connect semiconductor chips
results in an increase in connection pitch. Additionally, it is
necessary to ensure a certain thickness of each chip for handling
the connection between bumps and pads. These circumstances hinder a
reduction in the thickness of the semiconductor module.
Furthermore, an increase in the number of stacked chips may cause
deterioration in the throughput of the stacking process and in the
connection yield.
[0005] On the other hand, there is another method of manufacturing
a semiconductor module in which semiconductor wafers are joined
together and are then divided into chips. In this method, bumps for
providing electrical connection between wafers can be omitted. This
results in solving the above-mentioned problems which may be caused
when bumps are used.
[0006] When the method of dividing the joined semiconductor wafers
into chips is employed, it is impossible to select only
non-defective semiconductor chips to be stacked. Accordingly, the
method requires a countermeasure for avoiding the situation in
which a failure occurs in the entire semiconductor module when a
defective semiconductor chip is present. The situation in which a
failure occurs in the entire semiconductor module can be avoided in
the following manner, for example. That is, a trimming region is
formed in advance for each of wiring lines connected to a via land,
and if a defective chip is found, a laser beam is applied to the
trimming region to disconnect the corresponding wiring line.
[0007] However, an increase in the number of disconnected wiring
lines leads to an increase in the trimming region. This may result
in limitation of the degree of freedom of design and deterioration
in the throughput. Additionally, other problems such as a cutting
failure due to insufficient welding of wiring lines, a
short-circuit failure due to scattering of a metal material of
wiring lines, and a lack of cutting stability due to difficulty in
controlling the shape of a cut portion may occur. Especially in the
case of using a copper wiring line, the difficulty in welding and
cutting increases, which makes these problems more significant.
[0008] To join semiconductor wafers together, an effective
structure or manufacturing process for ensuring electrical
connection between via holes that penetrate wafers and
semiconductor elements formed on each wafer and for ensuring
electrical connection with external parts has not been established
yet.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 is a schematic plan view illustrating a configuration
in the vicinity of a via land according to an embodiment;
[0010] FIGS. 2 to 11 are sectional views schematically illustrating
an exemplary process of the manufacturing method of a semiconductor
device according to the first embodiment;
[0011] FIG. 12 is a schematic diagram illustrating a semiconductor
module according to a second embodiment; and
[0012] FIG. 13 is a schematic plan view of a semiconductor device
including a via land having another shape.
DETAILED DESCRIPTION
[0013] In general, according to one embodiment, a first substrate
includes a first semiconductor element provided above a first front
surface of the first substrate; a first metal layer electrically
connected to the first semiconductor element and having a first gap
above the first front surface of the first substrate; and a first
insulating layer formed above each of the first metal layer and the
first front surface. The first substrate also includes a first
conductor embedded in a first via hole at a forming position of the
first metal layer, the first via hole penetrating the first
substrate in a thickness direction thereof. A second substrate
includes a second semiconductor element provided above a second
front surface of the second substrate; and a second conductor
embedded in a second via hole penetrating the second substrate in a
thickness direction thereof. A first back surface opposed to the
first front surface of the first substrate and the second front
surface of the second substrate are joined together so as to
connect the first conductor with the second conductor. The first
conductor includes a first portion having a diameter equal to that
of the first gap in a range between the first metal layer and the
first front surface; and a second portion having a diameter greater
than that of the first gap and smaller than an outer diameter of
the first metal layer in a range between the first metal layer and
the first back surface. The first insulating layer has a gap formed
above the first metal layer, the gap being greater than the first
gap and smaller than the outer diameter of the first metal
layer.
[0014] Exemplary embodiments of a semiconductor device and a
manufacturing method thereof will be explained below in detail with
reference to the accompanying drawings. The present invention is
not limited to the following embodiments.
FIRST EMBODIMENT
[0015] A semiconductor device and a manufacturing method thereof
according to a first embodiment will be described with reference to
the drawings. FIG. 1 is a schematic plan view of a via land
according to the first embodiment. FIGS. 2 to 11 are sectional
views each schematically illustrating an exemplary process of the
manufacturing method of a semiconductor device according to the
first embodiment. As illustrated in FIG. 2, insulating layers 12
and 14 are formed on a semiconductor wafer 10, and a via land 16
made of metal (for example, copper) is formed on the insulating
layer 12. The via land 16 has a doughnut shape in plan view (in a
direction perpendicular to the principal surface of the
semiconductor wafer 10), and the insulating layer 12 formed below
the via land 16 is exposed at a central portion. The via land 16 is
connected to a metal wiring line (hereinafter referred to as
"wiring line") 18 at an end portion. The wiring line 18 is
connected to a semiconductor element not illustrated (for example,
a semiconductor memory such as a flash memory or a DRAM (Dynamic
Random Access Memory)). As illustrated in FIG. 1, the insulating
layer 14 is formed in a region at a predetermined distance or
further from the center of the land so that a portion (a portion in
the range from the land center to the predetermined distance) of
the via land 16 is exposed. Herein, A represents the outer diameter
of the via land 16; B represents the outer diameter of a portion of
the via land 16 which is not, covered by the insulating layer 14
(an opening diameter of the insulating layer 14); and C represents
the inner diameter of the via land 16 (diameter excluding the via
land). In the structure as described above, the relation of
A>B>C is maintained. For example, A is 20 .mu.m; B is 14
.mu.m; and C is 7 .mu.m.
[0016] A plurality of chips (for example, about more than 700 chips
for a wafer of 300 mm) is formed on the semiconductor wafer 10, and
each chip has the structure of the via land 16 as illustrated in
FIGS. 1 and 2. In the state of the semiconductor wafer 10, an
operational test is performed on each chip with a test device such
as a probe card. Thus, defective semiconductor chips are specified,
which makes it possible to create drawing data, which is called a
wafer map, representing the positions of the defective chips on the
semiconductor wafer 10.
[0017] Next, as illustrated in FIG. 3, an etchant 71 is applied
onto the via land 16 of a defective chip. As a result, the exposed
portion of the via land 16 is removed. In the manner as described
above, the semiconductor wafer 10 in which a part of the via land
of each defective chip is removed can be obtained.
[0018] Then, the semiconductor wafer 10 is stacked with a second
wafer 0 serving as a base substrate. The semiconductor wafer 0 has
a number of connecting pads 2 corresponding to the number of the
via lands 16. The semiconductor wafer 0 and the semiconductor wafer
10 are joined together in the state where the connecting pads 2 of
the semiconductor wafer 0 are aligned so as to be positioned
immediately above the via land 16 which is provided on each chip of
the semiconductor wafer 10. In the first embodiment, an adhesive
layer 6 is used to join the semiconductor wafers 0 and 10 together.
Alternatively, the semiconductor wafers 0 and 10 may be directly
joined together without using the adhesive layer 6. More
alternatively, a layer such as an insulating layer may be formed on
either one or both of the semiconductor wafer 0 and the
semiconductor wafer 10, and the semiconductor wafers 0 and 10 may
be joined together through the insulating layer or the like. For
example, an insulating layer for covering the insulating layer 14
and the via land 16 may be further formed. At this time, the
combined thickness of the wafer 0 and the wafer 10 is 775 .mu.m,
for example.
[0019] After that, in the state where the semiconductor wafer 0 is
held, the back surface of the semiconductor wafer 10 is ground and
polished to a thickness of 20 .mu.m. At this time, since the
semiconductor wafer 10 is joined with the semiconductor wafer 0,
the rigidity to withstand the polishing can be ensured. After the
polishing, an insulating layer 17 is formed on the back surface
(polished surface) of the semiconductor wafer 10 as illustrated in
FIG. 4.
[0020] A resist pattern (not illustrated) is formed on the back
surface using a well-known technique and dry etching is then
performed, thereby forming a via hole 15. The cross-section of the
via hole 15 taken along the direction in parallel with the
principal surface of the semiconductor wafer 10 has a substantially
circular shape in the first embodiment. The center of the
cross-section substantially coincides with the center of the via
land 16 in plan view, and an inner diameter D (for example, 10
.mu.m) of the cross-section satisfies the relation of A>D>C
(A represents the outer diameter of the via land 16; C represents
the inner diameter (diameter excluding the via land) of the via
land 16; and D represents the inner diameter of the via hole 15).
Accordingly, during the etching process for forming the via hole 15
penetrating the wafer 10, the via land 16 serves as a mask for
inhibiting etching after a portion in the range from the back
surface to the via land 16 of the wafer (including the insulating
layers 17 and 12) is etched. Etching is continuously carried out
through a gap portion of the via land 16 which is not blocked by
the via land 16. Etching is continued until the adhesive layer 6 is
etched to reach the electrode pads 2 of the semiconductor wafer
0.
[0021] The via hole 15 thus formed has steps formed at positions
corresponding to the via lands 16 as illustrated in FIG. 5. This
results in formation of two regions: a large diameter region
ranging from the back surface of the semiconductor wafer 10 to the
via land 16; and a small diameter region ranging from the via land
16 to the electrode pad 2 of the semiconductor wafer 0. In this
case, the surface, which faces the back surface of the
semiconductor wafer 10, of each of a part of the electrode pad 2
and a part of the via land 16 is exposed. If etching is performed
such that the side surfaces of the via hole 15 are substantially
perpendicular to the semiconductor wafer 10, the exposed portion of
the electrode pad 2 has a diameter of about 7 .mu.m and the exposed
portion of the via land 16 has a diameter of about 10 .mu.m (in
this case, however, the via land 16 has a doughnut shape with an
inner diameter of about 7 .mu.m). Accordingly, the exposed area of
the electrode pad 2 is substantially equal to the exposed area of
the via land 16.
[0022] After that, an insulating film 13 is formed on the inner
wall of the via hole 15. Then, as illustrated in FIG. 6, the
insulation film 13 formed on the surface facing the back surface of
the semiconductor wafer 10 is removed by RIE (Reactive Ion
Etching), so that the insulating film 13 remains only on the side
walls of the via hole 15.
[0023] Further, a plating seed layer is formed within the via hole
15, as needed, and copper plating is carried out using the
semiconductor wafer 0 as a plating electrode. As illustrated in
FIG. 7, a metal 11 (for example, copper) is filled in the via hole
15. Because the via hole 15 is formed in each chip region, the
plating is performed in the state where the plurality of via holes
15 is electrically connected in parallel to the semiconductor wafer
0. The use of the semiconductor wafer 0 as an electrode enables
bottom-up filling, reduction of a void failure, and improvement in
uniformity of the plating between the via holes 15 in the
semiconductor wafer 10. Additionally, even if the via holes have a
high aspect ratio, the filling property can be improved.
[0024] As a result, the surface of the via land 16 which faces the
back surface side of the semiconductor wafer 10 is electrically
connected to the metal 11 formed in the via hole 15. At the same
time, the surface of the electrode pad 2 which faces the back
surface side of the wafer 10 is electrically connected to the metal
11 formed in the via hole 15. Further, the exposed area of the via
land 16 is substantially equal to the exposed area of the electrode
pad 2, which makes it possible to satisfactorily maintain the
electrical connection between the exposed portions and the metal 11
formed in the via hole.
[0025] After that, the same processes are repeated. Specifically, a
semiconductor element and a via land 26 are formed on each chip
region of another semiconductor wafer 20, and a failure test is
then performed. As illustrated in FIG. 3, a predetermined wiring
line is removed in each defective chip. After that, as illustrated
in FIG. 8, the element surface of the semiconductor wafer 20 and
the back surface (polished surface) of the semiconductor wafer 10
are joined together using an adhesive layer 72. Then, the back
surface of the semiconductor wafer 20 is polished to thereby thin
the semiconductor wafer 20 to a thickness of 20 .mu.m. An
insulating film 23 is formed on the polished surface, and etching
is then performed on the back surface of the semiconductor wafer 20
to thereby form a via hole 25. The via hole 25 has a diameter
greater than that of the gap of the via land 26, and the via hole
25 is formed such that the center of the via hole 25 substantially
coincides with the center of the via land 26 in plan view. Thus,
the via hole 25 has a large diameter portion ranging from the back
surface of the semiconductor wafer 20 to the via land 26, and a
small diameter portion ranging from the via land 26 to the metal 11
formed in the via hole 15. During the etching process, the back
surface of the semiconductor wafer 10 and the front surface of the
semiconductor wafer 20 are joined together through the adhesive
layer 72. Accordingly, not only the semiconductor wafer 20 but also
the adhesive layer 72 is etched to expose the metal 11 of the
semiconductor wafer 10. In the manner as described above, the via
hole 25 penetrating the semiconductor wafer 20 is formed. After
formation of the insulating film 23 on the side walls, a metal 21
is filled in the via hole 25 using the semiconductor wafer 0 as a
plating electrode (FIG. 8).
[0026] FIG. 9 illustrates a structure in which semiconductor wafers
0, 10, 20, 30, 40 are stacked (components of the structure are
illustrated in other figures, so reference numerals and explanation
thereof are omitted). In this case, however, it has turned out as a
result of a test that the semiconductor wafer 20 includes defective
chips at illustrated positions. For this reason, a part of the via
land is removed using an etchant in the manner as described above,
and the other semiconductor wafers 10 and 30 are then stacked. This
allows the process for the via hole to be finished without being
inhibited by the via land, during formation of the via hole in the
semiconductor wafer 20. As a result, the chip in the semiconductor
wafer 20 and the conductor formed in the via hole are electrically
disconnected.
[0027] After that, as illustrated in FIG. 10, the front surface of
the semiconductor wafer 0 is ground and polished to expose the
connecting pads 2 (electrodes). The structure in which the
semiconductor wafers 10 to 40 are stacked has a thickness of 80
.mu.m. Accordingly, if the structure is held or clamped during the
polishing of the semiconductor wafer 0, the semiconductor wafer 0
can be suitably polished. This makes it possible to manufacture a
structure including a via hole penetrating the entire structure and
conductor portions (connecting pads 2 and conductor exposed to the
back surface of the semiconductor wafer 40) which are electrically
connected to the via hole and exposed to the front and back
surfaces of the structure.
[0028] After that, the stacked layer structure of the semiconductor
wafer is divided into chips by a well-known technique such as
dicing or scribing. As a result of polishing and removing an upper
portion of the semiconductor wafer 0, the stacked layer structure
has a thickness of 80 .mu.m or more. This enables favorable
division.
[0029] FIG. 11 illustrates a structure in which semiconductor
modules 100-1 and 100-2 which are formed in the manner as described
above are stacked through bumps 50. In the structure illustrated in
FIG. 11, the two semiconductor modules 100-1 and 100-2 are each
formed by stacking four semiconductor substrates. Alternatively,
modules having different number of substrates to be stacked (for
example, five layers or three layers) may be stacked. For example,
when a semiconductor module having a 4-layer structure includes a
defective semiconductor chip, the semiconductor module may be
stacked with a semiconductor module having a 5-layer structure. On
the other hand, when the semiconductor module having the 4-layer
structure includes no defective semiconductor chip, the
semiconductor module is further stacked with a semiconductor module
having the 4-layer structure. Thus, the stack of semiconductor
modules having different layer structures depending on the presence
or absence of a defective chip enables adjustment of the entire
memory capacity to be maintained constant.
SECOND EMBODIMENT
[0030] FIG. 12 is a schematic diagram of a semiconductor module
according to a second embodiment. As for components fulfilling the
same functions as those of the semiconductor module illustrated in
the first embodiment, reference numerals and explanation thereof
are omitted.
[0031] Generally, via holes (and conductor formed therein) are used
for a signal line, a ground line, a power supply line, and the
like. In some cases, there is no need to expose electrodes to the
front surface of a semiconductor module, depending on the intended
use. In this case, as illustrated in FIG. 12, a via land 52 in the
semiconductor wafer 10 may have a structure with no gap. Insulating
layers 54 and 56 are formed on the via land 52. In this case, the
following process can be employed. That is, a transparent base
substrate, such as glass, is prepared in place of the semiconductor
wafer 0 and the base substrate and the front surface of the
semiconductor wafer 10 are temporarily joined together using an
adhesive layer, which makes it possible to polish the back surface
of the semiconductor wafer 10. Then, as in the first embodiment,
the plurality of joined semiconductor wafers is subjected to heat
treatment and other treatments, and the entirety of the
semiconductor wafer 10 and the base substrate is separated and
removed. This leads to a reduction in cost of the semiconductor
wafer 0. It is also possible to employ a structure in which an
electrode to be electrically connected to a via hole is provided on
the semiconductor wafer 10 and the electrode is exposed to the
front surface after the base substrate is removed.
[0032] There has conventionally been known a method of establishing
electrical conduction between substrates using a via hole upon
stack of a SOI (Silicon-On-Insulator) substrate. Specifically, the
front surface (element forming surface) of a wafer having a
semiconductor element formed thereon and the front surface (element
forming surface) of an SOI substrate having a semiconductor element
formed thereon are joined together by oxide bonding. After that,
the Si substrate formed on the back surface side of the SOI
substrate is removed using an etchant to expose an SiO.sub.2 film
(BOX film). Thereafter, a via hole is formed to obtain electrical
conduction between the both elements of the SOI substrate and the
wafer and the via hole. However, this structure is based on the
premise of using an expensive SOI substrate, resulting in
limitation of the application range. Further, joining of the
element forming surfaces may result in lowered joining yield.
Furthermore, there has been disclosed no method of forming a via
hole penetrating a module (a structure having a plurality of
semiconductor wafers stacked therein). Unlike such a conventional
technique, the above embodiments are not limited to an SOI
substrate and thus are widely applicable. Furthermore, in the above
embodiments, the element forming surfaces are not joined together,
thereby preventing the joining yield from being lowered. Moreover,
each via hole is formed at the predetermined position after the
wafers are joined together. This provides an advantage of easily
forming the via hole penetrating the stacked structure even in the
case where a large number of wafers are stacked.
[0033] Note that the present invention is not limited to the above
embodiment, but can be modified in various manners. For example,
the number of wafers to be stacked is not limited to four, but
eight or more wafers may be stacked. An increase in the number of
wafers to be stacked may facilitate handling for separation or
removal of a wafer or a base substrate.
[0034] As the base substrate which is thereafter separated or
removed from the wafer structure, various materials including a
semiconductor wafer and a transparent substrate such as glass may
be used. In the case of performing a heat treatment during the
separation/removal process to be performed thereafter, however, it
is necessary to select a material in consideration of thermal
expansion/contraction. It should be noted that when glass or the
like is used as the base substrate, it is difficult to use the base
substrate as a plating electrode.
[0035] A method other than plating may be used to fill a conductor
into a via hole. It is not necessary to fill the conductor in all
the space within the via hole. For example, the conductor may be
disposed conformally.
[0036] Further, it is sufficient that the relation of A
(representing the outer diameter of the via land)>B
(representing the outer diameter of a portion of the via land which
is not covered by the upper insulating film)>C (representing the
inner diameter of the via land) and the relation of A>D
(representing the via hole diameter)>C are satisfied in a
specific cross-section. Specifically, as for the magnitude relation
between the gap and the diameter, it is sufficient that the
magnitude relation between the gap of the metal layer in a certain
cross-section (a surface perpendicular to the front surface of the
substrate) and the diameter of the cross-section is ensured. It is
not necessary to ensure the magnitude relation in any
cross-section. For example, provided that the magnitude relation in
a predetermined cross-section is ensured, the gap of the metal
layer or the like in the vertical cross-section may be greater than
the hole diameter.
[0037] FIG. 13 is a schematic plan view of a semiconductor device
including a via land having another shape. As illustrated in FIG.
13, for example, a via land 504 has a U-shape (the outline of the
via land 504 covered with an upper insulating layer 510 is
indicated by the dotted line). Thus, in a cross-section parallel to
the lateral direction of FIG. 13, the relation of A>B>C is
maintained. Meanwhile, in a cross-section parallel to the
longitudinal direction (vertical direction) of FIG. 13, the via
lands 504 are not provided at predetermined intervals, which makes
it impossible to define the relation among A, B, and C. In such a
structure, however, if a via hole having a circular shape in
cross-section and having the relation of B>D>C is formed at
the center in FIG. 13, the via land functions as a mask during
etching for formation of the via hole, thereby achieving an object
of the present invention. From the same point of view, it is
understood that even in the case where wiring lines formed in
parallel with each other at predetermined intervals are used in
place of the via land, for example, the same function as the via
land of the second embodiment can be obtained.
[0038] More alternatively, the via hole may be formed so as to
satisfy the relation A>D>B. Also in this case, electrical
insulation between the via hole (conductor formed therein) and the
via land is not established only by removing the exposed portion of
the via land in a defective chip, but the via land functions as a
mask during etching for formation of the via hole. The name "via
land" is used in the embodiments because a via land is provided in
the middle of a through via hole and is electrically connected to
the conductor formed in the via hole. However, the same function
can also be obtained by using wiring lines or other metal
films.
[0039] When the cross-section of a via hole or the like has a
circular shape, the filling property of the conductor can be
improved. The shape of the cross-section of each via hole is not
limited to a circular shape, but may be a rectangular shape or
another shape. More alternatively, the cross-section may be
tapered.
[0040] The process for forming the semiconductor element and the
like may be carried out before the process for joining the wafer
and the base substrate or after the joining process. The order of
the other processes can be changed freely to the extent that can be
reasonably recognized by those skilled in the art based on the
scope of the present invention.
[0041] The front surface of each substrate includes the front
surface and a region extending in the height and depth directions
in the vicinity of the front surface. The formation of elements and
the like on the front surface of each substrate includes formation
of elements on the front surface and in a region in the vicinity of
the front surface.
[0042] The joining of substrates includes indirect joining of
substrates through an adhesive layer or the like. Furthermore, the
case where holes are continuously formed indicates temporal
continuity and includes the case of etching both holes at once
within the same chamber (without inhibiting a change of an etchant
component). Moreover, as for the electrical connection relation,
there is no need to directly connect the components. The components
may be indirectly connected to each other.
[0043] While certain embodiments have been described, these
embodiments have been presented by way of example only, and are not
intended to limit the scope of the inventions. Indeed, the novel
embodiments described herein may be embodied in a variety of other
forms; furthermore, various omissions, substitutions and changes in
the form of the embodiments described herein may be made without
departing from the spirit of the inventions. The accompanying
claims and their equivalents are intended to cover such forms or
modifications as would fall within the scope and spirit of the
inventions.
* * * * *