U.S. patent application number 13/492473 was filed with the patent office on 2012-10-04 for trench-gate ldmos structures.
Invention is credited to Steven Sapp, Peter H. Wilson.
Application Number | 20120248528 13/492473 |
Document ID | / |
Family ID | 40942645 |
Filed Date | 2012-10-04 |
United States Patent
Application |
20120248528 |
Kind Code |
A1 |
Wilson; Peter H. ; et
al. |
October 4, 2012 |
TRENCH-GATE LDMOS STRUCTURES
Abstract
MOSFET devices for RF applications that use a trench-gate in
place of the lateral gate conventionally used in lateral MOSFET
devices. A trench-gate provides devices with a single, short
channel for high frequency gain. Embodiments of the present
invention provide devices with an asymmetric oxide in the trench
gate, as well as LDD regions that lower the gate-drain capacitance
for improved RF performance. Refinements to these TG-LDMOS devices
include placing a source-shield conductor below the gate and
placing two gates in a trench-gate region. These improve device
high-frequency performance by decreasing gate-to-drain capacitance.
Further refinements include adding a charge balance region to the
LDD region and adding source-to-substrate or drain-to-substrate
vias.
Inventors: |
Wilson; Peter H.; (Boulder
Creek, CA) ; Sapp; Steven; (Felton, CA) |
Family ID: |
40942645 |
Appl. No.: |
13/492473 |
Filed: |
June 8, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12499778 |
Jul 8, 2009 |
8198677 |
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13492473 |
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|
10951259 |
Sep 26, 2004 |
7576388 |
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12499778 |
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10269126 |
Oct 3, 2002 |
7033891 |
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10951259 |
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60506194 |
Sep 26, 2003 |
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Current U.S.
Class: |
257/330 ;
257/E29.257 |
Current CPC
Class: |
H01L 29/4175 20130101;
H01L 29/7835 20130101; H01L 29/41775 20130101; H01L 29/66659
20130101; H01L 29/402 20130101; H01L 29/0847 20130101; H01L 29/7834
20130101; H01L 29/41766 20130101; H01L 29/42368 20130101; H01L
29/0634 20130101; H01L 29/407 20130101; H01L 29/7831 20130101; H01L
29/4236 20130101; H01L 29/66621 20130101 |
Class at
Publication: |
257/330 ;
257/E29.257 |
International
Class: |
H01L 29/78 20060101
H01L029/78 |
Claims
1. An apparatus, comprising: a first silicon region of a first
conductivity type, the first silicon region having a surface; a
gate-trench region extending from the surface of the first silicon
region into the first silicon region, the gate trench region
comprising: a source-shield region comprising a first conductive
region; a gate region comprising a second conductive region and
between the surface of the first silicon region and the
source-shield region, the gate-trench region having an asymmetric
insulating layer along two of its opposing sidewalls; a source
region comprising a dopant region of a second conductivity type,
the dopant region laterally extending along one side of the gate
trench region and contacting a source electrode; and a
lightly-doped drain region of the second conductivity type
laterally extending below and along an opposing side of the one
side of the gate trench region and contacting a drain
electrode.
2. The apparatus of claim 1, wherein the source-shield region is
between the gate region and the lightly-doped drain region.
3. The apparatus of claim 1, wherein the source-shield region is a
polysilicon region.
4. The apparatus of claim 1, wherein the source-shield region and
gate regions are polysilicon regions.
5. The apparatus of claim 1, wherein the lightly doped drain region
partially extends along a first sidewall of the gate trench such
that a channel region along the first sidewall between the source
region and the lightly doped drain region extends along the
vertical dimension.
6. The apparatus of claim 1, further comprising: a charge-balance
region of the first conductivity type, the charge-balance region in
the lightly-doped drain region.
7. The apparatus of claim 1, wherein the first silicon region is an
epitaxial layer formed on a substrate, the MOSFET further
comprising: a source-substrate via coupling the source to the
substrate.
8. The apparatus of claim 1, wherein the first silicon region is an
epitaxial layer formed on a substrate, the MOSFET further
comprising: a drain-substrate via coupling the source to the
substrate.
9. An apparatus, comprising: a first silicon region of a first
conductivity type, the first silicon region having a surface; a
gate-trench region extending from the surface of the first silicon
region into the first silicon region, the gate trench region
comprising: a first gate region comprising a first conductive
region; a second gate region comprising a second conductive region
and between the surface of the first silicon region and the first
gate region, the gate-trench region having an asymmetric insulating
layer along two of its opposing sidewalls; a source region
comprising a dopant region of a second conductivity type, the
dopant region laterally extending along one side of the gate trench
region and contacting a source electrode; and a lightly-doped drain
region of the second conductivity type laterally extending below
and along an opposing side of the one side of the gate trench
region and contacting a drain electrode.
10. The apparatus of claim 9, wherein the first gate region is
between the second gate region and the lightly-doped drain
region.
11. The apparatus of claim 9, wherein the first and second gate
regions are polysilicon regions.
12. The apparatus of claim 9, wherein the lightly doped drain
region partially extends along a first sidewall of the gate trench
such that a channel region along the first sidewall between the
source region and the lightly doped drain region extends along the
vertical dimension.
13. The apparatus of claim 9, further comprising: a charge-balance
region of the first conductivity type, the charge-balance region in
the lightly-doped drain region.
14. The apparatus of claim 9, wherein the first silicon region is
an epitaxial layer formed on a substrate, the MOSFET further
comprising: a source-substrate via coupling the source to the
substrate.
15. The apparatus of claim 9, wherein the first silicon region is
an epitaxial layer formed on a substrate, the MOSFET further
comprising: a drain-substrate via coupling the source to the
substrate.
16. An apparatus, comprising: a first silicon region of a first
conductivity type, the first silicon region having a surface; a
gate-trench region extending from the surface of the first silicon
region into the first silicon region, the gate trench region
including a gate region comprising a conductive region, the
gate-trench region also including an asymmetric insulating layer
along two of its opposing sidewalls; a source region comprising a
dopant region of a second conductivity type, the dopant region
laterally extending along one side of the gate trench region and
contacting a source electrode; and a lightly-doped drain region of
the second conductivity type laterally extending below and along an
opposing side of the one side of the gate trench region and
contacting a drain electrode, the lightly-doped drain region
comprising a charge-balance region of the first conductivity
type.
17. The apparatus of claim 16, wherein the charge-balance region is
between the gate-trench region and the drain electrode.
18. The apparatus of claim 17, wherein the first silicon region is
an epitaxial layer formed on a substrate, the MOSFET further
comprising: a source-substrate via coupling the source to the
substrate.
19. The apparatus of claim 17, wherein the first silicon region is
an epitaxial layer formed on a substrate, the MOSFET further
comprising: a drain-substrate via coupling the source to the
substrate.
20. The apparatus of claim 17, wherein the lightly doped drain
region partially extends along a first sidewall of the gate trench
such that a channel region along the first sidewall between the
source region and the lightly doped drain region extends along the
vertical dimension.
Description
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] This application is a continuation application of U.S.
patent application Ser. No. 12/499,778, filed Jul. 8, 2009, which
is a divisional application of U.S. patent application Ser. No.
10/951,259, filed Sep. 26, 2004, now U.S. Pat. No. 7,576,388. U.S.
patent application Ser. No. 10/951,259, filed Sep. 26, 2004, now
U.S. Pat. No. 7,576,388, claims priority to and the benefit of U.S.
Provisional Application No. 60/506,194, filed Sep. 26, 2003 and is
a continuation-in-part of U.S. patent application Ser. No.
10/269,126, filed Oct. 3, 2002, now U.S. Pat. No. 7,033,891. Each
of the disclosures of the patent applications listed above is
incorporated herein by reference in its entirety.
[0002] The following patent application is commonly assigned with
the present application and is incorporated by reference herein in
its entirety:
[0003] U.S. patent application Ser. No. 60/405,369, entitled
"Improved MOS Gating Method for Reduced Miller Capacitance and
Switching Losses", filed Aug. 23, 2002.
BACKGROUND
[0004] The invention generally relates to methods for fabricating
integrated circuits (ICs) and semiconductor devices and the
resulting structures. More particularly, the invention relates to
metal oxide semiconductor-field-effect transistor (MOSFET) devices
and methods for making such devices. Even more particularly, the
invention relates to improvements that may be made to trench-gate
laterally-diffused MOSFET devices and methods for making such
improved devices.
[0005] In IC fabrication, devices such as transistors may be formed
on a semiconductor wafer or substrate, which is typically made of
silicon. MOSFET devices are widely used in numerous electronic
apparatus, including automotive electronics, disk drives and power
supplies. Generally, these apparatus function as switches and are
used to connect a power supply to a load.
[0006] One of the applications in which MOSFET devices have been
used is for radio frequency (RF) applications. Such RF MOSFET
devices are generally lateral transistors. See, for example, the
lateral MOSFET device described in U.S. Pat. No. 5,949,104, as well
as the device illustrate in FIG. 1. Such lateral MOSFET devices
often have a diffused source that allows a backside contact for
improved thermal conducting and reduced parasitics.
[0007] Recent advances in lateral (or laterally-diffused) MOSFET
(LDMOS) devices have improved the performance and cost
characteristics of lateral MOSFET devices when compared to vertical
MOSFET devices for RF power amplifiers in base stations
applications. Such RF LDMOS devices have been particularly useful
for wireless base station applications. The RF vertical (or
vertically-diffused) VDMOS structure unfortunately suffers from
certain limitations relative to the LDMOS such as high output
capacitance (which decreases efficiency), decreased power gain,
narrowing of the usable bandwidth, and source inductance that
decreases the operating efficiency.
[0008] Thus, what is needed are circuits, methods, and apparatus
that provide an improved LDMOS having reduced output capacitance,
increased power gain, and more useable bandwidth.
SUMMARY
[0009] Embodiments of the present invention provide MOSFET devices
for RF applications that use a trench-gate in place of the lateral
gate conventionally used in lateral MOSFET devices. A trench-gate
provides devices with a single, short channel for high frequency
gain. Embodiments of the present invention provide devices with an
asymmetric oxide in the trench gate, as well as LDD regions that
lower the gate-drain capacitance for improved RF performance. Such
features allow these devices to maintain the advantages of the
LDMOS structure such as better linearity, thereby increasing the RF
power gain. The trench-gate LDMOS (TG-LDMOS) of the invention also
reduces the hot carrier effects when compared to regular LDMOS
devices by reducing the peak electric field and impact
ionization.
[0010] Refinements to these TG-LDMOS devices include placing a
source-shield conductor below the gate and placing two gates in a
trench-gate region. These improve device high-frequency performance
by decreasing gate-to-drain capacitance. Further refinements
include adding a charge balance region to the LDD region and adding
source-to-substrate or drain-to-substrate vias. Various embodiments
of the present invention may incorporate one or more of these or
the other features described herein.
[0011] An exemplary embodiment of the present invention provides a
MOSFET. This MOSFET includes a first silicon region of a first
conductivity type, the first silicon region having a surface, and a
gate-trench region extending from the surface of the first silicon
region into the first silicon region. The gate trench region
includes a source-shield region including a first conductive
region, and a gate region comprising a second conductive region and
between the surface of the first silicon region and the
source-shield region. The gate-trench region has an asymmetric
insulating layer along two of its opposing sidewalls. The MOSFET
further includes a source region including a dopant region of a
second conductivity type, the dopant region laterally extending
along one side of the gate trench region and contacting a source
electrode; and a lightly-doped drain region of the second
conductivity type laterally extending below and along an opposing
side of the one side of the gate trench region and contacting a
drain electrode.
[0012] Another exemplary embodiment provides another MOSFET. This
transistor includes a first silicon region of a first conductivity
type, the first silicon region having a surface, a gate-trench
region extending from the surface of the first silicon region into
the first silicon region. The gate trench region includes a first
gate region comprising a first conductive region, a second gate
region comprising a second conductive region and between the
surface of the first silicon region and the first gate region. The
gate-trench region has an asymmetric insulating layer along two of
its opposing sidewalls. This device further includes a source
region comprising a dopant region of a second conductivity type,
the dopant region laterally extending along one side of the gate
trench region and contacting a source electrode, and a
lightly-doped drain region of the second conductivity type
laterally extending below and along an opposing side of the one
side of the gate trench region and contacting a drain
electrode.
[0013] A further exemplary embodiment provides another MOSFET. This
transistor includes a first silicon region of a first conductivity
type, the first silicon region having a surface, a gate-trench
region extending from the surface of the first silicon region into
the first silicon region, the gate trench region including a gate
region comprising a conductive region. The gate-trench region also
including an asymmetric insulating layer along two of its opposing
sidewalls. The device also includes a source region comprising a
dopant region of a second conductivity type, the dopant region
laterally extending along one side of the gate trench region and
contacting a source electrode, and a lightly-doped drain region of
the second conductivity type laterally extending below and along an
opposing side of the one side of the gate trench region and
contacting a drain electrode, the lightly-doped drain region
comprising a charge-balance region of the first conductivity
type.
[0014] A better understanding of the nature and advantages of the
present invention may be gained with reference to the following
detailed description and the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 illustrates a prior art MOSFET device;
[0016] FIG. 2 illustrates a MOSFET device according to an
embodiment of the present invention;
[0017] FIGS. 3-5 illustrate a MOSFET device according to an
embodiment of the present invention at various processing stages
during manufacture;
[0018] FIG. 6 illustrates a MOSFET device according to another
embodiment of the present invention.
[0019] FIG. 7 shows a cross section view of a TG-LDMOS having a
source shield integrated with the gate structure in accordance with
an embodiment of the present invention;
[0020] FIGS. 8A-8D depict an exemplary sequence of process steps
for manufacturing the source-shield TG-LDMOS in FIG. 7 in
accordance with one embodiment of the present invention;
[0021] FIGS. 9A and 9B respectively show a cross section view of a
TG-LDMOS having two control gates and a corresponding transistor
symbol in accordance with another embodiment of the present
invention;
[0022] FIGS. 10A-10D depict an exemplary sequence of process steps
for manufacturing the dual-gate TG-LDMOS in FIG. 9A in accordance
with one embodiment of the present invention;
[0023] FIGS. 11A and 11B show cross section views of two TG-LDMOS
structures wherein a charge-balancing technique is used to improve
the breakdown voltage in accordance with another embodiment of the
present invention;
[0024] FIGS. 12A and 12B respectively show a cross section view of
TG-LDMOS structure having a source-substrate via and a variation
thereof in accordance with an embodiment of the present
invention;
[0025] FIG. 12C shows integration of the source-substrate via of
FIG. 12A with the source shield TG-LDMOS structure of FIG. 7;
[0026] FIG. 13A through 13C show a cross section view of TG-LDMOS
structures;
[0027] FIG. 14 is a cross section view illustrating how the
source-substrate via can be advantageously used to obtain a smaller
cell pitch;
[0028] FIG. 15 is a cross section view showing one technique for
interconnecting the source-shield to the source terminal;
[0029] FIG. 16 is a cross section view showing the combination of
the dual-gate structure depicted in FIG. 9A with the source to
substrate connection technique depicted in FIG. 12A;
[0030] FIG. 17 is a cross section view showing the dual-gate
structure of FIG. 9A in combination with the charge balance
technique of FIG. 11;
[0031] FIG. 18 is a cross section view showing a variation of the
dual-gate structure in combination with the charge balance
technique of FIG. 11; and
[0032] FIG. 19 is a cross section view showing the same variation
of the dual-gate structure depicted in FIG. 18 in combination with
an n+ drain sinker.
DETAILED DESCRIPTION
[0033] The following description provides specific details in order
to provide a thorough understanding of the invention. The skilled
artisan, however, would understand that the invention can be
practiced without employing these specific details. Indeed, the
invention can be practiced by modifying the illustrated system and
method and can be used in conjunction with apparatus and techniques
conventionally used in the industry. For example, the MOSFET
devices are described for RF applications, but could be used in
non-RF applications such as switching.
[0034] As noted above, the invention generally comprises a
structure that combines the benefits of the LDMOS structure (i.e.,
a low gate-to-drain capacitance and a good linearity) with the
benefits of a short gate channel. Thus, any structure that combines
theses feature can be employed in the invention. In one embodiment
of the present invention, these benefits are combined by using a
trench gate laterally-diffused MOSFET device as described below. By
using this structure, the breakdown capabilities of conventional
LDMOS structure can be improved. In addition, the carrier effects
(i.e., injection) are improved, and the peak electric field and
impact ionization of the drain region is reduced.
[0035] To achieve these benefits, the structure illustrated in the
FIG. 2 is used in the invention. In FIG. 2, the MOSFET device 5
comprises a semiconductor substrate 10, typically of
monocrystalline silicon (Si), with an epitaxial layer 60 formed
thereon. In one embodiment of the present invention, the silicon
substrate 10 can have a first conductivity type, such as B (boron),
with a dopant concentration of about 2.times.10.sup.19
atoms/cm.sup.3. In another embodiment of the present invention, the
substrate can have a resistivity ranging from 0.005 to 0.01 ohm
centimeter. A contact region 55 can be located on the "backside" of
the substrate 10. In one embodiment of the present invention, the
contact region 55 is a metal contact. In one embodiment of the
present invention, the depth of the epitaxial layer 60 can range
from about 3 to about 9 microns and can have a first conductivity
dopant concentration of about 1.2.times.10.sup.15 atoms/cm.sup.3.
In another embodiment of the present invention, the epitaxial layer
can have a resistivity ranging from about 20 to about 30 ohm
centimeters.
[0036] A gate structure 90 is located between source region 95 and
drain region 100. The gate structure 90 is separated from the
source region 95 by a body region 40. And the gate structure 90 is
separated from the drain region 100 by a lightly doped drain (LDD)
region 75.
[0037] The gate structure 90 contains gate conductor 30, as well as
an insulating layer 80 surrounding that part of the gate conductor
30 in the trench 85. The MOSFET device contains channel region 25
of a first conductivity type (p-type in one embodiment of the
present invention) that is adjacent to the side of the insulating
layer 80 of the gate structure 90 nearest the source region 95.
Because of this configuration of the gate in the trench 85, the
gate structure 90 is often referred to as a trench gate in which
length of the gate is controlled by the depth of the trench 85. In
one embodiment of the present invention, the trench depth can range
from about 0.5 to about 4.0 microns. In another embodiment of the
present invention, the depth of the trench can be about 1 to about
2 microns. In yet another embodiment of the present invention, the
trench depth can be about 1.5 microns.
[0038] With this configuration of the gate structure 90, the thin
insulating layer between the channel region 25 and the conducting
layer 30 operates as a high-quality gate insulating layer.
[0039] In addition, the insulating layer 80 (which in some
embodiments of the invention is asymmetric) can also reduce the
gate to drain capacitance (Cgd). As well, the thick bottom oxide
(with a thickness of about 1 k.ANG. to about 4 k.ANG.) can reduce
the gate-to-drain overlap capacitance and thereby lower the gate
charge.
[0040] By applying a positive gate voltage to device 5, the channel
region 25 can change the polarity from a first conductivity type to
a second conductivity type. This polarity change--called
inversion--permits the carriers to drift (e.g., flow) from the
dopant region 70 to the lightly doped drain (LDD) region 75. Thus,
the channel region 25 can be modulated by a positive gate
voltage.
[0041] Source region 95 comprises dopant region 35 and source
electrode 15. The dopant region 35 is typically of a first
conductivity type with a concentration ranging from about
5.times.10.sup.15 to about 1.times.10.sup.19 atoms/cm.sup.3. In one
embodiment of the present invention, the concentration of dopant
region 35 is about 1.times.10.sup.19 atoms/cm.sup.3. The source
electrode 15 is located over dopant region 35 and overlaps body
region 40. The body region 40 is typically of a first conductivity
type with a concentration greater than or equal to the
concentration of the epitaxial layer 60. In one embodiment of the
present invention, the concentration of body region 40 is about
2.5.times.10.sup.15 atoms/cm.sup.3.
[0042] As known in the art, source electrode 15 can be separated
from the body region 40 by dopant region 70 of a second
conductivity type. As well, the source electrode 15 can be
separated from the gate structure 90 by a distance (a) that depends
on the desired characteristics of the gate. Generally, this
distance (a) can range from about 0.5 to about 1.5 microns.
[0043] The drain region 100 contains a drain electrode 20 overlying
a portion of LDD region 75. In one embodiment of the present
invention, the drain electrode 20 is separated from the gate by a
distance (b) depending on the desired drain-source breakdown
voltage. In one embodiment of the present invention, this distance
typically can be between about 3 to about 5 microns. In another
embodiment of the present invention, the drain electrode is
separated from gate by a distance of about 4 microns. The drain
electrode 20 is also separated from the LDD region 75 by a dopant
region 65. In one embodiment of the present invention, the dopant
region 65 is of a second conductivity type with a concentration of
ranging from about 1.times.10.sup.15 to 1.times.10.sup.16
atoms/cm.sup.3.
[0044] The LDD region 75 contains a first drain drift region 45 of
the MOS structure. The first drain drift region 45 is formed
completely within the epitaxial layer 60, with a part underlying
the trench 85. In one embodiment of the present invention, the
first enhanced drain drift region 45 has second conductivity type
when the epitaxial layer 60 has a first conductivity type. In one
embodiment of the present invention, the first enhanced drain drift
region 45 can have a dopant concentration ranging from about
1.times.10.sup.11 to about 5.times.10.sup.13 atoms/cm.sup.3. In
another embodiment of the present invention, this dopant
concentration is about 2.times.10.sup.12 atoms/cm.sup.3. The first
enhanced drain region 45 can have lateral dimensions ranging from
about 0.5 to about 5.0 microns and vertical dimensions ranging from
about 0.2 to about 0.5 microns
[0045] The LDD region 75 also contains a second enhanced drain
drift region 50 that is adjacent to and contacting the first drain
drift region 45. The second drain drift region 50 is also formed
completely within the epitaxial layer 60. In one embodiment of the
present invention, the second drain drift region 50 has second
conductivity type when the epitaxial layer 60 has a first
conductivity type. In one embodiment of the present invention, the
second drain drift region can have a dopant concentration greater
than the first drain drift region 45. In one embodiment of the
present invention, the dopant concentration can range from about
1.times.10.sup.11 to about 1.times.10.sup.14 atoms/cm.sup.3. In
another embodiment of the present invention, this dopant
concentration is about 1.times.10.sup.13 atoms/cm.sup.3. The second
drain region 50 can have lateral dimensions ranging from more than
0 to about 5 microns and vertical dimensions substantially similar
to the first drain drift region 45.
[0046] Using the two drain drift regions 45 and 50 in LDD region 75
allows one to increase the maximum drain drift current density of
the device, as well as increase the drain-to-source breakdown
voltage. Indeed, the effective electrical field in the LDD region
75 is strong enough to cause the avalanche effect of carrier
multiplication at certain critical concentration of carriers. Thus,
the critical carrier concentration can be related to the breakdown
voltage in device 5. In one embodiment of the present invention,
three or more drift regions that are uniformly graded from a light
dopant concentration to a heavier dopant concentration can be used
as LDD region 75.
[0047] In one embodiment of the present invention, the second drain
drift region 50 has a concentration higher than the concentration
of the first drain drift region 45. This configuration can result
in the redistribution of the critical electrical fields in the
channel region 25 and can result in an increase of the
drain-to-source breakdown voltage. The maximum current density in
the source-drain channel of the device can also be increased when
the total concentration in the drain drift region is increased.
[0048] Using the two drain drift regions 45 and 50 also allow the
LDD region 75 to act as a non-linear resistor, especially when the
applied voltage is varied. This non-linear behavior suggests the
existence of a pinch-off point in the LDD region 75. In other
words, as the applied voltage is increase, the depletion region
present in the LDD region 75 can expand and lead to a pinch-off
point.
[0049] Configuring the LDD region 75 as indicated above can also be
used to support efficient operation of device 5. The dopant profile
of the LDD region 75 can be controlled by having different sectors
each with a different dopant concentration. The different doping
concentrations can be configured to ensure that any breakdown does
not occur near the upper surface of the device, but deeper within
the LDD region 75 near the interface of the dopant region 65 and
LDD region 75. The ability to configure the LDD region 75 in this
manner must be carefully balanced, of course, with the other
operating parameters of the device such as Cgd and the drain to
source capacitance (Cds).
[0050] As noted above, the drift drain region 45 extends under the
trench 85. In one embodiment of the present invention, the dopant
concentration of the region under the trench 85 should be higher
than the concentration of the remainder of LDD region 75. This
region is an extension of LDD region 75 and helps create a current
flow from the drain to the source. The concentration of this region
should be tailored to the required drain-source breakdown voltage,
as well as to not to substantially increase the gate to drain
capacitance.
[0051] By using a trench gate, the devices of the invention are
able to achieve several improvements over existing LDMOS devices.
First, the devices of the invention have an improved RF power gain
and efficiency due to the reduction of the Cgd resulting from the
asymmetric insulating material in the trench and the shorter
channel. Second, the devices of the invention are able to reduce
the hot carrier effects by reducing the peak electric field. Third,
the operating voltages of the devices of the invention can be
increased above the capabilities of existing LDMOS devices.
[0052] The device illustrated in FIG. 2 can be made by any process
resulting in the depicted structure. In one embodiment of the
present invention, the process described below and illustrated in
FIGS. 3-5 is used to make the structure depicted in FIG. 2.
[0053] Referring to FIG. 3, the process begins with substrate 10.
Any substrate known in the art can be used in the invention.
Suitable substrates include silicon wafers, epitaxial Si layers,
polysilicon layers, bonded wafers such as used in
silicon-on-insulator (SOI) technologies, and/or amorphous silicon
layers, all of which may be doped or undoped. If the substrate is
undoped, it can then be doped with a first conductivity type dopant
to the concentration noted above by any method known in the
art.
[0054] Next, the backside contact region 55 is formed. In one
embodiment of the present invention, the contact region 55 can be
formed by a metallization process. Then, if the epitaxial layer 60
is not already present, it is formed on the substrate 10 by any
process known in the art. If the epitaxial layer is not doped in
situ, then the desired doping concentration can be formed using any
known process. Next, the various dopant regions 35, 40, 45, 50, 65,
and 70 can be formed as known in the art.
[0055] As depicted in FIG. 3, trench 85 is then formed in the upper
surface of the epitaxial layer 60. The trench 85 can be are formed
by any suitable masking and etching process known in the art. For
example, the etching process can begin by forming a mask (not
shown) with an opening(s) where the trench(es) will be formed. The
silicon in the trench is then removed by etching through the mask.
The parameters of the etching process are controlled to preferably
form round bottom corners, smooth and continuous sidewalls, flat
and clean trench bottom surfaces, and trench depth, thereby
maintaining the integrity of the device characteristics using the
trenches. After forming the trenches, the mask is removed by any
suitable process known in the art.
[0056] As depicted in FIG. 4, the trench 85 is then filled with the
material for insulating layer 80. This material for the insulating
layer can be any high-quality insulating material known in the art,
such as silicon nitride, silicon oxide, or silicon oxynitride. In
one embodiment of the present invention, the insulating layer is
silicon oxide (or "oxide"). In this embodiment of the present
invention, an oxide layer is provided on the top surface of the
epitaxial layer 60, including the trench 85. Any suitable method
known in the art--including oxidation and deposition--yielding a
high quality oxide layer can be used to provide this oxide layer.
The portions of the oxide layer on the surface of the epitaxial
layer 60 are then removed by any known process, leaving the oxide
solely within the trench 85.
[0057] Next, a second trench 105 is formed within the insulating
layer 80. This second trench can be formed in a manner
substantially similar to the method used to form the first trench
85, with a few modifications. The first modification is that the
mask material and the etching chemical may be different to account
for the difference between etching silicon and etching the material
for the insulating layer 80, e.g., oxide. The second modification
is that the width of the mask openings for the second trench 105
will be smaller than the first trench 85.
[0058] After the second trench 105 is formed, the conductive
material 110 for the gate, source, and drain is deposited to fill
and overflow the remaining portions of the second trench 105 as
illustrated in FIG. 5. This conductive layer can be suitable
material that can be used as a gate conductor, such as a metal,
metal alloy, or polysilicon. In one embodiment of the present
invention, the conductive layer is heavily doped polysilicon. The
conductive layer can be deposited using any known deposition
process, including chemical vapor deposition process. Optionally,
the conductive layer 105 can be doped with any suitable dopant to
the desired concentration, particularly when the conductive layer
is polysilicon or when a silicide can be used to reduce the
resistance of the gate. Excess (and unneeded) portions of the
conductive layer 105 are then removed using any conventional
process to form the gate conductor 30, the source electrode 15, and
the drain electrode 20. In another embodiment of the present
invention, additional deposition, masking, and etching steps can be
used if the conductive material for the gate conductor, the source
electrode, and the drain electrode will be different.
[0059] After the above processes are concluded, conventional
processing can continue to finish the MOSFET device. As well, other
processing needed to complete other parts of the semiconductor
device can then be carried out, as known in the art.
[0060] In the embodiment of the present invention described above
and illustrated in the Figures, the first conductivity type is a
p-type dopant and the second conductivity type is an n- type
dopant. In another embodiment of the present invention, the device
can be configured with the first conductivity type being a n-type
dopant and the second conductivity type dopant being a p-type
dopant.
[0061] The devices of the invention can also be modified to contain
more than a single gate. For example, as depicted in FIG. 6, the
devices of the invention can contain two trench gates between the
source and drain. In the embodiment of the present invention shown
in FIG. 6, the device can contain one gate with a symmetric oxide
and one gate with an asymmetric oxide. In another embodiment of the
present invention, both gates can contain an asymmetric oxide. The
device in FIG. 6 is manufactured similar to the device depicted in
FIG. 2, except that two trenches with two gate structures could be
provided instead of a single trench. Other modifications are
described below:
[0062] FIG. 7 shows a cross section view of a TG-LDMOS having a
source shield 710 integrated with the gate structure 720 in
accordance with an embodiment of the invention. The source shield
is located below the gate 730 and is electrically connected (not
shown) to the source terminal 740. In one embodiment, the
connection to the source terminal 740 is made by extending the
source shield 710 in the direction perpendicular to the page and
then routing it up to the trench surface where electrical contact
is made to the source metal 750. Such devices can be used in RF
applications and in high power switching applications. As shown,
the TG-LDMOS has a vertical channel but employs a lateral drift
region which together with an n-type region wrapping around a
bottom portion of the trench forms a contiguous n-type region. The
trench has a thick insulator along its bottom and an asymmetrical
insulator along its sidewalls (i.e., has a thicker insulator along
its drain-side sidewall than its source-side sidewall) to reduce
parasitic capacitance.
[0063] The source shield 710 improves device high frequency gain by
reducing the gate-to-drain capacitance (Cgd) and improves the
breakdown voltage characteristics. While in operation, the electric
field resulting from the biased gate 730 is terminated in the
shield plate (source-shield 710) thus minimizing Cgd. There is a
slight increase in input or Ciss capacitance due to the presence of
the source shield 710 but this can be compensated by input
impedance matching. Accordingly, by providing a "shield" between
the gate 730 and the drain 760, Cgd is significantly reduced thus
increasing the maximum oscillation frequency. Moreover, the source
shield 710 helps reduce the hot carrier effects by reducing the
peak electric field and impact ionization
[0064] The process technology for forming the source-shield
TG-LDMOS in FIG. 7 is compatible with conventional silicon MOSFET
technology. In one embodiment, the process steps described below
and illustrated in FIGS. 8A-8D is used to make the source-shield
TG-LDMOS in FIG. 7.
[0065] A silicon substrate such as silicon wafers or epitaxial
silicon layers may be used. If the substrate is undoped, it can
then be doped with a first conductivity type dopant to a desired
concentration by any method known in the art. In one embodiment,
highly doped silicon wafer is used to reduce source resistance in
the substrate. In FIG. 8A, a p+ type substrate 810 is used. If an
epitaxial layer is not already present, it is formed on the
substrate using conventional methods. If the epitaxial layer is not
doped in situ, then the desired doping concentration may be
obtained using conventional methods. As shown in FIG. 8A, the
various dopant regions such as the p+ type sinker 820 and n- type
LDD region 830 are formed as known in the art. For example,
conventional sinker mask implant and drive-in steps and LDD mask
implant and drive-in steps may be carried out to form the p+ type
sinker 820 and n- type LDD regions 830, respectively. Other dopant
regions such as the p- type body region (not shown) and n+ contact
regions (not shown) may also be formed at this stage even though
they are shown being formed in later stages.
[0066] A trench 850 is then formed in the upper surface of the
epitaxial layer using conventional masking and etching steps. For
example, the etching process can begin by forming an oxide hard
mask with an opening where the trench 850 is to be formed. The
silicon in the trench area 850 is then removed by etching through
the mask opening. The parameters of the etching process are
controlled to preferably form rounded corners and smooth and clean
trench sidewalls and bottom surfaces, thereby maintaining the
integrity of the device characteristics. In one embodiment, after
the trench surfaces are cleaned, the portion of the LDD region 830
which wraps abound the trench is formed by carrying out a
conventional implant (e.g., angled implant) or plasma immersion
doping or equivalent, followed by activation. The oxide hard mask
may be then be removed or left in place for subsequent
processing.
[0067] In FIG. 8B, the trench 850 is then filled with insulating
material 860. The insulating material can be any high-quality
insulating material known in the art, such as silicon nitride,
silicon dioxide, or silicon oxynitride. In the embodiment shown in
FIG. 8B, the insulating layer is silicon dioxide (or "oxide") which
is formed on the top surface of the epitaxial layer and in the
trench. Any suitable method known in the art--including oxidation
and deposition--yielding a high quality oxide layer can be used to
form this oxide layer. The portions of the oxide layer on the
surface of the epitaxial layer are then removed using conventional
methods (e.g., CMP or etch techniques), thus leaving the oxide
solely within the trench.
[0068] Using a mask (shown in FIG. 8B as the top layer), a trench
852 is then formed within and on the source-side of the
oxide-filled trench. In one embodiment, the trench 852 is formed in
the oxide by etching the oxide through the mask opening. Such
etching step would need to be selective to oxide over silicon to
prevent etching of the silicon along the left sidewall (source
side) if the mask opening overlaps the left edge of the trench due
to for example misalignment. A thermal oxide could then be formed
on the exposed silicon sidewall. A conductive material is deposited
to fill the trench and then recessed into the oxide trench to form
the "shield electrode" 870. This conductive material may, for
example, be from the same material as the gate conductor, such as a
metal, metal alloy, or polysilicon.
[0069] In FIG. 8C, conventional oxidation and etch steps are
carried out to refill the oxide trench 850. Using a mask (shown in
FIG. 8C as the top layer), the oxide above and to the left of the
shield electrode is partially removed so that a layer of oxide
remains over the shield electrode and the n- type LDD 830 along the
left sidewall (i.e., source-side) of the trench becomes exposed, as
shown. In an alternate embodiment, a selective deposition technique
is used to form the oxide layer over the shield electrode.
[0070] In FIG. 8D, a gate oxide layer 880 is formed along the
exposed silicon sidewall of the trench using conventional methods.
A suitable conductive material (e.g., polysilicon) is then
deposited and etched back to from the gate electrode. Using a mask,
implant and drive-in steps are performed to form the p- type body
region 890, as is known in the art. Using source/drain mask,
conventional implant and activation steps are performed to form the
n+ type source 892 and drain 894 regions. The final structure shown
in FIG. 7 is obtained upon forming dielectric and metal layers (not
shown), including the back metal, using conventional methods.
[0071] FIG. 9A shows a cross section view of a TG-LDMOS having two
control gates 910 and 920 in accordance with another embodiment of
the invention. A trench structure having dual-gates is disclosed in
the above-referenced patent application entitled "Improved MOS
Gating Method for Reduced Miller Capacitance and Switching Losses".
However, the dual-gate structure in the above-referenced
application is not implemented in a TG-LDMOS structure and is
different from the FIG. 9A structure in many respects.
[0072] In FIG. 9A, both control gates (Gate-1 910 and Gate-2 920)
overlap the channel region 930, and thus both control gates need to
be properly biased to turn on the MOSFET. The top gate (Gate-1) 910
modulates the current flow when the bottom gate (Gate-2) 920 is
biased appropriately. The bottom gate 920 can be continuously
biased or only biased prior to a switching event. FIG. 9B shows a
transistor symbol of the dual gate TG-LDMOS. The dual-gate
technique in FIG. 9A helps reduce the device gate-to-drain
capacitance (Cgd) to extremely low levels which in turn reduces
switching losses of any MOS-gated device. Thus, the switching
efficiency is improved allowing operation at higher frequencies.
The dual-gate structure is particularly suitable for use in such
applications as high voltage RF devices or other high frequency
switching MOSFETs. In RF MOSFET devices, the lower Cgd is highly
desirable because it increases RF gain and minimizes signal
distortion. Also, Gate-2 920 acts much like the shield element 710
in FIG. 7 to shield the dynamic Gate-1 910 although it is biased
differently than that in FIG. 7.
[0073] The process technology for forming the dual-gate TG-LDMOS in
FIG. 9A is compatible with conventional silicon MOSFET technology.
In one embodiment, process steps similar to those depicted in FIGS.
8A-8D with some modifications in connection with forming the lower
gate, which would be known to one skilled in the art, may be used.
An alternate set of process steps described below and illustrated
in FIGS. 10A-10D may also be used to make the dual-gate TG-LDMOS in
FIG. 9A.
[0074] Process steps depicted in FIGS. 10A-10D are similar to those
described above for TG-LDMOS structure in FIG. 7 except for
adjustments in the vertical positions and few other differences.
The particular sequence of steps described herein is not intended
to be limiting, and may be modified in ways known to one skilled in
this art for optimum results.
[0075] In FIG. 10A, p- type body region 1010, n- type LDD 1020, and
n+ type source 1030 and drain 1040 regions are formed using
conventional mask, implant, and drive-in steps. A first trench and
the portion of the LDD region wrapping around the trench are formed
in a manner similar to that in FIG. 8A.
[0076] In FIG. 10B, after filling the first trench with a
dielectric material (e.g., oxide) and etching back to the planar
surface, a second trench 1050 is formed in the silicon next to the
dielectric-filled trench. This new trench can be etched
conventionally into silicon and is provided with a thick oxide on
the bottom and gate oxide on the sidewall. This can be accomplished
using selective oxide deposition, or a LOCOS technique as disclosed
in U.S. Pat. Nos. 6,437,386, 6,368,920, and 6,444,528, relevant
portions of which are incorporated herein by reference. If the
depth of the trench does not extend much below the LDD or body
region, then an implant into the trench bottom would suffice to
bridge the drain LDD structure to the trench sidewall where the
channel will be formed. A threshold adjustment implant into the
left (source side) sidewall of the trench may be carried out using
an angled implant. This step might be necessary depending on the
trench bottom LDD process.
[0077] In FIG. 10C, a conformal polysilicon layer 1060 is deposited
lining the trench. A dielectric 1070 is deposited and planarized to
fill the polysilicon-lined trench. The polysilicon is etched back
to the plane surface. Using a mask (not shown), the polysilicon is
recessed by etching to reach the top of the polysilicon lining the
bottom of the trench. The original gate oxide can be removed and a
new oxide layer grown. The dielectric layer at the bottom of the
top gate (gate-1) will be relatively thin and this can be increased
with additional oxide depositions and planarization prior to gate-1
polysilicon.
[0078] In FIG. 10D, Gate-1 polysilicon 1080 is deposited and
planarized. The polysilicon for both gates can be recessed to
reduce capacitance. The remaining dielectric and metal layers,
including back metal, can be added by conventional means to achieve
the structure depicted in FIG. 9A.
[0079] FIGS. 11A and 11B show cross section views of two TG-LDMOS
structures wherein a charge-balancing technique is used to improve
the breakdown voltage in accordance with another embodiment of the
invention. As shown in FIG. 11A, a p- type region 1110 extends
laterally in the n- type LDD drift region 1120 between the trench
and the drain. The laterally extending p- type region 1110 may have
a fixed or graded doping concentration. The laterally-extending p-
type region results in a more uniform electric field in the LDD
drift region thus improving the device breakdown voltage.
[0080] In alternate embodiments, the charge balance structure 1110
can be configured in parallel stripes and can be either floating or
electrically connected to the drain terminal 1130. They can also be
positioned on the surface (the easiest embodiment to manufacture).
Alternatively, floating charge balance junctions can be arranged as
islands dispersed within the body of the LDD region. The charge
balance structures allow the LDD structure 1120 to have higher
doping concentration and thus lower resistance. These charge
balance techniques can be integrated with the source shield
structure 1140 as shown in FIG. 11B, with a dual gate structure, or
with other TG-LDMOS structures to improve the breakdown
voltage.
[0081] FIGS. 12A and 13A show cross section views of TG-LDMOS
structures having a source-substrate via 1210 and drain-substrate
via 1310, respectively, in accordance with other embodiments of the
invention. The two via structures are substantially similar except
that in the source-substrate via structure 1210, the back side 1220
is a source coupled to a p+ substrate 1230, and in the
drain-substrate via structure 1310, the back side 1320 is a drain
coupled to a n+ substrate 1330. The source-substrate via 1210 and
drain-substrate via 1310 are used to reduce the source and drain
resistance by replacing the relatively high resistance p+ sinker
used for connection to the substrate with a trench filled with
highly conductive material such as tungsten or in situ doped
polysilicon. They also allow the surface area consumed by the
substrate connection to be reduced.
[0082] Further, the source-to-substrate 1210 and drain-to-substrate
1310 connections allow monolithic integration of the TG-LDMOS with
other components such as additional DMOS for High Side/Low Side
monolithic integrated half bridge. They also can be used for chip
scale packaging (CSP) where it is desirable to bump a driver onto
the TG-LDMOS.
[0083] FIGS. 12B and 13B show alternate embodiments wherein the
connection to the substrate is further facilitated by a p+ layer
1240 formed around the source-substrate via 1210 and a n+ layer
1340 formed around the drain-substrate via 1310, respectively. The
highly doped p+ 1240 and n+ 1340 layers may be formed by implanting
dopants into the trench sidewall. In an alternate embodiment, an
oxide-lined polysilicon-filled trench is used for simplicity.
[0084] The source-substrate connection and drain-substrate
connection may be integrated with any TG-LDMOS structure. As an
example, FIGS. 12C and 13C show integration of these connections
with the source-shield structure of FIG. 7.
[0085] Typically, a connection to the source from a package pin is
made through a bond wire. But these bond wires add inductance that
may degrade performance. The source-to-substrate via 1210 allows a
connection to the source to be made through the back metal 1220,
thus reducing this inductance and source-series resistance.
[0086] These vias may be manufactured using one or more of several
techniques. For example, the vias may be etched chemically or
mechanically, by laser drilling, micromachining, or other
technique. The vias may then be filled or plated with a conductive
material, such as metal. The vias may be insulated or not,
depending on the exact configuration of substrate, epitaxial, and
other diffusions and implant material.
[0087] FIG. 14 is a cross section view illustrating how the
source-substrate via 1410 can be advantageously used to obtain a
smaller cell pitch. Similar advantage is obtained by the
drain-substrate connection. In FIG. 14, the source-substrate via
1410 is used only in the peripheral cell 1420 to provide the
source-to-substrate connection. Surface source interconnections
1430 are used to interconnect to source regions 1440 within the
central half-cells 1450. By using such structure, there is no need
to have a trench source connection (or lateral diffusion "sinker")
in each unit cell. Thus, the pitch of the cell can be substantially
reduced. It is to be understood, that although in FIG. 14 only two
central half-cells 1450 are shown between the peripheral cells
1420, in practice, many more central half-cells 1450 are
present.
[0088] Any two or more of the different structural features
illustrated in FIGS. 7, 9A, 11, 12A, and 13A may be combined
together depending on the desired device characteristics and design
goals. A number of different possibilities are shown in FIGS.
15-19. Some of these Figures also illustrate variations in
implementation of the basic concepts illustrated in one of more of
FIGS. 7, 9A, 11, 12A, and 13A. Many other variations and
combinations would be obvious to one of ordinary skill in this art
in view of this disclosure.
[0089] FIG. 15 shows one technique for interconnecting the
source-shield 1510 to the source terminal 1520. The source-shield
1510 is extended laterally along the bottom of the trench and then
vertically to an upper portion of the trench where it is
electrically connected to the source electrode 1520. FIG. 16 shows
the combination of the dual-gate structure depicted in FIG. 9A with
the source to substrate connection technique depicted in FIG.
12A.
[0090] FIG. 17 shows the dual-gate structure of FIG. 9A in
combination with the charge balance technique of FIG. 11. FIG. 18
shows a variation of the dual-gate structure wherein the lower gate
(Gate-2) 1820 does not extend vertically parallel to the upper gate
1810 (although connection to Gate-2 is provided in a third
dimension), in combination with the charge balance technique of
FIG. 11. By using charge-balancing techniques in combination with
the dual-gate or source-shield techniques, a significantly greater
breakdown voltage is achieved.
[0091] FIG. 19 shows the same variation of the dual-gate structure
depicted in FIG. 18 in combination with an n+ drain sinker 1910. In
another embodiment, the n+ drain sinker 1910 in FIG. 19 may be
replaced with the drain-substrate via 1310 shown in FIG. 13A. Note
that the dual-gate structure shown in FIGS. 12 and 13 are easier to
manufacture than the structure shown in FIG. 9A.
[0092] In the different embodiments described above, it is
important to obtain high quality uniform insulating layers in the
trench area. The insulator at the corners of a trench typically
thinner than other areas because of deposition difficulties (oxide
grows faster on a planar surface than on a curved surface), and
film stress at the silicon-oxide interface at the corners (concave
or convex) is greater. The combination of film stress and thinner
oxide lead to less resistance to high electric fields and thus
higher leakage current. Use of high-k dielectric can substantially
reduces the leakage current. A combination of thermally grown SiO2
and nitride may be used to overcome the leakage problem.
Alternatively, a thin high quality high-k dielectric may be used
either alone or in combination with, for example, an under-layer of
thermally grown oxide. Further, the high-k dielectric may be used
only for the gate insulator where thin oxide (e.g., <100 .ANG.)
is used for greater transconductance (gm).
[0093] The various improvements described herein enable maintaining
of the advantages of the LDMOS structure (e.g., better linearity),
while increasing the RF power gain and the device breakdown
voltage. The DC dynamic losses in a high voltage switching diode
translates into the device rise and fall times which in turn are
proportional to the Gate to Drain capacitance (Cgd or Qgd, i.e.,
the Miller capacitance). By greatly reducing Cgd, the rise and fall
times are greatly reduced and hence the dynamic losses are greatly
reduced. Thus, the dramatic reduction in parasitic capacitance
allows safer operation even at fast switching and achieves higher
efficiencies at low currents and higher voltages.
[0094] The above description of exemplary embodiments of the
invention has been presented for the purposes of illustration and
description. It is not intended to be exhaustive or to limit the
invention to the precise form described, and many modifications and
variations are possible in light of the teaching above. The
embodiments were chosen and described in order to best explain the
principles of the invention and its practical applications to
thereby enable others skilled in the art to best utilize the
invention in various embodiments and with various modifications as
are suited to the particular use contemplated.
* * * * *