U.S. patent application number 11/412268 was filed with the patent office on 2012-09-27 for systems, methods, and apparatus for real-time video encoding.
Invention is credited to Douglas Chin, Nader Mohsenian.
Application Number | 20120243613 11/412268 |
Document ID | / |
Family ID | 37419090 |
Filed Date | 2012-09-27 |
United States Patent
Application |
20120243613 |
Kind Code |
A9 |
Mohsenian; Nader ; et
al. |
September 27, 2012 |
Systems, methods, and apparatus for real-time video encoding
Abstract
Presented herein are systems, methods, and apparatus for
real-time high definition television encoding. In one embodiment,
there is presented a method for encoding video data. The method
comprises receiving an estimates of amounts of data for encoding
earlier pictures; providing target rates based on the estimates of
data for encoding the earlier pictures; receiving measures
indicative of the actual data for encoding the earlier pictures;
and providing at least one target rate for encoding at least one
later picture based on the target rates for encoding the earlier
pictures and the measures indicative of the actual data for
encoding the earlier pictures.
Inventors: |
Mohsenian; Nader; (San Jose,
CA) ; Chin; Douglas; (Windham, NH) |
Prior
Publication: |
|
Document Identifier |
Publication Date |
|
US 20060256869 A1 |
November 16, 2006 |
|
|
Family ID: |
37419090 |
Appl. No.: |
11/412268 |
Filed: |
April 27, 2006 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11043575 |
Jan 26, 2005 |
|
|
|
11412268 |
Apr 27, 2006 |
|
|
|
60681307 |
May 16, 2005 |
|
|
|
Current U.S.
Class: |
375/240.24 |
Current CPC
Class: |
H04N 19/172 20141101;
H04N 19/61 20141101; H04N 19/124 20141101; H04N 19/115 20141101;
H04N 19/149 20141101; H04N 19/152 20141101 |
Class at
Publication: |
375/240.24 |
International
Class: |
H04N 11/04 20060101
H04N011/04; H04B 1/66 20060101 H04B001/66; H04N 11/02 20060101
H04N011/02; H04N 7/12 20060101 H04N007/12 |
Claims
1. A method for encoding video data, said method comprising:
receiving at least one estimated amount of data for encoding at
least one earlier portion; providing at least one target rate based
on the at least one estimated amount of data for encoding the at
least one earlier portion; receiving at least one measure
indicative of the actual data for encoding the at least one earlier
portion; and providing at least one target rate for encoding at
least one later portion based on the at least one target rate for
encoding the at least one earlier portion and the at least one
measure indicative of the actual data for encoding the at least one
earlier portion.
2. The method of claim 1, wherein receiving the at least one
measure further comprises: receiving a count of BINs for encoding
the at least one earlier portion.
3. The method of claim 2, further comprising: estimating an amount
of bits from the count of BINS.
4. The method of claim 3, further comprising: receiving a count of
bits for encoding the at least one earlier portion; comparing the
count of bits for encoding the at least one earlier portion to the
estimated amount of bits from the count of BINS for the at least
one earlier portion.
5. The method of claim 4, further comprising: receiving a count of
BINs for encoding the at least one later portion; and estimating an
amount of bits from the count of BINs for encoding the at least one
later portion, based on the comparison of the count of bits for
encoding the at least one earlier portions to the estimated amount
of bits from the count of BINs for the at least one earlier
portion.
6. The method of claim 1, wherein the at least one earlier portion
comprises a macroblock.
7. The method of claim 1, wherein the later portion comprises a
macroblock.
8. A master server for encoding video data, said master server
comprising: at least one port for receiving estimates of amounts of
data for encoding earlier portions, providing target rates for the
earlier portions, receiving indications of the actual data for
encoding the earlier portions, and providing at least one target
rate for encoding at least one later portion based on the target
rates for encoding the earlier portions and the indications of the
actual data for encoding the earlier portions.
9. The master server of claim 8, wherein receiving indications of
the actual data for encoding the earlier portions further
comprises: receiving a count of BINs for encoding the earlier
portions.
10. The master server of claim 9, further comprising: a first
memory for storing a first plurality of instructions for estimating
an amount of bits from the count of BINs.
11. The master server of claim 10, wherein the at least one port
receives a count of bits for encoding the earlier pictures and
wherein execution of the plurality of instructions causes comparing
the count of bits for encoding the earlier pictures to the
estimated amount of bits from the count of BINs for the earlier
portions.
12. The master server of claim 11, wherein the at least one port
receives a count of BINs for encoding the at least one later
portion; and wherein execution of the plurality of instructions
causes estimating an amount of bits from the count of BINs for
encoding the at least one later portion, based on the comparison of
the count of bits for encoding the earlier portions to the
estimated amount of bits from the count of BINs for the earlier
portions.
13. The master server of claim 12, further comprising: a second
memory for storing the estimated rates and the target rates.
14. The master server of claim 8, wherein the earlier portions
comprise macroblocks.
15. The master server of claim 8, wherein the at least one later
portion comprises at least one macroblock.
Description
BACKGROUND OF THE INVENTION
[0001] Advanced Video Coding (AVC) (also referred to as H.264 and
MPEG-4, Part 10) can be used to compress video content for
transmission and storage, thereby saving bandwidth and memory.
However, encoding in accordance with AVC can be computationally
intense.
[0002] In certain applications, for example, live broadcasts, it is
desirable to compress high definition television content in
accordance with AVC in real time. However, the computationally
intense nature of AVC operations in real time may exhaust the
processing capabilities of certain processors. Parallel processing
may be used to achieve real time AVC encoding, where the AVC
operations are divided and distributed to multiple instances of
hardware which perform the distributed AVC operations,
simultaneously.
[0003] Ideally, the throughput can be multiplied by the number of
instances of the hardware. However, in cases where a first
operation is dependent on the results of a second operation, the
first operation may not be executable simultaneously with the
second operation. In contrast, the performance of the first
operation may have to wait for completion of the second
operation.
[0004] AVC uses temporal coding to compress video data. Temporal
coding divides a picture into blocks and encodes the blocks using
similar blocks from other pictures, known as reference pictures. To
achieve the foregoing, the encoder searches the reference picture
for a similar block. This is known as motion estimation. At the
decoder, the block is reconstructed from the reference picture.
However, the decoder uses a reconstructed reference picture. The
reconstructed reference picture is different, albeit imperceptibly,
from the original reference picture. Therefore, the encoder uses
encoded and reconstructed reference pictures for motion
estimation.
[0005] Using encoded and reconstructed reference pictures for
motion estimation causes encoding of a picture to be dependent on
the encoding of the reference pictures. This can be disadvantageous
for parallel processing.
[0006] Additional limitations and disadvantages of conventional and
traditional approaches will become apparent to one of ordinary
skill in the art through comparison of such systems with the
present invention as set forth in the remainder of the present
application with reference to the drawings.
BRIEF SUMMARY OF THE INVENTION
[0007] Presented herein are systems, methods, and apparatus for
encoding video data in real time, substantially as shown in and/or
described in connection with at least one of the figures, as set
forth more completely in the claims.
[0008] These and other advantages and novel features of the present
invention, as well as illustrated embodiments thereof will be more
fully understood from the following description and drawings.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
[0009] FIG. 1 is a block diagram of an exemplary master system for
encoding video data in accordance with an embodiment of the present
invention;
[0010] FIG. 2 is a flow diagram for encoding video data in
accordance with an embodiment of the present invention;
[0011] FIG. 3 is a block diagram of a system for encoding video
data in parallel, in accordance with an embodiment of the present
invention;
[0012] FIG. 4 is a block diagram describing a rate controller
system in accordance with an embodiment of the present
invention;
[0013] FIG. 5 is a flow diagram for encoding video data in
accordance with another embodiment of the present invention;
and
[0014] FIG. 6 is a block diagram describing an exemplary computer
system configured in accordance with an embodiment of the present
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0015] Referring now to FIG. 1, there is illustrated a block
diagram of an exemplary master system 105 for encoding video data
in accordance with an embodiment of the present invention. The
master system 105 includes at least one port 107.
[0016] The video data include a picture 108. The picture 108
comprises earlier portions 11E, and later portions 110L. The
earlier portions 110E are encoded earlier than the later portions
110L. The at least one port 110 receives an estimated amount of
data for encoding the earlier portions 110E. The estimated amount
of data can be an estimate of the amount of data for encoding the
earlier portions 110E, based on certain parameters, such as lossy
compression parameters. The lossy compression parameters can
include, for example, the quantization step size.
[0017] The amount of data for encoding the earlier portions 110E
can be estimated in a variety of ways. According to certain
embodiments of the invention, the amount of data for encoding the
picture can be estimated in the manner described in "Systems,
Methods, and Apparatus for Real-Time High Definition Encoding",
U.S. application patent Ser. No. ______, (attorney docket number
16285US01, filed ______, by ______, which is incorporated herein by
reference for all purposes. Alternatively, the amount of data for
encoding the picture can be estimated in the manner described in
"Open Loop Spatial Estimation", U.S. application patent Ser. No.
______, (attorney docket number 16283US01), filed ______, by
______, which is incorporated herein by reference for all
purposes.
[0018] The estimates of the amount of data for encoding the earlier
portions 110E can come from a variety of sources. For example, in
certain embodiments of the present invention, the estimates can
come from an encoder, or plurality of encoders. The plurality of
encoders can operate in parallel. Alternatively, the master 105,
itself, can provide the estimate of the amount of data for encoding
the earlier pictures.
[0019] The master 105, via the at least one port 107 provides
target rates for the earlier portions 110E. The target rates can be
an amounts of data budgeted for encoding the earlier portions 110E.
The earlier portions 110E can then be encoded in a variety of
ways.
[0020] The earlier portions 110E and later portions 110L can be
portions of the same picture or different pictures, wherein the
earlier portion 110E is a portion of an earlier encoded picture and
wherein the later portion 110L is a portion of a later encoded
picture.
[0021] Certain encoding standards such as Advanced Video Coding
(AVC), VC-1, and MPEG-2 use a combination of lossy and lossless
compression for encoding video data. In lossless compression,
information from the video data is not lost from the compression.
However, in lossy compression, some information from the video data
is lost to improve compression. An example of lossy compression is
the quantization of transform coefficients.
[0022] Lossy compression involves trade-off between quality and
compression. Generally, the more information that is lost during
lossy compression, the better the compression rate, but, the more
the likelihood that the information loss perceptually changes the
video data 102 and reduces quality. One example of lossy
compression is the quantization of transform coefficients.
[0023] In certain embodiments of the present invention, the target
rates can be used for controlling the lossy compression of the
earlier portions 110E. For example, the lossy compression can be
controlled by controlling a quantization step size used for
quantizing transform coefficients.
[0024] The at least one port 107 receives an indicator indicating
the actual amount of data used to encode the earlier portions 110E.
The indicator indicating the actual amount of data for encoding the
picture can comprise, for example, an actual bit count of the data
encoding the picture, or a measure of the data encoding the picture
after certain intermediate stages of the encoding. In certain
embodiments of the present invention, the indicator indicating the
amount of data can be an estimate of the amount of data for
encoding the picture based on a measure of the data encoding the
picture after certain intermediate stages of the encoding.
[0025] The indicator indicating the actual amount of data used to
encode the earlier portions 110E can be compared to the target rate
provided for encoding the earlier portions 110E. Where the
indicator indicates that the actual amount of data for encoding the
picture is different from the target rate beyond a certain
threshold, the target rates for later portions 110L, as a function
of the estimated amount of data for encoding the later pictures
110L can be adjusted.
[0026] Accordingly, the at least one port 107 provides at least one
target rate for encoding at least one later portion 110L that is
based on the target rates for encoding the earlier pictures and the
measures indicative of the actual data for encoding the earlier
pictures.
[0027] Referring now to FIG. 2, there is illustrated a flow diagram
for encoding video data in accordance with an embodiment of the
present invention. At 205, estimates of amounts of data for
encoding earlier portions are received. At 210 target rates based
on the estimates of data for encoding the earlier portions are
provided. At 215, measures indicative of the actual data for
encoding the earlier portions are received. At 220, at least one
target rate for encoding at least one later portion based on the
target rates for encoding the earlier portion and the measures
indicative of the actual data for encoding the earlier portion, is
provided.
[0028] Advanced Video Coding (AVC) (also referred to as H.264 and
MPEG-4, Part 10) can be used to compress video content for
transmission and storage, thereby saving bandwidth and memory.
However, encoding in accordance with AVC can be computationally
intense.
[0029] In certain applications, for example, live broadcasts, it is
desirable to compress high definition television content in
accordance with AVC in real time. However, the computationally
intense nature of AVC operations in real time may exhaust the
processing capabilities of certain processors. Parallel processing
may be used to achieve real time AVC encoding, where the AVC
operations are divided and distributed to multiple instances of
hardware that perform the distributed AVC operations,
simultaneously.
[0030] Referring now to FIG. 3, there is illustrated a block
diagram of an exemplary system 300 for encoding video data in
parallel, in accordance with an embodiment of the present
invention. The system 300 comprises a picture rate controller 305,
a macroblock rate controller 310, a pre-encoder 315, hardware
accelerator 320, spatial from original comparator 325, an activity
metric calculator 330, a motion estimator 335, a mode decision and
transform engine 340, an arithmetic encoder 350, and a CABAC
encoder 355.
[0031] The picture rate controller 305 can comprise software or
firmware residing on the master 105. The macroblock rate controller
310, pre-encoder 315, spatial from original comparator 325, mode
decision and transform engine 340, spatial predictor 345,
arithmetic encoder 350, and CABAC encoder 355 can comprise software
or firmware residing on any number of encoders 302. The pre-encoder
315 includes a complexity engine 360 and a classification engine
365. The hardware accelerator 320 can either be a central resource
accessible by each of the encoders 302, or decentralized hardware
at the encoders 302.
[0032] The hardware accelerator 320 searches original reference
pictures for blocks that are similar to blocks in the earlier
portion 110E. The hardware accelerator 320 can comprise and/or
operate substantially like the hardware accelerator described in
"Systems, Methods, and Apparatus for Real-Time High Definition
Encoding", U.S. application patent Ser. No. ______, (attorney
docket number 16285US01, filed ______, by ______, which is
incorporated herein by reference for all purposes.
[0033] The spatial from original comparator 325 examines the
quality of the spatial prediction of blocks in the earlier pictures
110E, using the original earlier pictures 110E. The spatial from
original comparator 325 can comprise and/or operate substantially
like the spatial from original comparator 325 described in "System
and Method for Open Loop Spatial Prediction in A Video Encoder",
U.S. application patent Ser. No. ______, (attorney docket number
16283US01), filed ______, by ______, which is incorporated herein
by reference for all purposes.
[0034] The pre-encoder 315 comprises a complexity engine 360 that
estimates the amount of data of data for encoding the earlier
pictures 11E, based on the results of the hardware accelerator 320
and the spatial from original comparator 325. The pre-encoder 315
also comprises a classification engine 365. The classification
engine 365 classifies certain content from the earlier pictures
110E that is perceptually sensitive, such as human faces, where
additional data for encoding is desirable.
[0035] Where the classification engine 365 classifies certain
content from the earlier pictures 110E to be perceptually
sensitive, the classification engine 365 indicates the foregoing to
the complexity engine 360. The complexity engine 360 can adjust the
estimate of data for encoding the earlier pictures 110E. The
complexity engine 365 provides the estimate of the amount of data
for encoding the pictures by providing an amount of data for
encoding the picture with a nominal quantization parameter Qp. It
is noted that the nominal quantization parameter Qp is not
necessarily the quantization parameter used for encoding the
earlier pictures 110E.
[0036] The picture rate controller 305 provides target rates for
the earlier pictures to the macroblock rate controller 310. The
motion estimator 335 performs the motion estimation while the
spatial predictor 345 performs the spatial predictions. The mode
decision & transform engine 340 determines whether to use
spatial encoding or temporal encoding, and calculates, transforms,
and quantizes the prediction error E from the reference block.
[0037] The complexity engine 360 indicates the complexity of each
macroblock 320 at the macroblock level based on the results from
the hardware accelerator 320, while the classification engine 365
indicates whether a particular macroblock contains sensitive
content. Based on the foregoing, the complexity engine 360 provides
an estimate of the amount of bits that would be required to encode
the macroblock 320. The macroblock rate controller 310 determines a
quantization parameter and provides the quantization parameter to
the mode decision & transform engine 340. The mode decision
& transform engine 340 comprises a quantizer Q. The quantizer Q
uses the foregoing quantization parameter to quantize the
transformed prediction error.
[0038] The mode decision & transform engine 340 provides the
transformed and quantized prediction error E to the arithmetic
encoder 350. The arithmetic encoder 350 codes the quantized
prediction error into BINS. The BINS measure can be measures that
are indicative of the actual amounts of data for encoding the
earlier pictures. Accordingly, the picture rate controller 305
receives the number of BINS that encoded the earlier pictures
110E.
[0039] In certain embodiments of the present invention, the
macroblock rate controller 310 can estimate an amount of bits for
encoding the earlier macroblocks 110E of pictures, such as
macroblocks. Additionally, the macroblock rate controller 310 can
maintain statistics from earlier macroblocks 110E, such as the
target rate given and the estimated bits for encoding the earlier
macroblocks 110E, the target rates for encoding the earlier
macroblocks 110E, and the estimated amount of bits for encoding the
earlier macroblocks 110E from the count of BINs.
[0040] The picture rate controller 305 can use the foregoing as
feedback. For example, if the target rate is exceeded beyond a
certain threshold for earlier pictures that are a certain type of
pictures, such as B-pictures, P-pictures, or I-pictures, in a
particular group of pictures, the picture rate controller 305 can
bias the target rate lower for later pictures that are the certain
type in the particular group of pictures. Similarly, if the target
rate exceeds the estimate bits for encoding the earlier pictures
that are a certain type from the BINs count, the picture rate
controller 305 can bias the target rate higher for later pictures
that are the certain type.
[0041] The CABAC encoder 355 converts the bins to CABAC encoded
data. In certain embodiments of the present invention, the picture
rate controller 305 can also receive the count of bits for encoding
the earlier pictures 110E. The counts of bits can be used to adjust
the estimate of the bits from the BINs count. For example, the
picture rate controller 305 can store the estimated amount of bits
from the BINs count for comparison to the actual bit count for
encoding the earlier pictures 110E. Where the actual bit count for
encoding the earlier pictures 110E is outside the estimated amount
of bits from the BINs count, the estimate of bits from the BINs
count of later pictures can be adjusted. Thus in certain
embodiments of the present invention, the estimate of bits for
encoding later pictures 110L can be also be based on the comparison
of the count of bits for encoding the earlier pictures to the
estimated amount of bits from the count of BINs for the earlier
pictures.
[0042] Referring now to FIG. 4, there is illustrated a block
diagram of the macroblock rate controller 310. The macroblock rate
controller 310 comprises a target rate generator 405, a target rate
bias 410, and BINs to bits estimator 415, memory 420, and a port
425.
[0043] The target rate generator 405 receives estimates of amounts
of data for encoding earlier macroblocks 110E, and provides target
rates based on the estimates of data for encoding the earlier
macroblocks 110E. The memory 420 stores the estimates of the
amounts of data for encoding the earlier macroblocks 110E, and the
target rate given by the target rate generator 405.
[0044] The BINs to bits estimator 415 receives the count of BINs
for encoding the earlier macroblocks 110E from the arithmetic
encoder 350 via port 425, and estimates an amount of bits from the
count of BINS of the actual data for encoding the earlier
macroblocks 110E. The memory 420 stores the BINs count and the
estimated amount of bits from the count of BINs.
[0045] The BINs to bits estimator 415 provides the estimate of bits
from the BINs count to the target rate generator 405. The target
rate generator 405 compares the estimated bits from the BINs count
to the target rate. If the estimated bits from the BINs count is
beyond a predetermined margin of error from the target rate, the
target rate generator 405 appropriately biases the target rate for
later macroblocks 110L. Accordingly, the target rate generator 405
provides target rates via port 425 for encoding later macroblocks
110L that are also based on the target rates for encoding the
earlier macroblocks 110E, and the estimated amount of data for
encoding the earlier macroblocks 110E based on the BINs count.
[0046] The BINs to bits estimator 415 receives the actual bit count
from the CABAC encoder 355 via port 425. The BINs to bits estimator
415 compares the actual bit count for encoding the earlier pictures
110E from the CABAC encoder 355 to the estimated bit count from the
BINs count for the earlier macroblocks 110E. If the actual bit
count for encoding the earlier macroblocks 110E varies from the
CABAC encoder 355 varies from the estimated bit count from the BINs
count for the earlier macroblocks 110E beyond a predetermined
margin of error, the bit rate estimator 415 appropriately biases
the estimated amount of bits from the count of BINs for the later
macroblocks 110L.
[0047] Thus, when the BINs to bits estimator 415 receives a count
of BINs for encoding later macroblocks 110L, via port 425, the BINs
to bits estimator 415 estimates an amount of bits from the count of
BINS for encoding the later macroblocks 110L, based on the
comparison of the count of bits for encoding the earlier
macroblocks 110E to the estimated amount of bits from the count of
BINs for the earlier macroblocks 110E.
[0048] The biasing at the target rate generator 405 and the BINs to
bits estimator 415 can be selective for certain types of pictures,
such as for I-pictures, P-pictures, or B-pictures in a particular
group of pictures.
[0049] Referring now to FIG. 5, there is illustrated a flow diagram
for controlling the rate of video data encoding. At 505, the target
rate generator 405 receives estimates of amounts of data for
encoding earlier macroblocks 110E, and provides (at 510) target
rates based on the estimates of data for encoding the earlier
macroblocks 110E. The memory 420 stores (at 515) the estimates of
the amounts of data for encoding the earlier macroblocks 110E, and
the target rate given by the target rate generator 405.
[0050] The BINs to bits estimator 415 receives the count of BINs
for encoding the earlier macroblocks 110E from the arithmetic
encoder 350 via port 425 at 520, and estimates (at 530) an amount
of bits from the count of BINS of the actual data for encoding the
earlier macroblocks 110E. At 535, the memory 420 stores the BINs
count and the estimated amount of bits from the count of BINs.
[0051] The BINs to bits estimator 415 provides (at 535) the
estimate of bits from the BINs count to the target rate generator
405. The target rate generator 405 compares (at 540) the estimated
bits from the BINs count to the target rate. If at 545, the
estimated bits from the BINs count is beyond a predetermined margin
of error from the target rate, the target rate generator 405
appropriately biases (at 550) the target rate for later macroblocks
110L. If at 545, the estimated bits form the BINs count is beyond
the predetermined margin of error, 550 is bypassed. At 555, the
target rate generator 405 provides target rates via port 425 for
encoding later macroblocks 110L that are also based on the target
rates for encoding the earlier macroblocks 110E, and the estimated
amount of data for encoding the earlier macroblocks 110E based on
the BINs count.
[0052] At 560, the BINs to bits estimator 415 receives the actual
bit count from the CABAC encoder 355 via port 425. The BINs to bits
estimator 415 compares (at 565) the actual bit count for encoding
the earlier macroblocks 110E from the CABAC encoder 355 to the
estimated bit count from the BINs count for the earlier macroblocks
110E. If at 570, the actual bit count for encoding the earlier
macroblocks 110E varies from the CABAC encoder 355 varies from the
estimated bit count from the BINs count for the earlier macroblocks
110E beyond a predetermined margin of error, the bit rate estimator
415 appropriately biases (at 575) the estimated amount of bits from
the count of BINs for the later macroblocks 110L.
[0053] At 580, the BINs to bits estimator 415 receives a count of
BINS for encoding later macroblocks 110L, via port 425, the BINs to
bits estimator 415, and estimates (at 585) an amount of bits from
the count of BINS for encoding the later macroblocks 110L, based on
the comparison of the count of bits for encoding the earlier
macroblocks 110E to the estimated amount of bits from the count of
BINS for the earlier macroblocks 110E.
[0054] Referring now to FIG. 6, there is illustrated a block
diagram of an exemplary computer system configured in accordance
with an embodiment of the present invention. A CPU 60 is
interconnected via system bus 62 to random access memory (RAM) 64,
read only memory (ROM) 66, an input/output (I/O) adapter 68, a user
interface adapter 72, a communications adapter 84, and a display
adapter 86. The input/output (I/O) adapter 68 connects peripheral
devices such as hard disc drives 40, floppy disc drives 41 for
reading removable floppy discs 42, and optical disc drives 43 for
reading removable optical disc 44 (such as a compact disc or a
digital versatile disc) to the bus 62. The user interface adapter
72 connects devices such as a keyboard 74, a mouse 76 having a
plurality of buttons 67, a speaker 78, a microphone 82, and/or
other user interfaces devices such as a touch screen device (not
shown) to the bus 62. The communications adapter 84 connects the
computer system to a data processing network 92. The display
adapter 86 connects a monitor 88 to the bus 62.
[0055] An embodiment of the present invention can be implemented as
sets of instructions resident in the random access memory 64 of one
or more computer systems configured generally as described in FIG.
6. For example, the flow chart of FIGS. 2 and 5 can be implemented
as sets of instructions in a computer system. Additionally, the
systems described in FIG. 4 can also be implemented as sets of
instructions in a computer system. Until required by the computer
system 58, the set of instructions may be stored in another
computer readable memory, for example in a hard disc drive 40, or
in removable memory such as an optical disc 44 for eventual use in
an optical disc drive 43, or a floppy disc 42 for eventual use in a
floppy disc drive 41. The physical storage of the sets of
instructions physically changes the medium upon which it is stored
electrically, magnetically, or chemically so that the medium
carries computer readable information.
[0056] The embodiments described herein may also be implemented as
a board level product, as a single chip, an application specific
integrated circuit (ASIC), or with varying levels of the decoder
system integrated with other portions of the system as separate
components.
[0057] The degree of integration of the decoder system may
primarily be determined by the speed and cost considerations.
Because of the sophisticated nature of modern processor, it is
possible to utilize a commercially available processor, which may
be implemented external to an ASIC implementation.
[0058] If the processor is available as an ASIC core or logic
block, then the commercially available processor can be implemented
as part of an ASIC device wherein certain functions can be
implemented in firmware. Alternatively, the foregoing can be
implemented as hardware accelerator units controlled by the
processor.
[0059] While the present invention has been described with
reference to certain embodiments, it will be understood by those
skilled in the art that various changes may be made and equivalents
may be substituted without departing from the scope of the present
invention.
[0060] Additionally, many modifications may be made to adapt a
particular situation or material to the teachings of the present
invention without departing from its scope. For example, although
the invention has been described with a particular emphasis on the
AVC encoding standard, the invention can be applied to a video data
encoded with a wide variety of standards.
[0061] Therefore, it is intended that the present invention not be
limited to the particular embodiment disclosed, but that the
present invention will include all embodiments falling within the
scope of the appended claims.
* * * * *