U.S. patent application number 13/486940 was filed with the patent office on 2012-09-27 for semiconductor integrated circuit.
This patent application is currently assigned to Renesas Electronics Corporation. Invention is credited to Mototsugu OKUSHIMA.
Application Number | 20120243134 13/486940 |
Document ID | / |
Family ID | 40623477 |
Filed Date | 2012-09-27 |
United States Patent
Application |
20120243134 |
Kind Code |
A1 |
OKUSHIMA; Mototsugu |
September 27, 2012 |
SEMICONDUCTOR INTEGRATED CIRCUIT
Abstract
A semiconductor integrated circuit including an output pad from
which an output signal is outputted, an output signal line
connected with said output pad, a first pad configured to function
as a ground terminal or a power supply terminal, a first wiring
connected with said first pad, an output driver connected with said
output pad and configured to generate said output signal, an ESD
protection device connected with a output signal line and having a
function to discharge surge applied to said output pad, a first
trigger MOS transistor used as a trigger device, a first protection
target device connected between said output signal line and a first
interconnection, a first resistance element connected between a
gate and a source of said first trigger MOS transistor, and a
switching device.
Inventors: |
OKUSHIMA; Mototsugu;
(Kanagawa, JP) |
Assignee: |
Renesas Electronics
Corporation
Kawasaki-shi
JP
|
Family ID: |
40623477 |
Appl. No.: |
13/486940 |
Filed: |
June 1, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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12289904 |
Nov 6, 2008 |
8194369 |
|
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13486940 |
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Current U.S.
Class: |
361/56 |
Current CPC
Class: |
H01L 27/0262
20130101 |
Class at
Publication: |
361/56 |
International
Class: |
H02H 9/04 20060101
H02H009/04 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 12, 2007 |
JP |
2007-293233 |
Claims
1. A semiconductor integrated circuit comprising: an output pad
from which an output signal is outputted; an output signal line
connected with said output pad; a first pad configured to function
as a ground terminal or a power supply terminal; a first wiring
connected with said first pad; an output driver connected with said
output pad and configured to generate said output signal; an ESD
(electrostatic discharge) protection device connected with an
output signal line and having a function to discharge surge applied
to said output pad; a first trigger MOS (metal-oxide semiconductor)
transistor used as a trigger device; a first protection target
device connected between said output signal line and a first
interconnection; a first resistance element connected between a
gate and a source of said first trigger MOS transistor; and a
switching device, wherein a current flowing through said first
protection target device is detected by use of said first
resistance element, wherein said ESD protection device comprises a
bipolar transistor, wherein said first pad comprises a VSS (voltage
source-source, source or substrate supply voltage of a negative or
ground potential) pad configured to function as a ground terminal,
wherein said first interconnection comprises a ground
interconnection, and wherein said first trigger MOS transistor is
connected between said ground interconnection and a base of said
bipolar transistor, and is turned on or off in response to a
voltage generated in said first resistance element.
2. The semiconductor integrated circuit according to claim 1,
wherein said first trigger MOS transistor comprises an NMOS (n
channel MOS) transistor, and wherein said first trigger MOS
transistor is connected between an N gate and said ground line of a
thyristor.
3. The semiconductor integrated circuit according to claim 2,
wherein said first protection target device comprises a protection
target NMOS transistor including a drain connected with said output
signal line and a source connected with said first resistance
element, and wherein said first trigger MOS transistor has the
drain connected with the N gate of said thyristor, a gate connected
with a connection node between said first resistance element and
the source of said protection target NMOS transistor, and a source
connected to the ground line.
4. The semiconductor integrated circuit according to claim 1,
wherein said bipolar transistor comprises a parasitic bipolar
transistor which is parasitic to said MOS transistor.
5. The semiconductor integrated circuit according to claim 4,
wherein said output driver comprises said MOS transistor.
6. A semiconductor integrated circuit comprising: an output pad
from which an output signal is outputted; an output signal line
connected with said output pad; a first pad configured to function
as a ground terminal or a power supply terminal; a first wiring
connected with said first pad; an output driver connected with said
output pad and configured to generate said output signal; an ESD
(electrostatic discharge) protection device connected with said
output signal line and having a function to discharge surge applied
to said output pad; a first trigger MOS (metal-oxide semiconductor)
transistor used as a trigger device; a first protection target
device connected between said output signal line and a first
interconnection; and a first resistance element connected between a
gate and a source of said first trigger MOS transistor, wherein a
current flowing through said first protection target device is
detected by use of said first resistance element, wherein said ESD
protection device comprises a thyristor, wherein said first pad
comprises a VSS (voltage source-source, source or substrate supply
voltage of a negative or ground potential) pad configured to
function as a ground terminal, wherein said first interconnection
comprises a ground interconnection, and wherein said first trigger
MOS transistor is connected between a P gate and said ground
interconnection of said thyristor, and is turned on or off in
response to the voltage generated in said first resistance element.
Description
[0001] The present Application is a Continuation Application of
U.S. patent application Ser. No. 12/289,904 which was filed on Nov.
6, 2008, which claims a priority on convention based on Japanese
Patent Application No. 2007-293233 which was filed on Nov. 12,
2007. The Disclosures thereof are incorporated herein by
reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor integrated
circuit, and more particularly, to a semiconductor integrated
circuit provided with an ESD (electrostatic discharge) protection
device for preventing breakdown of an internal circuit due to
application of an ESD surge.
[0004] 2. Description of Related Art
[0005] A semiconductor integrated circuit is generally provided
with an ESD protection device for protecting an internal circuit
from ESD surge applied to an input/output pad. The ESD protection
device discharges the ESD surge applied to the input/output pad to
a power supply line or a ground line, thereby protecting the
internal circuit.
[0006] A thyristor is a typical ESD protection device. Since the
thyristor has high discharge capacity and can reduce a parasitic
capacitance, it is used as the ESD protection device for high-speed
interface. The semiconductor integrated circuit including the
thyristor as the ESD protection device is disclosed in "A
PNP-Triggered SCR with Improved Trigger Techniques for High-Speed
I/O ESD Protection in Deep Sub-Micron CMOS LSIs" by Y. Morishita
(EOS/ESD Symposium 2005). This document discloses an ESD protection
circuit which uses an NMOS transistor having a gate connected to a
gate bias circuit, as a trigger device of the thyristor. In
addition, U.S. Pat. No. 7,233,467 discloses protection of an input
circuit connected to an input pad. In detail, U.S. Pat. No.
7,233,467 discloses circuit topology in which a resistance element
is connected between a source of the NMOS transistor of an input
buffer and the ground line. In the semiconductor integrated circuit
in this publication, by passing a current to the resistance element
through the thyristor when the
[0007] ESD surge is applied, the voltage of the source of the NMOS
transistor in the input buffer is increased, thereby protecting the
NMOS transistor against the ESD surge.
[0008] FIG. 1 is a circuit diagram showing an example of
configuration of a semiconductor integrated circuit 100 using the
thyristor as the ESD protection device. The semiconductor
integrated circuit 100 has a VDD pad 111 connected to a power
supply line 101, an output pad 112 connected to an output signal
line 102 and a VSS pad 113 connected to a ground line 103. A last
stage output driver 116 of an internal circuit 115 is connected to
the output pad 112. The last stage output driver 116 is formed of a
PMOS transistor P1 and an NMOS transistor N1. The internal circuit
115 further has a previous stage pre-driver 117 for driving a gate
of the NMOS transistor N1. The previous stage pre-driver 117 is
formed of a PMOS transistor P2 and an NMOS transistor N2.
[0009] A thyristor 114 is connected between the output pad 112 and
the VSS pad 113 to function as the ESD protection device. When the
ESD surge is applied to the output pad 112, the thyristor 114
discharges the ESD surge to the ground line 103 to protect the last
stage output driver 116. Although the semiconductor integrated
circuit shown in FIG. 1 is not provided with a trigger device, in
many cases, the trigger device is connected to the thyristor used
as the ESD protection device and the thyristor is triggered by the
trigger device.
[0010] A problem caused by using the thyristor as the ESD
protection device is difficulty in properly triggering the
thyristor, in particular, in triggering the thyristor with a low
voltage. This problem is serious, especially, if a gate of the NMOS
transistor N1 of the last stage output driver 116 is in the
floating state when the ESD surge is applied to the output pad 112.
When the NMOS transistor N2 of the previous stage pre-driver 117 is
in the off state, the gate of the NMOS transistor N1 is set to the
floating state and current flows through the NMOS transistor N1.
When excessive current flows through the NMOS transistor N1 before
the thyristor 114 operates, the NMOS transistor N1 is subjected to
breakdown.
[0011] A method for solving such a problem is that a surge current
flowing through a device to be protected (hereinafter referred to
as a "protection target device") is detected and the thyristor is
operated in response to the detected surge current. By detecting
the surge current flowing through the protection target device, and
triggering and operating the thyristor according to the surge
current before the protection target device is subjected to
breakdown, the protection target device can be surely protected.
Such a method is disclosed in Current detection trigger scheme for
SCR based ESD protection of Output drivers in CMOS technologies
avoiding competitive triggering by Benjamin Van Camp, et al.
(EOS/ESD Symposium, 2005) and U.S. Patent Application Publication
(2005/0286188).
[0012] FIG. 2 is a circuit diagram showing a configuration of a
semiconductor integrated circuit configured to detect the current
flowing through the protection target device and to trigger the
thyristor. The semiconductor integrated circuit 200 has a thyristor
114, an output driver 116, a current detecting resistance element
118, diodes 119 and 120, an ESD clamp circuit 121, a power supply
clamp circuit 122 and a diode 123. The semiconductor integrated
circuit 200 shown in FIG. 2 is configured so that a current
I.sub.NMOS flowing through the NMOS transistor N1 of the output
driver 116 is detected by the current detecting resistance element
118 and the thyristor 114 is triggered in response to the detected
current I.sub.NMOS.
[0013] A problem of the semiconductor integrated circuit in FIG. 2
is that since an N gate Gn of the thyristor 114 is electrically
connected to the output pad 112, an output capacitance of the
output pad 112 increases. A configuration of the thyristor 114
contributes to the increase in the output capacitance. FIG. 3 is a
sectional view showing the configuration of the thyristor 114. An N
well 132 and a P well 133 are formed in a P-type substrate 131 to
be adjacent to each other. An N.sup.+ region 134 which function as
the N gate Gn and a P.sup.+ region 135 connected to the output pad
112 are formed in the N well 132. Here, the "N.sup.+ region" refers
to a region in which high-concentration n-type impurities are
doped. The "P+ region" refers to a region in which
high-concentration P-type impurities are doped. An N.sup.+ region
136 connected to the ground line 103 and the P.sup.+ region 137
which functions as a P gate Gp are formed in the P well 133. A P
well 138 is formed in the P-type substrate 131, and a P.sup.+
region 139 connected to the ground line 103 is formed in the P well
138. In FIG. 3, a capacitance of the PN junction between the N well
132 and the P.sup.+ region 135 is shown as C1 and the capacitance
of the PN junction between the N well 132 and the P well 133 is
shown as C2.
[0014] As shown in FIGS. 4A and 4B, when the N gate Gn is connected
to the output pad 112 (via the current detecting resistance element
118), an output capacitance C.sub.total substantially corresponds
to a capacitance C2. Since it is difficult to reduce a junction
area between the N well 132 and the P well 133, it is difficult to
make the capacitance C2 smaller, which means that it is difficult
to reduce the output capacitance C.sub.total. Increase in an output
capacitance of the output pad 112 is disadvantageous in outputting
an output signal at high speed.
[0015] Japanese Patent Application Publication (JP-P2005-340380A)
discloses circuit topology configured to detect a current flowing
through a protection target device and trigger the thyristor while
reducing the parasitic capacitance (output capacitance). FIG. 5 is
a circuit diagram showing a configuration of a semiconductor
integrated circuit 300 disclosed in this publication. The
semiconductor integrated circuit 300 has a thyristor 114, an output
driver 116, diodes 119 and 120, a resistance element 124 and a PMOS
transistor 125 used as a trigger device. The output driver 116 is
formed from the PMOS transistor P1 and the NMOS transistor N1, and
the resistance element 124 is connected between the NMOS transistor
N1 and the ground line 103. A gate of the PMOS transistor 125 is
connected to the power supply line 101, a drain thereof is
connected to the P gate Gp of the thyristor 114 and a source
thereof is connected to a connection node VO between the NMOS
transistor N1 and the resistance element 124.
[0016] An operation of the semiconductor integrated circuit 300 in
FIG. 5 is substantially as follows. When ESD surge is applied to
the output pad 112, a parasitic bipolar transistor of the NMOS
transistor N1 is turned on through a snap-back operation, so that a
current flows into the connection node VO between the NMOS
transistor N1 and the resistance element 124. Thereby, a voltage of
the connection node VO rapidly increases. When the voltage of the
connection node VO increases and a gate-source voltage Vgs of the
PMOS transistor 125 (gate voltage using source voltage as
reference) becomes lower than a threshold voltage-Vth, the PMOS
transistor 125 is turned on to supply a trigger to the thyristor
114.
[0017] With the circuit configuration shown in FIG. 5, since both
of the N gate Gn and the P gate GP of the thyristor 114 are
electrically isolated from the output pad 112, an output
capacitance of the output pad 112 can be reduced.
[0018] However, the semiconductor integrated circuit 300 in FIG. 5
has a problem that decrease in the resistance value of a path to
which an output signal is outputted and reliability in triggering
of the thyristor 114 cannot be achieved at a time. To allow the
parasitic bipolar transistor of the NMOS transistor N1 to be turned
on through the snap-back operation, a voltage of about 5V is
generally required. It is difficult to make the gate voltage of the
PMOS transistor 125 lower than a source voltage through the
snap-back operation. In addition, in the semiconductor integrated
circuit 300 in FIG. 5, to reduce a loss in outputting the output
signal, the resistance value of the resistance element 124 must be
made small. However, when the resistance value of the resistance
element 124 is made small, increase in the voltage of the
connection node VO becomes moderate. As a result, even when the ESD
surge is applied, the thyristor 114 is hard to operate.
[0019] Such a problem is applied to the semiconductor integrated
circuit 200 in FIGS. 4A and 4B. To reduce the loss in outputting
the output signal, the resistance value of the current detecting
resistance 118 must be made small. However, when the resistance
value of the current detecting resistance element 118 is made
small, difference in voltage between an anode and the N gate Gn of
the thyristor 114 becomes smaller so that the thyristor 114 is hard
to operate.
SUMMARY
[0020] Such a problem is applied to the semiconductor integrated
circuit 200 in FIGS. 4A and 4B. To reduce the loss in outputting
the output signal, the resistance value of the current detecting
resistance 118 must be made small. However, when the resistance
value of the current detecting resistance element 118 is made
small, difference in voltage between an anode and the N gate Gn of
the thyristor 114 becomes smaller so that the thyristor 114 is hard
to operate.
[0021] In an aspect of the present invention, a semiconductor
integrated circuit includes: an output pad from which an output
signal is outputted; an output signal line connected with the
output pad; a first pad configured to function as a ground terminal
or a power supply terminal; a first wiring connected with the first
pad; an output driver connected with the output pad and configured
to generate the output signal; an ESD protection device connected
with the output signal line and having a function to discharge
surge applied to the output pad; and a first trigger MOS transistor
used as a trigger device. The output driver includes: a first
protection target device connected between the output signal line
and the first interconnection; and a first resistance element
connected between the first protection target device and the first
interconnection. The first trigger MOS transistor configured to
detect a voltage generated in the first resistance element by a
gate of the first trigger MOS transistor and to allow the ESD
protection device operate in response to the detected voltage.
[0022] According to the present invention, it is possible to
provide a semiconductor integrated circuit which can simultaneously
achieve reduction in the resistance value of the path to which the
output signal is outputted and reliability in triggering of the ESD
protection device while having a low output capacitance.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The above and other objects, advantages and features of the
present invention will be more apparent from the following
description of certain embodiments taken in conjunction with the
accompanying drawings, in which:
[0024] FIG. 1 is a circuit diagram showing a configuration of a
conventional semiconductor integrated circuit including a thyristor
as an ESD protection device;
[0025] FIG. 2 is a circuit diagram showing a configuration of
another conventional semiconductor integrated circuit including a
thyristor as the ESD protection device;
[0026] FIG. 3 is a sectional view showing a configuration of the
thyristor shown in FIG. 2;
[0027] FIGS. 4A and 4B are equivalent circuit diagrams of the
semiconductor integrated circuit in FIG. 2;
[0028] FIG. 5 is a circuit diagram showing a configuration of
another conventional semiconductor integrated circuit including a
thyristor as the ESD protection device;
[0029] FIG. 6A is a circuit diagram showing a configuration of a
semiconductor integrated circuit of a first embodiment of the
present invention;
[0030] FIG. 6B is a sectional view showing a configuration of a
thyristor in a semiconductor integrated circuit in the first
embodiment;
[0031] FIG. 7 is a graph showing an operation of the semiconductor
integrated circuit in the first embodiment;
[0032] FIGS. 8A and 8B are circuit diagrams showing an equivalent
circuit of the thyristor and an NMOS transistor N3 in the
semiconductor integrated circuit in the first embodiment;
[0033] FIG. 9 is a circuit diagram showing the configuration of the
semiconductor integrated circuit according to a second embodiment
of the present invention;
[0034] FIG. 10 is a circuit diagram showing the configuration of
the semiconductor integrated circuit according to a third
embodiment of the present invention;
[0035] FIG. 11 is a circuit diagram showing the configuration of
the semiconductor integrated circuit according to a fourth
embodiment of the present invention;
[0036] FIG. 12 is a circuit diagram showing the configuration of
the semiconductor integrated circuit according to a fifth
embodiment of the present invention;
[0037] FIGS. 13A and 13B are circuit diagrams showing the
configuration of the semiconductor integrated circuit according to
a sixth embodiment of the present invention;
[0038] FIG. 14 is a circuit diagram showing the configuration of
the semiconductor integrated circuit according to a seventh
embodiment of the present invention;
[0039] FIG. 15 is a circuit diagram showing the configuration of
the semiconductor integrated circuit according to an eighth
embodiment of the present invention; and
[0040] FIG. 16 is a circuit diagram showing a modified example of
the semiconductor integrated circuit of the first embodiment of the
present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0041] Hereinafter, a semiconductor integrated circuit 10 according
to the present invention will be described with reference to the
attached drawings.
First Embodiment
[0042] FIG. 6A is a circuit diagram showing a configuration of a
semiconductor integrated circuit 10 according to a first embodiment
of the present invention. The semiconductor integrated circuit 10
has a VDD pad 11 connected to a power supply line 21, an output pad
12 connected to an output signal line 22, a VSS pad 13 connected to
a ground line 23 and a thyristor 14. The VDD pad 11 serves as a
power supply terminal to which a power supply voltage is supplied,
and the VSS pad 13 serves as a ground terminal to be grounded. The
output pad 12 is used to output an output signal to an external
unit. The thyristor 14 has a function of discharging ESD surge to
the ground line 23 when the ESD surge is applied to the output pad
12.
[0043] A last stage output driver 16 of an internal circuit is
connected to the output signal line 22. The last stage output
driver 16 has a PMOS transistor P1 connected between the power
supply line 21 and the output signal line 22 and an NMOS transistor
N1 connected between the ground line 23 and the output signal line
22. The PMOS transistor P1 is connected to the power supply line 21
at its source and connected to the output signal line 22 at its
drain. The NMOS transistor N1 is connected to the output signal
line 22 at its drain and connected to a node A at its source. In an
ordinary operation, an output signal generated by the last stage
output driver 16 is supplied to the output pad 12 via the output
signal line 22 and outputted from the output pad 12 to the external
unit. As described later, in the present embodiment, the NMOS
transistor N1 of the last stage output driver 16 is a protection
target device.
[0044] FIG. 6B is a sectional view showing a configuration of the
thyristor 14. As shown in FIG. 6B, the thyristor 14 has a same
configuration as the thyristor 14 shown in FIG. 3. An N well 32 and
a P well 33 are formed in a P-type substrate 31 to be adjacent to
each other. An N.sup.+ region 34 and a P.sup.+ region 35 are formed
in the N well 32, and the N.sup.+ region 34 functions as an N gate
Gn and the P.sup.+ region 35 functions as an anode. The P.sup.+
region 35 (that is, anode) is connected to the output pad 12.
Furthermore, an N.sup.+ region 36 and a P.sup.+ region 37 are
formed in the P well 33, and the N.sup.+ region 36 functions as a
cathode and the P.sup.+ region 37 functions as a P gate Gp. The
N.sup.+ region 36 (that is, cathode) is connected to the ground
line 23. A P well 38 is connected to the P-type substrate 31 and a
P.sup.+ region 39 connected to the ground line 23 is formed in the
P well 38. A portion between the P wells 33 and 38 in the P-type
substrate 31 serves as a substrate resistance Rsub for biasing the
P gate Gp. In FIG. 6B, a junction capacitance formed between the N
well 32 and the P.sup.+ region 35 is shown as C1 and a junction
capacitance formed between the N well 32 and the P well 33 is shown
as C2.
[0045] In the semiconductor integrated circuit 10 in the present
embodiment, a resistance element Rn is connected to the node A
which is connected to the source of the NMOS transistor N1, and the
ground line 23, and an NMOS transistor N3 is connected to the
thyristor 14. As described later, the resistance element Rn is used
to detect a current flowing through the NMOS transistor N1 as the
protection target device. The NMOS transistor N3 is used as a
trigger device for generating a trigger to operate the thyristor
14. The NMOS transistor N3 is connected to the N gate Gn of the
thyristor 14 at its drain, is connected to the ground line 23 at
its source and is connected to the node A at its gate. The NMOS
transistor N3 detects a voltage generated in the resistance element
Rn and operates in response to the voltage generated in the
resistance element Rn.
[0046] An operation of the semiconductor integrated circuit 10,
especially, the NMOS transistor N3 and the thyristor 14 in the
present embodiment will be described. When the ESD surge of
positive polarity to the VSS pad 13 is applied to output pad 12, a
current may flow through the NMOS transistor N1. In this case, the
current also flows through the resistance element Rn to increase a
voltage at the node A. Thus, a gate--source voltage of the NMOS
transistor N3 increases, so that the NMOS transistor N3 is turned
on. Then, the NMOS transistor N3 generates a trigger to activate
the thyristor 14. In this example, the NMOS transistor N3 pulls a
current from the N gate Gn to activate the thyristor 14. Once the
thyristor 14 is activated, the voltage of the output pad 12 is kept
low until the surge current stops flowing. Thus, no current flows
through the NMOS transistor N1, to prevent breakdown of the NMOS
transistor N1.
[0047] Even when no current flows into the NMOS transistor N1, the
NMOS transistor N3 serves as a transistor in an off state, a gate
of which is grounded. Accordingly, the parasitic bipolar transistor
is turned on in response to a snap-back operation of the NMOS
transistor N3, thereby activating the thyristor 14.
[0048] Since the semiconductor integrated circuit 10 in the present
embodiment is configured so that the voltage generated in the
resistance element Rn is detected by the gate of the NMOS
transistor N3, the thyristor 14 can be reliably activated depending
on the current flowing through the NMOS transistor N1, even if the
resistance element Rn is small. For example, it is assumed that the
resistance element Rn is a resistance of 1 formed from a metal
wiring resistance and the current of 300 mA, which does not to
cause breakdown of the NMOS transistor N1, flows through the NMOS
transistor N1. Also, in this case, since the voltage of the node A
increases to 0.3V, a trigger can be generated to activate the
thyristor 14, if a threshold voltage Vt of the NMOS transistor N3
is 0.3V.
[0049] FIG. 7 is a graph showing an operation of the semiconductor
integrated circuit 10 in the present embodiment. A horizontal axis
represents a voltage applied to the output pad 12 and a vertical
axis represents a current flowing into the output pad 12. In the
operation shown in FIG. 7, when the voltage of 5V is applied and
the current of about 500 mA flows through the NMOS transistor N1,
the thyristor 14 operates and the NMOS transistor N1 is effectively
protected.
[0050] In addition, in the semiconductor integrated circuit 10 in
the present embodiment, since the NMOS transistor N3 is connected
between the N gate Gn of the thyristor 14 and the ground line 23
and the N gate Gn is electrically isolated from the output pad 12,
an output capacitance can be decreased. FIGS. 8A and 8B are
diagrams showing an equivalent circuit of the thyristor 14 and the
NMOS transistor N3. In the present embodiment, since the NMOS
transistor N3 is connected between the N gate Gn of the thyristor
14 and the ground line 23, the output capacitance C.sub.total of
the output pad 12 corresponds to a synthetic capacitance obtained
by serially connecting a parallel-connected capacitance of the
capacitance C2 formed between the N well 32 and the P well 33 and a
capacitance Ct1 of the NMOS transistor N3 to a capacitance C1
formed in the PN junction between the N well 32 and the P.sup.+
region 35. That is,
C.sub.total=C1//(C2+Ct1),
Here, "//" is a symbol representing a synthetic capacitance of
serially connected capacitances. When the capacitance C1 is made
very small, the output capacitance C.sub.total of the output pad 12
approximately corresponds to the capacitance C1. That is,
C.sub.total.apprxeq.C1.
[0051] It should be noted that the capacitance C1 can be easily
made small by reducing the area of the PN junction between the N
well 32 and the P.sup.+ region 35. In other words, in the
semiconductor integrated circuit 10 in the present embodiment,
reduction in the output capacitance C.sub.total of the output pad
12 can be achieved. Thus, the feature of reduction in the output
capacitance C.sub.total of the output pad 12 by use of the
thyristor 14 is impaired.
[0052] As described above, the semiconductor integrated circuit 10
in the present embodiment can both achieve reduction in the
resistance value of the path to which the output signal is
outputted and increase reliability in triggering of the ESD
protection target element while having a low output
capacitance.
Second Embodiment
[0053] FIG. 9 is a circuit diagram showing the configuration of a
semiconductor integrated circuit 10A according to a second
embodiment of the present invention. The semiconductor integrated
circuit 10A of the second embodiment has the configuration for
protecting the PMOS transistor P1 of the last stage output driver
16 from the electrostatic breakdown. In detail, a resistance
element Rp is connected between the power supply line 21 and a node
B and the PMOS transistor P1 is connected between the node B and
the output signal line 22. The resistance element Rp is used to
detect a current flowing through the PMOS transistor P1 as a
protection target device. The PMOS transistor P3 used as a trigger
device is connected to the P gate Gp of the thyristor 14. The PMOS
transistor P3 is connected to the P gate Gp of the thyristor 14 at
its drain, is connected to the node B at its source and is
connected to the power supply line 21 at its gate. A power clamp 17
is connected between the power supply line 21 and the ground line
23.
[0054] An operation of the semiconductor integrated circuit 10A, in
particular, the PMOS transistor P3 and the thyristor 14 in the
present embodiment will be described below.
[0055] When the ESD surge of positive polarity to the VSS pad 13 is
applied to output pad 12 and surge current flows through the PMOS
transistor P1 and the power clamp 17, the voltage of the power
supply line 21 becomes lower than the voltage of the node B due to
voltage drop of the resistance element Rp. Then, the gate voltage
of the PMOS transistor P3 becomes lower than the source voltage of
the PMOS transistor P3, so as to turn on the PMOS transistor P3.
Thus, the PMOS transistor P3 generates a trigger for activating the
thyristor 14. In the present embodiment, the PMOS transistor P3
supplies the current and activates the thyristor 14. Once the
thyristor 14 is activated, the voltage of the output pad 12 is kept
low until the surge current stops flowing. In this way, no current
flows through the PMOS transistor P1, to prevent breakdown of the
PMOS transistor P1.
[0056] Since the semiconductor integrated circuit 10A in the second
embodiment is configured so that a voltage applied to the
resistance element Rp is detected by the gate of the PMOS
transistor P3, even if the resistance element Rp is small, the
thyristor 14 can be reliably activated depending on the current
flowing through the PMOS transistor P1. In addition, since the N
gate Gn and the P gate Gp of the thyristor 14 are electrically
isolated from the output pad 12, an output capacitance of the
output pad 12 can be decreased.
Third Embodiment
[0057] FIG. 10 is a circuit diagram showing the configuration of a
semiconductor integrated circuit 10B according to a third
embodiment of the present invention. The semiconductor integrated
circuit 10B in the third embodiment has the configuration of a
combination of the semiconductor integrated circuits 10 and 10A in
the first and second embodiments, for protecting both of the NMOS
transistor N1 and the PMOS transistor P1 against electrostatic
breakdown. In detail, the resistance element Rn is connected
between the ground line 23 and the node A and the NMOS transistor
N1 is connected between the node A and the output signal line 22.
The gate of the NMOS transistor N3 used as the trigger device is
connected to the node A. The NMOS transistor N3 is connected to the
N gate Gn of the thyristor 14 at its drain, and is connected to the
ground line 23 at its source. Furthermore, the resistance element
Rp is connected between the power supply line 21 and the node B and
the PMOS transistor P1 is connected between the node B and the
output signal line 22. A source of the PMOS transistor P3 used as
the trigger device is connected to the node B. The PMOS transistor
P3 is connected to the P gate Gp of the thyristor 14 at its drain
and is connected to the power supply line 21 at its gate. The power
clamp 17 is connected between the power supply line 21 and the
ground line 23. To reduce a layout area, it is preferred that the
PMOS transistors P1, P3 are formed in a same N well. In this case,
the NMOS transistors N1 and N3 are formed in the P well, it is
preferred that the NMOS transistors N1 and N3 are formed in a same
P well for the same reason.
[0058] An operation at the time when the surge current flows
through the NMOS transistor N1 is the same as in the semiconductor
integrated circuit 10 in the first embodiment. An operation at the
time when the surge current flows through the PMOS transistor P1 is
the same as in the semiconductor integrated circuit 10A in the
first embodiment. With the configuration in the third embodiment,
the thyristor 14 can be activated before the current flows through
either the NMOS transistor N1 or the PMOS transistor P1, and both
of the NMOS transistor N1 and the PMOS transistor P1 are subjected
to breakdown. Furthermore, by triggering both the P gate Gp and the
N gate Gn of the thyristor 14, the thyristor 14 can be activated at
higher speed.
Fourth Embodiment
[0059] FIG. 11 is a circuit diagram showing the configuration of a
semiconductor integrated circuit 10C according to a fourth
embodiment of the present invention. In the fourth embodiment, a
current limiting resistance R1 is serially connected to the NMOS
transistor N3 used as the trigger device. The current limiting
resistance R1 prevents an excessive current from flowing through
the NMOS transistor N3 after the thyristor 14 starts to operate, so
that the NMOS transistor N3 is subjected to breakdown. Although the
current limiting resistance R1 is introduced between the drain of
the NMOS transistor N3 and the N gate Gn of the thyristor 14 in the
circuit shown in FIG. 11, the current limiting resistance R1 may be
connected between the source of the NMOS transistor N3 and the
ground line 23.
[0060] Similarly, in the semiconductor integrated circuits 10A and
10B shown in FIGS. 9 and 10, the current limiting resistance may be
serially connected to the PMOS transistor P3. The current limiting
resistance may be connected between the drain of the PMOS
transistor P3 and the P gate Gp of the thyristor 14, and between
the source of the PMOS transistor P3 and the node B.
Fifth Embodiment
[0061] FIG. 12 is a circuit diagram showing the configuration of a
semiconductor integrated circuit 10D according to a fifth
embodiment of the present invention. The semiconductor integrated
circuit 10D in the fifth embodiment supplies triggers to the N gate
Gn of the thyristor 14 from the NMOS transistor N3 and to the P
gate Gn from the NMOS transistor N4. In detail, the NMOS transistor
N4 is connected to the P gate Gp of the thyristor 14 at its source,
is connected to the power supply line 21 at its drain and is
connected to the node A at its gate.
[0062] Both of the NMOS transistors N3 and N4 detect the voltage of
the node A (that is, a connection node between the resistance
element Rn and the source of the NMOS transistor N1) and generate
the trigger. By supplying trigger to both of the N gate Gn and the
P gate Gp of the thyristor 14, the thyristor 14 can be triggered at
high speed. A trigger current supplied to the P gate Gp flows from
the output pad 12 through the NMOS transistor N4 via a parasitic
diode formed of the drain of the PMOS transistor P1 of the output
driver 16 and the N well, and reaches P gate Gp.
Sixth Embodiment
[0063] FIGS. 13A and 13B are circuit diagrams showing the
configuration of a semiconductor integrated circuit 10E of a sixth
embodiment of the present invention. A configuration of the
semiconductor integrated circuit 10E in the present embodiment
contributes to effectively restrict latch-up of the thyristor 14
while increasing the discharge capacity of the thyristor 14. The
discharge capacity of the thyristor 14 depends on base resistance
of an NPN bipolar transistor of the thyristor 14. That is, when the
thyristor 14 has the configuration shown in FIG. 6B, the substrate
resistance Rsub between the P wells 33 and 38 of the P-type
substrate 31 corresponds to a base resistance of the NPN bipolar
transistor. When the substrate resistance Rsub is large, the
performance of the NPN bipolar transistor of the thyristor 14 is
improved to increase the discharge capacity of the thyristor 14,
which is advantageous for electrostatic protection. However, when
the substrate resistance Rsub increases, latch-up can occur in the
normal operation.
[0064] In the semiconductor integrated circuit 10E in the sixth
embodiment, by providing an inverter 18 and an NMOS transistor N5,
both of improvement in the discharge capacity of the thyristor 14
and prevention of latch-up of the thyristor 14 are achieved. In
response to the voltage at the node A, the inverter 18 controls
on/off of the NMOS transistor N5. In detail, an input terminal of
the inverter 18 is connected to the node A and an output terminal
of the inverter 18 is connected to the gate of the NMOS transistor
N5. A power supply terminal of the inverter 18 is connected to the
power supply line 21 and the ground terminal is connected to the
ground line 23. The NMOS transistor N5 is a switch element which
electrically connect/separate the P gate Gp of the thyristor 114
to/from the ground line 23 in response to the output signal of the
inverter 18. The NMOS transistor N5 is connected to the P gate Gp
of the thyristor 114 at its drain and is connected to the ground
line 23 at its source. A threshold voltage of the inverter 18 (that
is, the voltage at the output signal of the inverter 18 is switched
between High and Low) is set to be approximately same as the
threshold voltage of the NMOS transistor N3. The ON-resistance of
the NMOS transistor N5 is set to be smaller than the substrate
resistance Rsub.
[0065] FIG. 13A shows an operation of the semiconductor integrated
circuit 10E at the time when the ESD surge is applied to the output
pad 12 and FIG. 13B shows an operation of the semiconductor
integrated circuit 10E in the normal operation. Referring to FIG.
13A, when the ESD surge is applied to the output pad 12 so that
current flows through the resistance element Rn (and the NMOS
transistor N1), the voltage of the node A increases. At this time,
the output signal of the inverter 18 is pulled down to a "Low"
level and the NMOS transistor N5 is turned off. In this case, the
substrate resistance Rsub serves as a base resistance of the NPN
transistor of the thyristor 14. As described above, when the
substrate resistance Rsub is increased, the discharge capacity of
the thyristor 14 is improved.
[0066] With the configuration of the semiconductor integrated
circuit 10E in the present embodiment, even when the substrate
resistance Rsub is increased, latch-up is hard to occur in the
normal operation. Referring to FIG. 13B, in the normal operation,
the output signal of the inverter 18 is pulled up to a "High" level
and the NMOS transistor N5 is turned on. Since the ON-resistance of
the NMOS transistor N5 is smaller than the substrate resistance
Rsub, when the NMOS transistor N5 is turned on, the base resistance
of the NPN transistor of the thyristor 14 becomes small. For this
reason, latch-up is prevented from occurring in the normal
operation.
Seventh Embodiment
[0067] FIG. 14 is a circuit diagram showing the configuration of a
semiconductor integrated circuit 10F according to a seventh
embodiment of the present invention. One feature of the
semiconductor integrated circuit 10F in the present embodiment is
that a parasitic bipolar transistor of the MOS transistor is used
as the ESD protection device. In the semiconductor integrated
circuit 10F in the present embodiment, a parasitic NPN transistor
PTr1 of the NMOS transistor N1 of the last stage output driver 16
is used as the ESD protection device. The semiconductor integrated
circuit 10F in the seventh embodiment will be described in detail
below.
[0068] The semiconductor integrated circuit 10F in the present
embodiment has the configuration that the PMOS transistor P1 of the
last stage output driver 16 is protected against the ESD surge. To
detect a current flowing through the PMOS transistor P1, the
resistance element Rp is connected between the source of the PMOS
transistor P1 and the power supply line 21. A PMOS transistor P3 is
used as the trigger device. To reduce a layout area, it is
preferred that the PMOS transistors P1 and P3 are formed on a same
N well. The PMOS transistor P3 is connected to the node B at its
source, is connected to the power supply line 21 at its gate and is
connected to a back gate of the NMOS transistor N1 (that is, the
P.sup.+ region formed in the P well on which the NMOS transistor N1
is formed) at its drain. It should be noted that the back gate of
the NMOS transistor N1 serves as a base of the parasitic NPN
transistor. The P well and the P.sup.+ region for grounding the
P-type substrate on which the NMOS transistor N1 is formed are
formed independent of the back gate of the NMOS transistor N1. The
substrate resistance Rsub in FIG. 14 is accomplished in the
semiconductor integrated circuit 10F as a resistance of the P-type
substrate 31.
[0069] An operation of the semiconductor integrated circuit 10F in
the seventh embodiment will be described below. When the ESD surge
of positive polarity to the VSS pad 13 is applied to the output pad
12 so that a surge current flows through the PMOS transistor P1 and
the power clamp 17, the voltage of the power supply line 21 becomes
lower than the voltage of the node B due to a voltage drop of the
resistance element Rp. Then, the gate voltage of the PMOS
transistor P3 becomes lower than the source voltage of the PMOS
transistor P3, thereby turning on the PMOS transistor P3. Also, the
PMOS transistor P3 generates a trigger for activating the parasitic
NPN transistor PTr1. In the present embodiment, the PMOS transistor
P3 supplies a current to the base Gp of the parasitic NPN
transistor PTr1 and activates the parasitic NPN transistor PTr1.
Once the parasitic NPN transistor PTr1 is activated, no current
flows through the PMOS transistor P1 to prevent breakdown of the
PMOS transistor P1, since the voltage of the output pad 12 is kept
low until the surge current ends flowing.
[0070] From the above-mentioned description, those skilled in the
art could easily understand that a bipolar element (including the
parasitic bipolar transistor of the MOS transistor) can be used as
the ESD protection device in place of the thyristor. For example, a
normal NPN bipolar transistor can be used in place of the parasitic
NPN transistor PTr1 of the NMOS transistor N1.
Eighth Embodiment
[0071] FIG. 15 is a circuit diagram showing the configuration of a
semiconductor integrated circuit 10G according to an eighth
embodiment of the present invention. In the eighth embodiment, the
circuit configuration which can achieve both of high discharge
capacity and restriction of latch-up as in the sixth embodiment is
applied to the semiconductor integrated circuit 10F in the seventh
embodiment.
[0072] More specifically, in the eighth embodiment, the inverter 18
and the NMOS transistor N5 are added. The input terminal of the
inverter 18 is connected to the node A and the output terminal of
the inverter 18 is connected to the gate of the NMOS transistor N5.
The power supply terminal of the inverter 18 is connected to the
power supply line 21 and the ground terminal of the inverter 18 is
connected to the ground line 23. The NMOS transistor N5 is
connected to the back gate of the NMOS transistor N1 (that is, the
base of the parasitic NPN transistor PTr1) at its drain and is
connected to the ground line 23, at its source. The threshold
voltage (that is, a voltage at which an output signal of the
inverter 18 is switched between High and Low) of the inverter 18 is
set to be approximately same as the threshold voltage of the PMOS
transistor P3. The ON-resistance of the NMOS transistor N5 is set
to be smaller than the substrate resistance Rsub.
[0073] When the ESD surge is applied to the output pad 12 so that a
current flows through the resistance element Rn (and the NMOS
transistor N1), a voltage at the node A increases. In response to
the increase in the voltage of the node A, the output signal of the
inverter 18 is pulled down to a "low" level and the NMOS transistor
N5 is turned off. In this case, the substrate resistance Rsub
functions as a base resistance of the parasitic NPN transistor.
Those skilled in the art could understand that when the substrate
resistance Rsub is increased, a discharge capacity of the parasitic
NPN transistor is improved. On the other hand, in the normal
operation, the output signal of the inverter 18 is pulled up to a
"high" level and the NMOS transistor N5 is turned on. Since the
ON-resistance of the NMOS transistor N5 is smaller than the
substrate resistance Rsub when the NMOS transistor N5 is turned on,
the base resistance of the parasitic NPN transistor becomes small.
For this reason, latch-up is prevented from occurring in the normal
operation.
[0074] It should be noted that the present invention is not limited
to the above-mentioned embodiments and various modifications can be
made. Furthermore, especially when a plurality of protection target
devices exist, the resistance element Rn or Rp need not be provided
for each protection target device. For example, when the protection
target devices are the NMOS transistors N1a and N1b as shown in
FIG. 16, the resistance element Rn can be connected to only the
NMOS transistor N1a and no resistance for detecting a current is
connected to the NMOS transistor N1b. Even with such configuration,
the NMOS transistors N1a and Nib are effectively protected against
ESD surge.
[0075] In the present embodiment, although the output pad 12 is
used as an output of the output signal, the pad 12 can be also used
as an input of the signal. In this case, the pad 12 is connected to
an input buffer provided separately from the last stage output
driver 16 and serves as an I/O pad.
[0076] Note that, in the above-mentioned embodiments, a plurality
of operations can be combined as long as the operations do not
conflict.
[0077] Although the present invention has been described above in
connection with several embodiments thereof, it would be apparent
to those skilled in the art that those embodiments are provided
solely for illustrating the present invention, and should not be
relied upon to construe the appended claims in a limiting
sense.
* * * * *