U.S. patent application number 13/489458 was filed with the patent office on 2012-09-27 for thin film transistor.
This patent application is currently assigned to AU OPTRONICS CORPORATION. Invention is credited to Chun-Hsiun Chen, Pei-Ming Chen, Wei-Ming Huang, Guang-Ren Shen.
Application Number | 20120241743 13/489458 |
Document ID | / |
Family ID | 44530520 |
Filed Date | 2012-09-27 |
United States Patent
Application |
20120241743 |
Kind Code |
A1 |
Shen; Guang-Ren ; et
al. |
September 27, 2012 |
THIN FILM TRANSISTOR
Abstract
A thin film transistor (TFT) and a fabricating method thereof
are provided. The TFT includes a channel layer, an ohmic contact
layer, a dielectric layer, a source, a drain, a gate, and a gate
insulating layer. The channel layer has an upper surface and a
sidewall. The ohmic contact layer is disposed on a portion of the
upper surface of the channel layer. The dielectric layer is
disposed on the sidewall of the channel layer, and does not overlap
with the ohmic contact layer. The source and the drain are disposed
on portions of the ohmic contact layer and the dielectric layer. A
portion of dielectric layer is not covered by the source or the
drain. The gate is above or below the channel layer. The gate
insulating layer is disposed between the gate and the channel
layer.
Inventors: |
Shen; Guang-Ren; (Yunlin
County, TW) ; Chen; Pei-Ming; (Taipei County, TW)
; Chen; Chun-Hsiun; (Hsinchu City, TW) ; Huang;
Wei-Ming; (Taipei City, TW) |
Assignee: |
AU OPTRONICS CORPORATION
Hsinchu
TW
|
Family ID: |
44530520 |
Appl. No.: |
13/489458 |
Filed: |
June 6, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12779955 |
May 14, 2010 |
8232147 |
|
|
13489458 |
|
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Current U.S.
Class: |
257/57 ; 257/66;
257/E29.273 |
Current CPC
Class: |
H01L 29/786
20130101 |
Class at
Publication: |
257/57 ; 257/66;
257/E29.273 |
International
Class: |
H01L 29/786 20060101
H01L029/786 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 3, 2010 |
TW |
99106133 |
Claims
1. A thin film transistor disposed on a substrate, the thin film
transistor comprising: a channel layer having an upper surface and
a sidewall; an ohmic contact layer disposed on a portion of the
upper surface of the channel layer; a dielectric layer disposed on
the sidewall of the channel layer, wherein the dielectric layer and
ohmic contact are not overlapped; a source and a drain disposed on
the ohmic contact layer and on a portion of the dielectric layer,
and a portion of the dielectric layer is not covered by the source
or the drain; a gate disposed above or below the channel layer; and
a gate insulating layer disposed between the gate and the channel
layer.
2. The thin film transistor as claimed in claim 1, wherein the gate
insulating layer is disposed on the substrate to cover the gate and
the dielectric layer extends from the sidewall of the channel layer
to the substrate when the gate is below the channel layer.
3. The thin film transistor as claimed in claim 2, further
comprising a passivation layer covering the source, the drain, the
dielectric layer, and the channel layer.
4. The thin film transistor as claimed in claim 1, wherein the gate
insulating layer covers the source, the drain, the dielectric
layer, and a portion of the channel layer when the gate is above
the channel layer.
5. The thin film transistor as claimed in claim 4, further
comprising passivation layer covering the gate and the gate
insulating layer.
6. The thin film transistor as claimed in claim 4, further
comprising a buffer layer between the dielectric layer and the
substrate and between the channel layer and the substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional application of U.S.
application Ser. No. 12/779,955 filed on May 14, 2010, now pending,
which claims the priority benefit of Taiwan application serial no.
99106133, filed on Mar. 3, 2010. The entirety of each of the
above-mentioned patent applications is hereby incorporated by
reference herein and made a part of specification.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention is related to a semiconductor device and a
fabricating method thereof, and in particular to a thin film
transistor and a fabricating method thereof.
[0004] 2. Description of Related Art
[0005] In recent years, as optoelectronic technology and
semiconductor fabrication technology increasingly mature,
development of flat panel displays has boomed. Since liquid crystal
displays have advantages such as low operating voltage, no
radioactive emissions, light weight, and small volume, liquid
crystal displays have gradually replaced conventional cathode ray
tube displays to become the mainstream product. Generally, liquid
crystal displays may be classified into amorphous silicon thin film
transistor liquid crystal displays (a-Si TFT-LCDs) and low
temperature poly-silicon thin film transistor liquid crystal
displays (LTPS TFT-LCDs).
[0006] FIG. 1A is a schematic cross-sectional view of a
conventional thin film transistor. Please refer to FIG. 1A, a thin
film transistor 100 is disposed on a substrate 101 and includes a
gate 110, a patterned amorphous silicon layer 120 (which is a
channel layer), a source 130, and a drain 132, wherein each of the
source 130 and the drain 132 is connected to the channel layer 120
through an ohmic contact layer 140. When a high voltage is applied
to the gate 100, the thin film transistor 100 is turned on, so that
the channel layer 120 is in a conductive state, thereby connecting
the source 130 and the drain 132. However, when a high voltage is
not applied to the gate 110, the thin film transistor 100 is turned
off, a leakage current is often generated by the channel layer 120
as the channel layer is irradiated by external light, thereby
affecting reliability of the thin film transistor 100. In order to
reduce leakage currents, conventional art provides an improvement
method by performing a plasma treatment during the process of
fabricating the thin film transistor 100. FIG. 1B is a schematic
view of a conventional plasma treatment. Please refer to FIG. 1B,
the plasma treatment is performed after the ohmic contact layer 140
and a photoresist layer 150 are formed and before a second metallic
layer that is used to form the source 130 and the drain 132 is
deposited. A plasma 160 used in the plasma treatment process may be
an oxygen plasma (O.sub.2-plasma) or an argon plasma (Ar-plasma).
After the plasma treatment is performed, a layer of silicon oxide
(SiOx) thin film is formed on sidewalls 121 and 123 of the channel
layer 120, so as to reduce the leakage current.
[0007] FIG. 1C is a schematic cross-sectional view of a
conventional thin film transistor. Please refer to both FIGS. 1A
and 1C, the difference between FIGS. 1A and 1C lies in that a
source 170, a drain 172, and an ohmic contact layer 180 of the thin
film transistor 102 are fabricated by using the same
photolithography and etch process (PEP), so that the source 170 and
the drain 172 have substantial the same pattern as the ohmic
contact layer 180. However, in the thin film transistor shown in
FIG. 1C, the drawbacks resulted from leakage currents still cannot
be effectively solved.
SUMMARY OF THE INVENTION
[0008] The invention provides a thin film transistor and a
fabricating method thereof which are capable of reducing leakage
currents.
[0009] The invention provides a fabricating method of a thin film
transistor which includes the following steps. A gate is formed on
a substrate. A gate insulating layer is formed on the substrate, so
as to cover the gate. A channel material layer, an ohmic contact
material layer, and a patterned photoresist layer are sequentially
formed on the gate insulating layer, wherein the patterned
photoresist layer is located above the gate. The channel material
layer and the ohmic contact material layer are patterned by using
the patterned photoresist layer as a mask, so as to form a channel
layer and an ohmic contact layer which is between the channel layer
and the patterned photoresist layer. A dielectric layer is formed
on the patterned photoresist layer, on a sidewall of the channel
layer, on a sidewall of the ohmic contact layer, and on a portion
of the gate insulating layer. The patterned photoresist layer and a
portion of the dielectric layer that is in contact with the
patterned photoresist layer are removed, so as to expose the ohmic
contact layer. A source and a drain are formed on a portion of the
dielectric layer and on a portion of the ohmic contact layer, and a
portion of the ohmic contact layer that is not covered by the
source or the drain is removed.
[0010] According to an embodiment of the invention, the fabricating
method of the thin film transistor further includes a step of
forming a passivation layer so as to cover the source, the drain, a
portion of the dielectric layer, and a portion of the channel
layer.
[0011] The invention also provides a fabricating method of a thin
film transistor which includes the following steps. A channel
material layer, an ohmic contact material layer, and a patterned
photoresist layer are sequentially formed on a substrate; The
channel material layer and the ohmic contact material layer are
patterned by using the patterned photoresist layer as a mask, so as
to form a channel layer and an ohmic contact layer which is between
the channel layer and the patterned photoresist layer. A dielectric
layer is formed on the patterned photoresist layer, on a sidewall
of the channel layer, and on a sidewall of the ohmic contact layer.
The patterned photoresist layer and a portion of the dielectric
layer that is in contact with the patterned photoresist layer are
removed, so as to expose the ohmic contact layer. A source and a
drain are formed on a portion of the dielectric layer and on a
portion of the ohmic contact layer, and a portion of the ohmic
contact layer that is not covered by the source or the drain is
removed. A gate insulating layer is formed on the substrate, so as
to cover the source, the drain, a portion of the dielectric layer,
and a portion of the channel layer. A gate is formed on the gate
insulating layer, wherein the gate is above the channel layer.
[0012] According to an embodiment of the invention, the method of
removing the patterned photoresist layer and the portion of the
dielectric layer that is in contact with the patterned photoresist
layer includes a lift-off process.
[0013] According to an embodiment of the invention, after the
patterned photoresist layer is removed, the dielectric layer is
connected to the sidewall of the ohmic contact layer, and the
dielectric layer and the ohmic contact layer are not
overlapped.
[0014] According to an embodiment of the invention, the fabricating
method of the thin film transistor further includes a step of
forming a passivation layer so as to cover the gate and the gate
insulating layer.
[0015] According to an embodiment of the invention, the above
dielectric layer further covers a portion of the substrate.
[0016] According to an embodiment of the invention, the fabricating
method of the thin film transistor further includes a step of
forming a buffer layer on the substrate before the channel material
layer is formed, wherein the above dielectric layer further covers
a portion of the buffer layer.
[0017] The invention also provides a thin film transistor which is
suitable for being disposed on a substrate. The thin film
transistor includes a channel layer, an ohmic contact layer, a
dielectric layer, a source, a drain, a gate, and a gate insulating
layer. The channel layer has an upper surface and a sidewall. The
ohmic contact layer is disposed on a portion of the upper surface
of the channel layer. The dielectric layer is disposed on the
sidewall of the channel layer, wherein the dielectric layer and
ohmic contact layer are not overlapped. The source and the drain
are disposed on portions of the ohmic contact layer and the
dielectric layer, and a portion of the dielectric layer is not
covered by the source or the drain. The gate is above or below the
channel layer. The gate insulating layer is disposed between the
gate and the channel layer.
[0018] According to an embodiment of the invention, when the gate
is below the channel layer, the gate insulating layer is disposed
on the substrate to cover the gate, and the dielectric layer
extends from the sidewall of the channel layer to the
substrate.
[0019] According to an embodiment of the invention, the thin film
transistor further includes a passivation layer so as to cover the
source, the drain, a portion of the dielectric layer, and a portion
of the channel layer.
[0020] According to an embodiment of the invention, when the gate
is above the channel layer, the gate insulating layer covers the
source, the drain, a portion of the dielectric layer, and a portion
of the channel layer.
[0021] According to an embodiment of the invention, the thin film
transistor further includes a passivation layer so as to cover the
gate and the gate insulating layer.
[0022] According to an embodiment of the invention, the thin film
transistor further includes a buffer layer which is between the
dielectric layer and the substrate and between the channel layer
and the substrate.
[0023] In summary, the thin film transistors and the fabricating
methods thereof of the invention are effective in inhibiting
leakage currents, thereby enhancing reliability.
[0024] In order to make the aforementioned and other objects,
features and advantages of the invention comprehensible, preferred
embodiments accompanied with figures are described in detail
below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The accompanying drawings are included to provide a further
understanding of the invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the invention and, together with the description,
serve to explain the principles of the invention.
[0026] FIG. 1A is a schematic cross-sectional view of a
conventional thin film transistor.
[0027] FIG. 1B is a schematic view of a conventional plasma
treatment.
[0028] FIG. 1C is a schematic cross-sectional view of a
conventional thin film transistor.
[0029] FIGS. 2A to 2H are schematic cross-sectional views showing a
process of fabricating a thin film transistor according to the
first embodiment of the invention.
[0030] FIGS. 3A to 3I are schematic cross-sectional views showing a
process of fabricating a thin film transistor according to the
second embodiment of the invention.
DESCRIPTION OF THE EMBODIMENTS
First Embodiment
[0031] FIGS. 2A to 2H are schematic cross-sectional views showing a
process of fabricating a thin film transistor according to the
first embodiment of the invention. Please refer to FIG. 2A. The
fabricating method of a thin film transistor 220 according to the
present embodiment includes the following steps. First, a gate 222
is formed on the substrate 210. The gate 222 may be formed through
a first photolithography and etch process (1st PEP). The material
of the substrate 210 may be an inorganic transparent material (such
as glass, quartz, other suitable materials, or combinations
thereof), an organic transparent material (such as a polyolefin, a
polysuccinate, a polyol, a polyester, rubber, a thermoplastic
polymer, a thermosetting polymer, a polyaromatic hydrocarbon, a
polymethylmethacrylate, a poly carbonate, other suitable materials,
derivatives of the above, or combinations thereof), an inorganic
non-transparent material (such as silicon sheets, ceramic,
derivatives of the above, or combinations thereof), or combinations
thereof.
[0032] Please refer to FIG. 2B. A gate insulating layer 224 is
formed on the substrate 210, so as to cover the gate 222 and the
substrate 210. For example, the material of the gate insulating
layer 224 is an inorganic material such as silicon oxide (SiOx) or
silicon nitride (SiNx). Please refer to FIG. 2C. Next, a channel
material layer 226, an ohmic contact material layer 228, and a
patterned photoresist layer 230 are sequentially formed on the gate
insulating layer 224, wherein the patterned photoresist layer 230
is above the gate 222, and the material of the patterned
photoresist layer 230 may be a photoresist (PR), a metal, or a
removable material. The material of the ohmic contact material
layer 228 may be an N-type doped semiconductor material, such as
N-type doped amorphous silicon (n.sup.+ a-Si), and the material of
the channel material layer 226 may be amorphous silicon (a-Si).
[0033] Please refer to FIG. 2D. Next, by using the patterned
photoresist layer 230 as a mask, a portion of the ohmic contact
material layer 228 which is not covered by the patterned
photoresist layer 230 and a portion of the channel material 226 are
removed, thereby forming a patterned channel layer 226a and an
ohmic contact layer 228a between the channel layer 226a and the
photoresist layer 230.
[0034] Please refer to FIG. 2E. A dielectric layer 232 is formed on
the patterned photoresist layer 230, on a sidewall of the channel
layer 226a, on a sidewall of the ohmic contact layer 228a and on
the gate insulating layer 224. The method for depositing the
dielectric layer 232 may be physical vapor deposition (PVD),
chemical vapor deposition (CVD), or solution spin-coating. The
material of the dielectric layer 232 may be silicon oxide (SiOx),
silicon nitride (SiNx), or silicon oxynitride (SiON), the physical
vapor deposition is, for example, sputtering, and the chemical
vapor deposition is, for example, plasma enhanced chemical vapor
deposition (PECVD).
[0035] Please refer to FIG. 2F. Next, the patterned photoresist
layer 230 and a portion of the dielectric layer 232 that is in
contact with the patterned photoresist layer 230 are removed, so
that the ohmic contact layer 228a is exposed. The method of
removing the patterned photoresist layer 230 and the portion of the
dielectric layer 232 that is in contact with the patterned
photoresist layer 230 may be a lift-off process. After the
patterned photoresist layer 230 is removed, the dielectric layer
232 is connected to the sidewall of the ohmic contact layer 228a,
and the dielectric layer 232 and the ohmic contact layer 228a are
not overlapped.
[0036] Please refer to FIG. 2G. Afterwards, a source 234 and a
drain 236 are formed on a portion of the dielectric layer 232 and
on a portion of the ohmic contact layer 228a, and a portion of the
ohmic contact layer 228a that is not covered by the source 234 or
the drain 236 is removed. As shown in FIG. 2G, the source 234 and
the drain 236 are formed by a third photolithography and etch
process (3rd PEP), and the 3rd PEP process is a half-tone mask
(HTM) process, a grayscale mask (GM) process, or a slit mask (SM)
process, so that in the present embodiment, the number of
photolithography and etch processes that are used is further
reduced, thereby reducing the fabrication cost and time. Please
refer to FIG. 2H. Last, a passivation layer 238 which covers the
source 234, the drain 236, a portion of the dielectric layer 232
and a portion of the channel layer 226a is formed, so as to protect
the thin film transistor 220.
[0037] As shown in FIG. 2H, the thin film transistor 220 is a
bottom-gate thin film transistor and has the gate 222, the gate
insulating layer 224, the channel layer 226a, the ohmic contact
layer 228a, the dielectric layer 232, the source 234, the drain
236, and the passivation layer 238. The gate 222 is below the
channel layer 226a. The gate insulating layer 224 is disposed
between the gate 222 and the channel layer 226a. The ohmic contact
layer 228a is disposed on a portion of the upper surface of the
channel layer 226a. The dielectric layer 232 is disposed on the
sidewall of the channel layer 226a, and the dielectric layer 232
and ohmic contact layer 228a are in contact but are not overlapped.
The source 234 and the drain 236 are disposed on portions of the
ohmic contact layer 228a and the dielectric layer 232, and a
portion of the dielectric layer 232 is not covered by the source
234 and the drain 236. The passivation layer 238 covers the source
234, the drain 236, a portion of the dielectric layer 232, and a
portion of the channel layer 226a.
Second Embodiment
[0038] FIGS. 3A to 3I are schematic cross-sectional views showing a
process of fabricating a thin film transistor according to the
second embodiment of the invention. Please refer to FIG. 3A. The
fabrication method of a thin film transistor 320 according to the
present embodiment includes the following steps. First, a buffer
layer 322 is formed on a substrate 310, wherein the material of the
buffer layer 322 may be a dielectric material such as silicon oxide
or silicon nitride.
[0039] Please refer to FIGS. 3B to 3D. Next, a channel material
layer 324, an ohmic contact material layer 326, and a patterned
photoresist layer 328 are sequentially formed on the buffer layer
322, wherein the material of the channel material layer 324 may be
amorphous silicon or polysilicon (poly-Si). Similarly, by using the
patterned photoresist layer 328 as a mask, the channel material
layer 324 and the ohmic contact material layer 326 are patterned,
so that a channel layer 324a and an ohmic contact layer 326a
between the channel layer 324a and the patterned photoresist layer
328 are formed. Then, a dielectric layer 330 is formed on the
patterned photoresist layer 328, a sidewall of the channel layer
324a, a sidewall of the ohmic contact layer 326a, and a portion of
the buffer layer 322.
[0040] Please refer to FIGS. 3E and 3F. Next, the patterned
photoresist layer 328 and a portion of the dielectric layer 330
which is in contact with the patterned photoresist layer 328 are
removed, so that the ohmic contact layer 326a is exposed. After the
patterned photoresist layer 328 is removed, the dielectric layer
330 is connected to the sidewall of the ohmic contact layer 326a,
and the dielectric layer 330 and the ohmic contact layer 326a are
not overlapped. Afterwards, a source 332 and a gate 334 are formed
on a portion of the dielectric layer 330 and on a portion of the
ohmic contact layer 326a, and a portion of the ohmic contact layer
326a that is not covered by the source 332 or the drain 334 is
removed.
[0041] Please refer to FIGS. 3G to 3I. Next, a gate insulating
layer 336 is formed on the substrate 310, so as to cover the source
332, the drain 334, a portion of the dielectric layer 330, and a
portion of the channel layer 326a. Then, a gate 338 is formed on
the gate insulating layer 336, wherein the gate 338 is above the
channel layer 324a. Last, a passivation layer 340 is formed to
cover the gate 338 and the gate insulating layer 336.
[0042] As shown in FIG. 31, the thin film transistor 320 is a
top-gate thin film transistor and has the buffer layer 322, the
channel layer 324a, the ohmic contact layer 326a, the dielectric
layer 330, the source 332, the drain 334, the gate 338, and the
passivation layer 340. The buffer layer 322 is between the
dielectric layer 330 and the substrate 310 and between the channel
layer 324a and the substrate 310. The ohmic contact layer 326a is
disposed on a portion of the upper surface of the channel layer
324a. The dielectric layer 330 is disposed on the sidewall of the
channel layer 324a, and the dielectric layer 330 and ohmic contact
layer 326a are in contact but are not overlapped. The source 332
and the drain 334 are disposed on portions of the ohmic contact
layer 326a and the dielectric layer 330, and a portion of the
dielectric layer 330 is not covered by the source 332 and the drain
334. The gate 338 is above the channel layer 324a. The gate
insulating layer 336 is disposed between the gate 338 and the
channel layer 324a, and covers the source 332, the drain 334, a
portion of the dielectric layer 330, and a portion of the channel
layer 324a. The passivation layer 340 covers the gate 338 and the
gate insulating layer 336.
[0043] It should be noted that when the material of the channel
layer 324a is amorphous silicon, the buffer layer 332 may be
omitted in the structure of the thin film transistor 320, meaning
that the step of forming the buffer layer 332 may be omitted to
directly form the channel layer 324a on the substrate 310, and that
a portion of the dielectric layer 330 covers the substrate 310.
[0044] In summary, the thin film transistors and the fabricating
methods thereof according to the embodiments of the invention are
effective in inhibiting leakage currents. In addition, since
patterning of the dielectric layer may be accomplished by a
lift-off process, manufacturing cost and time are reduced.
[0045] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
invention without departing from the scope or spirit of the
invention. In view of the foregoing, it is intended that the
present invention cover modifications and variations of this
invention provided they fall within the scope of the following
claims and their equivalents.
* * * * *