U.S. patent application number 13/485749 was filed with the patent office on 2012-09-20 for two-stage block synchronization and scrambling.
This patent application is currently assigned to BROADCOM CORPORATION. Invention is credited to Scott Richard Powell, Ba-Zhong Shen, Gottfried Ungerboeck.
Application Number | 20120237032 13/485749 |
Document ID | / |
Family ID | 35708394 |
Filed Date | 2012-09-20 |
United States Patent
Application |
20120237032 |
Kind Code |
A1 |
Ungerboeck; Gottfried ; et
al. |
September 20, 2012 |
TWO-STAGE BLOCK SYNCHRONIZATION AND SCRAMBLING
Abstract
A two-stage block synchronization and scrambling module includes
a synchronization PRNG module, a scramble PRNG module, a summing
module, and a storage module. The synchronization PRNG module is
clocked once per N+1 bit PCS frame (N arbitrary) to produce a
synchronization bit and a pseudo-random starting state for the
scramble PRNG. The scramble PRNG module is clocked N times per PCS
frame to produce a cipher stream starting with a pseudo-random
state from the synchronization PRNG. The summing module is operably
coupled to sum the cipher stream and a PCS frame payload to produce
scrambled payload. The storage module is operably coupled to store
the scrambled payload with the synchronization bit. Synchronization
bits from successive frames are a running bit-serial representation
of the synchronization PRNG state and are used by the receiver to
synchronize with the transmit scrambler.
Inventors: |
Ungerboeck; Gottfried;
(Langnau am Albis, CH) ; Powell; Scott Richard;
(Aliso Viejo, CA) ; Shen; Ba-Zhong; (Irvine,
CA) |
Assignee: |
BROADCOM CORPORATION
Irvine
CA
|
Family ID: |
35708394 |
Appl. No.: |
13/485749 |
Filed: |
May 31, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11255698 |
Oct 21, 2005 |
8213611 |
|
|
13485749 |
|
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|
60624557 |
Nov 3, 2004 |
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Current U.S.
Class: |
380/268 |
Current CPC
Class: |
H04L 25/03866
20130101 |
Class at
Publication: |
380/268 |
International
Class: |
H04L 9/12 20060101
H04L009/12; H04L 9/16 20060101 H04L009/16 |
Claims
1. A method for execution by a receive module, comprising:
receiving, by the receive module, a frame via a transmission
medium, the frame including a synchronization bit and a scrambled
payload; producing state bits from the synchronization bit and
previously received synchronization bits in previously received
frames by the receive module; producing N stream descrambling bits
based on the state bits for the frame by the receive module; and
combining the N stream descrambling bits with the scrambled payload
of the frame to obtain N payload bits.
2. The method of claim 1, wherein the combining the N stream
descrambling bits with the scrambled payload of the frame
comprises: modulo-2 adding the N stream descrambling bits with the
scrambled payload of the frame to obtain the N payload bits.
3. The method of claim 1, wherein: the producing the state bits for
the frame is performed via a recover-synchronization Pseudo Random
Number Generation process; and the producing the N stream
descrambling bits is performed via a descramble Pseudo Random
Number Generation process that is initialized with the state bits
and clocked N times per frame.
4. The method of claim 3, wherein the recover-synchronization
Pseudo Random Number Generation process comprises: performing a
continuously operating Maximum-Length Shift Register (MLSR)
function with primitive-polynomial feedback of degree m to produce
a pseudo random binary sequence with period length 2.sup.m-1 that
includes 2.sup.m-1 ones and 2.sup.m-1-1 zeros, wherein the state
bits include m preceding output bits, and, within one period,
m-tuple of the state bits cycles through 2.sup.m-1 non-zero binary
m-tuples.
5. The method of claim 3, wherein the descramble Pseudo Random
Number Generation process comprises: performing a continuously
operating Maximum-Length Shift Register (MLSR) function with
primitive-polynomial feedback of degree m to produce a pseudo
random binary sequence with period length 2.sup.m-1 that includes
2.sup.m-1 ones and 2.sup.m-1-1 zeros, wherein m state bits include
m preceding output bits, and, within one period, m-tuple of them
state bits cycles through 2.sup.m-1 non-zero binary m-tuples.
6. The method of claim 3, further comprising: initializing the
descramble Pseudo Random Number Generation process at a starting
point of subsequence of the N scrambling bits within a
2.sup.m2-1-periodic sequence in accordance with a continuous
operation, where, for given primitive polynomials, transfer of the
state bits from the recover-synchronization Pseudo Random Number
Generation process to the descramble Pseudo Random Number
Generation process occurs in a manner such that the subsequences of
the N descrambling bits start at pseudo-randomly distributed
starting points, which include the starting point.
7. The method of claim 6, further comprising: reversing order of
the state bits transferred from the recover-synchronization Pseudo
Random Number Generation process to the descramble Pseudo Random
Number Generation process when the given primitive polynomials
includes two primitive polynomials that are identical with degree
m; generating a 2.sup.m-1-periodic sequence by the
recover-synchronization Pseudo Random Number Generation process;
and producing, by the descramble Pseudo Random Number Generation
process, the subsequences of length N starting at pseudo-randomly
distributed points within the 2.sup.m-1-periodic sequence, wherein
the state bits produced via the recover-synchronization Pseudo
Random Number Generation process cycle through 2.sup.m-1 non-zero
binary m-tuples and length-N subsequences includes 2.sup.m-1
starting points.
8. The method of claim 6, further comprising: maintaining order of
transferring the state bits from the recover-synchronization Pseudo
Random Number Generation process to the descramble Pseudo Random
Number Generation process when the given primitive polynomials
includes two primitive polynomials of same degree m with
time-reversed coefficients relative to each of the two primitive
polynomials.
9. The method of claim 1, further comprising: utilizing a fly-wheel
technique to recover the state bits reliably in the presence of
transmission errors.
10. A receive module, comprising: a synchronization and descramble
module coupled to receive a frame including a synchronization bit
and a scrambled payload, produce state bits from the
synchronization bit and previously received synchronization bits
from previously received frames, produce N stream descrambling bits
based on the state bits for the frame by the receive module and
combine the N stream descrambling bits with the scrambled payload
of the frame to obtain N payload bits; and a frame recovery module
coupled to receive the N payload bits and recover the frame using
the N payload bits.
11. The receive module of claim 10, wherein the synchronization and
descramble module comprises: a modulo-2 adder coupled to add the N
stream descrambling bits with the scrambled payload of the
frame.
12. The receive module of claim 10, wherein the synchronization and
descramble module comprises: a recover-synchronization Pseudo
Random Number Generator (PRNG) for generating the state bits for
the frame from the synchronization bit and the previously received
synchronization bits; and a descramble Pseudo Random Number
Generator (PRNG), the descramble PRNG being initialized with the
state bits and clocked N times per frame to generate the N stream
descrambling bits.
13. The receive module of claim 12, wherein the
recover-synchronization Pseudo Random Number Generator further
comprises: a continuously operating Maximum-Length Shift Register
(MLSR) with primitive-polynomial feedback of degree m to produce a
pseudo random binary sequence with period length 2.sup.m-1 that
includes 2.sup.m-1 ones and 2m.sup.-1-1 zeros, wherein the state
bits include m preceding output bits, and, within one period,
m-tuple of the state bits cycles through 2.sup.m-1 non-zero binary
m-tuples.
14. The receive module of claim 12, wherein the descramble Pseudo
Random Number Generator further comprises: a continuously operating
Maximum-Length Shift Register (MLSR) with primitive-polynomial
feedback of degree m to produce a pseudo random binary sequence
with period length 2.sup.m-1 that includes 2.sup.m-1 ones and
2.sup.m-1-1 zeros, wherein m state bits include m preceding output
bits, and, within one period, m-tuple of the m state bits cycles
through 2.sup.m-1 non-zero binary m-tuples.
15. The receive module of claim 12, wherein the descramble Pseudo
Random Number Generator further functions to: initialize at a
starting point of subsequence of the N descrambling bits within a
2.sup.m2-1-periodic sequence in accordance with a continuous
operation, where, for given primitive polynomials, transfer of the
state bits from the recover-synchronization Pseudo Random Number
Generator to the descramble Pseudo Random Number Generator occurs
in a manner such that the subsequences of the N descrambling bits
start at pseudo-randomly distributed starting points, which
including the starting point.
16. The receive module of claim 12, wherein the
recover-synchronization Pseudo Random Number Generator further
functions to: reverse order of the state bits transferred to the
descramble Pseudo Random Number Generator when the given primitive
polynomials includes two primitive polynomials that are identical
with degree m; generate a 2.sup.m-1-periodic sequence; and produce
the subsequences of length N starting at pseudo-randomly
distributed points within the 2.sup.m-1-periodic sequence, wherein
the state bits cycle through 2.sup.m-1 non-zero binary m-tuples and
length-N subsequences includes 2.sup.m-1 starting points.
17. The receive module of claim 12, wherein the
recover-synchronization Pseudo Random Number Generator further
functions to: maintain order of transferring the state bits to the
descramble Pseudo Random Number Generator when the given primitive
polynomials includes two primitive polynomials of same degree m
with time-reversed coefficients relative to each of the two
primitive polynomials.
18. A synchronization and descrambling module comprises: a frame
storage module for receiving a currently received frame via a
transmission medium, the currently received frame including a
synchronization bit and a scrambled payload; a
recover-synchronization pseudo random number generator (PRNG)
module for receiving the synchronization bit from the currently
received frame and previously received synchronization bits from
previously received frames and producing state bits from the
synchronization bit and the previously received synchronization
bits; a descramble PRNG module clocked N times per PCS frame to
produce a cipher stream based on the state bits; and a summing
module operably coupled to sum the cipher stream and the scrambled
payload of the currently received frame to obtain a PCS frame
payload.
19. The synchronization and descrambling module of claim 18,
wherein the recover-synchronization PRNG comprises: a continuously
operating Maximum-Length Shift Register (MLSR) with
primitive-polynomial feedback of degree m to produce a pseudo
random binary sequence with period length 2.sup.m-1 that includes
2.sup.m-1 ones and 2.sup.m-1-1 zeros, wherein the state bits
include m preceding output bits, and, within one period, m-tuple of
the state bits cycles through 2.sup.m-1 non-zero binary
m-tuples.
20. The synchronization and descrambling module of claim 18,
wherein the descramble PRNG comprises: a continuously operating
Maximum-Length Shift Register (MLSR) with primitive polynomial
feedback of degree m to produce a pseudo random binary sequence
with period length 2.sup.m-1 that includes 2.sup.m-1 ones and
2.sup.m-1-1 zeros, wherein m state bits include m preceding output
bits, and, within one period, m-tuple of the m state bits cycles
through 2.sup.m-1 non-zero binary m-tuples.
Description
CROSS REFERENCE TO PRIORITY APPLICATIONS
[0001] The present U.S. Utility Patent Application claims priority
pursuant to 35 U.S.C. .sctn.120, as a continuation, to the
following U.S. Utility Patent Application which is hereby
incorporated herein by reference in its entirety and made part of
the present U.S. Utility Patent Application for all purposes:
[0002] 1. U.S. Utility application Ser. No. 11/255,698, entitled,
"Two-Stage Block Synchronization and Scrambling" (Attorney Docket
No. BP4242), filed Oct. 21, 2005, pending, which claims priority
pursuant to 35 U.S.C .sctn.119(e) to the following U.S. Provisional
Patent Application which is hereby incorporated herein by reference
in its entirety and made part of the present U.S. Utility Patent
Application for all purposes: [0003] a. U.S. Provisional
Application Ser. No. 60/624,557, entitled, "Two-Stage Block
Synchronization and Scrambling" (Attorney Docket No. BP4242), filed
Nov. 3, 2004.
BACKGROUND OF THE INVENTION
[0004] 1. Technical Field of the Invention
[0005] This invention relates generally to data communications and
more particularly to synchronization and scrambling of frames of
Ethernet data communications.
[0006] 2. Description of Related Art
[0007] As is known, Ethernet is a standard that defines data
conveyance protocols for data transmissions and has multiple
variations thereof depending on desired data rates and transmission
mediums. For example, Ethernet standards include 10 BASE-T (10
megabit-per-second (Mbps) data rate over a twisted pair), 10 BASE-F
(10 Mbps over a fiber optic cable), 100 BASE-TX (100 Mbps over
twisted pairs), 100 BASE-FX (100 Mbps over a fiber optic cable),
1000 BASE-T (1 gigabit-per-second (Gbps) over twisted pairs), 1000
BASE-X (1 Gbps over fiber optic cables), and 10GBase-T (10 Gbps
over twisted pairs).
[0008] As is also known, an Ethernet protocol is often used in a
wired local area network (LAN), which typically has a star
topology, ring topology, bus topology or hub/tree topology. A star
topology LAN typically includes a private automatic branch exchange
(PABX) and/or a private digital exchange (PDX) to switch voice
and/or data between end user devices and/or data terminal equipment
(DTE). A ring topology LAN passes cable access from one user to
another until the users are interconnected in a loop or ring. A bus
topology LAN typically employs one of the Ethernet protocols to
convey data within the network. A hub technology LAN is essentially
a bus or ring topology with the wiring to a central unit.
[0009] Regardless of the LAN topology, transmitted data must be
randomized for proper timing recovery and synchronization. Data
randomization is typically accomplished by adding digitally
generated pseudo-random sequences to the data--a process known as
scrambling. The pseudo-random sequences repeat after a large number
of clock cycles and can either be of self-synchronizing or
cipher-stream type. Self-synchronizing scramblers have the well
known disadvantage of error propagation. Cypher-stream scramblers
require a synchronization scheme and, in frame (or block) based
transmission, must be synchronized with frame boundaries. If the
frame length is not equal to the repeat length of the pseudo-random
sequence, degradation of the sequence statistics can occur. This
can lead to loss in performance and other undesirable
properties.
[0010] Therefore, a need exists for a method and apparatus which
permits cipher-stream scrambling to be used in frame based data
transmission systems with a method for synchronization and a method
for maintaining the desired random properties of the scrambling
sequence.
BRIEF SUMMARY OF THE INVENTION
[0011] The present invention is directed to apparatus and methods
of operation that are further described in the following Brief
Description of the Drawings, the Detailed Description of the
Invention, and the claims. Other features and advantages of the
present invention will become apparent from the following detailed
description of the invention made with reference to the
accompanying drawings.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0012] FIG. 1 is a schematic block diagram of a portion of a local
area network in accordance with the present invention;
[0013] FIG. 2 is a schematic block diagram of a portion of another
local area network in accordance with the present invention;
[0014] FIG. 3 is a schematic block diagram of a transceiving module
in accordance with the present invention;
[0015] FIG. 4 is a schematic block diagram of a synchronization and
scramble module in accordance with the present invention;
[0016] FIG. 5 is a schematic block diagram of a synchronization and
descramble module in accordance with the present invention;
[0017] FIG. 6 is a schematic block diagram of another embodiment of
a synchronization and scramble module in accordance with the
present invention; and
[0018] FIG. 7 is a schematic block diagram of yet another
embodiment of a synchronization and scramble module in accordance
with the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0019] In general, a two-stage block synchronization and scrambling
module includes a synchronization PRNG module, a scramble PRNG
module, a summing module, and a storage module. The synchronization
PRNG module is clocked once per N+1 bit PCS frame (N arbitrary) to
produce a synchronization bit and a pseudo-random starting state
for the scramble PRNG. The scramble PRNG module is clocked N times
per PCS frame to produce a cipher stream starting with a
pseudo-random state from the synchronization PRNG. The summing
module is operably coupled to sum the cipher stream and a PCS frame
payload to produce scrambled payload. The storage module is
operably coupled to store the scrambled payload with the
synchronization bit. Synchronization bits from successive frames
are a running bit-serial representation of the synchronization PRNG
state and are used by the receiver to synchronize with the transmit
scrambler.
[0020] FIG. 1 is a schematic block diagram of a portion of a local
area network (LAN) that includes a first device 12, a second device
14, and a LAN connection 16. The LAN connection 16 provides local
area network connectivity for the first and second devices 12 and
14 to a local area network. Such a local area network may be
configured as a star topology, a ring topology, a bus topology or a
hub/tree topology.
[0021] Each of the devices 12 and 14 may be a computer, a printer,
a filer server, a web server, an email server, an application
server, and/or any other type of server including terminal servers.
Regardless of the particular construct of the devices 12 and 14,
each device 12 and 14 includes a processing module 18, 28, memory
20, 30, and a transceiving module 22, 32. Each of the processing
modules 18, 28 may be a single processing device or a plurality of
processing devices. Such a processing device may be a
microprocessor, micro-controller, digital signal processor,
microcomputer, central processing unit, field programmable gate
array, programmable logic device, state machine, logic circuitry,
analog circuitry, digital circuitry, and/or any device that
manipulates signals (analog and/or digital) based on operational
instructions. The memory 20, 30 may be a single memory device or a
plurality of memory devices. Such a memory device may be a
read-only memory, random access memory, volatile memory,
non-volatile memory, static memory, dynamic memory, flash memory,
cache memory, and/or any device that stores digital information.
Note that when the processing module 18, 28 implements one or more
of its functions via a state machine, analog circuitry, digital
circuitry, and/or logic circuitry, the memory storing the
corresponding operational instructions may be embedded within, or
external to, the circuitry comprising the state machine, analog
circuitry, digital circuitry, and/or logic circuitry.
[0022] Each of the transceiving modules 22, 32 includes a transmit
module 24, 34, and a receive module 26, 36. The transmit module 24,
34, which will be described in greater detail with reference to
FIGS. 3, 4, 6 and 7, is operably coupled to transmit scrambled and
synchronized frames on the LAN connection 16, where the scrambling
and synchronization is in accordance with the present invention and
the frame formatting is in accordance with one or more LAN standard
or other proprietary scheme. For example, the frame formatting may
be in accordance with IEEE P802.3 an (10GBASE-T), which prescribes
a 10Gbps Ethernet operation over 4 wire twisted pair.
[0023] The receive module 26, 36, which will be described in
greater detail with reference to FIGS. 3 and 5, is operably coupled
to receive scrambled and synchronized frames on the LAN connection
16, where the scrambling and synchronization is in accordance with
the present invention and the frame formatting is in accordance
with one or more LAN standard or other proprietary scheme. Upon
receiving the scrambled and synchronized frames, the receive module
26, 36 descrambles the frames to recover the original frames.
[0024] FIG. 2 is a schematic block diagram of a portion of another
LAN that includes devices 12 and 14 coupled to a switch/router 25
via LAN connections 16. Such a LAN may be a data center that may be
connected to other networks. Generally, a data center may be viewed
as a cluster of relatively high powered and capable processors
(i.e., the devices 12 and 14) that may include any one or more of a
filer server, a web server, an email server, an application server,
and/or any other type of server including terminal servers that are
configured in a star type configuration to an Ethernet
switch/router 25. The data center may be located in a region such
as a building, a campus, or some other finite locale in which a
number of networks interface and from which a number of end users
are serviced. The Ethernet switch/router 25 may also be
communicatively coupled to the Internet itself (via any appropriate
firewall and Internet-adapted WAN (Wide Area Network) router), or
any other WAN as well.
[0025] In such data centers, a common means of connectivity between
devices is via hard cabling. The IEEE P802.3an (10GBASE-T) Task
Force has been particularly commissioned to develop and standardize
a copper 10 Giga-bit Ethernet standard that runs over 4 wire
twisted pair cables. This is particularly appropriate for data
center applications including the connectivity between end-devices
(e.g., any of the servers depicted above and/or network
authentication servers) and an Ethernet switch/router within the
data center. Such interconnectivity requires very high speed
operation for proper support of the traffic within and through the
data center.
[0026] FIG. 3 is a schematic block diagram of a transceiving module
22, 32 that includes the transmit module 24, the receive module 26,
and an optional splitter 45. In one embodiment, the transceiving
module 22, 32 functions in a half duplex mode, where the splitter
operably couples the transmit module 24 to the LAN connection 16
when the transceiving module 24, 34 is in a transmit mode and
couples the receive module 26, 36 to the LAN connection 16 when the
transceiving module 24, 34 is in a receive mode. In another
embodiment, the transceiving module 22, 32 functions in a full
duplex module such that the splitter is eliminated and the transmit
module 24, 34 and the receive module 26, 36 are independently
coupled to the LAN connection 16. For example, each coupling may
include a twisted pair.
[0027] As is also shown, the transmit module 24 includes a
synchronization and scramble module 40 and a PCS (physical coding
sublayer) frame generating module 42. The PCS frame generating
module 42 is operably coupled to generate PCS frame payloads from
data it receives from the processing module of the associated
device. The PCS frame generating module 42 may generate the PCS
frame payload in accordance with one or more Ethernet protocols
including, but not limited to, IEEE P802.3an (10GBASE-T).
[0028] The synchronization and scramble module 40 is operably
coupled to scramble the PCS frame payload and to provide
corresponding synchronization information to produce the scrambled
and synchronized frames that are transmitted on the LAN connection
16. In one embodiment, the corresponding synchronization
information is a synchronization bit generated per frame of the
scrambled PCS frame payload. The synchronization and scramble
module 40 will be described in greater detail with reference to
FIGS. 4, 6 and 7.
[0029] The receive module 26, 36 includes a synchronization and
descramble module 44 and a PCS frame recovery module 46. The
synchronization and descramble module 44 is operably coupled to
receive scrambled and synchronized frames and, based on the
synchronization information, descramble the scrambled and
synchronized frames to produce recovered frames. The PCS frame
recovery module 46 receives the recovered frames and recovers
original data therefrom in accordance with a standard to which the
original frames were created. For example, the standard may be one
or more versions of the Ethernet standard including, but not
limited to, IEEE P802.3an (10GBASE-T).
[0030] FIG. 4 is a schematic block diagram of an embodiment of the
synchronization and scramble module 40 that includes a
synchronization pseudo random noise generator (PRNG) module 50, a
scramble PRNG module 52, a summing module 54, and a storage module
56. The synchronization PRNG module 50 is clocked once per PCS
frame to generate and insert a synchronization bit 58 per PCS
frame. Synchronization bits from successive frames are a running
bit-serial representation of the state of the synchronization PRNG
in the transmitter. This enables verification of PCS frame
synchronization and fly-wheel re-synchronization in the receive
module 26, 36. In addition, the synchronization PRNG module 50
generates state information 60 to indicate at least an initial
pseudo-random starting point of the pseudo random noise
sequence.
[0031] The scramble PRNG module 52, which is clocked once for each
bit (or symbol) in the PCS frame, generates a cipher-scrambling
sequence (i.e., a cipher stream) 62 for use within PCS frames. The
cipher-scrambling sequence may be modulo-2 added to a PCS
payload.
[0032] The summing module 54 is operably coupled to sum a PCS
(physical coding sublayer) frame payload 64 with the cipher stream
62 to produce a scrambled payload 66.
[0033] The storage module 56 is operably coupled to store the
scrambled payload 66 in accordance with the synchronization bit 58.
In the transmit mode, the synchronized and scrambled data frame is
read from the storage module 56 and provided on the LAN connection
16. Note that storing and reading operations can proceed in
parallel such that the entire PCS frame need not be physically
stored.
[0034] FIG. 5 is a schematic block diagram of an embodiment of the
synchronization and descramble module 44 that includes a recover
synchronization PRNG module 70, a descramble PRNG module 72, a
subtraction module 74, and a storage module 76. In general, the
operation of the synchronization and descramble module 44 is the
inverse of the operation of the synchronization and scramble module
40.
[0035] In operation, the synchronized and scrambled data frame
received via the LAN connection 16 is stored in the storage module
76. The recover synchronization PRNG module 70 receives a
resynchronization bit 78, which corresponds to the synchronization
bit inserted into the PCS frame and is a running bit-serial
representation of the state of transmitter synchronization PRNG 50.
Based thereon, the receiver synchronization PRNG 70 can be
synchronized with the transmitter PRNG 50 to generate state
information 80. The descramble PRNG module 72 uses the state
information 80 to produce a cipher-descrambling sequence (i.e., a
decipher stream) 82 for interpreting the scrambled PCS frames. The
cipher-descrambling sequence may be mod-2 added to a PCS payload
and will correspond to the cipher-scrambling sequence produced by
the scramble PRNG module 52.
[0036] The subtraction module 74 subtracts the decipher stream 82
from the scrambled payload 86 to produce recovered PCS frame
payload 88. As one of ordinary skill in the art will appreciate,
the summing module 54 and the subtraction module 74 may be more
complex mathematical function elements. For example, the summing
module 54 may perform an interleave function and the subtraction
module 74 may perform the corresponding deinterleaving function. As
a further example, the summing module 54 may function as an encoder
where the PCS frame is encoded based on the cipher stream 62 and
the subtraction module 74 may be a decoder decoding the scrambled
payload based on the decipher stream 82 to recover a PCS frame.
Further, the summing modules 54 and 74 may implement finite field
arithmetic in the case of multi-bit scrambling schemes.
[0037] FIG. 6 is a schematic block diagram of an embodiment of the
synchronization and scramble module 40 that includes a 1.sup.st
production module 90, a 2.sup.nd production module 92, a combining
module 94, and the storage module 56. In general, the
synchronization and scramble module 40 may be used in any system in
which information is transmitted in frames. For every frame, the
synchronization and scramble module 40 conveys one synchronization
bit 100, N payload bits 104 and other bits onto the LAN connection.
The 1.sup.st production module 90 produces a new synchronization
bit 100 for each frame and thereby transitions to a new state.
Further at the beginning of each frame, the 2.sup.nd production
module 92 is initialized with state bits 98 of theist production
module 90. The 2.sup.nd production module 92 is then clocked N
times to produce N stream scrambling bits 102, which are combined
with N payload bits 104 of the frame by the combining module to
produce a scrambled frame 106. The storage module 56 stores the
scramble module 56 for subsequent transmission on the LAN
connection.
[0038] FIG. 7 is a schematic block diagram of an embodiment of the
synchronization and scramble module 40 that includes a 1.sup.st
production module 90, a 2.sup.nd production module 92, a combining
module 94, and the storage module 56. In this embodiment, the
1.sup.St production module 90 may be realized by a synchronization
pseudo random number generator (PRNG) module 52, which may include
a continuously operating Maximum Length Shift Register (MLSR) 110;
the 2.sup.nd production module 92 may be realized by a scramble
PRNG module 52, which may include a continuously operating Maximum
Length Shift Register (MLSR) 112; and the combining module 94 may
include a modulo-2 adder 114.
[0039] In this embodiment, the Maximum-Length Shift Registers
(MLSR) 110 and 112 have feedback connections that are determined by
primitive polynomials of degree m.sub.1 and m.sub.2, respectively,
where m.sub.1 and m.sub.2 may be identical. The continuously
operating MLSR 110 and 112, with primitive-polynomial feedback of
degree m, generates a pseudo random binary sequence with period
length 2.sup.m-1 comprising 2.sup.m-1 ones and 2.sup.m-1-1 zeros.
The m state bits are the m preceding output bits, and within one
period the m-tuple of state bits cycles through all 2.sup.m-1
non-zero binary m-tuples.
[0040] The initialization of the Scramble PRNG 52 defines the
starting point of the subsequence of N scrambling bits within the
2.sup.m.sup.21-periodic sequence that would be produced in
continuous operation. For given primitive polynomials, the transfer
of state bits from the Synchronization PRNG 50 to the Scramble PRNG
52 should occur in a manner such that the subsequences of N
scrambling bits start at pseudo-randomly distributed starting
points. This can be accomplished in various ways. One possibility
is to let the two primitive polynomials be identical with degree m,
and reverse the order of the m state bits transferred from the
Synchronization PRNG 50 to the Scramble PRNG 52. Then the
Synchronization PRNG 50 generates a 2.sup.m-1-periodic sequence,
and the Scramble PRNG 52 produces subsequences of length N starting
at pseudo-randomly distributed points within the same
2.sup.m-1-periodic sequence. Since the state bits of the
Synchronization PRNG 50 cycle through all 2.sup.m-1 non-zero binary
m-tuples, the length-N subsequences will start all 2.sup.m-1
possible starting points. The m-bit state of the synchronization
PRNG 50 is transmitted in a bit-serial manner, one bit per frame,
as the synchronization bit 58,100.
[0041] A similar effect will be achieved by choosing two primitive
polynomials of same degree m with time-reversed coefficients
relative to each other, and not reversing (i.e., maintained) the
order of the transferred m state bits. The list of choices may be
continued, for example, with pairs of primitive polynomials of same
degree and non-time reversed coefficients, or primitive polynomials
of different degrees and various ways to transfer state bits.
[0042] As one of ordinary skill in the art will appreciate, the
term "substantially" or "approximately", as may be used herein,
provides an industry-accepted tolerance to its corresponding term
and/or relativity between items. Such an industry-accepted
tolerance ranges from less than one percent to twenty percent and
corresponds to, but is not limited to, component values, integrated
circuit process variations, temperature variations, rise and fall
times, and/or thermal noise. Such relativity between items ranges
from a difference of a few percent to magnitude differences. As one
of ordinary skill in the art will further appreciate, the term
"operably coupled", as may be used herein, includes direct coupling
and indirect coupling via another component, element, circuit, or
module where, for indirect coupling, the intervening component,
element, circuit, or module does not modify the information of a
signal but may adjust its current level, voltage level, and/or
power level. As one of ordinary skill in the art will also
appreciate, inferred coupling (i.e., where one element is coupled
to another element by inference) includes direct and indirect
coupling between two elements in the same manner as "operably
coupled". As one of ordinary skill in the art will further
appreciate, the term "compares favorably", as may be used herein,
indicates that a comparison between two or more elements, items,
signals, etc., provides a desired relationship. For example, when
the desired relationship is that signal 1 has a greater magnitude
than signal 2, a favorable comparison may be achieved when the
magnitude of signal 1 is greater than that of signal 2 or when the
magnitude of signal 2 is less than that of signal 1.
[0043] The preceding discussion has presented a method and
apparatus for synchronizing and scrambling frames within an
Ethernet-based network. As one of ordinary skill in the art will
appreciate, other embodiments may be derived from the teachings of
the present invention without deviating from the scope of the
claims.
* * * * *