U.S. patent application number 13/476605 was filed with the patent office on 2012-09-13 for copyback optimization for memory system.
This patent application is currently assigned to APPLE INC.. Invention is credited to Mark Alan Helm, Nir Jacob Wakrat.
Application Number | 20120233387 13/476605 |
Document ID | / |
Family ID | 40801795 |
Filed Date | 2012-09-13 |
United States Patent
Application |
20120233387 |
Kind Code |
A1 |
Wakrat; Nir Jacob ; et
al. |
September 13, 2012 |
Copyback Optimization for Memory System
Abstract
In a copyback or read operation for a non-volatile memory
subsystem, data page change indicators are used to manage transfers
of data pages between a register in non-volatile memory and a
controller that is external to the non-volatile memory.
Inventors: |
Wakrat; Nir Jacob; (San
Jose, CA) ; Helm; Mark Alan; (Santa Cruz,
CA) |
Assignee: |
APPLE INC.
Cupertino
CA
|
Family ID: |
40801795 |
Appl. No.: |
13/476605 |
Filed: |
May 21, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12193638 |
Aug 18, 2008 |
8185706 |
|
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13476605 |
|
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61049330 |
Apr 30, 2008 |
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Current U.S.
Class: |
711/103 ;
711/E12.008 |
Current CPC
Class: |
G06F 11/1068
20130101 |
Class at
Publication: |
711/103 ;
711/E12.008 |
International
Class: |
G06F 12/02 20060101
G06F012/02 |
Claims
1. A method comprising: obtaining a data page from non-volatile
memory of a memory subsystem; determining if the data page has
changed; and if the data page has changed, sending the data page to
a controller for processing; if the data page is unchanged, sending
metadata associated with the data page to the controller for
processing.
Description
RELATED APPLICATION
[0001] This application is a continuation (and claims the benefit
of priority under 35 USC 120) of U.S. application Ser. No.
12/193,638, filed Aug. 18, 2008, now allowed, which claims the
benefit of priority from U.S. Provisional Application No.
61/049,330, for "Copyback Optimization for Memory System," filed
Apr. 30, 2008. Both of these prior applications are incorporated by
reference herein in their entirety.
TECHNICAL FIELD
[0002] This subject matter is generally related to memory
systems.
BACKGROUND
[0003] Flash memory is a type of electrically erasable programmable
read-only memory (EEPROM). Because flash memories are non-volatile
and relatively dense, they are used to store files and other
persistent objects in handheld computers, mobile phones, digital
cameras, portable music players, and many other devices in which
other storage solutions (e.g., magnetic disks) are inappropriate.
When data stored in flash memory is processed, a data page is read
out of flash memory and stored in a register. The register contents
is transferred to a controller that is external to the non-volatile
memory for processing. The processed data page is placed back in
the register so that the processed data page can be written back to
flash memory.
SUMMARY
[0004] In a copyback or read operation for a non-volatile memory
subsystem, data page change indicators are used to manage transfers
of data pages between a register in non-volatile memory and a
controller that is external to the non-volatile memory.
DESCRIPTION OF DRAWINGS
[0005] FIG. 1A is a block diagram of an example memory system for
implementing an optimized copyback process.
[0006] FIG. 1B is a block diagram of another example memory system
for implementing an optimized copyback process.
[0007] FIG. 2 is a flow diagram of an example optimized copyback
process 200 for computing and storing data change indicators used
by the memory systems of FIGS. 1A and 1B.
[0008] FIGS. 3A-3C are flow diagrams of an example optimized
copyback process implemented by the memory systems of FIGS. 1A and
1B.
[0009] FIG. 4 is a flow diagram of an example optimized read
operation implemented by the memory systems of FIGS. 1A and 1B.
[0010] FIG. 5 illustrates example data structures used by the
copyback process of FIGS. 3A-3C.
DETAILED DESCRIPTION
Examples of Memory Subsystems
[0011] FIG. 1A is a block diagram of an example memory system 100
for implementing an optimized copyback process. In some
implementations, the system 100 can include a memory subsystem 102
coupled to a host device 124 through an external bus 122 (e.g.,
Open NAND Flash Interface (ONFI), ATA). The host device 124 can be
any electronic device including but not limited to smart phones,
media players, text messaging devices, portable computers, solid
state drives, digital cameras, etc. The memory subsystem 102 can be
any non-volatile memory subsystem (e.g., managed NAND).
[0012] The host device 124 can include a system-on-chip (SoC) 126
and volatile memory 128. The SoC 126 can include hardware and
software for interacting with the memory subsystem 102, such as
transmitting read and write requests made by applications running
on the host device 124.
[0013] The memory subsystem 102 can include non-volatile memory 104
(also referred to as "raw memory") and an external controller 116.
The memory 104 can include a memory cell array 106, an internal
state machine 108, a memory register 110 and data change indicator
(DCI) 130. The controller 116 can include a processor 118, volatile
memory 114 and error correction code (ECC) engine 120. Other
configurations for the memory subsystem 102 are possible. For
example, a cache register can be included in the data path between
the memory cell array 106 and the memory register 110 to allow the
internal state machine to read the next data page from the memory
cell array 106 while transferring the current page to the
controller 116 over internal bus 112.
[0014] FIG. 1B is a block diagram of another example memory system
130 for implementing an optimized copyback process. The system 130
shows only the memory subsystem 102, the operation of which was
described in reference to FIG. 1A.
Copyback Operations
[0015] Copyback can be a memory subsystem command to move data from
one page to another page. Copyback can be used in wear leveling and
other non-volatile memory management operations. In a typical
copyback operation, a data page is read from the memory cell array
106 and stored in the memory register 110 by the internal state
machine. The external controller 116 reads or clocks the data page
out of the memory register 110 so that the processor 118 can
perform a desired operation on the data page (e.g., an ECC
operation). The processed data page can be written back to the
memory register 110 by the controller 116. The internal state
machine 108 can write the contents of the memory register 110 into
a new data page in the memory cell array 106. By avoiding the
transfer of the entire contents of register 110 to the external
controller 116, processing times and power consumption can be
reduced.
Example Process For Writing New Data Pages
[0016] FIG. 2 is a flow diagram of an example optimized copyback
process 200 for computing and storing data change indicators used
by the memory systems of FIGS. 1A and 1B. In some implementations,
the process 200 can begin when new data page is transferred into a
memory register of a memory subsystem (202). A DCI can be computed
for the data page and stored in the memory subsystem (204). Some
examples of data change indicators can include error detection
codes (EDCs), including but not limited to: checksum, Hamming code,
parity bit, cyclic redundancy check (CRC), polarity symbol
reversal, Turbo code, etc. An EDC can also be part of an ECC, such
as Reed-Solomon code, Reed-Muller code, Binary Golay code, and
low-density parity-check codes. After the DCIs are computed and
stored, the register contents can be written to non-volatile memory
(206). DCIs can be used for the optimized copyback process
described in reference to FIGS. 3A-3C.
Example Optimized Copyback Process
[0017] FIGS. 3A-3C are flow diagrams of an example optimized
copyback process 300 implemented by the memory systems of FIGS. 1A
and 1B. In some implementations, the process 300 can begin by
reading a data page from non-volatile memory (e.g., memory cell
array 106) and storing the data page in a memory register (302)
(e.g., register 110). A DCI (e.g., DCI 130) can be verified for the
data page in the memory register (304). In some implementations,
the DCI can be previously computed and stored in the memory
subsystem when the data page is first written to non-volatile
memory (e.g., using process 200). In other implementations, the DCI
can be computed "on the fly" as part of the read operation or as a
separate operation. The memory subsystem can report to an external
controller (e.g., external controller 116) that the read operation
has completed (306).
[0018] If the DCI for the data page in the register indicates that
the data page has changed (308), the data page can be transferred
to the external controller (310), an ECC can be computed for the
data page (312) and the ECC information for the data page can be
corrected in the external controller (314). The data page and
associated ECC can be transferred back to the memory register
(316). A new DCI can be computed for the data page in the memory
register (318).
[0019] If the DCI for the data page in the register indicates that
the data page has not changed (308), an ECC can be computed for new
metadata associated with the data page (320). The new metadata and
associated ECC can be transferred to the memory register (322). A
new DCI can be computed for the metadata in the memory register
(324). The memory register contents can be written to a new data
page in non-volatile memory (326).
Optimized Read Operation
[0020] FIG. 4 is a flow diagram of an example optimized read
operation implemented by the memory systems of FIGS. 1A and 1B. In
some implementations, the process 400 can begin by reading a data
page from non-volatile memory and storing the data page in a memory
register (402). A pre-computed DCI associated with the data page
can be clocked into the memory register from a storage location in
the memory subsystem and verified (404). The DCI can also be
computed "on the fly." The status of the DCI can be read to
determine if the data page has changed (406).
[0021] If the data page has changed (408), an ECC for the new
metadata associated with the data page can be computed and
transferred, together with the new metadata to the memory register
(412). A new DCI can be computed for the metadata in the memory
register and the register contents can be written to a new data
page in non-volatile memory (414).
[0022] If the data page has not changed (408), the memory register
contents can be transferred to an external controller and an ECC
can be computed by the external controller (410). An ECC for the
new metadata associated with the data page can be computed and
transferred by the external controller, together with the new
metadata to the memory register (412). A new DCI can be computed
for the metadata in the memory register and the register contents
can be written to a new data page in non-volatile memory (414).
Example Data Structures
[0023] FIG. 5 illustrates example data structures used by the
copyback process of FIGS. 3A-3C. In the example shown, a data page
500 in non-volatile memory includes metadata 502, metadata ECC 504,
data 506 and data ECC 508. If the data has not changed than only
the metadata 502 and the metadata ECC 504 are transferred from the
register to the external controller 510 for processing. The
processed metadata 502 and metadata ECC 504 are transferred back to
the memory subsystem and stored in the memory register. The data
page can the be written to a new data page in non-volatile memory
(e.g., a memory cell array).
[0024] A number of implementations have been described.
Nevertheless, it will be understood that various modifications may
be made. For example, elements of one or more implementations may
be combined, deleted, modified, or supplemented to form further
implementations. As yet another example, the logic flows depicted
in the figures do not require the particular order shown, or
sequential order, to achieve desirable results. In addition, other
steps may be provided, or steps may be eliminated, from the
described flows, and other components may be added to, or removed
from, the described systems. Accordingly, other implementations are
within the scope of the following claims.
* * * * *