U.S. patent application number 13/035924 was filed with the patent office on 2012-08-30 for system to operationally connect logic nodes.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to William L. Brodsky, Eric J. McKeever, John G. Torok.
Application Number | 20120221760 13/035924 |
Document ID | / |
Family ID | 46719791 |
Filed Date | 2012-08-30 |
United States Patent
Application |
20120221760 |
Kind Code |
A1 |
Brodsky; William L. ; et
al. |
August 30, 2012 |
SYSTEM TO OPERATIONALLY CONNECT LOGIC NODES
Abstract
A system to operationally connect logic nodes may include an
inter-nodal circuit to provide communications between any connected
logic nodes. The system may also include a fabric bus that may be
physically separate from the inter-nodal circuit, the fabric bus
may provide logical connections restricted to any two connected
logic nodes. The system may further include a clock circuit carried
by the inter-nodal circuit that controls both the inter-nodal
circuit and the fabric bus.
Inventors: |
Brodsky; William L.;
(Binghamton, NY) ; McKeever; Eric J.;
(Poughkeepsie, NY) ; Torok; John G.;
(Poughkeepsie, NY) |
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
46719791 |
Appl. No.: |
13/035924 |
Filed: |
February 26, 2011 |
Current U.S.
Class: |
710/311 |
Current CPC
Class: |
G06F 13/4217
20130101 |
Class at
Publication: |
710/311 |
International
Class: |
G06F 13/36 20060101
G06F013/36 |
Claims
1. A system comprising: an inter-nodal circuit to provide
communications between any connected logic nodes; a fabric bus that
is physically separate from the inter-nodal circuit, the fabric bus
to provide logical connections restricted to any two connected
logic nodes; and a clock circuit carried by the inter-nodal circuit
that controls both the inter-nodal circuit and the fabric bus.
2. The system of claim 1 wherein the inter-nodal circuit and clock
circuit comprise a low speed circuit and the fabric bus comprises a
high speed bus.
3. The system of claim 1 wherein the inter-nodal circuit, the clock
circuit, and the fabric bus operationally join at least two
connected logic nodes.
4. The system of claim 1 wherein the connected logic nodes comprise
computer servers.
5. The system of claim 1 further comprising at least one of an
electronic and optical connection carried by the inter-nodal
circuit and the fabric bus configured to mate with pads on the
connected logic nodes.
6. The system of claim 1 wherein the inter-nodal circuit comprises
a plurality of inter-nodal circuits and the fabric bus comprises a
plurality of fabric buses, which connect additional logic nodes
added to the system.
7. The system of claim 1 wherein at least one of the inter-nodal
circuit and the fabric bus comprises a flexible material.
8. The system of claim 7 wherein at least one of the inter-nodal
circuit and the fabric bus comprises a substantially rigid material
adjoining the flexible material.
9. The system of claim 1 wherein at least one of the inter-nodal
circuit and the fabric bus comprises a preformed offset along its
length.
10. A system comprising: an inter-nodal circuit to provide
communications between any connected computer servers; a fabric bus
that is physically separate from the inter-nodal circuit, the
fabric bus to provide logical connections restricted to any two
connected computer servers; and a clock circuit carried by the
inter-nodal circuit that controls both the inter-nodal circuit and
the fabric bus, and the clock circuit, the inter-nodal circuit, and
the fabric bus operationally join at least two connected computer
servers.
11. The system of claim 10 wherein the inter-nodal circuit and
clock circuit comprise a low speed circuit and the fabric bus
comprises a high speed bus.
12. The system of claim 10 further comprising at least one of an
electronic and optical connection carried by the inter-nodal
circuit and the fabric bus configured to mate with pads on the
connected computer servers.
13. The system of claim 10 wherein the inter-nodal circuit
comprises a plurality of inter-nodal circuits and the fabric bus
comprises a plurality of fabric buses, which connect additional
computer servers added to the system.
14. The system of claim 10 wherein at least one of the inter-nodal
circuit and the fabric bus comprises a flexible material.
15. The system of claim 14 wherein at least one of the inter-nodal
circuit and the fabric bus comprises a substantially rigid material
adjoining the flexible material.
16. The system of claim 10 wherein at least one of the inter-nodal
circuit and the fabric bus comprises a preformed offset along its
length.
17. A system comprising: an inter-nodal low speed circuit to
provide communications between any connected logic nodes; a fabric
high speed bus that is physically separate from the inter-nodal
circuit, the fabric high speed bus to provide logical connections
restricted to any two connected logic nodes; a clock circuit
carried by the inter-nodal circuit that controls both the
inter-nodal circuit and the fabric bus; and at least one of an
electronic and optical connection carried by the inter-nodal
circuit and the fabric bus configured to mate with pads on the
connected logic nodes.
18. The system of claim 17 wherein the inter-nodal circuit, the
clock circuit, and the fabric bus operationally join at least two
connected logic nodes.
19. The system of claim 17 wherein at least one of the inter-nodal
circuit and the fabric bus comprises a flexible material; and
wherein at least one of the inter-nodal circuit and the fabric bus
comprises a substantially rigid material adjoining the flexible
material.
20. The system of claim 17 wherein at least one of the inter-nodal
circuit and the fabric bus comprises a preformed offset along its
length.
Description
RELATED APPLICATIONS
[0001] This application contains subject matter related to the
following co-pending applications entitled "Electronic Assemblies
Mating System" and having an attorney docket number of
POU920100099US1, "Shared System to Operationally Connect Logic
Nodes" and having an attorney docket number of and POU920100101US1,
and "Logic Node Connection System" and having an attorney docket
number of POU920100102US1, the entire subject matters of which are
incorporated herein by reference in their entirety. The
aforementioned applications are assigned to the same assignee as
this application, International Business Machines Corporation of
Armonk, N.Y.
BACKGROUND
[0002] The invention relates to the field of computer systems, and,
more particularly, systems that operationally connect logic
nodes.
[0003] Recent developments of rack-mounted servers generally reside
in two specific categories. The first of these are stand-alone
servers which reside in a common rack, but do not communicate or
share computing resources such as processor, memory, and/or I/O
utilization, but share mechanical support, power, and/or cooling
infrastructure.
[0004] The second category is associated with integrated servers,
to which physical nodes not only utilize common mechanical support,
power, and/or cooling infrastructure, but also are required to
share computing resources. In this case, these physical nodes, e.g.
books, drawers, blades, logic nodes, and/or the like, are required
to share general communications such as common system-level
clocking, service support processing function, and/or the like as
well as specific inter-node computing functions via a fabric or
parallel communication bus structure.
SUMMARY
[0005] According to one embodiment of the invention, a system to
operationally connect logic nodes may include an inter-nodal
circuit to provide communications between any connected logic
nodes. The system may also include a fabric bus that may be
physically separate from the inter-nodal circuit, the fabric bus
may provide logical connections restricted to any two connected
logic nodes. The system may further include a clock circuit carried
by the inter-nodal circuit that controls both the inter-nodal
circuit and the fabric bus.
[0006] The inter-nodal circuit and clock circuit may comprise a low
speed circuit and the fabric bus may comprise a high speed bus. The
inter-nodal circuit, the clock, and the fabric bus may
operationally join at least two connected logic nodes.
[0007] The connected logic nodes may comprise computer servers. The
system may also include an electronic and/or optical connection
carried by the inter-nodal circuit and the fabric bus configured to
mate with pads on the connected logic nodes. The inter-nodal
circuit may comprise a plurality of inter-nodal circuits and the
fabric bus may comprise a plurality of fabric buses, which connect
additional logic nodes added to the system.
[0008] The inter-nodal circuit and/or the fabric bus may comprise a
flexible material. The inter-nodal circuit and/or the fabric bus
may comprise a substantially rigid material adjoining the flexible
material. The inter-nodal circuit and/or the fabric bus may
comprise a preformed offset along its length.
[0009] In an embodiment, the system may include an inter-nodal
circuit to provide communications between any connected computer
servers. The system may also include a fabric bus that may be
physically separate from the inter-nodal circuit, the fabric bus
may provide logical connections restricted to any two connected
computer servers. The system may further include a clock circuit
carried by the inter-nodal circuit that controls both the
inter-nodal circuit and the fabric bus, and the clock, the
inter-nodal circuit, and the fabric bus operationally join at least
two connected computer servers.
[0010] In an embodiment, the system may include an inter-nodal low
speed circuit to provide communications between any connected logic
nodes. The system may also include a fabric high speed bus that may
be physically separate from the inter-nodal circuit, the fabric bus
may provide logical connections restricted to any two connected
logic nodes, and a clock circuit carried by the inter-nodal circuit
that controls both the inter-nodal circuit and the fabric bus. The
system may further include an electronic and/or optical connection
carried by the inter-nodal circuit and the fabric bus configured to
mate with pads on the connected logic nodes.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a front view of a system to operationally connect
logic nodes in accordance with the invention.
[0012] FIG. 2 is a front view of the inter-nodal circuit of FIG.
1.
[0013] FIG. 3 is a top view of the inter-nodal circuit of FIG.
1.
[0014] FIG. 4 is a top view of the system of FIG. 1
[0015] FIG. 5 is a side view of the components of the fabric bus of
FIG. 1.
[0016] FIG. 6 is a front view of an alternative embodiment of the
system of FIG. 1.
[0017] FIG. 7 is a rear view of an alternative embodiment of the
system of FIG. 1.
[0018] FIG. 8 is a top view of an alternative embodiment of the
system of FIG. 1.
[0019] FIG. 9 is a side view of an alternative embodiment of the
components of the fabric bus of FIG. 5.
[0020] FIG. 10 is a top-side view of an alternative embodiment of
the components of the fabric bus of FIG. 5.
[0021] FIG. 11 is an exploded view of the alternative embodiment of
FIG. 10.
[0022] FIG. 12 is a top-side view of another alternative embodiment
of the components of the fabric bus of FIG. 5.
[0023] FIG. 13 is an exploded view of the alternative embodiment of
FIG. 10.
[0024] FIG. 14 is an iso view of a system to operationally connect
logic nodes with electrical flex connectors in accordance with the
invention.
[0025] FIG. 15 is a build sequence for FIG. 14.
[0026] FIG. 16 is a side view of an electrical seat belt assembly
in accordance with the invention.
[0027] FIG. 17 is an exploded view of the electrical seat belt
assembly of FIG. 16.
[0028] FIGS. 18-19 are an iso view of a three bay system to
operationally connect logic nodes with optical flex connectors in
accordance with the invention.
[0029] FIG. 20 is an iso view of a six bay system to operationally
connect logic nodes with optical flex connectors in accordance with
the invention.
[0030] FIGS. 21-22 are views of a three bay optical cold plate
system to operationally connect logic nodes in accordance with the
invention.
[0031] FIGS. 23-25 are views of six bay optical cold plate systems
to operationally connect logic nodes in accordance with the
invention.
[0032] FIGS. 26-27 are views of a six bay optical garage/cold plate
system to operationally connect logic nodes in accordance with the
invention.
DETAILED DESCRIPTION
[0033] The invention will now be described more fully hereinafter
with reference to the accompanying drawings, in which preferred
embodiments of the invention are shown. Like numbers refer to like
elements throughout, like numbers with letter suffixes are used to
identify similar parts in a single embodiment, and letter suffix
lower case n is a variable that indicates an unlimited number of
similar elements.
[0034] With reference now to FIG. 1, a system 10 to operationally
connect logic nodes 14a-14n is initially described. In an
embodiment, system 10 includes an inter-nodal circuit 12 to provide
communications between any connected logic nodes 14a-14n. The
system 10 also includes a fabric bus 16 to provide logical
connections restricted to any two connected logic nodes 14a-14n.
The system 10 further includes a clock circuit 18a-18n carried by
the inter-nodal circuit 12 that controls both the inter-nodal
circuit and the fabric bus 16.
[0035] In an embodiment, the inter-nodal circuit 12 and clock
circuit 18a-18n comprise a low speed circuit and the fabric bus 16
comprises a high speed bus. In another embodiment, the inter-nodal
circuit 12, the clock circuit 18a-18n, and the fabric bus 16
operationally join at least two connected logic nodes 14a-14n,
which means the logic nodes can share resources due to the
inter-nodal circuit, the clock, and the fabric bus.
[0036] In an embodiment, the connected logic nodes 14a-14n comprise
computer servers. In another embodiment and with reference to FIGS.
2-4, the system 10 also includes electronic connections 20a-20n
carried by the inter-nodal circuit 12 and the fabric bus 16
configured to mate with pads 24a-24n on the connected logic nodes
14a-14n. In another embodiment, the inter-nodal circuit 12
comprises a plurality of inter-nodal circuits and the fabric bus 16
comprises a plurality of fabric buses, which connect additional
logic nodes 14a-14n added to the system 10.
[0037] In an embodiment and with reference to FIG. 5, the
inter-nodal circuit 12 and/or the fabric bus 16 comprises a
flexible material 22a-22n. In another embodiment, the inter-nodal
circuit 12 and/or the fabric bus 16 comprises a substantially rigid
material 26a-26n adjoining the flexible material 22a-22n. In
another embodiment, the inter-nodal circuit 12 and/or the fabric
bus 16 comprises a preformed offset 28 along its length.
[0038] In an embodiment, the system 10 includes an inter-nodal
circuit 12 to provide communications between any connected computer
servers 14a-14n. The system 10 also includes a fabric bus 16 to
provide logical connections restricted to any two connected
computer servers 14a-14n. The system 10 further includes a clock
circuit 18a-18n carried by the inter-nodal circuit 12 that controls
both the inter-nodal circuit and the fabric bus 16, and the clock,
the inter-nodal circuit, and the fabric bus operationally join at
least two connected computer servers 14a-14n.
[0039] In an embodiment, the system 10 includes an inter-nodal low
speed circuit 12 to provide communications between any connected
logic nodes 14a-14n. The system 10 also includes a fabric high
speed bus 16 to provide logical connections restricted to any two
connected logic nodes 14a-14n, and a clock circuit 18a-18n carried
by the inter-nodal circuit 12 that controls both the inter-nodal
circuit and the fabric bus. The system 10 further includes
electronic connections 20-20n carried by the inter-nodal circuit 12
and the fabric bus 16 configured to mate with pads 24a-24n on the
connected logic nodes 14a-14n.
[0040] In view of the foregoing, the system 10 aids in
operationally connecting logic nodes. In contrast, current
rack-mounted servers have limitations.
[0041] Even though each category of rack-mounted servers has
historically retained reasonable market share, recent trends in
server consolidation, high performance computing, and increased
system single image performance require both increased packaging
density and effective inter-node communication means (i.e., cost,
performance etc.). Historically, the packaging styles and
communication functions have been addressed using the approaches
described in Table 1 below; including the Pros and Cons of
each.
TABLE-US-00001 TABLE 1 Interconnection Schemes Approach Description
Pros Cons 1 Two Build-as-go 2-D approach dimensional Low cost
requires Flex Circuit (pay-as-you-go) significant tail Applicable
to stock real drawer style estate physical Difficult I/O nodes
interconnection Supports routing effective front-back cooling 2
Vertical Applicable Prevents Rigid back- for both effective plane
Book, Blade front-back and Drawer cooling 3 Horizontal Applicable
Prevents Drawer Rigid back- for both physical node plane Book and
designs Blade High physical implementation node cost (total designs
cost as part Supports of base effective system) front to back 4
Optical Applicable Required card interface for both packaging Book,
Blade real estate and Drawer High physical node implementation
designs cost (pay-as- Ease of you-go, but interconnection
individual BMC routing still much greater than other approaches for
constant or increasing bandwidth)
[0042] As noted, no single approach addresses all needs.
Furthermore, recent efforts to maximize server packaging density,
has spirited the implementation of the more spatial effective
drawer-style packaging design approach. Unfortunately, none of the
aforementioned approaches provides the desired attributes of low
cost (pay-as-you-go) and effective front to back cooling without
requiring tailstock real estate and/or adversely effecting I/O
interconnection routing.
[0043] The core idea disclosed by system 10 is the creation of a
three-dimensional, flexible back-plane. In doing so, it provides a
means of implementing a low-cost, drawer-drawer scheme for
communications without adversely consuming the drawer's limited
tailstock real estate, effecting the it's front-back cooling path
and/or interfering with the required interconnecting routing, and
supports concurrent maintenance or system growth for additional
drawers.
[0044] As noted above, rack-mounted integrated servers require both
an inter-node general communications (GC) as well as shared
inter-node computing function on an interconnected fabric bus (FB).
System 10 houses as part of the GC system, e.g., inter-nodal
circuit 12, support for processing and clocking functions, each
derived from common & redundant system-level control cards.
These cards typically mate to the backplane and use common circuits
to reach each logical node 14a-14n. On the other hand, the FB,
e.g., fabric bus 16, is a means of interconnecting logical nodes
14a-14n on unique circuits to reach node pairs. Note, when only a
single logic node 14a-14n is present, only GC interconnection is
required. However, as nodes 14a-14n are added, they need to be
subsequently added together to ensure complete point-to-point
interconnection is established so computing resources can be shared
(see Table for a typical interconnecting scheme for a four logical
node system).
TABLE-US-00002 TABLE 2 Interconnections # of nodes GC FB 1 yes N/A
2 yes Nodes 1 to 2 3 yes Nodes 1 to 2, 1 to 3 and 2 to 3 4 yes
Nodes 1 to 2, 1 to 3, 2 to 3, 1 to 4, 2 to 4 and 3 to 4
[0045] To address the above needs, two schemes have been devised,
each using a flex circuit approach to complete the required
communications path. The first approach uses dedicated flex
circuits to address the GC 12 (i.e., flexible service processor
(FSP) 13a-13n and clocking (OSC) 18a-18n functions) and the fabric
bus (FB) 16 on completely separate physical assemblies. The second
approach, utilizes flex circuit assemblies with both individual and
combined communications to achieve the desired interconnectivity
results.
[0046] Description of the two schemes and their associated
embodiments is provided below. Note, although two schemes have been
shown, other renditions and/or combinations can be witnessed by
simply altering the bus assignments. etc.
[0047] Scheme #1: Dedicated Flex Circuits to address the required
GC and F B communications. For this implementation, two separate
and unique communication paths are established (see FIG. 1.). As
depicted, two flex circuit paths have been established.
[0048] Path #1: The first path provides GC 12, whereby a flex
circuit comprising of pluggable interconnects are assembled onto
the flex, to which separate OSC clock circuit 18a-18n and FSP cards
are subsequently plugged (see FIGS. 2 & 3). These cards are
both featureable as well as hot pluggable and this flex is
installed, one per system and can facilitate front-side or
rear-side card plugging, depending on the desired
configuration.
[0049] Path #2: The second path for the FB 16 consists of a series
or an assemblage of flex circuits. Each of these flex circuits are
designed to support the interconnection of the various fabric bus
16 portions required as logical nodes 14a-14n are added. Since the
necessity of these is based on the number of logical nodes 14a-14n
installed, these are now added only on a need be basis only (hence
a lower cost approach). To illustrate, Table 3 provides the typical
build scheme to support the drawer configuration depicted in FIG.
1. Note, unconnected flex circuits A2 & B2 are added, in order,
when adding Node #3 to facilitate ease of concurrent FB 16
expansion should Node#4 be added in the future. If concurrency is
not desired, this plan ahead feature can be omitted, further
lowering the cost of implementation.
TABLE-US-00003 TABLE 3 FB Installation Scheme # of Nodes GC FB 1
yes N/A 2 yes Install & Connect A1 3 yes Install A2 & B2
(not plugged) and Install & Connect B1 & C1 4 yes Connect
A2 & B2 and Install & Connect C2
[0050] FIG. 4 is provided to better visualize the GC 12 and FB 16
implementation in a drawer packaging format. The general layout is
provided for concept understanding, whereby the GC 12 and FB 16
connection locations are shown on the upper left and along the
right card edge respectively.
[0051] As shown, housed on the right hand card edge are a series of
Land Grid Array (LGA) pads 24a-24n to connect the various flex
circuits 12 and/or 16 as Nodes 14a-14n are added to the system 10.
In general, Fabric A 16 is either installed and connected or
installed only to facilitate the node 14a-14n upgrade path. Since
these overlap, the plan ahead noted in Table 3 provides for the
concurrent ease of install without adversely affecting the
operational fabric bus 16.
[0052] For the system 10 configuration depicted in FIG. 1, three
different flex sizes are used (see FIG. 5). As depicted, flex
circuits A and C are fairly straight-forward designs, while flex
circuit B uses an offset in its design to address any overlap when
installed in the system 10. To support the connection to the
aforementioned FB 16 flex circuits, a compression-style LGA
attachment mechanism is conceived to support the "build-as-you-go"
assembly.
[0053] In an alternative embodiment, scheme #2 discloses a shared
flex circuits to address the required GC 12 and FB 16
communications. For this implementation, a shared or common flex
circuit is used to address the GC 12 and FB B 16 communication
paths (see FIGS. 6 and 7). As depicted, two flex circuit paths have
again been established, but in this case, the FB B 16 circuits are
addressed via a common flex circuit positioned in the center back
of the system 10.
[0054] In one embodiment a path #1 is disclosed where the first
path provides GC 12 and FB 16-circuit B, whereby a flex circuit
comprising of pluggable interconnects are assembled onto the flex,
to which separate OSC 18a-18n and FSP 13a-13n cards are
subsequently plugged (see FIGS. 2 and 3) as well as the circuitry
to support FB B 16. The OSC 18a-18n and FSP 13a-13n cards are both
featureable as well as hot pluggable, and plug into the rear side
of the system 10. The FB B circuit is closed as drawers are added
to the system and is resident to the central electronic complex,
regardless of node population.
[0055] In another embodiment a scheme #2 is disclosed where scheme
#2 is similar to scheme #1, and the second path for the FB 16
consists of a series or an assemblage of flex circuits. Each of
these flex circuits are designed to support the interconnection of
the various fabric bus 16 portions required as logical nodes
14a-14n are added. However, in this case, FB B 16 is already
installed and therefore the flex circuit add is greatly simplified.
Since FB B 16 resides in the system 10, it is a costlier approach
then scheme #1, but the FB expansion association with concurrent
adds is greatly simplified. To illustrate, Table 4 provides the
typical build scheme to support the drawer configuration depicted
in FIGS. 6 and 7.
TABLE-US-00004 TABLE 4 FB Installation Scheme # of Nodes GC FB 1
yes N/A 2 yes Install & Connect A1 3 yes Install & Connect
C1 4 yes Install & Connect C2
[0056] FIG. 8 is provided below to better visualize the GC 12 and
FB 16 implementation in a drawer packaging format. The general
layout is provided for concept understanding, whereby the GC 12 and
FB 16 connection locations are shown on the upper left and along
the right card edge respectively.
[0057] As shown, housed on the right hand card edge are a series of
Land Grid Array pads 24a-24n to connect the various flex circuits
as Nodes 14a-14n are added to the system 10. In general, Fabric
Buses A &C 16 are only installed and connected to facilitate
the node 14a-14n upgrade path. For the system 10 configuration
depicted in FIGS. 6 and 7 above, two different flex sizes are used
as illustrated in FIG. 9.
[0058] Similar to scheme #1, the FB 16 flex connections are
facilitated via the same LGA actuation mechanism described in FIG.
5.
[0059] As depicted in FIG. 5, the device employs a blind-mate lever
or screw-driven actuation mechanism to individually mate and unmate
the various FB 16 connections. Each device contains both the means
of force application and any required degree of veridical
compliancy to minimize stress across the connection interface as
well as the necessary guidance system to accurately align the
interfaced prior to finalizing the connection.
[0060] As part of this disclosure, an optical version 29 to the
electrical flex circuits is also disclosed. Specifically, an active
optical fiber cable assembly is presented in FIGS. 10-13 (assembled
and exploded views). FIG. 11 includes six optical fibers 30, a
header 31, a seatbelt clip 32, a flex 33, an optical module
organizer 34, optical modules 35, and an interface 36. FIG. 13
includes another embodiment of optical version 29 and includes
module actuator and heat sink 37, optical cables 38, optical
modules 35, and a module LGA and organizer 39. As depicted this
assembly would be preassembled in a cluster of optical modules onto
a printed circuit board (PCB) organizer using an LGA interface to
the PCB and a Module Actuator/Heat sink. Assembled, one cluster per
end, these assemblies would be installed in the system 10 in a
similar manner as the aforementioned electrical flex
assemblies.
[0061] One difference is the necessity to address cooling of the
optics. To this end, integrated into the system 10 would be an
assembly interface to a cold-plate assembly.
[0062] The system 10 includes a number of different groups of
embodiments. Firstly, a rack-level flexible backplane that
facilitates "build-as-you-go" capability. In doing so, the circuits
offer a third dimensional interconnection means to which to allow
communication to multiple drawer entities 14a-14n. In addition, by
nature of both their construction as well as their placement, one
can exploit the enhanced packaging density and thermal cooling
effectiveness of drawer-style packaging.
[0063] Secondly, individual fabric bus 16 side circuits are readily
added without adversely effecting typical I/O connectivity routing
schemes. Also, by creating individual buses 16, wiring density is
reduced and therefore lending itself to inexpensive flex circuits.
Note, additional features, such as enhanced I/O connectivity can be
achieved by adding active components/circuitry to the individual
flex circuits 12 and/or 16. Examples of this include optical
interconnects to external I/O devices, system 10 control functions
to non-system resident computing functions, e.g., zHybrid and/or
the like.
[0064] Thirdly, flex circuit 12 and/or 16 LGA connection provides
the ability to guide & align the connection as well as
providing the required mating actuation force and interconnect
compliance (see FIGS. 14-19 and 20-27 for electrical and optical
versions, respectively).
[0065] In FIG. 14 the flex interconnect is configured for a four
drawer system 10, and each flex end contains 16.times.60 (960
channels) LGA on 1 mm pitch. Also, the system 10 level FSP 13a-13n
and OSC 18a-18n cards connect to rear of the drawer 14a-14n via a
fingered backplane.
[0066] In FIGS. 21 and 22, a single actuation screw for actuating
seatbelt clip to processor board LGA and for actuating optical
module heat spreader against the cold plate is illustrated. In
addition, multiple, in-line interconnect co-docking features (i.e.,
for FSP 13a-13n & OSC 18a-18n circuits) are illustrated.
[0067] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
the invention. As used herein, the singular forms "a", "an" and
"the" are intended to include the plural forms as well, unless the
context clearly indicates otherwise. It will be further understood
that the terms "comprises" and/or "comprising," when used in this
specification, specify the presence of stated features, integers,
steps, operations, elements, and/or components, but do not preclude
the presence or addition of one or more other features, integers,
steps, operations, elements, components, and/or groups thereof.
[0068] The corresponding structures, materials, acts, and
equivalents of all means or step plus function elements in the
claims below are intended to include any structure, material, or
act for performing the function in combination with other claimed
elements as specifically claimed. The description of the present
invention has been presented for purposes of illustration and
description, but is not intended to be exhaustive or limited to the
invention in the form disclosed. Many modifications and variations
will be apparent to those of ordinary skill in the art without
departing from the scope and spirit of the invention. The
embodiment was chosen and described in order to best explain the
principles of the invention and the practical application, and to
enable others of ordinary skill in the art to understand the
invention for various embodiments with various modifications as are
suited to the particular use contemplated.
[0069] While the preferred embodiment to the invention has been
described, it will be understood that those skilled in the art,
both now and in the future, may make various improvements and
enhancements which fall within the scope of the claims which
follow. These claims should be construed to maintain the proper
protection for the invention first described.
* * * * *