U.S. patent application number 13/505714 was filed with the patent office on 2012-08-30 for techniques for phase detection.
This patent application is currently assigned to RAMBUS INC.. Invention is credited to Farshid Aryanfar, Kun-Yung Chang, Hae-Chang Lee, Brian Leibowitz, Jie Shen.
Application Number | 20120218001 13/505714 |
Document ID | / |
Family ID | 43992339 |
Filed Date | 2012-08-30 |
United States Patent
Application |
20120218001 |
Kind Code |
A1 |
Leibowitz; Brian ; et
al. |
August 30, 2012 |
Techniques for Phase Detection
Abstract
A phase detection circuit can include two phase detectors that
each generate a non-zero output in response to input signals being
aligned in phase. The input signals are based on two periodic
signals. The phase detection circuit subtracts the output signal of
one phase detector from the output signal of the other phase
detector to generate a signal having a zero value when the periodic
signals are in phase. Alternatively, a phase detector generates a
phase comparison signal indicative of a phase difference between
periodic signals. The phase comparison signal has a non-zero value
in response to input signals to the phase detector being aligned in
phase. The input signals are based on the periodic signals. An
output circuit receives the phase comparison signal and generates
an output having a zero value in response to the periodic signals
being aligned in phase.
Inventors: |
Leibowitz; Brian; (San
Francisco, CA) ; Lee; Hae-Chang; (Los Altos, CA)
; Aryanfar; Farshid; (Sunnyvale, CA) ; Chang;
Kun-Yung; (Los Altos, CA) ; Shen; Jie;
(Fremont, CA) |
Assignee: |
RAMBUS INC.
Sunnyvale
CA
|
Family ID: |
43992339 |
Appl. No.: |
13/505714 |
Filed: |
October 31, 2010 |
PCT Filed: |
October 31, 2010 |
PCT NO: |
PCT/US10/54900 |
371 Date: |
May 2, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61260797 |
Nov 12, 2009 |
|
|
|
Current U.S.
Class: |
327/9 |
Current CPC
Class: |
H03L 7/085 20130101;
H03D 13/00 20130101; H03L 7/0814 20130101; H03L 7/08 20130101; H03L
7/0816 20130101 |
Class at
Publication: |
327/9 |
International
Class: |
H03D 13/00 20060101
H03D013/00 |
Claims
1. A circuit comprising: a first phase detector generating a first
phase comparison signal that is indicative of a phase difference
between first and second periodic signals, wherein the first phase
comparison signal has a non-zero value in response to first input
signals to the first phase detector being aligned in phase, and
wherein the first input signals are based on the first and the
second periodic signals; a second phase detector generating a
second phase comparison signal that is indicative of a phase
difference between the first and the second periodic signals,
wherein the second phase comparison signal has a non-zero value in
response to second input signals to the second phase detector being
aligned in phase, and wherein the second input signals are based on
the first and the second periodic signals; and a combiner circuit
that combines the first and the second phase comparison signals to
generate a third phase comparison signal having a zero value when
the first and the second periodic signals are aligned in phase.
2. The circuit of claim 1 further comprising: a first delay circuit
that delays the second periodic signal to generate a first delayed
signal, wherein the first input signals to the first phase detector
are the first periodic signal and the first delayed signal; and a
second delay circuit that delays the first periodic signal to
generate a second delayed signal, wherein the second input signals
to the second phase detector are the second periodic signal and the
second delayed signal.
3. The circuit of claim 2 wherein the first delay circuit delays
the second periodic signal by approximately 90 degrees to generate
the first delayed signal, wherein the second delay circuit delays
the first periodic signal by approximately 90 degrees to generate
the second delayed signal, and wherein the first and the second
phase detectors are quadrature phase detectors.
4. The circuit of claim 2 wherein the first and the second phase
detectors have substantially the same circuit designs, and wherein
the first and the second delay circuits have identical circuit
designs.
5. The circuit of claim 1 wherein the combiner circuit is a
subtraction circuit that subtracts the first phase comparison
signal from the second phase comparison signal to generate the
third phase comparison signal.
6. The circuit of claim 1 wherein the second phase comparison
signal is a phase shifted version of the first phase comparison
signal when the first and the second phase comparison signals are
plotted as a function of a phase difference between the first and
the second periodic signals.
7. The circuit of claim 1 wherein the first and the second phase
detectors are quadrature phase detectors.
8. The circuit of claim 1 further comprising: a first delay circuit
that delays the first periodic signal to generate a first delayed
signal; a second delay circuit that delays the second periodic
signal to generate a second delayed signal, wherein the first input
signals to the first phase detector are the first delayed signal
and the second delayed signal; a third delay circuit that delays
the first periodic signal to generate a third delayed signal; and a
fourth delay circuit that delays the second periodic signal to
generate a fourth delayed signal, wherein the second input signals
to the second phase detector are the third delayed signal and the
fourth delayed signal.
9. The circuit of claim 8 wherein the first delay circuit delays
the first periodic signal by approximately 45 degrees to generate
the first delayed signal, wherein the second delay circuit delays
the second periodic signal by approximately -45 degrees to generate
the second delayed signal, wherein the third delay circuit delays
the first periodic signal by approximately -45 degrees to generate
the third delayed signal, wherein the fourth delay circuit delays
the second periodic signal by approximately 45 degrees to generate
the fourth delayed signal, and wherein the first and the second
phase detectors are quadrature phase detectors.
10. The circuit of claim 8 wherein the first and the second phase
detectors have substantially the same circuit designs, wherein the
first and the fourth delay circuits have substantially the same
circuit designs, and wherein the second and the third delay
circuits have substantially the same circuit designs.
11. The circuit of claim 1 wherein the first and the second phase
detectors are zero phase detectors that have systematic static
phase offsets, and wherein the first input signals are the first
and the second periodic signals, and the second input signals are
the first and the second periodic signals.
12. The circuit of claim 11 wherein the first phase detector
comprises a first sample and hold circuit that samples the first
periodic signal with the second periodic signal, and wherein the
second phase detector comprises a second sample and hold circuit
that samples the second periodic signal with the first periodic
signal.
13. The circuit of claim 12 wherein the first sample and hold
circuit is coupled to a first low pass filter circuit, wherein the
first sample and hold circuit and the first low pass filter circuit
generate the first phase comparison signal, wherein the second
sample and hold circuit is coupled to a second low pass filter
circuit, wherein the second sample and hold circuit and the second
low pass filter circuit generate the second phase comparison
signal, and wherein the combiner circuit is a differencing
amplifier that generates the third phase comparison signal based on
the first and the second phase comparison signals.
14. The circuit of claim 12 wherein the first sample and hold
circuit comprises a first transistor coupled to a first capacitor,
wherein the first periodic signal is received at a channel input of
the first transistor, wherein the second periodic signal is
received at a control input of the first transistor, wherein the
second sample and hold circuit comprises a second transistor
coupled to a second capacitor, wherein the second periodic signal
is received at a channel input of the second transistor, and
wherein the first periodic signal is received at a control input of
the second transistor.
15. The circuit of claim 1 wherein the circuit is part of a
delay-locked loop.
16. The circuit of claim 1 wherein the circuit is part of a
phase-locked loop.
17. The circuit of claim 1 wherein the circuit is embedded in an
integrated circuit.
18. The circuit of claim 17 wherein the integrated circuit is a
memory integrated circuit.
19. The circuit of claim 17 wherein the integrated circuit is a
memory controller integrated circuit.
20. A circuit comprising: a phase detector generating a phase
comparison signal that is indicative of a phase difference between
first and second periodic signals, wherein the phase comparison
signal has a non-zero value in response to first and second input
signals to the phase detector being aligned in phase, and wherein
the first and the second input signals are based on the first and
the second periodic signals; and an output circuit receiving the
phase comparison signal and generating an output that is indicative
of the phase difference between the first and the second periodic
signals and that has a zero value in response to the first and the
second periodic signals being aligned in phase.
21. The circuit of claim 20 further comprising: a first chopper
switch circuit that periodically switches the first and the second
periodic signals to a first output of the first chopper switch
circuit, wherein the first chopper switch circuit periodically
switches the first and the second periodic signals to a second
output of the first chopper switch circuit, and wherein a signal
generated at the first output of the first chopper switch circuit
is the first input signal to the phase detector; and a delay
circuit that delays a signal generated at the second output of the
first chopper switch circuit to generate the second input signal to
the phase detector.
22. The circuit of claim 21 further comprising: a second chopper
switch circuit coupled to an output of the phase detector, wherein
the output circuit comprises a load circuit coupled to the second
chopper switch circuit, wherein the second chopper switch circuit
periodically switches the phase comparison signal and an inverted
phase comparison signal generated by the phase detector to an input
of the load circuit.
23. The circuit of claim 22 wherein the phase detector comprises a
pull-down network of transistors, and wherein the second chopper
switch circuit is coupled between the load circuit and the
pull-down network of transistors.
24. The circuit of claim 23 wherein the phase detector is an XOR
based phase detector.
25. The circuit of claim 22 wherein the input of the load circuit
is a differential input, and the phase comparison signal is a
differential signal.
26. The circuit of claim 22 wherein a clock signal controls
periodic switching of both the first and the second chopper switch
circuits.
27. The circuit of claim 20 further comprising: a first chopper
switch circuit that periodically switches the first and the second
periodic signals to a first output of the first chopper switch
circuit, and wherein the first chopper switch circuit periodically
switches the first and the second periodic signals to a second
output of the first chopper switch circuit; and a delay circuit
that delays a signal generated at the second output of the first
chopper switch circuit to generate the second input signal to the
phase detector.
28. The circuit of claim 20 further comprising: a first chopper
switch circuit that periodically switches the first and the second
periodic signals to a first output of the first chopper switch
circuit, and wherein the first chopper switch circuit periodically
switches the first and the second periodic signals to a second
output of the first chopper switch circuit; a delay circuit that
delays a signal generated at the second output of the first chopper
switch circuit to generate a delayed signal; and a second chopper
switch circuit coupled to the delay circuit and to the first
chopper switch circuit, wherein the second chopper switch circuit
periodically switches a signal generated at the first output of the
first chopper switch circuit and the delayed signal between inputs
of the phase detector to generate the first and the second input
signals to the phase detector, wherein a clock signal controls
periodic switching of both the first and the second chopper switch
circuits.
29. The circuit of claim 21 wherein the phase detector is a
quadrature phase detector, and the delay circuit has a delay of
approximately 90.degree..
30. The circuit of claim 20 wherein the phase comparison signal is
a differential signal.
31. The circuit of claim 20 wherein the circuit is part of a
delay-locked loop.
32. The circuit of claim 20 wherein the circuit is part of a
phase-locked loop.
33. The circuit of claim 20 wherein the circuit is embedded in an
integrated circuit.
34. A method comprising: comparing phases of first and second
periodic signals to generate a first phase comparison signal that
has a non-zero value in response to first input signals to a first
phase detector being in phase, and wherein the first input signals
are based on the first and the second periodic signals; comparing
phases of the first and the second periodic signals to generate a
second phase comparison signal that has a non-zero value in
response to second input signals to a second phase detector being
in phase, and wherein the second input signals are based on the
first and the second periodic signals; and combining the first and
the second phase comparison signals to generate a phase comparison
output that is indicative of a phase difference between the first
and the second periodic signals and that has a zero value when the
first and the second periodic signals are in phase.
35. The method of claim 34 further comprising: delaying the second
periodic signal to generate a first delayed signal, wherein the
first input signals to the first phase detector are the first
periodic signal and the first delayed signal; and delaying the
first periodic signal to generate a second delayed signal, wherein
the second input signals to the second phase detector are the
second periodic signal and the second delayed signal.
36. The method of claim 35 wherein delaying the second periodic
signal to generate a first delayed signal further comprises
delaying the second periodic signal by approximately 90 degrees to
generate the first delayed signal, and wherein delaying the first
periodic signal to generate a second delayed signal further
comprises delaying the first periodic signal by approximately 90
degrees to generate the second delayed signal.
37. The method of claim 34 wherein combining the first and the
second phase comparison signals to generate a phase comparison
output that is indicative of a phase difference between the first
and the second periodic signals and that has a zero value when the
first and the second periodic signals are aligned in phase further
comprises subtracting the first phase comparison signal from the
second phase comparison signal to generate the phase comparison
output.
38. The method of claim 34 further comprising: delaying the first
periodic signal to generate a first delayed signal; delaying the
second periodic signal to generate a second delayed signal, wherein
the first input signals to the first phase detector are the first
and the second delayed signals; delaying the first periodic signal
to generate a third delayed signal; and delaying the second
periodic signal to generate a fourth delayed signal, wherein the
second input signals to the second phase detector are the third and
the fourth delayed signals.
39. The method of claim 34 wherein comparing phases of first and
second periodic signals to generate a first phase comparison signal
further comprises sampling the first periodic signal with the
second periodic signal to generate the first phase comparison
signal, and wherein comparing phases of the first and the second
periodic signals to generate a second phase comparison signal
further comprises sampling the second periodic signal with the
first periodic signal to generate the second phase comparison
signal.
40. A method comprising: comparing phases of first and second
periodic signals to generate a phase comparison signal that has a
non-zero value in response to first and second input signals to a
phase detector being in phase, and wherein the first and the second
input signals are based on the first and the second periodic
signals; and generating an output based on the phase comparison
signal that is indicative of a phase difference between the first
and the second periodic signals and that has a zero value in
response to the first and the second periodic signals being in
phase.
41. The method of claim 40 further comprising: periodically
switching the first and the second periodic signals to a first
output of a first chopper switch circuit and periodically switching
the first and the second periodic signals to a second output of the
first chopper switch circuit, wherein a signal generated at the
first output of the first chopper switch circuit is the first input
signal to the phase detector; and delaying a signal generated at
the second output of the first chopper switch circuit to generate
the second input signal to the phase detector.
42. The method of claim 41 further comprising: alternately and
periodically switching the phase comparison signal and an inverted
version of the phase comparison signal between inputs of a load
circuit using a second chopper switch circuit.
43. The method of claim 40 further comprising: periodically
switching the first and the second periodic signals to a first
output of a first chopper switch circuit and periodically switching
the first and the second periodic signals to a second output of the
first chopper switch circuit; and delaying a signal generated at
the second output of the first chopper switch circuit to generate a
delayed signal.
44. The method of claim 43 further comprising: alternately and
periodically switching a signal generated at the first output of
the first chopper switch circuit and the delayed signal between
outputs of a second chopper switch circuit to generate the first
and the second input signals to the phase detector, wherein a clock
signal controls periodic switching of both the first and the second
chopper switch circuits.
45. The method of claim 43 further comprising: sampling the phase
comparison signal to generate first and second sampled signals; and
subtracting the first sampled signal from the second sampled signal
to generate the output.
46. The method of claim 41 wherein delaying a signal generated at
the second output of the first chopper switch circuit to generate
the second input signal to the phase detector further comprises
delaying the signal generated at the second output of the first
chopper switch circuit by approximately 90.degree. to generate the
second input signal to the phase detector.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This patent application claims the benefit of U.S.
provisional patent application 61/260,797, filed Nov. 12, 2009,
which is incorporated by reference herein in its entirety.
TECHNICAL FIELD
[0002] The present invention relates to electronic circuits, and
more particularly, to techniques for phase detection.
BACKGROUND
[0003] A phase detector circuit generates an output signal that is
indicative of the phase difference between two periodic input
signals. A zero phase detector ideally generates a zero output when
the two periodic input signals are aligned in phase with each
other. Zero phase detectors are used in many applications including
delay-locked loops (DLLs). As data rates increase in modern data
transmission systems, the DLLs in high-speed data transmission
systems require faster zero phase detectors. However, conventional
zero phase detectors have a modest speed limit before generating a
hard failure.
[0004] High-speed zero phase detectors have complex circuit
architectures that consume a large amount of power and die area. An
XOR based quadrature phase detector can operate at a relatively
high speed, but it generates a zero output signal when the periodic
input signals are 90 degrees out of phase. Therefore, it would be
desirable to provide a similarly high-speed zero phase detector
that generates a zero output signal when the periodic input signals
are in phase and that does not have many of the problems of
conventional zero phase detectors.
[0005] It would also be desirable to provide a high-speed
delay-locked loop (DLL) that converges to the point at which the
periodic input signals of the phase detector are aligned in phase.
In one type of DLL, the frequency of a high-speed reference clock
signal is divided by an input frequency divider circuit to generate
a lower speed clock signal. The lower speed clock signal is
provided to the input of a low speed phase detector in the DLL. The
input frequency divider circuit consumes a significant amount of
power and generates a substantial amount of jitter in the output
clock signal. Therefore, it would be desirable to provide a
high-speed DLL that consumes less power and generates less jitter
in the output clock signal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 illustrates an example of a circuit that generates a
zero output when the phases of two periodic input signals are
aligned.
[0007] FIG. 2A illustrates an example of a high-speed phase
detection circuit that uses two quadrature phase detectors and two
delay circuits to generate a zero output in response to the phases
of two periodic input signals being aligned.
[0008] FIG. 2B is a graph of the output voltage response of a
quadrature phase detector plotted over the phase difference (.phi.)
between two periodic input signals to the quadrature phase
detector.
[0009] FIG. 2C is a graph that shows an example of the output
voltage responses of the quadrature phase detectors in FIG. 2A
plotted over the phase difference (.phi.) between the periodic
input signals to the phase detectors.
[0010] FIG. 2D is a graph that shows an example of the output
voltage response of the phase detection circuit of FIG. 2A plotted
over the phase difference (.phi.) between the periodic input
signals.
[0011] FIG. 3 illustrates another example of a phase detection
circuit that uses two quadrature phase detectors to generate a zero
output in response to the phases of two periodic input signals
being aligned.
[0012] FIG. 4 illustrates an example of a phase detection circuit
that uses two zero phase detectors having static phase offsets to
generate a zero output in response to the phases of two periodic
input signals being aligned.
[0013] FIG. 5 illustrates an example of a phase detection circuit
that functions as a zero phase detector using chopper switches, a
quadrature phase detector, and sample and hold circuits.
[0014] FIG. 6A illustrates an example of a phase detection circuit
that generates a continuous time output signal using switches and a
quadrature phase detector.
[0015] FIG. 6B illustrates one example of a current mode logic
(CML) XOR circuit implementation of the phase detection circuit
shown in FIG. 6A.
[0016] FIG. 7 illustrates an example of a phase detection circuit
that samples two periodic input signals and then subtracts the
sampled values to generate a phase comparison signal.
[0017] FIG. 8A illustrates an example of a delay-locked loop (DLL)
circuit that can include one of the phase detection circuits shown
in FIGS. 1, 2A, 3, 4, 5, 6A-6B, and 7.
[0018] FIG. 8B illustrates an example of a phase-locked loop (PLL)
circuit that can include one of the phase detection circuits shown
in FIGS. 1, 2A, 3, 4, 5, 6A-6B, and 7.
[0019] FIG. 9 illustrates an example of a delay-locked loop (DLL)
circuit that aligns the phase of a feedback clock signal with the
phase of a reference clock signal using a quadrature phase
detector.
[0020] FIG. 10 illustrates a schematic diagram of a differential
current mode logic (CML) XOR based phase detector circuit that can
be used as a phase detector in the DLL of FIG. 9.
[0021] FIG. 11 is a graph that illustrates the output response of
the phase detector shown in FIG. 10.
DETAILED DESCRIPTION
[0022] As described herein, a phase detection circuit can function
as a high-speed zero phase detector. The phase detection circuit
does not require a large amount of die area or a large amount of
power consumption. According to some embodiments, the phase
detection circuit includes two high-speed phase detectors. Each of
the high-speed phase detectors generates a non-zero output in
response to input signals to the phase detector being aligned in
phase. The input signals to the phase detectors are based on two
periodic signals. The phase detection circuit subtracts the output
signal of one of the phase detectors from the output signal of the
other phase detector to generate a phase comparison signal having a
zero value when the periodic signals are aligned in phase.
[0023] In other embodiments, a phase detection circuit includes a
chopper switch circuit, a delay circuit, and a high-speed phase
detector. The chopper switch circuit periodically switches input
signals between outputs of the chopper switch circuit. The delay
circuit delays a first output signal of the chopper switch circuit
to generate a delayed signal. The high-speed phase detector
compares a phase of the delayed signal with a phase of a second
output signal of the chopper switch circuit to generate an output
signal. The output signal of the phase detector has a non-zero
value in response to the delayed signal and the second output
signal of the chopper switch circuit being aligned in phase. An
output signal of the phase detection circuit has a zero value in
response to the input signals of the chopper switch circuit being
aligned in phase.
[0024] FIG. 1 illustrates an example of a circuit 100 that
generates a zero output when the phases of two periodic input
signals are aligned. Circuit 100 has a phase detection block 101
that compares the phases of two periodic input signals A and B to
generate a first phase comparison signal VC. Phase detection block
101 also compares the phases of periodic input signals A and B to
generate a second phase comparison signal VD. Phase detection block
101 can include, for example, one or two constituent phase
detectors that generate signals VC and VD. Each of the constituent
phase detectors generates a non-zero output in response to input
signals to the phase detector being aligned in phase. A combiner
circuit 102 combines phase comparison signals VC and VD to generate
a third phase comparison signal OUT that has a zero value when
periodic input signals A and B are aligned in phase.
[0025] FIG. 2A illustrates an example of a high-speed phase
detection circuit that uses two quadrature phase detectors and two
delay circuits to generate a zero output in response to the phases
of two periodic input signals being aligned. Phase detection
circuit 200 includes two delay circuits 201-202, two high-speed
quadrature phase detectors 203-204, and a subtraction circuit 205.
A and B represent two periodic input signals. Signals A and B can
be, for example, clock signals. Signals A and B have the same
frequency.
[0026] Signal A is provided to a first input of quadrature phase
detector 203. Delay circuit 201 delays signal B by about 90.degree.
(i.e., about one-quarter of the period of signal B) to generate a
delayed periodic signal BD that is provided to a second input of
quadrature phase detector 203. Phase detector 203 generates an
output phase comparison voltage signal VC that is indicative of the
phase difference between input signals A and BD.
[0027] Delay circuit 202 delays signal A by about 90.degree. (i.e.,
about one-quarter of the period of signal A) to generate a delayed
periodic signal AD that is provided to a first input of quadrature
phase detector 204. Signal B is provided to a second input of
quadrature phase detector 204. Phase detector 204 generates an
output phase comparison voltage signal VD that is indicative of the
phase difference between input signals AD and B.
[0028] According to alternative embodiments of phase detection
circuit 200, quadrature phase detectors 203-204 are replaced with
phase detectors that generate zero output signals when the phases
of their periodic input signals have a phase offset other than
0.degree. or 90.degree., and delay circuits 201-202 have delays
that equal or approximately equal the phase offset.
[0029] FIG. 2B is a graph of the output voltage response of a
quadrature phase detector, such as phase detectors 203 and 204,
plotted over the phase difference (.phi.) between two periodic
input signals to the quadrature phase detector. As shown in FIG.
2B, the output voltage signal of a quadrature phase detector is
zero when the input signals to the quadrature phase detector have a
phase difference of +90.degree. or -90.degree.. When the periodic
input signals of a quadrature phase detector are aligned in phase
(i.e., have a 0.degree. phase difference), the output voltage
signal of the phase detector reaches a peak value.
[0030] FIG. 2C is a graph that shows an example of the output
voltage responses VC and VD of quadrature phase detectors 203 and
204, respectively, plotted over the phase difference (.phi.)
between periodic signals A and B. Because signal B is delayed by
about 90.degree. before being provided to an input of phase
detector 203 as delayed signal BD, the output voltage VC of phase
detector 203 reaches a peak value (i.e., an inflection point) when
the phase difference between signals A and B is about 90.degree..
When the phase difference between signals A and B is 0.degree., the
output voltage VC of phase detector 203 is near zero. The output
voltage VC of phase detector 203 may be zero when the phase
difference between A and B is slightly positive or slightly
negative, as shown in FIG. 2C, depending on the delay of circuit
201.
[0031] Because signal A is delayed by about 90.degree. before being
provided to an input of phase detector 204 as delayed signal AD,
the output voltage VD of phase detector 204 reaches a peak value
(i.e., an inflection point) when the phase difference between
signals A and B is about -90.degree.. When the phase difference
between signals A and B is 0.degree., the output voltage VD of
phase detector 204 is near zero. Output voltage VD may be zero when
the phase difference between signals A and B is slightly positive,
as shown in FIG. 2C, or slightly negative, depending on the delay
of circuit 202.
[0032] Referring again to FIG. 2A, subtraction circuit 205
subtracts the output voltage VD of phase detector 204 from the
output voltage VC of phase detector 203 to generate the output
voltage signal OUT of phase detection circuit 200. Thus,
VC-VD=OUT.
[0033] FIG. 2D is a graph that shows an example of the output
voltage response OUT of phase detection circuit 200 plotted over
the phase difference (.phi.) between periodic input signals A and
B. As shown in FIG. 2D, phase detection circuit 200 generates a
zero output voltage in OUT in response to a phase difference of
0.degree. between periodic input signals A and B. Phase detection
circuit 200 causes output voltage OUT to be greater than zero in
response to a phase difference between A and B that is between
0.degree. and 180.degree. (that is, periodic signal A lags periodic
signal B by between 0.degree. and) 180.degree.). Phase detection
circuit 200 causes output voltage OUT to be less than zero in
response to a phase difference between A and B that is between
-180.degree. and 0.degree.. Phase detection circuit 200 uses two
high-speed quadrature phase detectors 203-204 to create a circuit
that functions as a high-speed zero phase detector, as shown in
FIG. 2D.
[0034] Delay circuits 201-202 do not need to generate a precise
delay of 90.degree. in signals AD and BD. Phase detection circuit
200 functions as a zero phase detector that generates a zero value
in OUT when A and B are aligned in phase, even if delay circuits
201-202 generate delays in BD and AD that are greater than or less
than 90.degree.. For example, phase detection circuit 200 may
continue to function as a zero phase detector over a range of
variations of the delay of each of circuits 201-202 from 45.degree.
to 135.degree.. In some embodiments, phase detection circuit 200
may have an even wider zero phase detection range for variations of
the delays of circuits 201-202 that are greater than
+/-45.degree..
[0035] Delays circuits 201 and 202 have matching delays. Delay
circuits 201 and 202 have the same circuit and layout designs, so
that process, voltage, and temperature (PVT) variations cause the
delays of circuits 201-202 to vary by the same amount. Phase
detectors 203 and 204 have the same circuit and layout designs. As
a result, variations in output voltages VC and VD track each other
within a particular range (e.g.,
-45.degree.<.phi.<45.degree.) Subtraction circuit 205 cancels
out PVT induced variations in VC and VD near .phi.=0.degree. so
that OUT continues to have a zero voltage crossing at
.phi.=0.degree..
[0036] Delay circuits 201-202 can be any arbitrary delay circuits,
such as, delay chains of inverters, active buffer circuits,
resistor/capacitor/inductor (RLC) filter circuits, transmission
lines, etc. Each of the phase detectors 203-204 can be, for
example, an exclusive OR (XOR) based quadrature phase detector that
generates a zero output when the phase difference between its input
signals is 90.degree.. Subtraction circuit 205 can be an analog
circuit or a digital circuit.
[0037] Phase detection circuit 200 can be used in a wide variety of
applications. For example, phase detection circuit 200 and other
phase detection circuits described herein can be used in
delay-locked loops circuits (DLLs), in phase-locked loops circuits
(PLLs), in clock data recovery circuits, or in other loop circuit
designs. If phase detection circuit 200 uses high-speed XOR based
quadrature phase detectors 203-204, a DLL or PLL that uses phase
detection circuit 200 can achieve a higher reference clock
frequency than conventional zero phase detectors. A DLL or PLL
using phase detection circuit 200 can, for example, be designed to
increase the phase of signal B when the phase difference between
signals A and B is positive, and decrease the phase of signal B
when the phase difference between signals A and B is negative. In
this PLL/DLL example, the phase difference between signals A and B
converges to 0.degree. when the phase difference between A and B is
between -180.degree. and 180.degree.. The lock range for the DLL or
the PLL in this example is
-180.degree.<.phi.<180.degree..
[0038] FIG. 3 illustrates another example of a phase detection
circuit 300 that uses two quadrature phase detectors to generate a
zero output in response to the phases of two periodic input signals
A and B being in alignment. Phase detection circuit 300 includes
four delay circuits 301-304, two quadrature phase detectors
305-306, and subtraction circuit 307.
[0039] Each of delay circuits 301 and 304 has a delay of about
45.degree.. Each of delay circuits 302 and 303 has a delay of about
-45.degree.. A delay circuit generating a negative delay (e.g.,
-45.degree. can be constructed, for example, using LC filters.
45.degree. refers to one-eighth of a period of input signals A and
B. In an alternative embodiment of phase detection circuit 300,
each of delay circuits 301 and 304 has a delay of about
-45.degree., and each of delay circuits 302 and 303 has a delay of
about 45.degree..
[0040] Delay circuit 301 delays input signal A by about 45.degree.
to generate delayed signal A1 at an input of phase detector 305.
Delay circuit 302 delays input signal B by about -45.degree. to
generate delayed signal B1 at an input of phase detector 305. Delay
circuit 303 delays input signal A by about -45.degree. to generate
delayed signal A2 at an input of phase detector 306. Delay circuit
304 delays input signal B by about 45.degree. to generate delayed
signal B2 at an input of phase detector 306.
[0041] Phase detector 305 generates an output phase comparison
voltage signal VC that is indicative of the phase difference
between input signals A1 and B1. Phase detector 306 generates an
output phase comparison voltage signal VD that is indicative of the
phase difference between input signals A2 and B2. Each quadrature
phase detector 305-306 generates a zero output voltage VC/VD in
response to the input signals to that quadrature phase detector
having a phase difference of +90.degree. or -90.degree..
[0042] Subtraction circuit 307 subtracts output voltage VD from
output voltage VC to generate the output voltage signal OUT of
phase detection circuit 300. Phase detection circuit 300 functions
as a zero phase detector that generates a zero output when the
phase difference between signals A and B is 0.degree., even if
delay circuits 301 and 304 generate matching delays in signals A1
and B2 that are slightly greater than or slightly less than
45.degree., and delay circuits 302 and 303 generate matching delays
in signals B1 and A2 that are slightly greater than or slightly
less than -45.degree.. The graph of FIG. 2D is also an example of
the output voltage response OUT of phase detection circuit 300.
[0043] FIG. 4 illustrates an example of a phase detection circuit
400 that uses two zero phase detectors having systematic non-ideal
static phase offsets to generate a zero output in response to the
phases of two periodic input signals A and B being aligned. Phase
detection circuit 400 includes non-ideal zero phase detectors
401-402 with static offsets and subtraction circuit 403. Non-ideal
phase detectors 401 and 402 generate phase comparison voltage
signals VC and VD, respectively, that are indicative of the phase
difference between periodic input signals A and B. Subtraction
circuit 403 subtracts VD from VC to generate output signal OUT.
[0044] Non-ideal zero phase detectors 401-402 generate systematic
static phase offsets in their output signals VC and VD. The static
phase offsets cause detectors 401-402 to generate non-zero voltages
in VC and VD in response to a phase difference of 0.degree. between
signals A and B. The detector output voltages VC and VD therefore
respond as shown in FIG. 2C, with a systematic non-zero output when
the input phase difference .phi. is 0.degree.. However, the
detector output voltages VC and VD of non-ideal phase detectors
401-402 may not peak near 90.degree. as shown in FIG. 2C. Such
non-ideal zero phase detectors may operate faster than accurate
zero phase detectors without such systematic static phase
offsets.
[0045] Non-ideal zero phase detectors 401-402 have the same circuit
designs. As a result, PVT induced variations in the phase
comparison signals VC and VD track each other, and subtraction
circuit 403 cancels out the effects of these variations on output
signal OUT.
[0046] Phase detection circuit 400 generates an output signal OUT
having zero volts in response to a phase difference of 0.degree.
between signals A and B. Phase detection circuit 400 functions as a
zero phase detector using two non-ideal zero phase detectors that
do not generate zero outputs in response to the phases of their
input signals being aligned.
[0047] FIG. 5 illustrates an example of a phase detection circuit
500 that functions as a zero phase detector using one or more
chopper switches, a quadrature phase detector, and sample and hold
circuits. Phase detection circuit 500 generates a zero output in
response to two periodic input signals A and B being aligned in
phase. Phase detection circuit 500 includes chopper switches
501-502, delay circuit 503, quadrature phase detector 504, sample
and hold (S/H) circuits 505-506, and subtraction circuit 507.
[0048] Each of the chopper switches described herein periodically
switches its input signals between the two outputs of the chopper
switch in continuously alternating time periods. In circuit 500,
chopper switches 501-502 alternately route periodic input signals A
and B through delay circuit 503 based on the period of a digital
clock signal CLK. Clock signal CLK controls the switching period
and duty cycle of choppers switches 501-502. Chopper switches
501-502 eliminate the need for a second quadrature phase detector
in circuit 500.
[0049] When clock signal CLK is in a first logic state, chopper
switches 501-502 transmit signal A directly to the 1 input of phase
detector 504 via conductor 508. Also, when CLK is in the first
logic state, chopper switch 501 transmits signal B to an input of
delay circuit 503, delay circuit 503 delays signal B by about
90.degree. to generate a delayed version of signal B, and chopper
switch 502 transmits the delayed version of signal B to the 2 input
of phase detector 504. In this logic state, input signals A and B
are connected to quadrature phase detector 504 in a manner similar
to phase detector 203 in FIG. 2A.
[0050] When clock signal CLK is in a second logic state, chopper
switches 501-502 transmit signal B directly to the 2 input of phase
detector 504 via conductor 508. Also, when CLK is in the second
logic state, chopper switch 501 transmits signal A to the input of
delay circuit 503, delay circuit 503 delays signal A by about
90.degree. to generate a delayed version of signal A, and chopper
switch 502 transmits the delayed version of signal A to the 1 input
of phase detector 504. In this logic state, input signals A and B
are connected to quadrature phase detector 504 in a manner similar
to phase detector 204 in FIG. 2A.
[0051] Quadrature phase detector 504 generates a phase comparison
voltage signal VX that is indicative of the phase difference
between the periodic signals at its 1 and 2 inputs. Sample and hold
circuits 505 and 506 sample the voltage of signal VX to generate
sampled signals VY and VZ, respectively. The sampling rates of
circuits 505 and 506 are based on the timing of clock signals CLK
and CLKB, respectively. Circuit 505 samples VX when CLK is in a
first logic state, and circuit 506 samples VX when CLKB is in the
first logic state. Clock signals CLK and CLKB are 180.degree. out
of phase with each other. Circuit 505 holds the previously sampled
state of VX as signal VY when CLK is in a second logic state, and
circuit 506 holds the previously sampled state of VX as signal VZ
when CLKB is in the second logic state.
[0052] The sampling rate of circuits 505-506 is the same as the
switching rate of chopper switches 501-502. The CLK signal
typically has a lower frequency than the A and B input signals, so
that after the CLK logic state changes, quadrature phase detector
504 has sufficient time to develop an accurate phase measurement
before the result is sampled and the CLK logic state changes again.
Sample and hold circuits 505 and 506 are intended to sample the
voltage of signal VX just before the CLK logic state changes, to
avoid sampling VX during a transition period. Sampling VX during a
transition period can be avoided, for example, by clocking sample
and hold circuits 505 and 506 using an earlier version of CLK and
CLKB than is used to switch chopper switches 501 and 502.
[0053] Subtraction circuit 507 subtracts the voltage of signal VZ
from the voltage of signal VY to generate output signal OUT (i.e.,
VY-VZ=OUT). Phase detection circuit 500 generates a zero in output
signal OUT when the phase difference between periodic input signals
A and B is 0.degree.. However, the output signal OUT of circuit 500
may become discontinuous each time clock signal CLK changes state.
Quadrature phase detector 504 may have a phase response as shown in
FIG. 2B that is insensitive to which of the two input signals has
an earlier phase and is only sensitive to the magnitude of the
phase difference. Therefore, chopper switch 502 may be removed in
some embodiments.
[0054] FIG. 6A illustrates an example of a phase detection circuit
600 that generates a continuous time output signal using switches
and a quadrature phase detector. Phase detection circuit 600
functions as a zero phase detector that generates a zero output in
response to two periodic input signals A and B being aligned in
phase.
[0055] Phase detection circuit 600 includes chopper switch 601,
delay circuit 603, quadrature phase detector input stage circuit
604, inverting delay circuit 605, switch 606, and quadrature phase
detector low pass filter (LPF) output stage circuit 607.
[0056] A digital periodic clock signal CLK controls the switching
periods and duty cycles of switches 601 and 606. When CLK is in a
first logic state, chopper switch 601 transmits signal A directly
to the 1 input of phase detector input stage 604 via conductor 608,
and chopper switch 601 transmits signal B to an input of delay
circuit 603. Delay circuit 603 delays signal B by about 90.degree.
to generate a delayed version of signal B. The delayed version of
signal B is transmitted to the 2 input of phase detector input
stage 604.
[0057] When CLK is in a second logic state, chopper switch 601
transmits signal A to the input of delay circuit 603, and chopper
switch 601 transmits signal B directly to the 1 input of phase
detector input stage 604 via conductor 608. Delay circuit 603
delays signal A by about 90.degree. to generate a delayed version
of signal A. The delayed version of signal A is transmitted to the
2 input of phase detector input stage 604.
[0058] Quadrature phase detector input stage 604 generates a phase
comparison voltage signal VP that is indicative of the phase
difference between the periodic signals at its 1 and 2 inputs.
Quadrature phase detector input stage 604 generates a zero output
voltage in VP in response to the signals at its 1 and 2 inputs
being offset in phase by +/-90.degree.. Signal VP is transmitted to
an input of inverting delay circuit 605 and to a first input of
switch 606. Inverting delay circuit 605 inverts signal VP to
generate an inverted signal VPB (VPB=-VP) that is transmitted to a
second input of switch 606.
[0059] Switch 606 transmits signals VP and VPB to an input of phase
detector LPF output stage 607 in alternating time intervals in
response to clock signal CLK. Phase detector LPF output stage 607
averages phase comparison signal VP and its inverse signal VPB to
generate an output voltage signal OUT that is continuous in time.
Circuit 600 generates a zero voltage in output signal OUT in
response to a phase difference of 0.degree. between signals A and
B.
[0060] The frequency of clock signal CLK is greater than the cutoff
frequency of phase detector LPF output stage 607. Phase detector
LPF output stage 607 filters out the noise in signals VP and VPB
that is added to these signals by the switching of switch 606 and
the chopping operation of the phase detector.
[0061] Using only one quadrature phase detector in phase detection
600 and switch 601 to alternately switch A and B through delay
circuit 603 eliminates the possibility of mismatches between two
different phase detectors operating in parallel that can adversely
affect the output response. It also removes the area needed to
fabricate a second quadrature phase detector.
[0062] In one embodiment, the frequency of clock signal CLK is an
integer division of the frequency of periodic signals A and B. For
example, the frequency of A and B can be 4 or 8 times the frequency
of CLK.
[0063] FIG. 6B illustrates one example of a current mode logic
(CML) XOR circuit implementation of phase detection circuit 600
shown in FIG. 6A. In phase detection circuit 650 shown in FIG. 6B,
phase detector input stage 604 is implemented by CML XOR pull-down
network (PDN) circuit 614 and current source 619. Also in circuit
650, switch 606 is implemented by a chopper switch 612, and phase
detector LPF output stage 607 is implemented by resistors 615-616
and capacitors 617-618.
[0064] Chopper switch 601 and delay circuit 603 function as
described above with respect to FIG. 6A. The 1 and 2 inputs of CML
XOR PDN 614 function as the 1 and 2 inputs of phase detector input
stage 604. CML XOR PDN 614 compares the phases of the periodic
signals at its 1 and 2 inputs to generate differential current
signals IP and IPB, which serve the same purpose as voltage signals
VP and VPB in FIG. 6A, but exist in the current domain. Current
source 619 provides tail current for CML XOR PDN 614 and resistors
615-616.
[0065] Clock signal CLK controls the period and the duty cycle of
chopper switch 612. When CLK is in a first logic state, chopper
switch 612 transmits CML XOR PDN output current IP to output node
621 and output current IPB to output node 622. When CLK is in a
second logic state, chopper switch 612 transmits CML XOR PDN output
current IP to output node 622 and output current IPB to output node
621.
[0066] The output voltages OUT and OUTB of phase detection circuit
650 are generated at output nodes 621 and 622, respectively. Output
voltages OUT and OUTB function as a differential output voltage
signal. Differential output signal OUT/OUTB has a zero voltage in
response to a phase difference of 0.degree. between signals A and
B.
[0067] Load resistors 615 and 616 are coupled between output nodes
621 and 622, respectively, and a supply line that is at supply
voltage VCC. Capacitors 617 and 618 are also coupled between output
nodes 621 and 622, respectively, and the VCC supply line. Resistors
615-616 and capacitors 617-618 function as low pass filters that
convert the switched output currents IP and IPB from CML XOR PDN
614 and chopper switch 612 to output voltages OUT and OUTB.
[0068] CML XOR PDN 614 can be, for example, a symmetrical or an
asymmetrical pull-down network of n-channel field-effect
transistors that perform an XOR Boolean logic function. CML XOR PDN
614 may generate an offset in IP and IPB that is caused by
mismatches between transistors in PDN 614 or an asymmetric design
of PDN 614. However, any offset caused by PDN 614 is canceled out
by the averaging function performed by chopper switch 612 and the
output LPF stage 615-618. Because circuit 650 can function as
intended even with offsets in PDN 614, the area and the complexity
of the design of PDN 614 can be reduced.
[0069] The design of phase detection circuit 650 is merely one
example of an implementation of phase detection circuit 600. Phase
detection circuit 600 can also be implemented using other circuit
components. For example, LPF output stage 607 can be implemented
using an integrator circuit.
[0070] According to an alternative embodiment of phase detection
circuit 600, phase detector input stage 604 is a non-ideal zero
phase detector that has a static phase offset. Delay circuit 603 is
removed in this embodiment, and the second output of switch 601 is
coupled directly to the 2 input of input stage 604.
[0071] FIG. 7 illustrates another example of a phase detection
circuit 700. Phase detection circuit 700 has two sample and hold
circuits that sample two periodic input signals A and B. Phase
detection circuit 700 filters the sampled values of the two
periodic inputs signals and then subtracts the filtered sampled
values to generate an output phase comparison signal. Phase
detection circuit 700 functions as a zero phase detector that
generates a zero output in response to periodic input signals A and
B being aligned in phase.
[0072] Zero phase detector 700 includes n-channel metal oxide
semiconductor field-effect transistors (MOSFETs) 701-704,
capacitors 711-714, and differencing amplifier 720. Signal A is
provided to a first drain/source input of transistor 701, signal B
is provided to the gate of transistor 701, and inverse signal /B is
provided to the gate of transistor 702. Input signals B and /B are
digital periodic signals that are approximately 180.degree. out of
phase with each other.
[0073] Transistor 701 and capacitor 711 function as a first sample
and hold circuit.
[0074] When signal B is in a logic high state, and signal /B is in
a logic low state, transistor 701 is on, transistor 702 is off, and
the state of signal A is stored on capacitor 711. When signal B
transitions to a low logic state, the last value of signal A is
held on capacitor 711. Thus, negative transitions of signal B are
used to sample and hold signal A, which also has a negative
transition at the same time if A and B have a zero phase
difference, forming a non-ideal zero phase detector. The finite
threshold voltage of MOSFET 701, delay in sampling input signal A
onto capacitor 711, and other practical limitations lead to static
phase offsets in such a phase detector, but the phase detector is
relatively fast and simple to implement.
[0075] Transistor 702 and capacitor 712 function as a first
switched capacitor single-pole low pass filter (LPF) to filter the
response of the phase detector formed by transistor 701 and
capacitor 711. When signal B is in a logic low state, and signal /B
is in a logic high state, transistor 701 is off, transistor 702 is
on, and the voltage stored on capacitor 711 is averaged with the
voltage stored on capacitor 712 based on the capacitance ratios of
capacitors 711 and 712.
[0076] Capacitor 712 can have a much larger capacitance than
capacitor 711. For example, the capacitance of capacitor 712 can be
100 or more times larger than the capacitance of capacitor 711.
Transistor 702 and capacitor 712 attenuate high frequency
components of the voltage signal stored on capacitor 712.
Transistors 701-702 and capacitors 711-712 also function as a
non-ideal zero phase detector having a static phase offset.
[0077] Signal B is provided to a first drain/source input of
transistor 703, signal A is provided to the gate of transistor 703,
and inverse signal /A is provided to the gate of transistor 704.
Input signals A and /A are digital periodic signals that are
approximately 180.degree. out of phase with each other. It may be
desirable to adjust the phase relationship between signals B and /B
and the phase relationship between signals A and /A by using early
or late phases. For example, signals /A and /B can be designed to
have a duty cycle that is less than 50%.
[0078] Transistor 703 and capacitor 713 function as a second sample
and hold circuit. When signal A is in a logic high state, and
signal /A is in a logic low state, transistor 703 is on, transistor
704 is off, and the state of signal B is stored on capacitor 713.
When signal A transitions to a low logic state, the last value of
signal B is held on capacitor 713. Thus, negative transitions of
signal A are used to sample and hold signal B, which also has a
negative transition at the same time if A and B have a zero phase
difference, forming a non-ideal zero phase detector.
[0079] Transistor 704 and capacitor 714 function as a second
switched capacitor single-pole low pass filter to filter the
response of the phase detector formed by transistor 703 and
capacitor 713. When signal A is in a logic low state, and signal /A
is in a logic high state, transistor 703 is off, transistor 704 is
on, and the voltage stored on capacitor 713 is averaged with the
voltage stored on capacitor 714 based on the capacitance ratios of
capacitors 713 and 714.
[0080] Capacitor 714 can have a much larger capacitance than
capacitor 713. For example, the capacitance of capacitor 714 can be
100 or more times the capacitance of capacitor 713. Transistor 704
and capacitor 714 attenuate high frequency components of the
voltage signal stored on capacitor 714. Transistors 703-704 and
capacitors 713-714 also function as a non-ideal zero phase detector
having a static phase offset.
[0081] Differencing amplifier 720 amplifies the difference between
the voltage stored on capacitor 712 and the voltage stored on
capacitor 714 to generate an output signal OUT. Because both
capacitor voltages are subject to the same static phase offset from
the two non-ideal zero phase detectors, output signal OUT is a
phase comparison signal having a voltage that is indicative only of
the phase difference between periodic input signals A and B, and
not the discussed static phase offsets. Phase detection circuit 700
generates a zero voltage in output signal OUT in response to a
phase difference of 0.degree. between signals A and B.
[0082] Phase detection circuit 700 is shown as a single-ended
implementation in FIG. 7. According to another embodiment, phase
detection circuit 700 can compare the phases of differential
periodic input signals.
[0083] The phase detection circuits shown in FIGS. 1, 2A, 3, 4, 5,
6A-6B, and 7 can be used in delay-locked loop and phase-locked loop
circuits. FIG. 8A illustrates an example of a delay-locked loop
(DLL) circuit 800 that can include one of the phase detection
circuits shown in FIGS. 1, 2A, 3, 4, 5, 6A-6B, and 7. DLL 800 is
embedded in an integrated circuit 810. DLL 800 includes phase
detection circuit 801, loop filter circuit 802, and variable delay
circuit 803. Phase detection circuit 801 can be one of the phase
detection circuits 100, 200, 300, 400, 500, 600, 650, or 700.
[0084] Phase detection circuit 801 compares the phase of a periodic
feedback clock signal FBCLK to the phase of a periodic reference
clock signal REFCLK to generate a phase comparison signal VC.
Signal VC is indicative of the phase difference between REFCLK and
FBCLK. Loop filter circuit 802 filters the phase comparison signal
VC to generate a filtered phase comparison signal VCF.
[0085] Variable delay circuit 803 delays REFCLK to generate FBCLK.
Variable delay circuit 803 varies the delay provided to FBCLK
relative to REFCLK based on changes in the filtered phase
comparison signal VCF. DLL 800 drives the phase difference between
FBCLK and REFCLK to 0.degree.. When the phase difference between
FBCLK and REFCLK is 0.degree., DLL 800 maintains the phase of FBCLK
constant.
[0086] FIG. 8B illustrates an example of a phase-locked loop (PLL)
circuit 850 that can include one of the phase detection circuits
shown in FIGS. 1, 2A, 3, 4, 5, 6A-6B, and 7. PLL 850 is embedded in
an integrated circuit 860. PLL 850 includes phase detection circuit
851, loop filter circuit 852, oscillator circuit 853, and divider
circuit 854. Phase detection circuit 851 can be one of the phase
detection circuits 100, 200, 300, 400, 500, 600, 650, or 700.
[0087] Phase detection circuit 851 compares the phase of a periodic
feedback clock signal FBCLK to the phase of a periodic reference
clock signal REFCLK to generate a phase comparison signal VC.
Signal VC is indicative of the phase difference between REFCLK and
FBCLK. Loop filter circuit 852 filters the phase comparison signal
VC to generate a filtered phase comparison signal VCF.
[0088] Oscillator circuit 853 generates a periodic output clock
signal OUTCLK. Oscillator circuit 853 varies the frequency of
OUTCLK based on changes in the filtered phase comparison signal
VCF. Divider circuit 854 generates feedback clock signal FBCLK in
response to OUTCLK. Divider circuit 854 divides the frequency of
OUTCLK to generate the frequency of FBCLK. In some embodiments,
divider circuit 854 is removed, and the frequency of FBCLK is equal
to the frequency of OUTCLK. PLL 850 adjusts the phase and the
frequency of FBCLK until FBCLK and REFCLK have the same frequency
and are aligned in phase. When FBCLK and REFCLK have the same
frequency and are aligned in phase, PLL 850 maintains the phase and
the frequency of FBCLK constant.
[0089] FIG. 9 illustrates an example of a delay-locked loop (DLL)
circuit 900 that aligns the phase of a feedback clock signal FBCLK
with the phase of a reference clock signal REFCLK using a
quadrature phase detector. DLL 900 includes a quadrature phase
detector circuit 901, an analog-to-digital converter (ADC) circuit
902, a delay circuit 903, a subtraction circuit 904, a digital
accumulator (ACC) circuit 905, a multiplexer circuit 906, a digital
gain circuit 907, a digital accumulator circuit 908, and digitally
adjustable delay circuit 909. Circuits 903 and 904 together form a
differentiator.
[0090] Quadrature phase detector 901 can be a high-speed phase
detector that consumes a relatively small amount of power.
Quadrature phase detector 901 compares the phase of a periodic
feedback clock signal FBCLK to the phase of a periodic input
reference clock signal REFCLK to generate a phase comparison signal
VQ. The voltage of VQ is indicative of the phase difference between
REFCLK and FBCLK. Voltage VQ may represent a single-ended or
differential signal.
[0091] Quadrature phase detector 901 generates a zero voltage in VQ
in response to a difference of +or -90.degree. between the phases
of FBCLK and REFCLK. REFCLK and FBCLK have the same frequency.
90.degree. refers to one-quarter of a period of REFCLK and FBCLK.
Quadrature phase detector 901 generates a peak voltage in VQ in
response to a phase difference between FBCLK and REFCLK of
0.degree.. DLL 900 is designed to cause the output voltage VQ of
phase detector 901 to converge to a peak voltage that is caused by
the phases of FBCLK and REFCLK being in alignment. The peak voltage
in VQ occurs at an inflection point in a plot of the output
response of VQ.
[0092] Phase comparison signal VQ is an analog voltage signal. ADC
circuit 902 converts analog voltage VQ into a set of digital
signals X.sub.T. Digital signals X.sub.T are representative of the
voltage of VQ. ADC 902 can use, for example, a successive
approximation algorithm.
[0093] Delay circuit 903 performs a unit time interval delay
function on the digital value of signals X.sub.T to generate
digital signals X.sub.T-1. Digital signals X.sub.T-1 represent the
values of signals X.sub.T at preceding time intervals. Subtraction
circuit 904 subtracts signals X.sub.T-1 from signals X.sub.T to
indicate whether X.sub.T is larger or smaller than X.sub.T-1. Thus,
the result MSB of the subtraction performed by circuit 904 is
indicative of the slope of phase comparison signal VQ.
[0094] The MSB output by subtraction circuit 904 is 0 if phase
comparison signal VQ is increasing, and the MSB output by circuit
904 is 1 if phase comparison signal VQ is decreasing. Accumulator
circuit 905 converts the MSB output of circuit 904 into a single
sticky bit STB. Accumulator 905 sets the state of sticky bit STB
based on the history of the MSB output of circuit 904. Sticky bit
STB is transmitted to a select input of multiplexer circuit
906.
[0095] Multiplexer 906 transmits signals having a +1 value to
digital gain circuit 907 when the phase comparison signal VQ has
been increasing over multiple sampled values of VQ. Multiplexer 906
transmits signals having a -1 value to digital gain circuit 907
when the phase comparison signal VQ has been decreasing over
multiple sampled values of VQ. Digital gain circuit 907 sets the
gain of the +1 or -1 signals from multiplexer 906 to generate
scaled output signals that are transmitted to accumulator 908.
Accumulator 908 converts the output signals of circuit 907 into
multi-bit digital control signals DCS.
[0096] Digitally adjustable delay circuit 909 delays input
reference clock signal REFCLK to generate the feedback clock signal
FBCLK. FBCLK and REFCLK have the same frequency. The digital
control signals DCS generated by accumulator 908 control the delay
that digitally adjustable delay circuit 909 adds to FBCLK relative
to REFCLK. Digitally adjustable delay circuit 909 can be, for
example, a phase interpolator, a resonant delay circuit, an
adjustable delay chain, or any other suitable adjustable delay
circuit. An example of a resonant delay circuit that can be used to
implement adjustable delay circuit 909 is described in
commonly-assigned U.S. provisional patent application 61/252,126,
by Aryanfar et al., filed Oct. 15, 2009, which is incorporated by
reference herein in its entirety.
[0097] When multiplexer circuit 906 transmits a +1 value to circuit
907, control signals DCS cause the delay of adjustable delay
circuit 909 to increase. When multiplexer circuit 906 transmits a
-1 value to circuit 907, control signals DCS cause the delay of
adjustable delay circuit 909 to decrease.
[0098] DLL 900 causes the phase difference between FBCLK and REFCLK
to converge to 0.degree., which causes the phase comparison signal
VQ to reach a peak inflection point voltage. When the phase
comparison signal VQ is decreasing, DLL 900 adjusts the phase of
FBCLK to cause the phase comparison signal VQ to increase, until
phase comparison signal VQ reaches a peak voltage. When the phase
comparison signal VQ reaches its peak voltage, DLL 900 maintains
the delay that adjustable delay circuit 909 provides to
[0099] FBCLK at a constant value.
[0100] Quadrature phase detector 901 can be implemented, for
example, by a mixer circuit or by an XOR based phase detector
circuit. FIG. 10 illustrates a schematic diagram of a differential
current mode logic (CML) XOR based phase detector circuit 1000 that
can be used as phase detector 901 in DLL 900. Phase detector 1000
functions as a quadrature phase detector that generates a zero
output when the phase difference between its two periodic input
signals is +/-90.degree.. Phase detector 1000 is a high-speed phase
detector that can detect phase differences between periodic signals
having large frequencies (e.g., 16 GHz). Phase detector 1000
consumes a relatively small amount of power and generates a
relatively small amount of jitter in its output signals.
[0101] Phase detector 1000 includes resistors 1001-1002 and
n-channel MOSFETs 1003-1019. Resistors 1001-1002 are coupled to a
supply line at a supply voltage VCC. The circuit elements of phase
detector 1000 are coupled together in a symmetrical configuration
as shown in FIG. 10.
[0102] Phase detector 1000 receives two differential input signals.
Signals AP and AN are the first differential input signal, and
signals BP and BN are the second differential input signal. Signals
AP, AN, BP, and BN are provided to the gates of transistors
1003-1018 as shown in FIG. 10. If phase detector 1000 is phase
detector 901 in DLL 900, then differential signals AP/AN and BP/BN
are periodic signals REFCLK and FBCLK.
[0103] A constant bias voltage VBN is provided to the gate of
transistor 1019. Transistor 1019 provides tail current for phase
detector 1000.
[0104] Phase detector 1000 performs an XOR Boolean logic function
on differential input signals AP/AN and BP/BN to generate
differential output signal XOR/XNOR. Output voltage XOR is
generated at output node 1022, and output voltage XNOR is generated
at output node 1021.
[0105] According to some embodiments, phase detectors 101, 203 and
204, 305 and 306, 504, and 604/607 can be implemented using CML XOR
based phase detector 1000. According to other embodiments, phase
detectors 101, 203 and 204, 305 and 306, 504, and 604/607 can be
implemented using an asymmetrical CML XOR based phase detector
circuit design having less transistors than phase detector
1000.
[0106] FIG. 11 is a graph that illustrates the output response of
phase detector 1000 shown in FIG. 10. The vertical axis shown in
FIG. 11 indicates the voltage of the differential output signal
XOR/XNOR of phase detector 1000. The horizontal axis shown in FIG.
11 indicates the phase difference .phi. between the differential
input signals AP/AN and BP/BN of phase detector 1000 in
degrees.
[0107] When phase detector 1000 is used in a conventional DLL, the
differential output voltage XOR/XNOR of phase detector 1000
converges to a natural lock point of zero volts. As shown in FIG.
11, two of the natural lock points occur when the phase difference
between differential input signals AP/AN and BP/BN is
+/-90.degree., and the differential output voltage XOR/XNOR of
phase detector 1000 is zero.
[0108] When phase detector 1000 is used as phase detector 901 in
DLL 900, the differential output voltage XOR/XNOR of phase detector
1000 converges to the desired lock point shown in FIG. 11. The
desired lock point occurs at a peak inflection point of the output
voltage response of XOR/XNOR that is generated in response to a
phase difference of 0.degree. between differential input signals
AP/AN and BP/BN.
[0109] The circuitry described herein can be used in any suitable
integrated circuit, such as, for example, a memory integrated
circuit, a controller integrated circuit, a processor integrated
circuit, an analog integrated circuit, a digital integrated
circuit, etc.
[0110] According to an embodiment, a feedback loop circuit
comprises a phase detector, a loop filter, and a phase adjustment
circuit. The phase detector detects a phase relationship between
first and second clock signals. The loop filter generates an output
signal based on an output signal of the phase detector. The
feedback loop circuit operates such that the output signal of the
loop filter converges to where an average value of the output
signal of the phase detector is at a maximum value or an inflection
point. The phase adjustment circuit adjusts a phase of the second
clock signal in response to the output signal of the loop filter.
The phase adjustment circuit can comprise a resonant buffer
circuit, an oscillator, a delay line, or a phase interpolator
circuit. The phase detector can comprise a quadrature phase
detector, such as an XOR based phase detector, or a phase mixer
circuit. The feedback loop circuit can be a DLL or a phase-locked
loop (PLL). In the case of a PLL, the digitally adjustable delay
may be replaced by a digitally controlled oscillator (DCO), such as
a resonant tank oscillator or a ring oscillator.
[0111] According to another embodiment, a feedback loop circuit
comprises a quadrature phase detector, a loop filter, and a phase
adjustment circuit. The quadrature phase detector detects a phase
relationship between first and second clock signals. The loop
filter generates an output signal based on an output signal of the
quadrature phase detector. The feedback loop circuit operates such
that the output signal of the loop filter converges to where the
first and the second clock signals are in phase. The phase
adjustment circuit adjusts a phase of the second clock signal in
response to the output signal of the loop filter. The loop filter
can comprise a differentiator circuit. The feedback loop circuit
can be a DLL or a PLL.
[0112] The foregoing description of the exemplary embodiments has
been presented for the purposes of illustration and description.
The foregoing description is not intended to be exhaustive or
limiting to the examples disclosed herein. In some instances,
certain features of the embodiments can be employed without a
corresponding use of other features as set forth. Many
modifications, substitutions, and variations are possible in light
of the above teachings, without departing from the scope of the
claims.
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