U.S. patent application number 13/349468 was filed with the patent office on 2012-08-16 for test point design for a high speed bus.
This patent application is currently assigned to FLEXTRONICS AP, LLC. Invention is credited to Leon Wu.
Application Number | 20120204421 13/349468 |
Document ID | / |
Family ID | 44475542 |
Filed Date | 2012-08-16 |
United States Patent
Application |
20120204421 |
Kind Code |
A1 |
Wu; Leon |
August 16, 2012 |
TEST POINT DESIGN FOR A HIGH SPEED BUS
Abstract
A test point design comprising: a circuit board comprising a
plurality of layers including a power plane and a ground plane, the
circuit board further comprises a differential pair of signal lines
including a first signal line and a second signal line; and a pair
of test point pads including a first test point pad connected to
the first signal line and a second test point pad connected to the
second signal line, wherein a first portion of the power plane and
a first portion of the ground plane below the first test point pad
are removed and a second portion of the power plane and a second
portion of the ground plane below the second test point pad are
removed.
Inventors: |
Wu; Leon; (Taipei,
TW) |
Assignee: |
FLEXTRONICS AP, LLC
Broomfield
CO
|
Family ID: |
44475542 |
Appl. No.: |
13/349468 |
Filed: |
January 12, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12710622 |
Feb 23, 2010 |
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13349468 |
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Current U.S.
Class: |
29/847 |
Current CPC
Class: |
H05K 2203/162 20130101;
H05K 1/0245 20130101; H05K 1/0268 20130101; Y10T 29/49155 20150115;
Y10T 29/49156 20150115 |
Class at
Publication: |
29/847 |
International
Class: |
H05K 3/02 20060101
H05K003/02 |
Claims
1-11. (canceled)
12. A method of configuring a test point design for a circuit board
including a power plane and a ground plane, the method comprising;
a. removing a first portion of the power plane from a first
position on the power plane that is to be aligned with a first test
point pad on an outer layer of the circuit board; b. removing a
second portion of the power plane from a second position on the
power plane that is to be aligned with a second test point pad on
the outer layer of the circuit board; c. removing a first portion
of the ground plane from a first position on the ground plane that
is to be aligned with the first test point pad, wherein the first
position on the ground plane is aligned with the first position on
the power plane; d. removing a second portion of the ground plane
from a second position on the ground plane that is to be aligned
with the second test point pad, wherein the second position on the
ground plane is aligned with the second position on the power
plane; e. adding a pair of differential signal lines to the outer
layer of the circuit board, wherein the pair of differential signal
lines includes a first signal line and a second signal line; and f.
adding the first test point pad and the second test point pad to
the outer layer of the circuit board, wherein the first test point
pad is connected to the first signal line and the second test point
pad is connected to the second signal line.
13. The method of claim 12 further comprising staggering a position
of the first test point pad and a position of the second test point
pad relative to the pair of signal lines.
14. The method of claim 13 wherein the first test point pad and the
second test point pad are staggered such that a first perpendicular
line between a center of the first test point pad and the first
signal line is not aligned with a second perpendicular line between
a center of the second test point pad and the second signal
line.
15. The method of claim 13 wherein the pitch between the center of
the first test point pad and the center of the second test point
pad is about 65 millimeters.
16. The method of claim 13 wherein the pair of test point pads are
staggered by a pitch sufficient to enable a first probe to contact
the first test point pad and a second probe to contact the second
test point pad concurrently.
17. The method of claim 13 wherein the differential signal lines
are positioned adjacent to each other.
18. The method of claim 12 wherein a segment of the first signal
line connected to the first test pad, a segment of the second
signal line connected to the second test pad, the first test pad,
and the second test pad are all positioned in a same plane.
19. The method of claim 12 wherein the circuit board comprises a
plurality of power planes, and the first portion and the second
portion from one or more of the plurality of power planes nearest
the outer layer are removed.
20. The method of claim 12 wherein the circuit board comprises a
plurality of ground planes, and the first portion and the second
portion from one or more of the plurality of ground planes nearest
the outer layer are removed.
21. The method of claim 12 wherein the circuit board comprises a
plurality of power planes and a plurality of ground planes, and the
first portion and the second portion from one or more of the
plurality of power planes and one or more of the plurality of
ground planes nearest the outer layer are removed.
22. The method of claim 12 wherein the circuit board comprises a
plurality of layers including the power plane, the ground plane,
and the outer layer, further wherein each layer is formed using
semiconductor processing techniques and the first portions and
second portions of each of the power plane and the ground plane are
removed by selective etching.
23. The method of claim 22 wherein the removed first portion and
second portion of the power plane are filled by insulating material
from an insulating layer deposited over the power plane, and the
removed first portion and second portion of the ground plane are
filled by insulating material from an insulating layer deposited
over the ground plane.
24. The method of claim 12 wherein the circuit board comprises a
plurality of layers including the power plane, the ground plane,
and the outer layer, the method further comprises: a. separately
forming at least the power plane as part of a first layered
structure and the ground plane as part of a second layered
structure; b. coupling the first layered structure to the second
layered structure to form a combined layer structure; c. cutting a
first block and a second block from the combined layer structure,
wherein a position of the first block corresponds to the first
position on the ground plane and the first position on the power
plane, and a position of the second block corresponds to the second
position on the ground plane and the second position on the power
plane; and d. coupling the outer layer to the combined layer
structure so that the first test point pad is aligned with the
first block and the second test point pad is aligned with the
second block.
25. The method of claim 24 wherein the pair of differential signal
lines, the first test point pad, and the second test point pad are
formed on the outer layer prior to coupling the outer layer to the
combined layer structure.
26. The method of claim 24 wherein the outer layer is coupled to
the combined layer structure prior to forming the pair of
differential signal lines, the first test point pad, and the second
test point pad on the outer layer, and once coupled to the combined
layer structure, the pair of differential signal lines, the first
test point pad, and the second test point pad are formed on the
outer layer.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to signal lines on a printed
circuit board. More particularly, the present invention relates to
a test point design for a high speed bus.
BACKGROUND
[0002] Electrical signals are communicated between various
electronic components, such as integrated circuits, resistors,
capacitors, etc., using metal traces on a circuit board, such as a
printed circuit board (PCB). Circuit boards are configured to
connect the electronic components in a desired pattern to form an
electrical circuit, collectively referred to as printed circuit
assemblies (PCAs). A circuit board typically includes one or more
conductive layers separated by layers of insulating material,
referred to as substrates or dielectrics. The conductive layers are
etched into conductive patterns, or traces, for connecting the
electronic components, which are soldered to the circuit board. The
conductive layers may be selectively connected together by vias.
One or more of the conductive layers may be of solid metal for
providing a ground plane and/or a power plane. An outer layer of
the circuit board typically includes pads and lands to which the
electronic components are soldered. Most circuit boards also
include a solder mask layer, which is typically a plastic polymer.
The solder mask covers areas of the circuit board that should not
be soldered and includes cutouts or openings in regions where the
electronic components are to be soldered to the circuit board. The
solder mask, which is typically a plastic polymer, resists wetting
by solder, prevents solder from bridging between conductors and
creating short circuits, and may also provide protection against
environmental contaminants.
[0003] FIG. 1 illustrates a cut-out side view of an exemplary
circuit board. The circuit board includes multiple layers 28-60,
including dielectric layers 30, 34, 38, 42, 46, 50, 34, and 58,
ground planes 32, 40, 44, 48, and 56, and power planes 36 and 52.
The circuit board also includes a bottom layer 60 and a top layer
28. A pair of signal lines 2 and 4, and test point pads 6 and 8 are
configured on the top layer 28. It is understood that electronic
components and additional signal lines can be configured on the top
layer 28. Although not shown in FIG. 1, it is understood that a
solder mask can be added as part of the top layer 28. It is
understood that more or less than the number of dielectric layers,
ground plane layers, and power plane layers can be included in the
circuit board. It is also understood that additional conductive
layers can be added and selectively etched to provide conductive
patterns within the circuit board and between the various
electronic components and signal lines on the top layer 28.
[0004] Printed circuit assemblies (PCA's) are typically tested
after manufacture to verify the continuity of traces between pads
and vias on the circuit board and to verify that electronic
components loaded on the circuit board perform within
specifications. Circuit board testing is performed by applying
electrical signals to certain contact points, referred to as test
point pads, on the circuit board. A circuit board test device, such
as an automated in-circuit test (ICT), is capable of probing
conductive pads, vias, and traces on the circuit board under test.
The circuit board test device typically includes a test probe unit
having multiple test probes, each test probe capable of contacting
a certain test point pad of the circuit board and applying an
electrical signal to the test point pad. This necessitates having
test points within the layout of circuit boards that are accessible
by the test probes. Test point pads are usually circular targets
with a 25 to 35 millimeter diameter that are connected to traces on
the circuit board. In some cases, these test points are
deliberately added test point pads, and in other cases the test
points are pads surrounding vias already provided in the circuit
board.
[0005] Layout rules typically require test point pads to be at
least a minimum distance apart and may require the diameter of the
test point pads to greatly exceed the width of the traces. For
example, due to a width of the test probes, when two separate
probes simultaneously engage two adjacent test point pads, a
minimum distance between the adjacent test point pads is required
to provide sufficient physical space for access by the two separate
probes. This minimum distance is often measured from a center of
each of the two adjacent test point pads, and is referred to as
pitch. In many applications, the minimum pitch is about 65
millimeters.
[0006] In many applications, high-speed data is transmitted through
a pair of differential transmission signal lines, or traces. The
pair of signal lines are configured close together, often too close
to enable complimentary test point pads to be connected to the
signal lines because the minimum pitch between the two test point
pads can not be established.
[0007] FIG. 2 illustrates a top-down view of a pair of differential
transmission signal lines and corresponding test point pads
according to a conventional configuration. The pair of differential
signal lines includes a first signal line 2 and a second signal
line 4. A first test point pad 6 is used to test the first signal
line 2, and a second test point pad 8 is used to test the second
signal line 4. Due to the physical parameters of conventional test
probes, the first test point pad 6 and the second test point pad 8
must be spaced a minimum distance apart from each other in order to
permit a first test probe to contact the first test point pad 6
while a second test probe contacts the second test point pad 8.
This minimum distance is defined as pitch, and is shown as line 14
having a distance measured from a center of the first test point
pad 6 to a center of the second test point pad 8. As shown in FIG.
2, line 14 is perpendicular to the signal lines 2 and 4, and as
such the two test point pads 6 and 8 are said to be aligned. In
this configuration, the pitch 14 is great enough to prevent the
test point pads 6 and 8 from being connected directly to the signal
lines 2 and 4, respectively. Moving the test point pads 6 and 8 to
connect directly to the signal lines 2 and 4 would prohibit two
test probes from simultaneously accessing the test point pads 6 and
8. As such, the test point pad 6 is offset from the signal line 2
and the test point pad 8 is offset from the signal line 4, thereby
providing the minimum pitch 14. As the test point pads 6 and 8 are
no longer connected directly to the signal lines 2 and 4, the test
point pads 6 and 8 must be indirectly connected. An extension, or
bridge, 10 is coupled to the test point pad 6. A via (not shown)
couples the bridge 10 to a lower layer trace (not shown) that is
coupled to the signal line 2. Similarly, an extension, or bridge,
12 is coupled to the test point pad 8. A via (not shown) couples
the bridge 10 to a lower layer trace (not shown) that is coupled to
the signal line 4.
[0008] In operation, an electrical signal transmitted along signal
line 2 is divided into two signals at the test point pad 6. A first
of the signals is transmitted to the test point pad 6 and the
second signal continues along the signal line 2. When a test probe
is contacted to the test point pad 6, the first electrical signal
is transmitted to the test probe. However, when a test probe is not
contacted to the test point pad 6, this signal path is considered
"open" and the first electrical signal is reflected back to the
signal line 2. As such, the structure including the test point pad
6 and the signal line 2 is referred to as an "open stub". The open
stub effects the impedance of the signal line 2 at the test point
pad 6, and also effects the signal quality of the electrical signal
transmitted along the signal line 2. The effect of the open stub is
measured by the physical size of the test point pad 2. The larger
the open stub, the greater the change of impedance of the signal
line 2 at the test point pad 6, and the greater the decrease in
signal quality of the electrical signal transmitted along the
signal line 2. A similar open stub is formed by the test point pad
8.
[0009] FIG. 3A illustrates a top-down view of a pair of
differential transmission signal lines and corresponding test point
pads according to an alternative conventional configuration. The
configuration of FIG. 3A is similar to the configuration of FIG. 2
where the test point pads 6 and 8 are positioned with the minimum
pitch 14, except that a connecting line 16 connects the test point
pad 6 to the signal line 2, and a connecting line 18 connects the
test point pad 8 to the signal line 4. The connecting lines 16 and
18 are on the same layer as the signal lines 2 and 4 and the test
point pads 6 and 8. Using connecting lines on the same layer as the
signal lines and the test point pads eliminates the need to couple
the test point pads to the signal lines using an inner layer
conductive pattern, such as in FIG. 1. However, the open stub
structure is increased to include both the test point pad and the
connecting line. As such the effect of the open stub is increased,
which further changes the impedance of the signal line at the test
point pad and further decreases the signal quality of the
electrical signal transmitted along the signal line.
[0010] FIG. 3B illustrates a top-down view of a pair of
differential transmission signal lines and corresponding test point
pads according to another alternative conventional configuration.
The configuration of FIG. 3B is similar to the configuration of
FIG. 2 where the test point pads 6 and 8 are positioned with the
minimum pitch 14, except that the signals lines 22 and 24 are
altered to connect directly with the test point pads 6 and 8,
respectively. Redirecting the signal lines 22 and 24 to enable
direct connection with the test point pads 6 and 8, respectively,
eliminates the need to couple the test point pads to the signal
lines using an inner layer conductive pattern, such as in FIG.
1.
[0011] It is desired to control the transmission impedance value
across the entire run of each signal line. There are a number of
critical parameters that effect the impedance of the signal path.
These parameters include the signal line width, the signal line
separation with an adjacent signal line, the signal line thickness,
and the dielectric constants of the solder mask and board
materials. These parameters influence the inductance, capacitance,
and resistance (skin effect and DC) of the signal lines which
combine to determine the transmission impedance. The addition of a
test point pad to a signal line negatively impacts the transmission
impedance. A capacitance is formed between the test point pad and
the ground planes and power planes positioned below the test point
pad. Conceptually, the test point pad forms one of the conductors
of a capacitor and the ground planes and power planes form the
other conductor in the capacitor. This capacitance negatively
impacts the signal quality of the electrical signal transmitted
along the signal line connected to the test point pad.
SUMMARY OF THE INVENTION
[0012] A circuit board includes a pair of differential signal lines
and a pair of test point pads, one test point pad coupled to one of
the signal lines and another of the test point pads coupled to
another of the signal lines. The two test point pads are staggered
relative to each other and the two signal lines. The circuit board
includes a plurality of conductive layers and a plurality of
insulating layers. The conductive layers can be etched into
conductive patterns, or traces, for connecting the electronic
components, which are soldered to the circuit board. The conductive
layers may be selectively connected together by vias. One or more
of the conductive layers may be a metal plane for providing a
ground plane and/or a power plane. To minimize or eliminate the
capacitance generated between the test point pad and an underlying
ground plane and/or power plane, portions of the ground plane
and/or the portion of the power plane directly aligned with each
test point pad are removed.
[0013] In one aspect, a test point design is disclosed. The test
point design includes a circuit board comprising a plurality of
layers including a power plane and a ground plane, the circuit
board further comprises a differential pair of signal lines
including a first signal line and a second signal line, and a pair
of test point pads including a first test point pad connected to
the first signal line and a second test point pad connected to the
second signal line, wherein a first portion of the power plane and
a first portion of the ground plane below the first test point pad
are removed and a second portion of the power plane and a second
portion of the ground plane below the second test point pad are
removed. In some embodiments, first test point pad and the second
test point pad are staggered relative to the pair of signal lines.
The first test point pad and the second test point pad can be
staggered such that a first perpendicular line between a center of
the first test point pad and the first signal line is not aligned
with a second perpendicular line between a center of the second
test point pad and the second signal line. The pitch between the
center of the first test point pad and the center of the second
test point pad can be about 65 millimeters. In some embodiments,
the pair of test point pads are staggered by a pitch sufficient to
enable a first probe to contact the first test point pad and a
second probe to contact the second test point pad concurrently. The
differential signal lines are positioned adjacent to each other. A
segment of the first signal line connected to the first test pad, a
segment of the second signal line connected to the second test pad,
the first test pad, and the second test pad can be all positioned
in a same plane. The first test point pad and the second test point
pad are both positioned on an outer layer of the circuit board. In
some embodiments, the circuit board Includes a plurality of power
planes, and the first portion and the second portion from one or
more power planes nearest the first test point pad and the second
test point pad are removed. In some embodiments, the circuit board
includes a plurality of ground planes, and the first portion and
the second portion from one or more ground planes nearest the first
test point pad and the second test point pad are removed. In some
embodiments, the circuit board includes a plurality of power planes
and a plurality of ground planes, and the first portion and the
second portion from one or more power planes and one or more ground
planes nearest the first test point pad and the second test point
pad are removed.
[0014] In another aspect, a method of configuring a test point
design for a circuit board including a power plane and a ground
plane is disclosed. The method Includes removing a first portion of
the power plane from a first position on the power plane that is to
be aligned with a first test point pad on an outer layer of the
circuit board, removing a second portion of the power plane from a
second position on the power plane that is to be aligned with a
second test point pad on the outer layer of the circuit board,
removing a first portion of the ground plane from a first position
on the ground plane that is to be aligned with the first test point
pad, wherein the first position on the ground plane is aligned with
the first position on the power plane, removing a second portion of
the ground plane from a second position on the ground plane that is
to be aligned with the second test point pad, wherein the second
position on the ground plane is aligned with the second position on
the power plane, adding a pair of differential signal lines to the
outer layer of the circuit board, wherein the pair of differential
signal lines includes a first signal line and a second signal line,
and adding the first test point pad and the second test point pad
to the outer layer of the circuit board, wherein the first test
point pad is connected to the first signal line and the second test
point pad is connected to the second signal line. The method can
also include staggering a position of the first test point pad and
a position of the second test point pad relative to the pair of
signal lines. The first test point pad and the second test point
pad can be staggered such that a first perpendicular line between a
center of the first test point pad and the first signal line is not
aligned with a second perpendicular line between a center of the
second test point pad and the second signal line. The pitch between
the center of the first test point pad and the center of the second
test point pad can be about 65 millimeters. The pair of test point
pads can be staggered by a pitch sufficient to enable a first probe
to contact the first test point pad and a second probe to contact
the second test point pad concurrently. The differential signal
lines are positioned adjacent to each other. A segment of the first
signal line connected to the first test pad, a segment of the
second signal line connected to the second test pad, the first test
pad, and the second test pad can be all positioned in a same plane.
In some embodiments, the circuit board includes a plurality of
power planes, and the first portion and the second portion from one
or more of the plurality of power planes nearest the outer layer
are removed. In some embodiments, the circuit board includes a
plurality of ground planes, and the first portion and the second
portion from one or more of the plurality of ground planes nearest
the outer layer are removed. In some embodiments, the circuit board
includes a plurality of power planes and a plurality of ground
planes, and the first portion and the second portion from one or
more of the plurality of power planes and one or more of the
plurality of ground planes nearest the outer layer are removed. The
circuit board includes a plurality of layers including the power
plane, the ground plane, and the outer layer. In some embodiments,
each layer is formed using semiconductor processing techniques and
the first portions and second portions of each of the power plane
and the ground plane are removed by selective etching. In this
case, the removed first portion and second portion of the power
plane are filled by insulating material from an insulating layer
deposited over the power plane, and the removed first portion and
second portion of the ground plane are filled by insulating
material from an insulating layer deposited over the ground plane.
In some embodiments, the method also includes separately forming at
least the power plane as part of a first layered structure and the
ground plane as part of a second layered structure, coupling the
first layered structure to the second layered structure to form a
combined layer structure, cutting a first block and a second block
from the combined layer structure, wherein a position of the first
block corresponds to the first position on the ground plane and the
first position on the power plane, and a position of the second
block corresponds to the second position on the ground plane and
the second position on the power plane, and coupling the outer
layer to the combined layer structure so that the first test point
pad is aligned with the first block and the second test point pad
is aligned with the second block. In this embodiment, the pair of
differential signal lines, the first test point pad, and the second
test point pad can be formed on the outer layer prior to coupling
the outer layer to the combined layer structure. Alternatively, the
outer layer can be coupled to the combined layer structure prior to
forming the pair of differential signal lines, the first test point
pad, and the second test point pad on the outer layer, and once
coupled to the combined layer structure, the pair of differential
signal lines, the first test point pad, and the second test point
pad are formed on the outer layer.
[0015] Other features and advantages of the test point design will
become apparent after reviewing the detailed description of the
embodiments set forth below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The accompanying drawings, which are incorporated in and
form a part of this specification, illustrate embodiments of the
test point design and, together with the description, serve to
explain the principles of the test point design, but not limit the
test point design to the disclosed examples.
[0017] FIG. 1 illustrates an cut-out side view of an exemplary
circuit board.
[0018] FIG. 2 illustrates a top-down view of a pair of differential
transmission signal lines and corresponding test point pads
according to a conventional configuration.
[0019] FIG. 3A illustrates a top-down view of a pair of
differential transmission signal lines and corresponding test point
pads according to an alternative conventional configuration.
[0020] FIG. 3B illustrates a top-down view of a pair of
differential transmission signal lines and corresponding test point
pads according to another alternative conventional
configuration.
[0021] FIG. 4 illustrates a top-down view of a pair of differential
transmission signal lines and corresponding test point pads
positioned in a staggered configuration.
[0022] FIG. 5 illustrates an cut-out side view of an exemplary
circuit board including the pair of differential signal lines and
corresponding test point pads of FIG. 4.
[0023] FIG. 6 illustrates an isometric and conceptualized view of
the circuit board configuration of FIG. 5, showing only the
conductive planes.
[0024] FIG. 7 illustrates an exemplary graph of impedance versus
time for the signal line at the test point pad, where the test
point pads are staggered, but the portions of the ground planes and
power planes nearest the test point pads are not removed.
[0025] FIG. 8 illustrates the exemplary graph of impedance versus
time for the signal lines at the test point pads, where the test
point pads are staggered and the portions of the ground planes and
power planes nearest the test point pads are removed.
[0026] FIG. 9 illustrates exemplary graphs of differential
insertion losses versus frequency for the pair of differential
signal lines under various configurations.
[0027] The test point design is described relative to the several
views of the drawings. Where appropriate and only where identical
elements are disclosed and shown in more than one drawing, the same
reference numeral will be used to represent such identical
elements.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
[0028] Reference will now be made in detail to the embodiments of
the test point design, examples of which are illustrated in the
accompanying drawings. While the test point design will be
described in conjunction with the embodiments below, it will be
understood that they are not intended to limit the test point
design to these embodiments and examples. On the contrary, the test
point design is intended to cover alternatives, modifications and
equivalents, which may be included within the spirit and scope of
the test point design as defined by the appended claims.
Furthermore, in the following detailed description of the test
point design, numerous specific details are set forth in order to
more fully illustrate the test point design. However, it will be
apparent to one of ordinary skill in the prior art that the test
point design may be practiced without these specific details. In
other instances, well-known methods and procedures, components and
processes haven not been described in detail so as not to
unnecessarily obscure aspects of the test point design. It will, of
course, be appreciated that in the development of any such actual
implementation, numerous implementation-specific decisions must be
made in order to achieve the developer's specific goals, such as
compliance with application and business related constraints, and
that these specific goals will vary from one implementation to
another and from one developer to another. Moreover, it will be
appreciated that such a development effort might be complex and
time-consuming, but would nevertheless be a routine undertaking of
engineering for those of ordinary skill in the art having the
benefit of this disclosure.
[0029] Embodiments of the test point design are directed to a
circuit board including a pair of differential signal lines,
referred to individually as a first signal line and a second signal
line, and a pair of test point pads, a first test point pad
connected to the first signal line and a second test point pad
connected to the second signal line. The positions of the two test
point pads are staggered such that a line connected to the center
of the first test point pad and the center of the second test point
pad is not perpendicular to the two signal lines. The two test
point pads are also positioned at a minimum pitch sufficient to
allow two test probes to access the two test point pads
simultaneously. In this manner, the each test point pad is
connected directly to one of the signal lines while maintaining the
minimum pitch.
[0030] The circuit board includes a plurality of conductive layers
and a plurality of insulating layers. The conductive layers can be
etched into conductive patterns, or traces, for connecting the
electronic components, which are soldered to the circuit board. The
conductive layers may be selectively connected together by vias.
One or more of the conductive layers may be a metal plane for
providing a ground plane and/or a power plane. In some embodiments,
the pair of differential signal lines and the corresponding test
point pads are formed on a top layer of the circuit board. A solder
mask can be formed over the top layer, with openings in the solder
mask at each of the test point pads. In other embodiments, the pair
of differential signal lines and the corresponding test points pads
are formed on a bottom layer of the circuit board. In still other
embodiments, the pair of differential signal lines are formed on an
inner conductive layer or layers of the circuit board, and the
signal lines are routed from the inner layer(s) to an outer layer,
such as the top layer or the bottom layer, where each signal line
is connected to a corresponding test point pad. As such, at least a
portion of each signal line is formed on an outer layer of the
circuit board, where the portion of the signal line is connected to
a test point pad.
[0031] To minimize or eliminate the capacitance generated between
the test point pad and an underlying ground plane and/or power
plane, the portion of the ground plane and/or the portion of the
power plane directly aligned with the test point pad is removed. In
the configuration where the test point pad is formed on a top layer
of the circuit board, the portion of the ground plane and/or power
plane that is directly underneath the test point pad is removed. In
a configuration where the circuit board includes a plurality of
ground planes, the portion from one or more of the ground planes
nearest the test point pad is removed. In a configuration where the
circuit board includes a plurality of power planes, the portion
from one or more of the ground planes nearest the test point pad is
removed. It is a design configuration to determine how many of the
ground planes and/or power planes have a portion removed. The
further away are the removal of conductive portions of the ground
planes and/or power planes from the test point pad, the greater the
reduction of the undesired capacitance generated by the test point
pad. In some embodiments, the ground plane and the power plane
closest to the test point pad have a portion removed. In general,
any number of the conductive planes, ground plane(s) or power
plane(s), closest to the test point pad can have a portion
removed.
[0032] FIG. 4 illustrates a top-down view of a pair of differential
transmission signal lines and corresponding test point pads
positioned in a staggered configuration. The pair of differential
signal lines includes a first signal line 102 and a second signal
line 104. A first test point pad 106 is used to test the first
signal line 102, and a second test point pad 108 is used to test
the second signal line 104. The position of the first test point
pad 106 and the position of the second test point pad 108 are
staggered relative to the two signal lines 102. 104, that is the
two test point pads 106, 108 are not aligned with each other
relative to the two signal lines 106, 108. As shown in FIG. 4, a
line connecting the center of the first test point pad 106 and the
center of the second test point pad 108 is not perpendicular to the
two signal lines 102, 104. The two test point pads 106, 108 are
also positioned at a minimum pitch 114 sufficient to allow two test
probes to access the two test point pads 106, 108 simultaneously.
In this manner, each test point pad 106, 108 is connected directly
to one of the signal lines 102, 104, respectively, while
maintaining the minimum pitch 114. The two test point pads 106, 108
are staggered apart from each other by at least the minimum pitch
114 to permit a first test probe to contact the first test point
pad 106 while a second test probe simultaneously contacts the
second test point pad 108. In an exemplary application, the minimum
pitch is approximately 65 millimeters. It is understood that the
positions of the two test point pads 106, 108 can be staggered to
accommodate a minimum pitch that is greater than or less than 65
millimeters.
[0033] Since the two test point pads 106, 108 are connected
directly to the signal lines 102, 104, respectively, the physical
size of the open stub S corresponding to each test point pad 106,
108 is reduced compared to the case where the test point pad is
offset from the signal line, as in the conventional configuration
of FIG. 2. In an exemplary configuration where the test point pad
106 has the same radius as the test point pad 6 (FIG. 2), the open
stub S corresponding to the test point pad 106 is smaller than the
open stub T (FIG. 2) corresponding to the test point pad 6. A
smaller open stub value reduces the impedance effect of the test
point pad, which results in a higher signal quality of an
electrical signal passing through the signal line at the test point
pad.
[0034] FIG. 5 illustrates a cut-out side view of an exemplary
circuit board including the pair of differential signal lines and
corresponding test point pads of FIG. 4. The circuit board includes
multiple layers including dielectric layers 130, 134, 138, 142,
146, 150, 154, and 158, ground planes 132, 140, 144, 148, and 156,
and power planes 136 and 152. The circuit board also includes a
bottom layer 160 and a top layer 128. The pair of signal lines 102
and 104, and test point pads 106 and 108 are configured on the top
layer 128. It is understood that electronic components and
additional signal lines can be configured on the top layer 128.
Although not shown in FIG. 5, it is understood that a solder mask
can be added on the top layer 128, with openings in the solder mask
to allow test probe access to the test point pads 106 and 108. It
is understood that more or less than the number of dielectric
layers, ground plane layers, and power plane layers can be included
in the circuit board. It is also understood that additional
conductive layers can be added and selectively etched to provide
conductive patterns within the circuit board, including the signal
lines 102 and 104 on the top layer 28, and between the various
electronic components coupled to the circuit board.
[0035] In addition to staggering the position of the two test point
pads 106, 108, portions of one or more of the conductive planes
nearest the test point pads are removed, or "cut", conceptually
forming apertures, or holes, completely through a thickness of the
conductive planes. Each removed portion of the conductive plane is
that portion aligned, or "underneath" in the case where the test
point pads 106, 108 are formed on the "top" layer 128, with the
test point pad. As shown in FIG. 5, a portion 133 conceptually
represents a removed portion of the ground plane 132 that is
aligned with, or underneath, the test point pad 106. Similarly, a
portion 131 represents a removed portion of the ground plane 132
that is aligned with the test point pad 108. Depending on the
application and the desired adjustment of the capacitance effect
caused by the test point pads, one or more conductive layers can
have portions similarly removed. In the exemplary application of
FIG. 5, two additional conductive layers, the power plane 136 and
the ground plane 140, have portions removed. Specifically, a
portion 137 represents a removed portion of the power plane 136
that is aligned with the test point pad 106, and a portion 135
represents a removed portion of the power plane 136 that is aligned
with the test point pad 108. Also, a portion 141 represents a
removed portion of the ground plane 140 that is aligned with the
test point pad 106, and a portion 139 represents a removed portion
of the ground plane 140 that is aligned with the test point pad
108. It is understood that portions can be removed from more or
less than the three nearest conductive planes to the test point
pads.
[0036] FIG. 6 illustrates an isometric and conceptualized view of
the circuit board configuration of FIG. 5, showing only the
conductive planes. The view in FIG. 6 shows the signal lines 102,
104, the test point pads 106, 108, and the conductive planes 132,
136, and 140 with the portions aligned with the test point pads 106
and 108 removed. The insulting layers 130, 134, and 138 are not
shown in FIG. 6 to better illustrate the relationship between the
test point pads 106, 108 and the removed portions of the conductive
planes 132, 136, 140. In the exemplary configuration shown in FIG.
6, the shape of the test point pads 106, 108 is circular, and the
shape of the removed portions is square. In alternative
configurations, the test point pads can have shapes other than
circles and the removed portions of the conductive layers can have
shapes other than squares. In some embodiments, the shape of the
test point pad is the same as the shape of the removed portion. In
other embodiments, the shape and size of the removed portions is at
least large enough so that no part of the conductive planes from
which the portions are removed remains aligned within any part of
the test point pad.
[0037] Referring to FIG. 5, the removed portions 131, 133, 135,
137, 139, and 141 are representations of portions of the conductive
planes 132, 136, and 140 that have been removed. As such, the
portions 131, 133, 135, 137, 139, 141 do not include conductive
material. In some embodiments, the portions 131, 133, 135, 137,
139, 141 remain void, that is no material occupies the spaces
represented by the portions 131, 133, 135, 137, 139, 141. In other
embodiments, the portions 131, 133, 135, 137, 139, 141 are filled
with insulating material.
[0038] The portions 131, 133, 135, 137, 139, 141 can be formed
using any conventional fabrication process. In one embodiment, the
circuit board is formed by laminating multiple different layer
combinations together. For example, a substrate forms a dielectric
layer, and a conductive layer is deposited on the dielectric layer,
forming a layer combination, such as the dielectric layer 142 and
the ground plane 140. The conductive layer can then be selectively
etched to remove the desired portions, such as portions 139 and
141, that are to be aligned with corresponding test pad points.
Additional layer combinations can be formed in a similar manner,
such as a layer combination that includes the dielectric layer 138
and the power plane 136, a layer combination that includes the
dielectric layer 134 and the ground plane 132, and a layer
combination that includes the dielectric layer 130 and the top
layer 128. Each of the layer combinations is then laminated
together, or coupled together using any other conventional bonding
or joining method, to form the circuit board. The gaps formed in
the removed portions 131, 133, 135, 137, 139, 141 can be left void,
or filled with an insulating material prior to laminating the layer
combinations together.
[0039] In another embodiment, the circuit board is formed by
fabricating each layer on top of each other, for example using
conventional semiconductor fabrication processing methods. In this
embodiment, the portions 131, 133, 135, 137, 139, 141 are filled
with the insulating material used to form the overlaying layer. For
example, the portions 139 and 141 are filled with the material used
for the dielectric layer 138, the portions 135 and 137 are filled
with the material used for the dielectric layer 134, and the
portions 131 and 133 are filled with the material used for the
dielectric layer 130.
[0040] In still another embodiment, the circuit board is formed by
coupling multiple different layer combinations together, but
without etching the portions 131, 133, 135, 137, 139, 141 prior to
coupling. For example, layer combinations are coupled to form an
intermediate circuit board structure including the layers 132, 134,
136, 138, 140, 142, 144, 146, 148, 150, 152, 154, 156, 158, and
160, but not the dielectric layer 130 and the top layer 128. Before
adding the layer combination that includes the dielectric layer 130
and the top layer 128, the layers 132, 134, 136, 138, and 140 are
selectively cut to remove blocks from all the layers 132, 134, 136,
138, 140 that are aligned, or underneath, the test point pads 106
and 108. These removed blocks include the portions 131, 133, 135,
137, 139, and 141. In this manner, a block is removed below each
test point pad, where the block includes portions of the one or
more conductive layers and one or more insulating layers nearest
the test point pad. Once the blocks are removed, the top layer
combination including the dielectric layer 130 and the top layer
128 is added to the intermediate circuit board structure with the
blocks removed. The removed blocks can be left void or can be
filled with insulating material prior to adding the top layer
combination. If the blocks are left void, support is provided to
the test point pads by the underlying dielectric layer 130.
[0041] It is understood that any combination of the above
techniques can be used to form the circuit board with the removed
conductive plane portions. It is also understood that the circuit
board can be formed using any conventional circuit board
fabrication technique that enables the select removal of portions
of the conductive layer(s) nearest the test point pad.
[0042] In an exemplary high speed bus design, a desired design
target for the signal line impedance is 100 ohms. The further the
actual impedance is from 100 ohms, the more negatively performance
is influenced. Addition of test point pads to a pair of
differential signal lines pulls down the impedance from the desired
target level. However, removing the portions of the ground plane(s)
and power planes(s) nearest the test point pads pulls up the
impedance closer to the desired target level. FIG. 7 illustrates an
exemplary graph of impedance versus time for the signal line at the
test point pad, where the test point pads are staggered, but the
portions of the ground planes and power planes nearest the test
point pads are not removed. In this exemplary application, the
impedance is pulled down to approximately 84 ohms. FIG. 8
illustrates the exemplary graph of impedance versus time for the
signal lines at the test point pads, where the test point pads are
staggered and the portions of the ground planes 132 and 140 and
power plane 136 are removed. In this exemplary application, the
impedance is pulled up to approximately 79 ohms.
[0043] FIG. 9 illustrates exemplary graphs of differential
insertion losses versus frequency for the pair of differential
signal lines under various configurations. Graph A shows the
differential insertion losses versus frequency for the pair of
differential signal lines without test point pads added. Graph B
shows the differential insertion losses versus frequency for the
pair of differential signal lines with test point pads added in a
staggered configuration, but without the portions of the ground
planes and the power plane removed. Graph C shows the differential
insertion losses versus frequency for the pair of differential
signal lines with test point pads added in a staggered
configuration and with the portions of the ground planes and the
power plane removed. As shown in FIG. 9, removal of the portions of
the ground plane(s) and power plane(s) nearest the test point pads
reduces the impact on insertion loss.
[0044] The test point design is described above in terms of adding
test point pads to a top layer of a circuit board, and to removing
portions of one or more ground planes and one or more power planes
nearest the top layer. Alternatively, test point pads can be added
to signal lines formed on a bottom layer, and portions of one or
more ground planes and one or more power planes nearest the bottom
layer can be removed. Still alternatively, test point pads can be
added to both the top layer and to the bottom layer, and portions
can be removed from one or more ground planes and one or more power
planes nearest the top layer and from one or more ground planes and
one or more power planes nearest the bottom layer.
[0045] Embodiments of the test point design are described above in
terms of including both the staggered test point pad configuration
and the removed portions of the ground plane(s) and/or power
plane(s). In alternative embodiments, the staggered test point pad
configuration and the removed portions configuration can be
implemented as stand alone configurations.
[0046] Embodiments of the test point design are described above in
terms of maintaining a minimum pitch between two adjacent test
point pads. In alternative embodiments, the minimum pitch does not
have to be maintained, and adjacent test point pads can be
separated by a distance greater than the minimum pitch..
[0047] The test point design has been described in terms of
specific embodiments incorporating details to facilitate the
understanding of the principles of construction and operation of
the test point design. The specific configurations shown and the
methodologies described in relation to the various modules and the
interconnections therebetween are for exemplary purposes only. Such
reference herein to specific embodiments and details thereof is not
intended to limit the scope of the claims appended hereto. It will
be apparent to those skilled in the art that modifications may be
made in the embodiments chosen for illustration without departing
from the spirit and scope of the test point design.
* * * * *