U.S. patent application number 13/446124 was filed with the patent office on 2012-08-09 for method of fabrication of metal oxide semiconductor field effect transistor.
This patent application is currently assigned to UNITED MICROELECTRONICS CORP.. Invention is credited to Bang-Chiang Lan, Yu-Hsin Lin, Yi-Cheng Liu, Chen-Hua Tsai, Cheng-Tzung Tsai.
Application Number | 20120199849 13/446124 |
Document ID | / |
Family ID | 38648816 |
Filed Date | 2012-08-09 |
United States Patent
Application |
20120199849 |
Kind Code |
A1 |
Tsai; Chen-Hua ; et
al. |
August 9, 2012 |
METHOD OF FABRICATION OF METAL OXIDE SEMICONDUCTOR FIELD EFFECT
TRANSISTOR
Abstract
A method of fabrication of a metal oxide semiconductor field
effect transistor includes first providing a substrate on which a
gate structure is formed. Afterwards, a portion of the substrate is
removed to form a first recess in the substrate at both ends of the
gate structure. Additionally, a source/drain extension layer is
deposited in the first recess and a number of spacers are formed at
both ends of the gate structure. Subsequently, a portion of the
source/drain extension and the substrate are removed to form a
second recess in the source/drain extension and a portion of the
substrate outside of the spacer. In addition, a source/drain layer
is deposited in the second recess. Because the source/drain
extension and the source/drain layer have specific materials and
structures, short channel effect is improved and the efficiency of
the metal oxide semiconductor field effect transistor is
improved.
Inventors: |
Tsai; Chen-Hua; (Hsinchu
County, TW) ; Lan; Bang-Chiang; (Taipei City, TW)
; Lin; Yu-Hsin; (Tainan City, TW) ; Liu;
Yi-Cheng; (Hsinchu County, TW) ; Tsai;
Cheng-Tzung; (Taipei City, TW) |
Assignee: |
UNITED MICROELECTRONICS
CORP.
Hsinchu
TW
|
Family ID: |
38648816 |
Appl. No.: |
13/446124 |
Filed: |
April 13, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11308718 |
Apr 26, 2006 |
8207523 |
|
|
13446124 |
|
|
|
|
Current U.S.
Class: |
257/77 ; 257/288;
257/E29.084; 257/E29.242 |
Current CPC
Class: |
H01L 29/6656 20130101;
H01L 21/823807 20130101; Y10S 438/933 20130101; H01L 29/7848
20130101; Y10S 438/938 20130101; H01L 29/66636 20130101; Y10S
438/931 20130101; H01L 29/7834 20130101 |
Class at
Publication: |
257/77 ; 257/288;
257/E29.242; 257/E29.084 |
International
Class: |
H01L 29/161 20060101
H01L029/161; H01L 29/772 20060101 H01L029/772 |
Claims
1. A metal oxide semiconductor field effect transistor, comprising:
a substrate; a gate structure, disposed on the substrate; a spacer,
disposed on a side wall of the gate structure; a source/drain
extension layer, disposed in the substrate and below the spacer; a
source/drain layer, disposed in the substrate and outside of the
spacer, wherein the depth of the source/drain layer is larger than
the depth of the source/drain extension layer; and a dopant
diffusion barrier layer, disposed directly under the source/drain
extension layer and in a side of the source/drain extension layer
near the gate structure; wherein an entire of the source/drain
layer is comprised of a strained material comprising two different
atoms.
2. The metal oxide semiconductor field effect transistor of claim
1, wherein the strained material is silicon germanium.
3. The metal oxide semiconductor field effect transistor of claim
1, wherein the source/drain extension layer is comprised of the
strained material.
4. The metal oxide semiconductor field effect transistor of claim
3, wherein the dopant diffusion barrier layer is comprised of the
strained material.
5. The metal oxide semiconductor field effect transistor of claim
1, wherein the strained material is silicon carbide.
6. A metal oxide semiconductor field effect transistor, comprising:
a substrate; a gate structure, disposed on the substrate; a spacer,
disposed on a side wall of the gate structure; a source/drain
extension layer, disposed in the substrate and below the spacer; a
source/drain layer, disposed in the substrate and outside of the
spacer, wherein the depth of the source/drain layer is larger than
the depth of the source/drain extension layer; and a dopant
diffusion barrier layer, disposed directly under the source/drain
extension layer; wherein an entire of the source/drain extension
layer and the dopant diffusion barrier layer are comprised of a
strained material comprising two different atoms.
7. The metal oxide semiconductor field effect transistor of claim
6, wherein the source/drain extension layer and the dopant
diffusion barrier layer are located between an edge of the gate
structure and an edge of the source/drain layer.
8. The metal oxide semiconductor field effect transistor of claim
6, wherein the dopant diffusion barrier layer is further disposed
directly in a side of the source/drain extension layer near the
gate structure.
9. The metal oxide semiconductor field effect transistor of claim
8, wherein a gap is disposed between the source/drain extension
layer, the dopant diffusion barrier layer and the edge of the gate
structure.
10. The metal oxide semiconductor field effect transistor of claim
6, wherein the source/drain extension layer and the dopant
diffusion barrier layer are of different conductivity types.
11. A metal oxide semiconductor field effect transistor,
comprising: a substrate; a gate structure, disposed on the
substrate; a spacer, disposed on a side wall of the gate structure;
a source/drain extension layer, disposed in the substrate and below
the spacer; a source/drain layer, disposed in the substrate and
outside of the spacer, wherein the depth of the source /drain layer
is larger than the depth of the source/drain extension layer; and a
dopant diffusion barrier layer, disposed directly under the
source/drain extension layer; wherein a top surface of the
source/drain extension layer is higher than a top surface of the
substrate.
12. The metal oxide semiconductor field effect transistor of claim
11, wherein a top surface of the source/drain layer is higher than
the top surface of the source/drain extension layer.
13. The metal oxide semiconductor field effect transistor of claim
11, wherein an entire of the source/drain extension layer is
comprised of a strained material comprising two different
atoms.
14. The metal oxide semiconductor field effect transistor of claim
11, wherein the strained material is silicon germanium.
15. The metal oxide semiconductor field effect transistor of claim
14, wherein the germanium composition ratio of the source/drain
extension layer is of gradient distribution.
16. The metal oxide semiconductor field effect transistor of claim
15, wherein the germanium composition ratio of the portion of the
source/drain extension layer adjacent to the substrate is larger
than the germanium composition ratio of the portion of the
source/drain extension layer disposed at a farther distance to the
substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of an application Ser.
No. 11/308,718, filed on Apr. 26, 2006, now pending. The entirety
of the above-mentioned patent applications is hereby incorporated
by reference herein and made a part of this specification.
BACKGROUND OF THE INVENTION
[0002] 1. Field of Invention
[0003] The present invention is related to a semiconductor device
and its method of fabrication, especially is related to a method of
fabrication of a metal oxide semiconductor field effect transistor
having strained layer.
[0004] 2. Description of Related Art
[0005] The semiconductor industry and wafer fabrication is headed
towards higher efficiency and ultra large-scale integration. For
the sake of accomplishing higher effectiveness using the same
amount of footprint area, the wafer characteristic dimensions and
supply voltage will continue to diminish Generally speaking, if
other characteristics are held constant, the power consumption of
each device will increase according to the on/off frequency.
Therefore, although the supply voltage and the capacitance load are
decreased, the power consumption of the wafer is gradually
increasing. Furthermore, when the dimensions of the field effect
transistor have become smaller, the commonly known short channel
effect will become more pronounced, thus contributing to the
severity of the power consumption issue.
[0006] The method for improving short channel effect includes the
disposition of the source and the shallow source/drain extensions.
Using fabrication of the metal oxide semiconductor field effect
transistor as an example, an implantation of ions is performed
within an elongated region of high dosage first through a mask
after the gate is established, and at the two side walls of the
channel to form shallow extensions. Later, a spacer is formed at
the side wall of the gate, and a source/drain layer is formed in
the substrate outside of the spacer. Followed by an annealing
procedure is later performed. Annealing to activate the doping ion
is then performed, and the shallow extending internally dopant is
allowed to diffuse towards the channel region. Although the dopant
diffused towards the channel region can improve, for example, punch
through and other issues, the dopant diffusion rate is difficult to
control, and excessive dopant will damage the transistor
efficiency.
[0007] Furthermore, for improving further on the short channel
effect, conventional technology is using halo implant to inhibit
the so-called punch through effect. However, the ion for the halo
implant will decrease the drain current, and based on the fact of
continuous gate dimensional shrinkage, this issue will become more
pronounced, thus disallowing the transistor efficiency to further
improve.
SUMMARY OF THE INVENTION
[0008] The present invention is directed to a metal oxide
semiconductor field effect transistor, for raising the drain
current.
[0009] In one embodiment, a metal oxide semiconductor field effect
transistor includes a substrate, a gate structure disposed on the
substrate, a spacer disposed on a side wall of the gate structure;
and a source/drain structure. The source/drain structure includes a
source/drain extension layer disposed in the substrate and below
the spacer, a source/drain layer disposed in the substrate and
outside of the spacer, and a dopant diffusion barrier layer
disposed directly under the source/drain extension layer. The depth
of the source/drain layer is larger than the depth of the
source/drain extension layer. An entire of the source/drain
structure is comprised of a strained material comprising two
different atoms.
[0010] In one embodiment, a metal oxide semiconductor field effect
transistor includes a substrate, a gate structure disposed on the
substrate, a spacer disposed on a side wall of the gate structure,
a source/drain extension layer disposed in the substrate and below
the spacer, a source/drain layer disposed in the substrate and
outside of the spacer, and a dopant diffusion barrier layer
disposed directly under the source/drain extension layer. The depth
of the source/drain layer is larger than the depth of the
source/drain extension layer; and an entire of the source/drain
extension layer and the dopant diffusion barrier layer are
comprised of a strained material comprising two different
atoms.
[0011] In one embodiment, a metal oxide semiconductor field effect
transistor includes a substrate, a gate structure disposed on the
substrate, a spacer disposed on a side wall of the gate structure,
a source/drain extension layer disposed in the substrate and below
the spacer, a source/drain layer disposed in the substrate and
outside of the spacer, and a dopant diffusion barrier layer,
disposed directly under the source/drain extension layer. The depth
of the source/drain layer is larger than the depth of the
source/drain extension layer; and a top surface of the source/drain
extension layer is higher than a top surface of the substrate.
[0012] To better understand the aforementioned advantages,
characteristics, and functionalities, further aspects of the
present invention, and further features and benefits thereof, are
described below. The accompanying drawings, which are incorporated
herein and form a part of the specification, illustrate the present
invention and, together with the description, further server to
explain the principles of the invention and to enable a person
skilled in the pertinent art to make and use the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The accompanying drawings are included to provide a further
understanding of the invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the invention and, together with the description,
serve to explain the principles of the invention.
[0014] FIG. 1A to FIG. 1G are a plurality of cross-sectional views
illustrating the fabrication process of a metal oxide semiconductor
field effect transistor according to an embodiment of the present
invention.
[0015] FIG. 2 is a cross-sectional view of the metal oxide
semiconductor field effect transistor, according to another
embodiment of the present invention.
[0016] FIG. 3A to FIG. 3G are a plurality of cross-sectional views
illustrating the fabrication process of the metal oxide
semiconductor field effect transistor according to another
embodiment of the present invention.
[0017] FIG. 4 is a cross-sectional view of the metal oxide
semiconductor field effect transistor, according to another
embodiment of the present invention.
DESCRIPTION OF THE EMBODIMENTS
First Embodiment
[0018] FIG. 1A to FIG. 1G are a plurality of cross-sectional views
illustrating the fabrication process of the metal oxide
semiconductor field effect transistor according to an embodiment of
the present invention. In a first embodiment, the metal oxide
semiconductor field effect transistor of the present invention is
illustrated using a PMOS process as an example.
[0019] Referring to FIG. 1A, a substrate 100 is first provided,
where the substrate 100, for example, is a silicon-based substrate,
a pure silicon substrate, a silicon on insulator (SOI) substrate, a
germanium channel substrate, a substrate having bulk strain, or a
substrate having crystallographic orientation. A plurality of
isolation structures 102 are formed in the substrate 100. The
material of the isolation structure 102, for example, is silicon
oxide. A gate structure 104 is formed on the substrate 100 between
the isolation structures 102. The gate structure 104 at least
includes a gate dielectric layer 104a, a gate 104b, a spacer 104c
and a gate protection layer 104d. The material of the gate
dielectric layer 104a, for example, is silicon oxide, the material
of the gate 104b, for example, is doped polysilicon, the material
of the spacer 104c, for example, is silicon oxide, and the material
of the gate protection layer 104d, for example, is silicon nitride
or silicon oxide. Furthermore, a channel region 106 of the metal
oxide semiconductor field effect transistors is formed at the
substrate 100 and below the gate structure 104.
[0020] Later, referring to FIG. 1B, a dry etching process 108 is
performed, a portion of the substrate 100 is removed, and a recess
110 is formed at the two side walls of the gate structure 104 in
the substrate 100. The dry etching process 108, for example, is
reactive ion etching(RIE). A reaction gas used in the dry etching
process 108, for example, is hexafluroethane (C.sub.2F.sub.6) or
helium.
[0021] Later, referring to FIG. 1C, a source/drain extension layer
112 is formed inside the recess 110. The material of the
source/drain extension layer 112, for example, is silicon
germanium. The composite structure of the silicon germanium is
typically represented by SiXGe.sub.1-x, or SiGe can be directly
used for representation, wherein x is from 0 to 1. Furthermore, the
structure of the source/drain extension layer 112, for example,
includes epitaxy. The method of fabrication of the source/drain
extension layer 112, for example, is selective epitaxial
deposition, which allows silicon germanium to grow only on the
silicon, and not on the silicon oxide or the silicon nitride. In
other words, silicon germanium only grows in the recess 110, and
not on the spacer 104c, the gate protection layer 104d, and the
isolation structure 102. The selective epitaxial deposition, for
example, is vapor phase epitaxy, which includes reduced pressure
chemical vapor deposition epitaxial deposition, atmospheric
pressure chemical vapor deposition epitaxy, and ultra high vacuum
chemical vapor deposition epitaxy.
[0022] A point worthy to mention is that, because the lattice
constant of germanium is larger than silicon, therefore, the
source/drain extension layer 112 consists of the silicon germanium
is a strained layer. In other words, due to the inner stress, the
silicon germanium lattice of the source/drain extension layer 112,
produce an anisotropic structure, and thus changing the conduction
band and the valence band. Because the source/drain extension layer
112 is bonded to the substrate 100, the conduction band and the
valence band can be tailored to perform design discontinuously to
produce quantum well and built-in electric field, therefore, the
rate of penetration of the carrier of the interface between the
source/drain extension layer 112 and the substrate 100 is allowed
to be increased. In summary, the source/drain extension layer 112,
by employing silicon germanium as material, can improve the
efficiency of the metal oxide semiconductor field effect
transistor.
[0023] Furthermore, the source/drain extension layer 112, for
example, includes P-type dopants. The P-type dopants, for example,
are intended to perform in-situ doping injection and ex-situ doping
during the forming of the source/drain extension layer 112. In
comparison, in-situ doping allows the source/drain extension layer
112 to have higher active dopant concentration. Furthermore,
because the source/drain extension layer 112 is a strained layer
which uses silicon germanium as material, therefore, the
source/drain extension layer 112 will exert a stress on the channel
region 106. This stress and the aforementioned highly-activated
dopant concentration will increase the saturation-region drain
current, (Idsat), and the linear-region drain current, (Idlin), of
the transistor. Therefore, the P-type dopant can also, after the
forming of source/drain extension layer 112, perform ex-situ dopant
injection. Furthermore, the P-type dopants, for example, are boron
ions. One thing worth mentioning is that, after the forming of the
source/drain extension layer 112, the procedure of doped activation
annealing is typically performed, and the P-type dopant is allowed
to diffuse towards the channel region 106 below the gate structure
104. For the sake of effectively controlling the diffusion rate of
the P-type dopants in the present embodiment, prior to the forming
of the source/drain extension layer 112, a dopant diffusion barrier
layer 114 formed inside the recess 110 is further included, but the
present invention is not only limited to this. The material of the
dopant diffusion barrier layer 114, for example, is silicon
germanium. Furthermore, the dopant diffusion barrier layer 114, for
example, includes N-type dopants, for preventing excessive P-type
dopants from diffusing towards the channel region 106. The method
of fabrication of the dopant diffusion barrier layer 114, for
example, is the aforementioned selective epitaxial deposition.
Furthermore, in another embodiment, the germanium composition ratio
of the portion of the source/drain extension layer 112 adjacent to
the substrate 100, for example, is larger than the germanium
composition ratio of the portion of the source/drain extension
layer 112 disposed at a farther distance to the substrate 100. This
type of design allows the portion of the source/drain extension
layer 112 closer to the channel region 106 to have more germanium
atoms for preventing the excessive P-type dopant from diffusing
towards the channel region 106. Furthermore, the germanium
composition ratio of the source/drain extension layer 112, for
example, is of gradient distribution. As can be seen, when the
source/drain extension layer 112 includes P-type dopants, the
germanium distribution of the source/drain extension layer 112 can
be used to control the quantity of P-type dopants diffused towards
the channel region 106.
[0024] Later, referring to FIG. 1D, a spacer 116 is formed at the
two side walls of the gate structure 104. The material of the
spacer 116, for example, is silicon nitride, and the method of
fabrication of the spacer 116 is a conventional technique used and
known by those skilled in the art, therefore, no further details
are described here.
[0025] Later, referring to FIG. 1E, a dielectric layer 118 is
formed on the isolation structure 102. The material of the
dielectric layer 118, for example, is silicon oxide or silicon
nitride. The method of fabrication of the dielectric layer 118, for
example, includes forming a dielectric layer over all of the
structures illustrated in FIG. 1D, then performing a
photolithography and etching process to expose the spacer 116 and
the source/drain extension layer 112 thereby forming the dielectric
layer 118. Later, using the spacer 116 and the dielectric layer 118
as a mask, a dry etching process 120 is performed for removing
portions of the source/drain extension layer 112 and portions of
the substrate 100 to form a recess 122. Furthermore, because the
metal oxide semiconductor field effect transistor of the present
embodiment further includes the dopant diffusion barrier layer 114,
therefore, the dry etching process 120 further includes the removal
of a portion of the dopant diffusion barrier layer 114. In
addition, reaction gas used in the dry etching process 120 during
removal of silicon germanium is, for example, HBr, SF6, or
Cl.sub.2.
[0026] Later, referring to FIG. 1F, inside the recess 122, a
source/drain layer 124 is deposited. The material of the
source/drain layer 124, for example, is silicon germanium, and the
structure of the source/drain layer 124, for example, is an epitaxy
layer. In addition, because the material of the source/drain layer
124 is silicon germanium, therefore, the source/drain layer 124 is
a strained layer, thus can improve the efficiency of the metal
oxide semiconductor field effect transistor. The method of
fabrication of the source/drain layer 124, for example, is the
aforementioned selective epitaxial deposition, which only allows
silicon germanium to grow on the silicon, and not to grow on
silicon oxide or silicon nitride. In other words, silicon germanium
will only grow on the recess 122, and will not grow on the gate
protection layer 104d, the spacer 116 and the dielectric layer 118.
Furthermore, the source/drain layer 124, for example, includes
P-type dopants. For example, P-type dopants are intended to perform
in-situ doping injection during the forming of the source/drain
layer 124. In comparison with ex-situ doping, in-situ doping can
make the source/drain layer 124 to have higher activation doping
concentration. Furthermore, because the source/drain layer 124 is a
strained layer, using silicon germanium as the material, the
source/drain layer 124 therefore exerts a stress on the channel
region 106. This stress and the aforementioned high activation
doping concentration will increase the saturation-region drain
current and the linear-region drain current of the transistor.
Indeed, after the forming of the source/drain layer 124, ex-situ
doping injection can also be performed. Furthermore, the P-type
dopant of the source/drain layer 124, for example, is boron
ion.
[0027] Later, referring to FIG. 1G, the gate protection layer 104d
and the dielectric layer 118 are removed. The method for removing
the gate protection layer 104d and the dielectric layer 118, for
example, is a wet etching process, and this wet etching process,
for example, uses hot phosphoric acid or hydrofluoric acid as an
etchant. Later, a metal silicide layer 126 is formed on the gate
104b, on the gate structure 102 and also on the source/drain layer
124, for decreasing the contact resistance between the subsequently
formed contact and the source/drain layer 124 and the contact
resistance between the contact and the gate 104b. The material of
the metal silicide layer 126, for example, is Ni(SiGe). The method
of fabrication of the metal silicide layer 126, for example, is
first to deposit a layer of nickel, later a rapid thermal
anneal(RTA), is performed. The material and method of fabrication
of the aforementioned metal silicide layer 126 is an embodiment,
however, the present invention is not limited to this only. Later,
subsequent procedures are performed to complete the fabrication of
the metal oxide semiconductor field effect transistor.
[0028] Because the dopant diffusion barrier layer is formed prior
to forming the source/drain extension layer in the present
invention, therefore, after the forming the source/drain extension
layer, the P-type dopants is blocked because of activation
annealing when diffuse towards the channel region. Furthermore,
because the germanium composition ratio of the portion of the
source/drain extension layer 112 adjacent to substrate 100, for
example, is larger than the germanium composition ratio of the
portion of the source/drain extension layer 112 disposed at a
farther distance to the substrate 100, therefore, P-type dopants,
because of activation annealing, can have controlled diffusing rate
towards the channel region. Because the diffusing rate of the
P-type dopants towards the channel region is well controlled,
therefore, the fabrication tolerance is increased.
Second Embodiment
[0029] FIG. 2 is a cross-sectional view of a metal oxide
semiconductor field effect transistor, according to another
embodiment of the present invention.
[0030] Referring to FIG. 2, this metal oxide semiconductor field
effect transistor primarily includes a substrate 200, an isolation
structure 202, a gate structure 204, a spacer 216, a source/drain
extension layer 212, and a source/drain layer 224. The substrate
200, for example, is a silicon-based substrate, a silicon on
insulator (SOI) substrate, a germanium channel substrate, a
substrate having bulk strain, or a substrate having
crystallographic orientation. The gate structure 204 is disposed on
the substrate 200 between the isolation structures 202. A portion
of the substrate 200 below the gate structure 204 is the channel
region of the metal oxide semiconductor field effect transistor.
The spacer 216 is disposed on the side wall of the gate structure
204. The source/drain extension layer 212 is disposed in the
substrate 200 and under the spacer 216, and the source/drain layer
224 is disposed in the substrate 200 and outside of the spacer 216,
and the depth of the source/drain layer 224 is larger than the
depth of the source/drain extension layer 212. The source/drain
extension layer 212 and the source/drain layer 224 are both
strained layers. The following descriptions serve to illustrate the
advantages and structure of the two strained layers.
[0031] The structure of the source/drain extension layer 212, for
example, is epitaxy, and the structure of the source/drain layer
224 can also be epitaxy. Furthermore, the material of the
source/drain extension layer 212, for example, is silicon
germanium, and the material of the source/drain layer 224 can also
be silicon germanium. Furthermore, because germanium lattice
constant is larger than silicon, therefore, the adopting of silicon
germanium as material by the source/drain extension layer 212 and
the source/drain layer 224 is a strained layer. The source/drain
extension layer 212 and the source/drain layer 224 will exert
stress on the channel region 206, thus increasing the
saturation-region drain current and the linear-region drain current
of the transistor. Furthermore, the source/drain extension layer
212, by adopting silicon germanium as material, can allow the rate
of penetration of the carrier of the interface between the
source/drain extension layer 212 and the substrate 200 to be
increased, thus improving the efficiency of the metal oxide
semiconductor field effect transistor.
[0032] Furthermore, the source/drain extension layer 212, for
example, includes P-type dopants. This P-type dopants, for example,
are boron ions. The germanium composition ratio of a portion of the
source/drain extension layer 212 adjacent to the substrate 200, for
example, is larger than the germanium composition ratio of a
portion of the source/drain extension layer 212 disposed at a
farther distance to the substrate 200. The P-type dopants, for
blocking the source/drain extension layer 212, are thereby diffused
towards the channel region 206 because of heat, or at least control
the quantity of P-type dopants diffusing towards the channel region
206. Furthermore, the germanium composition ratio of the
source/drain extension layer 212, for example, is of gradient
distribution. Furthermore, the metal oxide semiconductor field
effect transistor of the present invention further includes a
dopant diffusion barrier layer 214, disposed between the
source/drain extension layer 212 and the substrate 200. The
material of the dopant diffusion barrier layer 214, for example, is
silicon germanium, and the dopant diffusion barrier layer 214, for
example, includes N-type dopants. Because of the set up of the
dopant diffusion barrier layer 214, the P-type dopants can be
further blocked or controlled, are thus diffused towards the
channel region 206, or at least control the quantity of the P-type
dopants diffused towards the channel region 206. In addition, the
source/drain layer 224 can also include P-type dopants, and these
P-type dopants, for example, are boron ions.
[0033] Because the source/drain extension layer and the
source/drain layer of the metal oxide semiconductor field effect
transistor of the present invention are of strained layers,
therefore, the source/drain extension layer and the source/drain
layer will exert stress towards the channel region, thereby
increasing the saturation-region drain current and the
linear-region drain current of the transistor. Furthermore, because
the material of the source/drain extension layer and the
source/drain layer are both silicon germanium, therefore, the
efficiency of the metal oxide semiconductor field effect transistor
can be increased. In addition, because the dopant diffusion barrier
layer is set up and the source/drain extension layer has a
specified distribution method for the germanium composition ratio,
therefore, the diffusion towards the channel region of the dopant
under heating inside the source/drain extension layer can be
blocked, or at least the quantity of the dopants diffused towards
the channel region can be controlled.
Third Embodiment
[0034] FIG. 3A to FIG. 3G are cross-sectional views illustrating a
fabrication process of a metal oxide semiconductor field effect
transistor according to a third embodiment of the present
invention.
[0035] In the third embodiment, a NMOS fabrication process is
described as an example for the illustration of the metal oxide
semiconductor field effect transistor of the present invention.
[0036] Referring to FIG. 3A, first, a substrate 300 is provided.
The substrate 300, for example, is a silicon-based substrate, a
silicon on insulator (SOI) substrate, a germanium channel
substrate, a substrate having bulk strain, or a substrate having
crystallographic orientation. A plurality of isolation structures
302 are formed in the substrate 300. The material of the isolation
structure 302, for example, is silicon oxide. A gate structure 304
is formed on the substrate 300 between the isolation structures
302. The gate structure 304 at least includes a gate dielectric
layer 304a, a gate 304b, and a spacer 304c, and a gate protection
layer 304d. The material of the gate dielectric layer 304a, for
example, is silicon oxide. The material of the gate 304b, for
example, is doped polysilicon, the material of the spacer 304c, for
example, is silicon oxide, and the material of the gate protection
layer 304d, for example, is silicon nitride or silicon oxide.
Furthermore, the substrate 300 below the gate structure 304 is the
channel region 306 of the metal oxide semiconductor field effect
transistor.
[0037] Later, referring to FIG. 3B, a dry etching process 308 is
performed, and a portion of the substrate 300 is removed at the two
side walls of the gate structure in the substrate 300 to form a
recess 310. The dry etching process 308, for example, is reactive
ion etching.
[0038] Later, referring to FIG. 3C, a source/drain extension layer
312 is formed inside the recess 310. The material of the
source/drain extension layer 312 for example, is silicon carbide.
The composite structure of the silicon carbide is typically
represented by SiXC.sub.1-x, or directly represented by SiC. In
which, the range for X is from 0 to 1. Furthermore, the structure
of the source/drain extension layer 312, for example, is epitaxy.
The method of fabrication of the source/drain extension layer 312,
for example, is selective epitaxial deposition, which allows
silicon carbide to only grow on the silicon, and not on the silicon
oxide or the silicon nitride. In other words, silicon carbide only
grows on the recess 310, and not on the spacer 304, the gate
protection layer 304d, and the isolation structure 302. The
selective epitaxial deposition, for example, is vapor-phase
epitaxial fabrication, which includes low-pressure chemical vapor
deposition epitaxial growth, atmospheric pressure CVD epitaxial
growth, and ultra-high vacuum CVD epitaxial growth.
[0039] One thing worthy of mentioning is that, the lattice constant
of carbon is less than silicon, therefore, the source/drain
extension layer 312 which adopts silicon carbide as material is a
strained layer. In other words, the silicon carbide lattice of the
source/drain extension layer 312, due to stretching stress,
produces an anisotropic structure, thereby changing the conduction
band and the valence band. When the source/drain extension layer
312 and the substrate 300 are integrated, the conduction band and
the valence band can be tailored to perform design discontinuously
to produce quantum well and built-in electric field, therefore, the
rate of penetration of the carrier of the interface between the
source/drain extension layer 312 and the substrate 300 is allowed
to be increased. In summary, the source/drain extension layer 312,
by adopting silicon carbide as material, can improve the efficiency
of the metal oxide semiconductor field effect transistor.
[0040] Furthermore, the source/drain extension layer 312, for
example, includes N-type dopants. N-type dopants, for example, are
intended to perform in-situ doping injection during the forming of
the source/drain extension layer 312. In comparison with ex-situ,
in-situ doping allows the source/drain extension layer 312 to have
higher activation doping concentration. The higher activation
doping concentration increases the saturation-region drain current
and the linear-region drain current of the transistor. Of course,
N-type dopants can also perform ex-situ doping injection after the
forming the source/drain extension layer 312. Furthermore, N-type
dopants, for example, are boron ions or arsenic ions. One thing
worthy of mentioning is that, after the forming of the source/drain
extension layer 312, the procedure for doping activation annealing
will typically be performed, thus allowing the diffusion of N-type
dopant towards the channel region 306 below the gate structure 304.
For the effective controlling of the diffusion rate of the N-type
dopants, in the present embodiment, prior to the forming of the
source/drain extension layer 312, a dopant diffusion barrier layer
314 formed inside the recess 310 is further included, but the
present invention is not limited to this. The material of the
dopant diffusion barrier layer 314, for example, is silicon
carbide. Furthermore, the dopant diffusion barrier layer 314, for
example, includes P-type dopants, for preventing excessive amount
of N-type dopant from diffusing towards the channel region 306. The
method of fabrication of the dopant diffusion barrier layer 314,
for example, is the aforementioned selective epitaxial deposition.
Furthermore, in another embodiment, the carbon composition ratio of
the portion of the source/drain extension layer 312 adjacent to the
substrate 300, for example, is larger than the carbon composition
ratio of the portion of the source/drain extension layer 312 at a
farther distance to the substrate 300. This type of design allows a
portion of the source/drain extension layer 312 adjacent to the
channel region 306 to have more carbon atoms, to block excessive
amount of N-type dopant to diffuse towards the channel region 306.
Furthermore, the carbon composition ratio of the source/drain
extension layer 312, for example, is of gradient distribution. Thus
it can be seen that, when the source/drain extension layer 312
includes N-type dopant, it is possible to utilize the carbon
distribution of the source/drain extension layer 312 to control the
amount of N-type dopant which is diffused towards the channel
region 306.
[0041] Later, referring to FIG. 3D, a spacer 316 is formed on the
two side walls of the gate structure 304. The material of the
spacer 316, for example, is silicon nitride, and the method of
fabrication of the spacer 316 in the present invention is of a
conventional technique used and known by those skilled in the art,
therefore, no further details are required.
[0042] Later, referring to FIG. 3E, a layer of dielectric layer 318
is formed on the isolation structure 302. The material of the
dielectric layer 318, for example, is silicon oxide or silicon
nitride. The method of fabrication of the dielectric layer 318, for
example, is to first form a layer of the dielectric layer over all
of the structures illustrated in FIG. 3D, then to perform
photolithography and etching to expose the spacer 316 and the
source/drain extension layer 312, and then to forming it. Later,
using the spacer 316 and the dielectric layer 318 as a mask, a dry
etching process 320 is performed for removing a portion of the
source/drain extension layer 312 and a portion of the substrate 300
to form a recess 322. Furthermore, because the metal oxide
semiconductor field effect transistor of the present embodiment
further includes the dopant diffusion barrier layer 314, therefore,
the dry etching process 320 further includes the removal of a
portion of the dopant diffusion barrier layer 314. In addition, the
reaction gas used in the dry etching process 320 during removal of
silicon carbide is, for example, CF.sub.4, C.sub.4F.sub.8, or
C.sub.5F.sub.10.
[0043] Later, referring to FIG. 3F, a source/drain layer 324 is
deposited inside the recess 322. The material of the source/drain
layer 324, for example, is silicon carbide, The structure of the
source/drain layer 324, for example, is epitaxy. In addition,
because the material of the source/drain layer 324 is silicon
carbide, therefore, the source/drain layer 324 is a strained layer,
thus the efficiency of the metal oxide semiconductor field effect
transistor can be improved. The method of fabrication of the
source/drain layer 324, for example, is the aforementioned
selective epitaxial deposition, to allow silicon carbide grow only
on the silicon, and not grow on silicon oxide or silicon nitride.
In other words, silicon carbide will only grow on the recess 322,
and will not grow on the gate protection layer 304d, the spacer 316
and the dielectric layer 318. Furthermore, the source/drain layer
324, for example, includes N-type dopant. N-type dopants, for
example, during the forming of the source/drain layer 324, are
intended to perform in-situ doping injection. In comparison with
ex-situ doping, in-situ doping can make the source/drain layer 324
to have higher activation doping concentration. The high activation
doping concentration will increase the saturation-region drain
current and the linear-region drain current of the transistor. Of
course, ex-situ doping injection can be performed after the forming
of the source/drain layer 324. Furthermore, N-type dopant of the
source/drain layer 324, for example, is phosphorous ion or arsenic
ion.
[0044] Later, referring to FIG. 3G, the dielectric layer 318 and
the gate protection layer 304d is removed. The method for removal
of the gate protection layer 304d and the dielectric layer 318, for
example, is a wet etching process, and this wet etching process,
for example, is using hot phosphoric acid or hydrofluoric acid as
an etchant. Later, a metal silicide layer 326 is formed on the gate
304b, on the gate structure 302 and also on the source/drain layer
324, for decreasing the contact resistance between the subsequently
formed contact and the source/drain layer 324, and the contact
resistance between the contact and the gate 304b. The material of
the silicide layer 326, for example, is nickel silicide or other
metal silicides. The method of fabrication of the metal silicide
layer 326, for example, is to first deposit a layer of nickel, and
then to perform a rapid thermal anneal. The material and method of
fabrication of the aforementioned metal silicide layer 326 is
exemplary, however, the present invention is not limited to this
only. Later, subsequent procedures are performed for the completion
of the fabrication of the metal oxide semiconductor field effect
transistor.
[0045] Because a layer of dopant diffusion barrier layer is first
formed prior to forming of the source/drain extension layer in the
present invention, therefore, the N-type dopants are blocked
because of activation annealing is then diffused towards the
channel region after forming of the source/drain extension layer.
Furthermore, because the carbon composition ratio of the portion of
the source/drain extension layer adjacent to the substrate, for
example, is larger than the carbon composition ratio of the portion
of the source/drain extension layer at a farther distance to the
substrate, therefore, N-type dopant, because of activation
annealing, can have controlled rate of diffusion towards the
channel region. Because the diffusion rate of the N-type dopants
towards the channel region is well controlled, therefore,
fabrication tolerance is increased.
Fourth Embodiment
[0046] FIG. 4 is a cross-sectional view of a metal oxide
semiconductor field effect transistor, according to another
embodiment of the present invention.
[0047] Referring to FIG. 4, the metal oxide semiconductor field
effect transistor mainly includes a substrate 400, an isolation
structure 402, a gate structure 404, a spacer 416, a source/drain
extension layer 412, and a source/drain layer 424. The substrate
400, for example, is a silicon-based substrate, a silicon on
insulator (SOI) substrate, a germanium channel substrate, a
substrate having bulk strain, and a substrate having
crystallographic orientation. The gate structure 404 is disposed on
the substrate 400 between the isolation structures 402. A portion
of the substrate below the gate structure 404 is the channel region
406 of the metal oxide semiconductor field effect transistor. The
spacer 416 is disposed on the side wall of the gate structure 404.
The source/drain extension layer 412 is disposed in the substrate
400 below the spacer 416, and the source/drain layer 424 is
disposed in the substrate 400 outside of the spacer 416, and the
depth of the source/drain layer 424 is larger than the depth of the
source/drain extension layer 412. The source/drain extension layer
412 and the source/drain layer 424 are both strained layers. The
following are the detailed description of the advantages and
structure of the two strained layers:
[0048] The structure of the source/drain extension layer 412, for
example, is epitaxy, and the structure of the source/drain layer
424 can also be epitaxy. Furthermore, the material of the
source/drain extension layer 412, for example, is silicon carbide,
and the material of the source/drain layer 424 can also be silicon
carbide. Because the carbon lattice is lesser than silicon,
therefore, the source/drain extension layer 412 and the
source/drain layer 424, which adopt silicon carbide as material,
are strained layers. The source/drain extension layer 412 and the
source/drain layer 424 will apply a tensile stress towards the
channel region 406. Furthermore, the source/drain extension layer
412 adopting silicon carbide as material can allow the rate of
penetration of the carrier of the interface between the
source/drain extension layer 412 and the substrate 400 to be
increased, thus improving the efficiency of the metal oxide
semiconductor field effect transistor.
[0049] Furthermore, the source/drain extension layer 412, for
example, includes N-type dopants. The N-type dopants, for example,
are phosphorous ions or arsenic ions. The carbon composition ratio
of the portion of the source/drain extension layer 412 adjacent to
the substrate 400, for example, is larger than the carbon
composition ratio of the portion of the source/drain extension
layer 412 at a farther distance to the substrate 400, as a result,
the N-type dopants of the source/drain extension layer 412, is
prevented from diffusing towards the channel region 406 because of
heat, or at least the quantity of N-type dopants diffused towards
the channel region 406 is controlled. Furthermore, the carbon
composition ratio of the source/drain extension layer 412, for
example, is of gradient distribution. Furthermore, the metal oxide
semiconductor field effect transistor of the present invention
further includes a layer of dopant diffusion barrier layer 414,
disposed between the source/drain extension layer 412 and the
substrate 400. The material of the dopant diffusion barrier layer
414, for example, is silicon carbide, and the dopant diffusion
barrier layer 414, for example, includes P-type dopant. Because of
the set up of the dopant diffusion barrier layer 414, therefore,
the N-type dopants, because of heating, is thus diffused towards
the channel region 406 and can be further blocked or controlled, or
at least the quantity of the N-type dopant diffused towards the
channel region 406 can be controlled. In addition, the source/drain
layer 424 can also include N-type dopant, and the N-type dopants,
for example, are phosphorous ions or arsenic ions.
[0050] Because the source/drain extension layer and the
source/drain layer of the metal oxide semiconductor field effect
transistor of the present invention are both strained layers and
the material of the source/drain extension layer and of the
source/drain layer are both silicon germanium, therefore, the
efficiency of the metal oxide semiconductor field effect transistor
can be increased. In addition, because of the set up of the dopant
diffusion barrier layer and the source/drain extension layer having
a specific distribution method for carbon composition ratio,
therefore, the dopant inside of the source/drain extension layer
which are diffused towards the channel region due to heating can be
blocked, or at least the quantity of the dopants which are diffused
towards the channel region can be controlled.
[0051] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
present invention without departing from the scope or spirit of the
invention. In view of the foregoing descriptions, it is intended
that the present invention covers modifications and variations of
this invention if they fall within the scope of the following
claims and their equivalents.
* * * * *