U.S. patent application number 13/331546 was filed with the patent office on 2012-07-26 for method for fabricating magnetic tunnel junction.
Invention is credited to Gyu An Jin, Dong Ha JUNG, Su Ryun Min.
Application Number | 20120187510 13/331546 |
Document ID | / |
Family ID | 46142410 |
Filed Date | 2012-07-26 |
United States Patent
Application |
20120187510 |
Kind Code |
A1 |
JUNG; Dong Ha ; et
al. |
July 26, 2012 |
METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION
Abstract
A method for fabricating a magnetic tunnel junction element
includes forming a magneto resistance layer including a first
magnetic layer, an insulation layer and a second magnetic layer on
a substrate, forming a magnetic loss area by doping a magnetic loss
impurity into a region of the magneto resistance layer to cause a
magnetic loss, and etching the magnetic loss area to form a
magnetic tunnel junction element.
Inventors: |
JUNG; Dong Ha; (Yongin-si,
KR) ; Jin; Gyu An; (Suwon-si, KR) ; Min; Su
Ryun; (Cheongju-si, KR) |
Family ID: |
46142410 |
Appl. No.: |
13/331546 |
Filed: |
December 20, 2011 |
Current U.S.
Class: |
257/421 ;
257/E29.323; 257/E43.006; 438/3 |
Current CPC
Class: |
H01L 43/12 20130101 |
Class at
Publication: |
257/421 ; 438/3;
257/E43.006; 257/E29.323 |
International
Class: |
H01L 29/82 20060101
H01L029/82; H01L 43/12 20060101 H01L043/12 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 24, 2011 |
KR |
10-2011-0006706 |
Claims
1. A method for fabricating a magnetic tunnel junction element,
comprising: forming a magneto resistance layer including a first
magnetic layer, an insulation layer and a second magnetic layer on
a substrate; forming a magnetic loss area by doping a magnetic loss
impurity into a region of the magneto resistance layer to cause a
magnetic loss; and etching the magnetic loss area to form a
magnetic tunnel junction element.
2. The method of claim 1, further comprising forming a hard mask
layer and a mask pattern on the magneto resistance layer after
forming the magneto resistance layer.
3. The method of claim 2, wherein the forming of the magnetic loss
area comprises doping the magnetic loss impurity into the magneto
resistance layer using the mask pattern as an etching mask.
4. The method of claim 2, wherein the etching of the magnetic loss
area is performed using the mask pattern as an etch barrier.
5. The method of claim 1, wherein the magnetic loss impurity
includes at least one selected from the group consisting of Ga, Ge,
As and In.
6. The method of claim 1, wherein the first magnetic layer
comprises a pinning layer including at least one selected from the
group consisting of IrMn, PtMn, MnO, MnS, MnTe, MnF.sub.2,
FeF.sub.2, FeCl.sub.2, FeO, CoCl.sub.2, CoO, NiCl.sub.2 and NiO,
and a pinned layer including at least one selected from the group
consisting of Fe, Co, Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi, MnSb,
CrO.sub.2, MnOFe.sub.2O.sub.3, FeOFe.sub.2O.sub.3,
NiOFe.sub.2O.sub.3, CuOFe.sub.2O.sub.3, EuO and
Y.sub.3Fe.sub.5O.sub.12.
7. The method of claim 1, wherein the second magnetic layer
includes at least one selected from the group consisting of Fe, Co,
Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi, MnSb, CrO.sub.2,
MnOFe.sub.2O.sub.3, FeOFe.sub.2O.sub.3, NiOFe.sub.2O.sub.3,
CuOFe.sub.2O.sub.3, EuO and Y.sub.3Fe.sub.5O.sub.12.
8. The method of claim 1, further comprising: forming a capping
layer to surround the magnetic tunnel junction element; and
oxidizing the capping layer.
9. The method of claim 8, wherein the capping layer includes at
least one selected from the group consisting of Al, Cr and Ta.
10. A semiconductor device including a magnetic tunnel junction
element, comprising: a patterned magneto resistance layer; and an
electrode layer on the patterned magneto resistance layer wherein
the patterned magneto resistance layer includes a magnetic loss
area formed by doping a magnetic loss impurity except for a region
for maintaining magnetic properties, wherein the magnetic loss
impurity causes a magnetic loss.
11. The semiconductor device of claim 10, wherein the magnetic loss
impurity includes at least one selected from the group consisting
of Ga, Ge, As and In.
12. The semiconductor device of claim 10, wherein the patterned
magneto resistance layer includes a first magnetic layer, an
insulation layer and a second magnetic layer.
13. The semiconductor device of claim 12, wherein the first
magnetic layer comprises a pinning layer including at least one
selected from the group consisting of IrMn, PtMn, MnO, MnS, MnTe,
MnF.sub.2, FeF.sub.2, FeCl.sub.2, FeO, CoCl.sub.2, CoO, NiCl.sub.2
and NiO, and a pinned layer including at least one selected from
the group consisting of Fe, Co, Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi,
MnSb, CrO.sub.2, MnOFe.sub.2O.sub.3, FeOFe.sub.2O.sub.3,
NiOFe.sub.2O.sub.3, CuOFe.sub.2O.sub.3, EuO and
Y.sub.3Fe.sub.5O.sub.12.
14. The semiconductor device of claim 13, wherein the second
magnetic layer includes at least one selected from the group
consisting of Fe, Co, Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi, MnSb,
CrO.sub.2, MnOFe.sub.2O.sub.3, FeOFe.sub.2O.sub.3,
NiOFe.sub.2O.sub.3, CuOFe.sub.2O.sub.3, EuO and
Y.sub.3Fe.sub.5O.sub.12.
15. The semiconductor device of claim 10, further comprising a
capping layer that surrounds the patterned magneto resistance layer
and the electrode layer.
16. The method of claim 15, wherein the capping layer including at
least one selected from the group consisting of Al, Cr and Ta.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority of Korean Patent
Application No. 10-2011-0006706, filed on Jan. 24, 2011, which is
incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] Exemplary embodiments of the present invention relate to a
method for fabricating a magnetic tunnel junction, and more
particularly, to a method for fabricating magnetic tunnel junctions
having a uniform critical dimension (CD).
[0003] A dynamic random access memory (DRAM) and a flash memory
device are representative of semiconductor devices. Here, the DRAM
has a fast data processing speed due to easier data access, whereas
the flash memory device stores nonvolatile data. Further, the DRAM
periodically refreshes data, whereas the flash memory device has a
slow data processing speed due to more difficult data access.
[0004] Recently, semiconductor devices combining benefits of both
the DRAM and the flash memory device have been developed. An
exemplary semiconductor device is a spin transfer random access
memory, which uses the quantum mechanical effect, i.e., magneto
resistance. The spin transfer random access memory has the easier
data accessibility of the DRAM and the non-volatile data storage
capacity of the flash memory device.
[0005] The spin transfer random access memory includes a magnetic
tunnel junction to store data. Generally, the magneto resistance
(MR) is changed depending on the magnetization direction between
two ferromagnetic layers. The spin transfer random access memory
senses a change in magneto resistance and reads whether data stored
in the magnetic tunnel junction is 1 or 0.
[0006] FIG. 1 illustrates a plan view of a conventional magnetic
tunnel junction and a sectional view taken along line of the
magnetic tunnel junction.
[0007] As illustrated in FIG. 1, the magnetic tunnel junction
includes a first magnetic layer 102, an insulation layer 103 and a
second magnetic layer 104, which are formed on a substrate 101. The
first magnetic layer 102 is a layer of which magnetization
direction is fixed, and a second magnetic layer 104 is a layer of
which magnetization direction is changed depending on a supply
direction of current.
[0008] If the magnetization directions of the first and second
magnetic layers 102 and 104 are the same, the resistance of the
magnetic tunnel junction is low. If the magnetization directions of
the first and second magnetic layers 102 and 104 are opposite to
each other, the resistance of the magnetic tunnel junction is high.
According to these characteristics, the magnetic tunnel junction
reads data by supplying current between the first and second
magnetic layers 102 and 104 and measuring the resistance of the
magnetic tunnel junction.
[0009] Here, critical dimensions (CDs) of magnetic tunnel junctions
may be changed in a process of patterning the magnetic tunnel
junctions. In FIG. 1, the lateral width W1 of a first magnetic
tunnel junction MTJ1 is patterned larger than the lateral width W2
of a second magnetic tunnel junction MTJ2. Also, the longitudinal
width of the first magnetic tunnel junction MTJ1 is patterned
larger than that of the second magnetic tunnel junction MTJ2. This
is because distributions of etch plasma in the magnetic tunnel
junctions MTJ1 and MTJ2 are different for each other in the process
of patterning the magnetic tunnel junctions MTJ1 and MTJ2. In a
case where the CDs of the magnetic tunnel junctions are different
from each other, tunneling magneto resistances (TMRs) and
resistances of area factors (RAs) in the magnetic tunnel junctions
are different from each other and makes it difficult to read data.
Here, the TMR and RA are magnetization characteristics of the
magnetic tunnel junction.
SUMMARY OF THE INVENTION
[0010] An embodiment of the present invention is directed to a
method for fabricating magnetic tunnel junctions having a uniform
CD.
[0011] In accordance with an embodiment of the present invention, a
method for fabricating a magnetic tunnel junction includes forming
a magneto resistance layer on a substrate, wherein the magneto
resistance layer comprises a first magnetic layer, an insulation
layer and a second magnetic layer; forming a magnetic loss area by
doping a magnetic loss impurity into a region of the magneto
resistance layer to cause a magnetic loss; and etching the magnetic
loss area to form the magnetic tunnel junction.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 illustrates a plan view of a conventional magnetic
tunnel junction and a sectional view taken along line I-I' of the
magnetic tunnel junction.
[0013] FIGS. 2A to 2F illustrate plan views of a magnetic tunnel
junction and sectional views taken along line II-II' of the
magnetic tunnel junction, illustrating a method for fabricating the
magnetic tunnel junction in accordance with an embodiment of the
present invention.
DESCRIPTION OF SPECIFIC EMBODIMENTS
[0014] Exemplary embodiments of the present invention will be
described below in more detail with reference to the accompanying
drawings. The present invention may, however, be embodied in
different forms and should not be construed as limited to the
embodiments set forth herein. Rather, these embodiments are
provided so that this disclosure will be thorough and complete, and
will fully convey the scope of the present invention to those
skilled in the art. Throughout the disclosure, like reference
numerals refer to like parts throughout the various figures and
embodiments of the present invention.
[0015] FIGS. 2A to 2F illustrate plan views of a magnetic tunnel
junction and sectional views taken along line II-II' of the
magnetic tunnel junction, illustrating a method for fabricating the
magnetic tunnel junction in accordance with an embodiment of the
present invention.
[0016] As illustrated in FIG. 2A, a first magnetic layer 2 is
formed on a substrate having a bottom layer 1 formed therein.
[0017] The bottom layer 1 includes a cell transistor for selecting
a magnetic tunnel junction and a contact plug for connecting a
junction area of the cell transistor and the magnetic tunnel
junction. Here, the contact plug is also referred to as a bottom
electrode.
[0018] The first magnetic layer 2 includes a diamagnetic layer
referred to as a pinning layer 2A and a ferromagnetic layer
referred to as a pinned layer 2B. The pinning layer 2A functions to
fix the magnetization direction of the pinned layer 2B. To this
end, the pinning layer 2A is formed of a thin film made of at least
one selected from the group consisting of IrMn, PtMn, MnO, MnS,
MnTe, MnF.sub.2, FeF.sub.2, FeCl.sub.2, FeO, CoCl.sub.2, CoO,
NiCl.sub.2 and NiO. The magnetization direction of the pinned layer
2B is fixed by the pinning layer 2A. To this end, the pinned layer
2B is formed of a thin film made of at least one selected from the
group consisting of Fe, Co, Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi,
MnSb, CrO.sub.2, MnOFe.sub.2O.sub.3, FeOFe.sub.2O.sub.3,
NiOFe.sub.2O.sub.3, CuOFe.sub.2O.sub.3, EuO and
Y.sub.3Fe.sub.5O.sub.12.
[0019] Subsequently, an insulation layer 3 is formed on the first
magnetic layer 2.
[0020] The insulation layer 3 may be a MgO layer. Alternatively,
the insulation layer 3 may be formed of a Group-TV semiconductor
layer or may be formed by adding a Group-III or Group V element
such as B, P or As to the Group-IV semiconductor layer so as to
control the electric conductivity thereof.
[0021] Subsequently, a second magnetic layer 4 is formed on the
insulation layer 3.
[0022] The magnetization of the second magnetic layer 4 is changed
depending on the supply direction of current. The second magnetic
layer 4 is formed of a thin film made of at least one selected from
the group consisting of Fe, Co, Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi,
MnSb, CrO.sub.2, MnOFe.sub.2O.sub.3, FeOFe.sub.2O.sub.3,
NiOFe.sub.2O.sub.3, CuOFe.sub.2O.sub.3, EuO and
Y.sub.3Fe.sub.5O.sub.12.
[0023] Hereinafter, the first magnetic layer 2, the insulation
layer 3 and the second magnetic layer 4 are together referred to as
a magneto resistance layer.
[0024] Subsequently, a hard mask layer 5 is formed on the second
magnetic layer 4.
[0025] The hard mask layer 5 protects the magnetic tunnel junction
and acts as a top electrode. The hard mask layer 5 is used as an
etch barrier for etching the second magnetic layer 4, the
insulation layer 3 and the first magnetic layer 2. To this end, the
hard mask layer 5 is formed of tungsten (W).
[0026] Subsequently, an etch barrier layer 6, an anti-reflection
layer 7 and mask patterns 8 are sequentially formed on the hard
mask layer 5.
[0027] The etch barrier layer 6 is a thin film for preserving an
etch margin of the mask pattern 8. Here, the etch barrier layer 6
in addition to the mask pattern 8 is used to etch the mask pattern
8. To this end, the etch barrier layer 6 is formed of amorphous
carbon (a-carbon).
[0028] The anti-reflection layer 7 prevents the profile of the mask
pattern 8 from being changed by reflection of light in a process of
forming the mask pattern 8, i.e., an exposure process. According to
an example, the anti-reflection layer 7 is formed of silicon
nitride (Si.sub.3N.sub.4).
[0029] The mask pattern 8 is a thin film for defining the profile
of the magnetic tunnel junction, and each constituent of the mask
pattern 8 defines one magnetic tunnel junction. Constituents of the
mask pattern 8 are formed to have the uniform size throughout and
are formed using a photo-resist.
[0030] As illustrated in FIG. 2B, a magnetic loss impurity 9 is
doped into the magneto resistance layer using the mask pattern 8 as
an ion implantation mask. Here, the doping is performed by ion
implantation.
[0031] As described above, the mask pattern 8 defines the profile
of the magnetic tunnel junction. Accordingly, the magneto
resistance layer (3 and 4) into which the magnetic loss impurity 9
is not doped by the mask pattern 8 is an area to act as the
magnetic tunnel junction, i.e., a magnetic area 11, and the magneto
resistance layer doped with the magnetic loss impurity 9 is an area
not to act as the magnetic tunnel junction, i.e., a magnetic loss
area 10. The magnetic area 11 substantially becomes a CD of the
magnetic tunnel junction. Since the sizes of constituents of the
mask pattern 8 are the same, the heights H1 and H2 of the magnetic
areas 11 are the same, and the widths W1 and W2 of the magnetic
areas 11 are the same. The same heights and widths mean that CDs of
the magnetic areas 11 are the same.
[0032] The magnetic loss impurity 9 is an impurity that causes loss
of magnetic properties of the magneto resistance layer and may be
any reasonably suitable element such as Ga, Ge, As and In. Here,
Ga, Ge, As and In are non-magnetic. Since the Ga, Ge, As and In
have a property in which they are not diffused even at a high
temperature, no diffusion occurs after being doped into the magneto
resistance layer. This means that the Ga, Ge, As and In can prevent
the magnetic area 11 from getting smaller due to expansion of the
magnetic loss area 10 from diffusion.
[0033] As illustrated in FIG. 2C, the etch barrier layer 6 and the
anti-reflection layer 7 are etched using the mask pattern 8 as an
etch barrier. In this case, a part or the entirety of the mask
pattern 8 is lost. Subsequently, the hard mask layer 5 is etched
using the etched etch barrier layer 6 as an etch barrier, thereby
forming a hard mask layer pattern 5A.
[0034] In the process of forming the hard mask layer pattern 5A, a
sidewall surface of the hard mask layer pattern 5A does not have a
vertical surface but has a slope. Thus, the width of a lower
surface of the hard mask layer pattern 5A is greater than that of
an upper surface of the hard mask layer pattern 5A. The width of
the upper surface of the hard mask layer pattern 5A is same as the
width of the mask pattern 8.
[0035] As illustrated in FIG. 2D, the magneto resistance layer is
etched using the hard mask layer pattern 5A as an etch barrier,
thereby forming magnetic tunnel junctions 12.
[0036] As described above, the width of the lower surface of the
hard mask layer pattern 5A is greater than that of the upper
surface of the hard mask layer pattern 5A. Therefore, when the
magneto resistance layer is etched using the hard mask layer
pattern 5A as an etch barrier, the entirety of the magnetic area 11
is included in the magnetic tunnel junction 12, and a part of the
magnetic loss area 10 is also included in the magnetic tunnel
junction 12. This is because the magnetic area 11 is defined/farmed
by using the mask pattern 8.
[0037] In the process of patterning the magnetic tunnel junctions
12, the widths W3 and W4 and heights H3 and H4 of the magnetic
tunnel junctions 12 may be different from each other depending on
the distribution of etch plasma. However, since the widths W1 and
W2 and heights H2 and H2 of the areas substantially having
magnetization directions in the respective magnetic tunnel
junctions 12, i.e., the magnetic areas 11, are the same, the
magnetic characteristics of the magnetic tunnel junctions 12 are
the same.
[0038] As illustrated in FIG. 2E, a capping layer 13 is formed on
the substrate having the magnetic tunnel junctions 12 formed
thereon.
[0039] The capping layer 13 is a thin film for protecting the
magnetic tunnel junctions 12. To this end, the capping layer 13 is
formed of a metal layer, e.g., at least one selected from the group
consisting of Al, Cr and Ta.
[0040] Subsequently, the metal layer used as the capping layer 13
is oxidized through an oxidation process.
[0041] Metallic polymer may be produced in the process of
patterning the magnetic tunnel junctions 12. Without the oxidation
process, the metallic polymer may cause the first and second
magnetic layers 2 and 4 to short-circuit to each other. If the
oxidation process is performed after the capping layer 13 is
formed, the metallic polymer is oxidized together with the capping
layer 13. Hence, although the metallic polymer is absorbed in areas
between the first and second magnetic layers 2 and 4, the two
layers 2 and 4 are not electrically connected to each other.
[0042] As illustrated in FIG. 2F, an interlayer insulating layer 14
is formed on the oxidized capping layer 13.
[0043] The interlayer insulating layer 14 is used to insulate the
magnetic tunnel junctions 12 from each other and to insulate the
layers from one another. The interlayer insulating layer 14 is
formed of an oxide-based material layer, e.g., at least one
selected from the group consisting of a boro silicate glass (BSG)
layer, a boro phopho silicate glass (BPSG) layer, a phospho
silicate glass (PSG) layer, a tetra ethyl ortho silicate (TEOS)
layer, a high density plasma (HDP) oxide layer and a spin on glass
(SOG) layer.
[0044] Subsequently, a spin transfer random access memory is
fabricated through an interconnection process.
[0045] As described above, in the spin transfer random access
memory in accordance with the exemplary embodiment of the present
invention, the CDs of the magnetic tunnel junctions 12 are defined
not by performing an etching process but by performing an impurity
doping process. Here, if the CDs of the magnetic tunnel junctions
12 are defined by performing the etching process, the CDs of the
magnetic tunnel junctions 12 may be different from each other by a
variable of the etch process, e.g., a distribution of etch plasma.
However, if the CDs of the magnetic tunnel junctions 12 are defined
by performing the impurity doping process, e.g., the ion
implantation process, the CDs of magnetic tunnel junctions 12 are
the same. Subsequently, although the magnetic tunnel junctions 12
are patterned through the etching process, the CDs of the magnetic
tunnel junctions 12 are not substantially changed.
[0046] After the magnetic tunnel junctions 12 are patterned, the
electric short circuit between the first and second magnetic layers
2 and 4 is prevented by performing the formation of the capping
layer 13 and the oxidation process. In the process of patterning
the magnetic tunnel junctions 12, the metallic polymer may act as a
bridge for electrically connecting the first and second magnetic
layers 2 and 4 to each other. However, in the present invention,
the metallic polymer is oxidized by forming the capping layer 13
and subsequently performing the oxidation process. Thus, the
electrical short circuit between the first and second magnetic
layers 2 and 4 may be prevented.
[0047] According to the present invention, CDs of magnetic tunnel
junctions are controlled not through an etching process but through
an impurity doping process, thereby improving the CD uniformity of
the magnetic tunnel junctions. Since a magnetic layer used in the
magnetic tunnel junction is a thin film that is hard to etch, it is
difficult to control the CD of the magnetic tunnel junction through
the etching process. Thus, in the present invention, the CD of the
magnetic tunnel junction is controlled through the impurity doping
process.
[0048] If an impurity is doped into the magnetic layer, the
magnetic layer loses magnetism, and accordingly, it is easy to etch
the magnetic layer. Thus, when the magnetic tunnel junction is
patterned, pattern collapse or pattern distortion of the magnetic
tunnel junction is not generated by an etching defect.
[0049] Since a magnetic loss area unrelated to magnetization
characteristics of the magnetic tunnel junction surrounds, together
with a capping layer, a circumference of a magnetic area for
maintaining magnetism, damage of the magnetic tunnel junction is
protected from external factors (e.g., etch plasma and wet
cleansing solution).
[0050] Thus, the magnetization characteristics of the magnetic
tunnel junctions can be unified, and accordingly, the operation
stability and reliability of the spin transfer random access memory
may be obtained.
[0051] While the present invention has been described with respect
to the specific embodiments, it will be apparent to those skilled
in the art that various changes and modifications may be made
without departing from the spirit and scope of the invention as
defined in the following claims.
* * * * *