U.S. patent application number 13/430405 was filed with the patent office on 2012-07-19 for scalable unified memory architecture.
This patent application is currently assigned to Rambus Inc.. Invention is credited to Richard E. Perego.
Application Number | 20120182304 13/430405 |
Document ID | / |
Family ID | 25329319 |
Filed Date | 2012-07-19 |
United States Patent
Application |
20120182304 |
Kind Code |
A1 |
Perego; Richard E. |
July 19, 2012 |
Scalable Unified Memory Architecture
Abstract
A memory architecture includes a memory controller coupled to
multiple modules. Each module includes a computing engine coupled
to a shared memory. Each computing engine is capable of receiving
instructions from the memory controller and processing the received
instructions. The shared memory is configured to store main memory
data and graphical data. Certain computing engines are capable of
processing graphical data. The memory controller may include a
graphics controller that provides instructions to the computing
engine. An interconnect on each module allows multiple modules to
be coupled to the memory controller.
Inventors: |
Perego; Richard E.;
(Thorton, CA) |
Assignee: |
Rambus Inc.
Sunnyvale
CA
|
Family ID: |
25329319 |
Appl. No.: |
13/430405 |
Filed: |
March 26, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12911624 |
Oct 25, 2010 |
8194087 |
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13430405 |
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11058051 |
Feb 15, 2005 |
7821519 |
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12911624 |
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09858836 |
May 15, 2001 |
6864896 |
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11058051 |
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Current U.S.
Class: |
345/542 |
Current CPC
Class: |
G09G 5/393 20130101;
G09G 2352/00 20130101; G09G 2360/125 20130101; G06T 1/60 20130101;
G09G 5/363 20130101 |
Class at
Publication: |
345/542 |
International
Class: |
G06F 15/167 20060101
G06F015/167 |
Claims
1. A system comprising: a processor subsystem; at least one main
memory interconnect coupled to the processor subsystem; and a
plurality of memory modules coupled to the main memory
interconnect, at least one memory module in the plurality storing
execution instructions for the processor subsystem, and at least
one memory module in the plurality further comprising a computing
engine to perform processing tasks, using memory located on that
memory module.
2. The system of claim 1, wherein the processor subsystem includes
a central processing unit to execute first instructions that
reference first data; a memory controller coupled to the central
processing unit to communicate the first instructions and the first
data; and a graphics controller coupled to the central processing
unit to process graphical data.
3. The system of claim 2, wherein a first memory module in the
plurality includes a first integrated-circuit computing engine
coupled to the subsystem to receive the first data; and first
integrated-circuit memory coupled to the integrated-circuit
computing engine to store the first data; and wherein the first
integrated-circuit computing engine writes the first data to the
first integrated-circuit memory and reads the first data from the
first integrated-circuit memory.
4. The system of claim 3, wherein a second memory module in the
plurality includes a second integrated-circuit computing engine
coupled to the subsystem to execute second instructions conveyed
from at least one of the central processing unit, the memory
controller, and the graphics controller, the second
integrated-circuit computing engine to process second data
responsive to the second instructions; and second
integrated-circuit memory coupled to the second integrated-circuit
computing engine to store the second data.
5. The system of claim 4, further wherein the main memory
interconnect conveys the first data to the first memory module and
the second instructions to the second memory module.
6. The system of claim 5, wherein the first and second memory
modules are interconnected by the main memory interconnect.
7. The system of claim 4, wherein the graphics controller
distributes the second instructions to the second module.
8. The system of claim 4, wherein the second instructions include
graphics instructions.
9. The system of claim 4, wherein the second instructions include
at least one of floating-point instructions, digital signal
processing instructions, data compression instructions, and data
decompression instructions.
10. The system of claim 2, wherein the central processing unit, the
memory controller, and the graphics controller are instantiated on
a plurality of integrated circuits.
11. The system of claim 2, wherein at least two of the central
processing unit, the memory controller, and the graphics controller
are instantiated on one integrated circuit.
12. The system of claim 1, wherein the at least one main memory
interconnect includes point-to-point interconnects extending
between the subsystem and respective ones of the memory
modules.
13. The system of claim 1, wherein the processor subsystem divides
image processing tasks into different portions and conveys the
portions to respective ones of the memory modules.
14. The system of claim 13, wherein the processor subsystem
references each of the portions to a respective display area.
15. A memory module for storing main-memory instructions executed
by a central processing unit and referencing first data, the memory
module comprising: first integrated-circuit memory to store the
main-memory instructions and the first data; second
integrated-circuit memory to store second instructions and second
data; and an integrated-circuit computing engine coupled to the
first and second integrated-circuit memories, the
integrated-circuit computing engine to convey the instructions and
first data between the central processing unit and the first
integrated-circuit memory and to execute the second instructions
with reference to the second data.
16. The memory module of claim 15, wherein the first
integrated-circuit memory consists of one or more first memory
integrated circuits and the second integrated-circuit memory
consists of one or more second memory integrated circuits separate
from the first memory integrated circuits.
17. The memory module of claim 15, wherein the integrated-circuit
computing engine uses the second instructions and second data to
process graphical images.
18. The memory module of claim 15, wherein the integrated-circuit
computing engine uses the second instructions and second data to
process floating-point instructions.
19. The memory module of claim 15, wherein the integrated-circuit
computing engine performs at least one of digital signal
processing, data compression, and data decompression on the second
data responsive to the second instructions.
20. The memory module of claim 19, wherein the integrated-circuit
computing engine further performs image processing responsive to
the second instructions.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of co-pending application
Ser. No. 12/911,624, filed Oct. 25, 2010, which is a continuation
of U.S. Pat No. 7,821,519, filed Feb. 15, 2005, which is a
continuation of U.S. Pat. No. 6,864,896, filed May 15, 2001. Each
of the above-referenced documents is entitled "Scalable Unified
Memory Architecture" and is incorporated herein by reference.
FIELD
[0002] The present invention relates to memory systems and, in
particular, to scalable unified memory architecture systems that
support parallel processing of data.
BACKGROUND
[0003] Various systems are available for storing data in memory
devices and retrieving data from those memory devices. FIG. 1
illustrates a computer architecture 100 in which a discrete
graphics controller supports a local graphics memory. Computer
architecture 100 includes a central processing unit (CPU) 102
coupled to a memory controller 104. Memory controller 104 is
coupled to a main memory 108, an I/O controller 106, and a graphics
controller 110. The main memory is used to store program
instructions which are executed by the CPU and data which are
referenced during the execution of these programs. The graphics
controller 110 is coupled to a discrete graphics memory 112.
Graphics controller 110 receives video data through a video input
114 and transmits video data to other devices through a display
interface 116.
[0004] The architecture of FIG. 1 includes two separate memories
(main memory 108 and graphics memory 112), each controlled by a
different controller (memory controller 104 and graphics controller
110, respectively). Typically, graphics memory 112 includes faster
and more expensive memory devices, while main memory 108 has a
larger storage capacity but uses slower, less expensive memory
devices.
[0005] Improvements in integrated circuit design and manufacturing
technologies allow higher levels of integration, thereby allowing
an increasing number of subsystems to be integrated into a single
device. This increased integration reduces the total number of
components in a system, such as a computer system. As subsystems
with high memory performance requirements (such as graphics
subsystems) are combined with the traditional main memory
controller, the resulting architecture may provide a single
high-performance main memory interface.
[0006] Another type of computer memory architecture is referred to
as a unified memory architecture (UMA). In a UMA system, the
graphics memory is statically or dynamically partitioned off from
the main memory pool, thereby saving the cost associated with
dedicated graphics memory. UMA systems often employ less total
memory capacity than systems using discrete graphics memory to
achieve similar levels of graphics performance. UMA systems
typically realize additional cost savings due to the higher levels
of integration between the memory controller and the graphics
controller.
[0007] FIG. 2 illustrates another prior art memory system 200 that
uses a unified memory architecture. A CPU/Memory Controller
subsystem 202 includes a CPU 208 and a memory controller and a
graphics controller combined into a single device 210. The
subsystem 202 represents an increased level of integration as
compared to the architecture of FIG. 1. Subsystem 202 is coupled to
a shared memory 204, which is used as both the main memory and the
graphics memory. Subsystem 202 is also coupled to an I/O controller
206, a video input 212, and a display interface 214.
[0008] The memory controller/graphics controller 210 controls all
memory access, both for data stored in the main memory portion of
shared memory 204 and for data stored in the graphics memory
portion of the shared memory. The shared memory 204 may be
partitioned statically or dynamically. A static partition allocates
a fixed portion of the shared memory 204 as "main memory" and the
remaining portion is the "graphics memory." A dynamic partition
allows the allocation of shared memory 204 between main memory and
graphics memory to change depending on the needs of the system. For
example, if the graphics memory portion is full, and the graphics
controller needs additional memory, the graphics memory portion may
be expanded if a portion of the shared memory 204 is not currently
in use or if the main memory allocation can be reduced.
[0009] Regardless of the system architecture, graphics rendering
performance is often constrained by the memory bandwidth available
to the graphics subsystem. In the system of FIG. 1, graphics
controller 110 interfaces to a dedicated graphics memory 112. Cost
constraints for the graphics subsystem generally dictate that a
limited capacity of dedicated graphics memory 112 must be used.
This limited amount of memory, in turn, dictates a maximum number
of memory devices that can be supported. In such a memory system,
the maximum graphics memory bandwidth is the product of the number
of memory devices and the bandwidth of each memory device.
Device-level cost constraints and technology limitations typically
set the maximum memory device bandwidth. Consequently, graphics
memory bandwidth, and therefore graphics performance, is generally
bound by the small number of devices that can reasonably be
supported in this type of system configuration.
[0010] Unified memory architectures such as that shown in FIG. 2,
help alleviate cost constraints as described above, and generally
provide lower cost relative to systems such as that shown in FIG.
1. However, memory bandwidth for the system of FIG. 2 is generally
bound by cost constraints on the memory controller/graphics
controller 210. Peak memory bandwidth for this system is the
product of the number of conductors on the memory data interface
and the communication bandwidth per conductor. The communication
bandwidth per conductor is often limited by the choice of memory
technology and the topology of the main memory interconnect. The
number of conductors that can be used is generally bound by cost
constraints on the memory controller/graphics controller package or
system board design. However, the system of FIG. 2 allows
theoretical aggregate bandwidth to and from the memory devices to
scale linearly with system memory capacity, which is typically much
larger than the capacity of dedicated graphics memory. The problem
is that this aggregate bandwidth cannot be exploited due to the
limiting factors described above relating to bandwidth limitations
at the memory controller/graphics controller.
[0011] A system architecture which could offer the cost savings
advantages of a unified memory architecture, while providing
scalability options to higher levels of aggregate memory bandwidth
(and therefore graphics performance) relative to systems using
dedicated graphics memory would be advantageous.
SUMMARY
[0012] The systems and methods described herein achieve these goals
by supporting the capability of locating certain processing
functions on the memory modules, while providing the capability of
partitioning tasks among multiple parallel functional units or
modules.
[0013] In one embodiment, an apparatus includes a memory controller
coupled to one or more modules. Each installed module includes a
computing engine coupled to a shared memory. The computing engine
is configured to receive information from the memory controller.
The shared memory includes storage for instructions or data, which
includes a portion of the main memory for a central processing unit
(CPU).
[0014] In another embodiment, the computing engine is a graphics
rendering engine.
[0015] In a particular implementation of the system, the shared
memory is configured to store main memory data and graphical
data.
[0016] Another embodiment provides that the computing engine is
coupled between the memory controller and the shared memory.
[0017] In a particular embodiment, the memory controller includes a
graphics controller.
[0018] In a described implementation, one or more modules are
coupled to a memory controller. Each installed module includes a
computing engine and a shared memory coupled to the computing
engine.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] FIG. 1 illustrates a prior art computer architecture in
which a discrete graphics controller supports a local graphics
memory.
[0020] FIG. 2 illustrates another prior art memory system that uses
a unified memory architecture.
[0021] FIG. 3 illustrates an embodiment of a scalable unified
memory architecture that supports parallel processing of graphical
data.
[0022] FIG. 4 is a flow diagram illustrating a procedure for
partitioning a processing task into multiple portions and
distributing the multiple portions to different rendering
engines.
[0023] FIG. 5 illustrates a graphical rendering surface divided
into sixteen different sections.
[0024] FIGS. 6 and 7 illustrate different memory modules containing
a rendering engine and multiple memory devices.
[0025] FIG. 8 illustrates a memory module containing two different
rendering engines and multiple memory devices associated with each
rendering engine.
DETAILED DESCRIPTION
[0026] The architecture described herein provides one or more
discretememory modules coupled to a common memory controller. Each
memory module includes a computing engine and a shared memory.
Thus, the data processing tasks can be distributed among the
various computing engines and the memory controller to allow
parallel processing of different portions of the various processing
tasks.
[0027] Various examples are provided herein for purposes of
explanation. These examples include the processing of graphical
data by one or more rendering engines on one or more memory
modules. It will be understood that the systems described herein
are not limited to processing graphical data. Instead, the systems
described herein may be applied to process any type of data from
any data source.
[0028] FIG. 3 illustrates an embodiment of a scalable unified
memory architecture 300 that supports parallel processing of
graphical data and/or graphical instructions. A CPU/memory
controller subsystem 302 includes a CPU 308 coupled to a memory
controller/graphics controller 310. One or more memory modules 304
are coupled to memory controller/graphics controller 310 in
subsystem 302. Each memory module 304 includes a rendering engine
312 and a shared memory 314 (i.e., main memory and graphics
memory). The main memory typically contains instructions and/or
data used by the CPU. The graphics memory typically contains
instructions and/or data used to process, render, or otherwise
handle graphical images or graphical information.
[0029] Rendering engine 312 may also be referred to as a "compute
engine" or a "computing engine." The shared memory 314 typically
includes multiple memory devices coupled together to form a block
of storage space. Each rendering engine 312 is capable of
performing various memory access and/or data processing functions.
For the embodiment shown in FIG. 3, memory controller/graphics
controller 310 is also coupled to an I/O controller 306 which
controls the flow of data into and out of the system. An optional
video input port 316 provides data to memory controller/graphics
controller 310 and a display interface 318 provides data output to
one or more devices (such as display devices or storage devices).
For systems which support video input or capture capability, a
video input port on the memory controller/graphics controller 310
is one way to handle the delivery of video source data. Another
means of delivery of video input data to the system would include
delivering the data from a peripheral module through the I/O
controller 306 to controller 310.
[0030] In the example of FIG. 3, CPU/memory controller subsystem
302 is coupled to four distinct memory modules 304. Each memory
module includes a rendering engine and a shared memory. Each
rendering engine 312 is capable of performing various data
processing functions. Thus, the four rendering engines are capable
of performing four different processing functions simultaneously
(i.e., parallel processing). Further, each rendering engine 312 is
capable of communicating with other rendering engines on other
memory modules 304.
[0031] The memory controller/graphics controller 310 distributes
particular processing tasks (such as graphical processing tasks) to
the different rendering engines, and performs certain processing
tasks itself. These tasks may include data to be processed and/or
instructions to be processed. Although four memory modules 304 are
shown in FIG. 3, alternate system may contain any number of memory
modules coupled to a common memory controller/graphics controller
310. This ability to add and remove memory modules 304 provides an
upgradeable and scalable memory and computing architecture.
[0032] The architecture of FIG. 3 allows the memory
controller/graphics controller 310 to issue high level primitive
commands to the various rendering engines 312, thereby reducing the
volume or bandwidth of data that must be communicated between the
controller 310 and the memory modules 304. Thus, the partitioning
of memory among multiple memory modules 304 improves graphical data
throughput relative to systems in which a single graphics
controller performs all processing tasks and reduces bandwidth
contention with the CPU. This bandwidth reduction occurs because
the primitive commands typically contain significantly less data
than the amount of data referenced when rendering the primitive.
Additionally, the system partitioning described allows aggregate
bandwidth between the rendering engines and the memory devices to
be much higher than the bandwidth between the controller and memory
modules. Thus, effective system bandwidth is increased for
processing graphics tasks.
[0033] FIG. 4 is a flow diagram illustrating a procedure for
partitioning a processing task into multiple portions and
distributing the multiple portions to different rendering engines.
Initially, the memory controller/graphics controller receives a
processing task (block 402). The memory controller/graphics
controller partitions the processing task into multiple portions
(block 404) and distributes each portion of the processing task to
a rendering engine on a memory module (block 406).
[0034] When all rendering engines have finished processing their
portion of the processing task, the memory controller/graphics
controller reassembles the finished portions of the task (block
410). In certain situations, the memory controller/graphics
controller may perform certain portions of the processing task
itself rather than distributing them to a rendering engine. In
other situations, the processing task may be partitioned such that
one or more rendering engines perform multiple portions of the
processing task. In another embodiment, the processing task may be
partitioned such that one or more rendering engines are idle (i.e.,
they do not perform any portion of the processing task).
[0035] For typical graphics applications, primitive data (e.g.,
triangles or polygons) are sorted by the graphics controller or CPU
according to the spatial region of the rendering surface (e.g., the
x and y coordinates) covered by that primitive. The rendering
surface is generally divided into multiple rectangular regions of
pixels (or picture elements), referred to as "tiles" or "chunks."
Since the tiles generally do not overlap spatially, the rendering
of the tiles can be partitioned among multiple rendering
engines.
[0036] An example of the procedure described with respect to FIG. 4
will be described with reference to FIG. 5, which illustrates a
graphical rendering surface divided into sixteen different sections
or "tiles" (four rows and four columns). The graphical rendering
surface may be stored in, for example, an image buffer or displayed
on a display device. If a particular image processing task is to be
performed on the graphical rendering surface shown in FIG. 5, the
memory controller/graphics controller may divide the processing
tasks into different portions based on the set of files intersected
by the primitive elements of the task. For example, four of the
sixteen tiles of the surface are assigned to a first rendering
engine (labeled "REO") on a first memory module. Another four files
of the surface are assigned to a different rendering engine
(labeled "RE1), and so on. This arrangement allows the four
different rendering engines (REO, RE1, RE2, and RE3) to process
different regions of the surface simultaneously. This parallel
processing significantly reduces the processing burden on the
memory controller/graphics controller. In this example, a
significant portion of the set of graphics rendering tasks is
performed by the four rendering engines, which allows the memory
controller/graphics controller to perform other tasks while these
rendering tasks are being processed.
[0037] In an alternate embodiment, each of the rendering engines is
assigned to process a particular set of rows or columns of the
rendering surface, where these rows or columns represent a band of
any size of pixels (at least one pixel wide). As shown in FIG. 5,
the rendering surface is divided into two or more horizontal pixel
bands (also referred to as pixel rows) and divided into two or more
vertical pixel bands (also referred, to as pixel columns). The
specific example of FIG. 5 shows a rendering surface divided into
four horizontal pixel bands and four vertical pixel bands. However,
in alternate embodiments the rendering surface may be divided into
any number of horizontal pixel bands and any number of vertical
pixel bands. For example, the rendering surface may be divided into
four sections or "quadrants" (i.e., two columns and two rows), in
which each of the rendering engines is assigned to a particular
quadrant of the rendering surface.
[0038] The example discussed above with respect to FIG. 5 is
related to graphics or image processing. However, the system
described herein may be applied to any type of processing in which
one or more processing functions can be divided into multiple tasks
that can be performed in parallel by multiple computing engines.
Other examples include floating point numerical processing, digital
signal processing, block transfers of data stored in memory,
compression of data, decompression of data, and cache control. For
example, a task such as decompression of a compressed MPEG (Moving
Picture Experts Group) video stream can begin by partitioning the
video stream into multiple regions or "blocks." Each block is
decompressed individually and the results of all block
decompressions are combined to form a complete video image. In this
example, each block is associated with a particular rendering
engine.
[0039] FIGS. 6 and 7 illustrate different memory modules containing
a rendering engine and multiple memory devices. The multiple memory
devices represent the shared memory 314 shown in FIG. 3. Although
the memory modules shown in FIGS. 6 and 7 each contain eight memory
devices, alternate memory modules may contain any number of memory
devices coupled to a rendering engine.
[0040] Referring to FIG. 6, a memory module 600 includes eight
memory devices 604 coupled to a rendering engine 602. The rendering
engine 602 is also coupled to a module interconnect 606 which
couples the memory module 600 to an associated interconnect on
another module, motherboard, device, or other system. A memory
interconnect 608 couples the memory devices 604 to the rendering
engine 602. The memory interconnect 608 may allow parallel access
to multiple memory devices 604, and may use either a multi-drop
topology, point-to-point topology, or any combination of these
topologies.
[0041] Referring to FIG. 7, a memory module 700 includes multiple
memory devices 704 coupled to a rendering engine 702. The rendering
engine 702 is also coupled to a pair of module interconnects 706
and 708, which couple the memory module 700 to another module,
motherboard, device, or system. A memory interconnect 710 couples
the memory devices 704 to the rendering engine 702 and may allow
parallel access to multiple memory devices 704. In an alternate
embodiment, module interconnects 706 and 708 are connected to form
a contiguous interconnect through the module 700 connecting the
rendering engine 702 to other devices in the system.
[0042] As discussed above, each memory module has its own memory
interconnect for communicating data between the memory module's
rendering engine and the various memory devices. The memory
interconnect on each memory module is relatively short and provides
significant bandwidth for communicating with the multiple memory
devices on the module. Further, the simultaneous processing and
communication of data on each memory module reduces the volume or
bandwidth of data communicated between the memory modules and the
memory controller/graphics controller. The memory interconnects
discussed herein may be a bus, a series of point-to-point links, or
any combination of these types of interconnects.
[0043] FIG. 8 illustrates a memory module 800 containing two
different rendering engines 802 and 810, and multiple memory
devices 804 and 812 associated with each rendering engine. In this
embodiment, two different memory interconnects 806 and 814 couple
the memory devices to the rendering engines. The two rendering
engines 802 and 810 are coupled to a common module interconnect
808. Thus, rendering engines 802 and 810 can process data and/or
tasks simultaneously. In another embodiment, each rendering engine
802 and 810 is coupled to an independent module interconnect (not
shown).
[0044] A particular embodiment of the memory modules shown in FIGS.
6, 7, and 8 uses multiple "Direct Rambus Channels" developed by
Rambus Inc. of Mountain View, Calif. The Direct Rambus Channels
connect the multiple memory devices to the associated rendering
engine. In this embodiment, the memory devices are Rambus DRAMs (or
RDRAMs.RTM.). However, other memory types and topologies may also
be used within the scope of this invention. For example, memory
types such as Synchronous DRAMs (SDRAMs), Double-Data-Rate (DDR)
SDRAMs, Fast-Cycle (FC) SDRAMs, or derivatives of these memory
types may also be used. These devices may be arranged in a single
rank of devices or multiple ranks, where a rank is defined as a
group of devices which respond to a particular class of commands
including reads and writes.
[0045] In a particular embodiment of the architecture shown in FIG.
3, processing functions that are associated with typical graphics
controller interface functions such as video input processing and
display output processing are handled by the memory
controller/graphics controller 310. Processing functions that are
associated with high-bandwidth rendering or image buffer creation
are handled by the rendering engines 312 on the memory modules.
[0046] Although particular examples are discussed herein as having
one or two rendering engines, alternate implementations may include
any number of rendering engines or computing engines on a
particular module. Further, a particular module may contain any
number of memory devices coupled to any number of rendering engines
and/or computing engines.
[0047] Thus, a system has been described that provides multiple
discrete memory modules coupled to a common memory controller. Each
memory module includes a computing engine and a shared memory. A
data processing task from the memory controller can be partitioned
among the different computing engines to allow parallel processing
of the various portions of the processing task.
[0048] Although the description above uses language that is
specific to structural features and/or methodological acts, it is
to be understood that the invention defined in the appended claims
is not limited to the specific features or acts described. Rather,
the specific features and acts are disclosed as exemplary forms of
implementing the invention.
* * * * *