U.S. patent application number 13/423591 was filed with the patent office on 2012-07-12 for semiconductor light emitting device and method for manufacturing same.
This patent application is currently assigned to KABUSHIKI KAISHA TOSHIBA. Invention is credited to Akihiro KOJIMA, Yoshiaki Sugizaki.
Application Number | 20120178192 13/423591 |
Document ID | / |
Family ID | 42736742 |
Filed Date | 2012-07-12 |
United States Patent
Application |
20120178192 |
Kind Code |
A1 |
KOJIMA; Akihiro ; et
al. |
July 12, 2012 |
SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING
SAME
Abstract
A semiconductor light emitting device, includes: a substrate
including a first major surface and a second major surface, the
first major surface including a recess and a protrusion, the second
major surface being formed on a side opposite to the first major
surface; a first electrode provided on the first major surface; a
semiconductor light emitting element provided on the first
electrode and electrically connected to the first electrode; a
second electrode provided on the second major surface; and a
through-electrode provided to pass through the substrate at the
recess and electrically connect the first electrode and the second
electrode.
Inventors: |
KOJIMA; Akihiro; (Kanagawa,
JP) ; Sugizaki; Yoshiaki; (Kanagawa, JP) |
Assignee: |
KABUSHIKI KAISHA TOSHIBA
Tokyo
JP
|
Family ID: |
42736742 |
Appl. No.: |
13/423591 |
Filed: |
March 19, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12575778 |
Oct 8, 2009 |
8174027 |
|
|
13423591 |
|
|
|
|
Current U.S.
Class: |
438/27 ;
257/E33.056; 257/E33.061; 438/26 |
Current CPC
Class: |
H01L 33/505 20130101;
H01L 2924/0002 20130101; H01L 33/58 20130101; H01L 33/62 20130101;
H01L 2924/00 20130101; H01L 2924/0002 20130101; H01L 33/44
20130101; H01L 33/486 20130101 |
Class at
Publication: |
438/27 ; 438/26;
257/E33.056; 257/E33.061 |
International
Class: |
H01L 33/50 20100101
H01L033/50; H01L 33/48 20100101 H01L033/48 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 18, 2009 |
JP |
2009-065646 |
Claims
1. A method for manufacturing a semiconductor light emitting
device, comprising: forming a first electrode on a first major
surface of a substrate including the first major surface and a
second major surface, the first major surface including a recess
and a protrusion, the second major surface being formed on a side
opposite to the first major surface; making a connection hole in
the substrate at the recess to communicate between the first major
surface and the second major surface; forming a second electrode in
the connection hole and on the second major surface; electrically
connecting the first electrode and the second electrode; and
mounting a semiconductor light emitting element on the first
electrode.
2. The method according to claim 1, further comprising grinding the
second major surface of the substrate to make the substrate thin
prior to making the connection hole.
3. The method according to claim 1, wherein the semiconductor light
emitting element is formed on a light emitting element substrate
and the semiconductor light emitting element is mounted on the
first electrode with the light emitting element substrate attached
on the light emitting element.
4. The method according to claim 3, wherein the light emitting
element substrate is removed after mounting the semiconductor light
emitting element.
5. A method for manufacturing a semiconductor light emitting
device, comprising: forming a first electrode on a first major
surface of a substrate; making a connection hole in the substrate
to communicate from the first major surface to a second major
surface, the second major surface being on a side opposite to the
first major surface; forming a second electrode in the connection
hole and on the second major surface; electrically connecting the
first electrode and the second electrode; mounting a semiconductor
light emitting element on the first electrode; forming a
sacrificial layer to cover the semiconductor light emitting
element; forming a reinforcing film on the sacrificial layer;
removing the sacrificial layer via an opening made in the
reinforcing film to make a gap between the semiconductor light
emitting element and the reinforcing film; forming a fluorescent
material on the reinforcing film; and performing heat treatment to
reform the fluorescent material.
6. The method according to claim 5, wherein the heat treatment
includes laser irradiation of the fluorescent material from a top
surface side of the fluorescent material.
7. The method according to claim 5, further comprising grinding the
second major surface of the substrate to make the substrate thin
prior to making the connection hole.
8. The method according to claim 5, wherein the semiconductor light
emitting element is formed on a light emitting element substrate
and the semiconductor light emitting element is mounted on the
first electrode with the light emitting element substrate attached
on the light emitting element.
9. The method according to claim 8, wherein the light emitting
element substrate is removed after mounting the semiconductor light
emitting element.
10. The method according to claim 5, further comprising forming a
protrusion and a recess on the first major surface of the substrate
prior to forming the first electrode, the first electrode being
formed on the protrusion.
11. The method according to claim 10, wherein the connection hole
is formed from the second major surface of the substrate to reach
the recess of the first major surface.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. application Ser.
No. 12/575,778, filed Oct. 8, 2009, and is based upon and claims
the benefit of priority from the prior Japanese Patent Application
No. 2009-065646, filed on Mar. 18, 2009, the entire contents of
each of which are incorporated herein by reference.
BACKGROUND
[0002] Although semiconductor light emitting devices for
illumination require monochromatic light emission in some cases,
basically, white light near sunlight is needed. White semiconductor
light sources include primary color (RGB) device arrays,
pseudo-white light sources using a color mixture from a blue light
emitting device and yellow light produced by self-excited light
emission at substrate defects of the blue light emitting device,
primary color fluorescent material excitation light sources using
ultraviolet light emitting devices, and the like (for example, JP-A
2007-243054 (Kokai), JP-A 2008-112867 (Kokai), and JP-A 2006-339060
(Kokai)).
[0003] For such semiconductor light emitting devices, technology is
known for removing a light emitting device substrate used during
crystal growth such as JP-A 2004-284831 (Kokai), Pioneer R&D,
2000, Vol. 12, No. 3, p. 77, and the like. Known technology for
sealing functioning devices in the wafer form includes Electronic
Components & Technology Conference, 2008, p. 824 and the
like.
[0004] In the case where semiconductor light emitting devices are
utilized as illumination to replace incandescent lightbulbs and
fluorescent lamps, a relatively high light output is necessary.
Therefore, insufficient heat dissipation of the semiconductor light
emitting device easily causes the undesirable deterioration of the
sealing resin protecting the semiconductor light emitting
device.
[0005] The life of a semiconductor light emitting device itself is
much longer than that of an incandescent lightbulb. The main causes
of the semiconductor light emitting device becoming unusable may
include oxidization, deterioration, and overheating of the metal of
the electrode portions, shorts of gold wire in the interior due to
shocks, etc. Product life refers to the point when the ability to
transmit light drops due to deterioration of the sealing resin and
the amount of light emission falls below a constant level. In
particular, the resin in components using fluorescent material
excitation by a light emitting device emitting blue to ultraviolet
light easily deteriorates due to the heat from the exciting device
and the ultraviolet rays; and it is difficult to realize high
output and long life.
[0006] In package structures in which a light emitting device chip
is mounted on a substrate of silicon and the like, thinner
substrates are desirable due to the need for good heat dissipation,
flexibility, etc. However, limitations are encountered when making
the entire surface of the substrate thinner from the aspects of
ease of handling, reliability, and the like.
SUMMARY
[0007] According to an aspect of the invention, there is provided a
semiconductor light emitting device, including: a substrate
including a first major surface and a second major surface, the
first major surface including a recess and a protrusion, the second
major surface being formed on a side opposite to the first major
surface; a first electrode provided on the first major surface; a
semiconductor light emitting element provided on the first
electrode and electrically connected to the first electrode; a
second electrode provided on the second major surface; and a
through-electrode provided to pass through the substrate at the
recess and electrically connect the first electrode and the second
electrode.
[0008] According to another aspect of the invention, there is
provided a method for manufacturing a semiconductor light emitting
device, including: forming a first electrode on a first major
surface of a substrate including the first major surface and a
second major surface, the first major surface including a recess
and a protrusion, the second major surface being formed on a side
opposite to the first major surface; making a connection hole in
the substrate at the recess to communicate between the first major
surface and the second major surface; forming a second electrode in
the connection hole and on the second major surface; electrically
connecting the first electrode and the second electrode; and
mounting a semiconductor light emitting element on the first
electrode.
[0009] According to still another aspect of the invention, there is
provided a method for manufacturing a semiconductor light emitting
device, including: forming a first electrode on a first major
surface of a substrate; making a connection hole in the substrate
to communicate from the first major surface to a second major
surface, the second major surface being on a side opposite to the
first major surface; forming a second electrode in the connection
hole and on the second major surface; electrically connecting the
first electrode and the second electrode; mounting a semiconductor
light emitting element on the first electrode; forming a
sacrificial layer to cover the semiconductor light emitting
element; forming a reinforcing film on the sacrificial layer;
removing the sacrificial layer via an opening made in the
reinforcing film to make a gap between the semiconductor light
emitting element and the reinforcing film; forming a fluorescent
material on the reinforcing film; and performing heat treatment to
reform the fluorescent material.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 is a schematic cross-sectional view of a
semiconductor light emitting device according to an embodiment;
[0011] FIG. 2 is a schematic view showing a planar layout of the
main components of the semiconductor light emitting device;
[0012] FIGS. 3A to 6C are schematic views showing a method for
manufacturing the semiconductor light emitting device according to
this embodiment.
DETAILED DESCRIPTION OF THE INVENTION
[0013] Embodiments of the invention will now be described with
reference to the drawings. Although several specific configurations
are described as examples herein, the invention is not limited to
the embodiments described hereinbelow; and the invention is
similarly practicable using configurations having similar
functions.
[0014] FIG. 1 is a schematic cross-sectional view of a
semiconductor light emitting device according to an embodiment.
FIG. 2 illustrates a planar layout example of the main components
illustrated in FIG. 1. FIG. 1 corresponds to a cross section along
line A-A' of FIG. 2.
[0015] The semiconductor light emitting device according to this
embodiment has a structure in which a semiconductor light emitting
element 20 having a chip configuration is mounted on a substrate
3.
[0016] The substrate 3 is thermally conductive and is, for example,
a silicon substrate. Sapphire, SiC, and the like also may be used
as the substrate 3. A silicon substrate is comparatively
inexpensive and is very easy to process.
[0017] The substrate 3 has a first major surface and a second major
surface formed on the side opposite to the first major surface. As
described below, the first major surface is selectively etched
using a mask (e.g., a silicon oxide film) 8 to form recesses and
protrusions.
[0018] The semiconductor light emitting element 20 includes an
n-type semiconductor 1 and a p-type semiconductor 2. The pn
junction between the n-type semiconductor 1 and the p-type
semiconductor 2 forms a light emitting portion. One example
includes using a semiconductor having a relatively large band gap
(e.g., GaN) between the n-type semiconductor 1 and the p-type
semiconductor 2 in a structure in which a semiconductor having a
relatively small band gap (e.g., InGaN) is interposed between the
n-type semiconductor 1 and the p-type semiconductor 2 as an
activation layer. Injected carriers (minority carriers) are
effectively confined to the activation layer, and a high luminous
efficacy is obtained by the effective light emission when the
minority carriers recombine. The semiconductor light emitting
element 20 is not limited to a light emitting diode and may include
an LD (Laser Diode).
[0019] A dielectric film 9 covers the first major surface of the
substrate 3 in which recesses and protrusions are formed. The
semiconductor light emitting element 20 and the substrate 3 are
thereby electrically insulated. An n-side interconnect electrode 4
and a p-side interconnect electrode 5 are formed on the dielectric
film 9 to form first electrodes. The n-side interconnect electrode
4 and the p-side interconnect electrode 5 are provided separately
and insulatively separated from each other on a protrusion 3a.
[0020] The semiconductor light emitting element 20 is mounted on
the n-side interconnect electrode 4 and the p-side interconnect
electrode 5 via an n-side bonding metal 6 and a p-side bonding
metal 7. In the semiconductor light emitting element 20, the n-type
semiconductor 1 is electrically connected to the n-side
interconnect electrode 4 via the n-side bonding metal 6; and the
p-type semiconductor 2 is electrically connected to the p-side
interconnect electrode 5 via the p-side bonding metal 7. The
semiconductor light emitting element 20 is mounted on the
protrusion 3a of the first major surface of the substrate 3.
[0021] The n-side bonding metal 6 and the p-side bonding metal 7
are made of, for example, a conductive material such as solder,
silver paste, gold bumps, etc., and bond the semiconductor light
emitting element 20 having a chip configuration to the n-side
bonding metal 6 and the p-side bonding metal 7 by thermal fusion,
thermal curing, ultrasonic bonding, and the like.
[0022] A reinforcing film 15 is provided on the n-side interconnect
electrode 4 and the p-side interconnect electrode 5. The
reinforcing film 15 is provided also above the semiconductor light
emitting element 20 in a dome configuration via a gap 30. A
fluorescent material 10 is provided on the reinforcing film 15. The
light extraction surface of the semiconductor light emitting
element 20 opposes the fluorescent material 10 via the gap 30 and
the reinforcing film 15.
[0023] The fluorescent material 10 is excited by light emitted by
the semiconductor light emitting device 20 and emits light having a
different wavelength than the semiconductor light emitting element
20. Examples of the fluorescent material 10 include, for example,
Y.sub.2O.sub.2S:Eu, YVO.sub.4:Eu, and the like for red; ZnS:(Cu,
Al), (Ba, Mg) Al.sub.10O.sub.17:(Eu, Mn), and the like for green;
and (Ba, Mn) Al.sub.10O.sub.17:Eu, (Sr, Ca, Ba,
Mg).sub.10(PO.sub.4).sub.6C.sub.12:Eu, and the like for blue.
[0024] The reinforcing film 15 has the functions of stabilizing and
maintaining the fluorescent material 10 above the gap 30 and
sealing the gap 30. The reinforcing film 15 is dielectric to
prevent shorts to the n-side interconnect electrode 4 and the
p-side interconnect electrode 5. The reinforcing film 15 is
transparent with respect to the light emission wavelength of the
semiconductor light emitting element 20 and has the ability to
transmit the light emitted by the semiconductor light emitting
element 20. A silicon oxide film, for example, may be used as the
reinforcing film 15 to realize such functions.
[0025] A lens 16 is provided on the fluorescent material 10 and has
functions of diffusing and spreading the light emitted by the
semiconductor light emitting element 20 and the fluorescent
material 10. The lens 16 may be formed by, for example, coating a
resin onto the fluorescent material 10 and subsequently imprinting
the resin into a concave configuration using a template.
[0026] Although the light for exciting the fluorescent material 10
in this embodiment is extracted from the top face of mainly the
n-type semiconductor 1, semiconductor materials generally have high
refractive indices, and much reflection occurs at the interface
with air (or a vacuum). For example, in the case of a GaN n-type
semiconductor 1 with a light emission wavelength of 380 nm, about
20% of the light is undesirably reflected when being output from
the n-type semiconductor 1.
[0027] Therefore, it is desirable to increase the efficiency by
forming an anti-reflection coating (hereinbelow referred to as "AR
coating") 40 on the top face (the light extraction surface) of the
semiconductor light emitting element 20 prior to or after mounting
the semiconductor light emitting element 20. In such a case,
providing a nitride film and an oxide film having a refractive
index of 1.6 and a thickness of 59 nm as the AR coating 40 can
reduce the reflection when light is output from the n-type
semiconductor 1 to 0.004% or less. By providing a 65 nm SiO.sub.2
film, reflection suppression to about 0.9% is possible.
Anti-reflection also is possible by providing fine recesses and
protrusions smaller than the light emission wavelength on the light
extraction surface of the n-type semiconductor 1.
[0028] An n-side bottom face bonding electrode 11 and a p-side
bottom face bonding electrode 12 are provided as second electrodes
on the second major surface of the substrate 3. The n-side bottom
face bonding electrode 11 and the p-side bottom face bonding
electrode 12 are insulated from the substrate 3 by a dielectric
film (e.g., made of a resin material such as polyimide) 13 formed
on the second major surface. The n-side bottom face bonding
electrode 11 and the p-side bottom face bonding electrode 12 also
are insulatively separated from each other by the dielectric film
13.
[0029] Through-holes are made in the substrate 3 from the bottom
face of a recess 3b to the second major surface. A
through-electrode 18 is provided in the interior of each of the
through-holes. The through-electrode 18 passes through the
dielectric film 9 formed below the n-side interconnect electrode 4
on the bottom face of the recess 3b to electrically connect the
n-side interconnect electrode 4 and the n-side bottom face bonding
electrode 11. Similarly, the through-electrode 18 passes through
the dielectric film 9 formed below the p-side interconnect
electrode 5 on the bottom face of the recess 3b to electrically
connect the p-side interconnect electrode 5 and the p-side bottom
face bonding electrode 12. The dielectric film 13 is provided also
on the through-hole side walls to insulate the through-electrode 18
from the substrate 3.
[0030] External connection terminals 14 are provided on exposed
portions of the n-side bottom face bonding electrode 11 and exposed
portions of the p-side bottom face bonding electrode 12 on the
second major surface side to connect to an external circuit. The
external connection terminals 14 may include, for example, solder
balls, metal bumps, and the like.
[0031] Planar illumination can be realized by mounting multiple
chips (the semiconductor light emitting elements 20) on the
substrate 3. An illumination source having a curved configuration
can be realized to enable utilization in a wide range of
applications by making the substrate 3 thin to provide flexibility.
For example, utilization is possible as a backlight of a bendable
liquid crystal display.
[0032] However, the substrate 3 is susceptible to reduced strength
in the case where the entire surface of the substrate 3 is made
uniformly thin to provide flexibility. Therefore, in this
embodiment, a thickness reduction is performed while ensuring the
strength by forming recesses and protrusions on the first major
surface side of the substrate 3 while grinding the entire surface
of the second major surface to make uniformly thin as described
below.
[0033] The connection holes and the through-electrodes 18 are
formed in the thin portions below the recesses 3b to provide
draw-outs to the second major surface side from the n-side
interconnect electrode 4 and the p-side interconnect electrode 5
provided on the first major surface side where the semiconductor
light emitting element 20 is mounted. In other words, because the
connection holes and the through-electrodes 18 are formed in the
portions having a relatively small aspect ratio (ratio of depth to
hole diameter), the processes are easier; the fillability of the
through-electrodes 18 is better; unfilled portions of the
through-electrodes 18 are prevented; and the reliability can be
improved.
[0034] From the aspect of ensuring the strength, it is desirable
that the surface area of the upper face of the protrusion 3a is
larger than the bottom face of the recess 3b on the first major
surface side of the substrate 3. The light emitting region of one
substrate 3 can be increased and a higher output can be realized by
mounting the semiconductor light emitting element 20 on the upper
face of the protrusion 3a having the relatively large surface
area.
[0035] Although higher outputs are necessary in the case where the
semiconductor light emitting device is used for illumination,
higher outputs are accompanied by increases of the amounts of light
and heat emitted by the light emitting element. Because this
embodiment has a structure in which the fluorescent material 10
does not directly cover the semiconductor light emitting element 20
and the gap 30 exists between the semiconductor light emitting
element 20 and the fluorescent material 10, the effects on the
resin components of the fluorescent material 10 from the light and
the heat from the semiconductor light emitting element 20 can be
reduced, and the deterioration of the resin components can be
suppressed. Also, the heat emitted by the semiconductor light
emitting element 20 can be dissipated to the second major surface
side via the substrate (e.g., silicon substrate) 3 having thermal
conductivity. This dissipation also reduces the effects of heat on
the fluorescent material 10. Thus, the semiconductor device
according to this embodiment can realize a long life while
providing a higher output.
[0036] In the case where the pressure of the atmosphere in the gap
30 is atmospheric pressure or more and, for example, the light
emitted by the semiconductor light emitting element 20 is
ultra-violet light, the light extraction efficiency to the
fluorescent material 10 on the exterior of the gap 30 is
susceptible to decrease due to reflection, diffusion, etc.
Accordingly, it is desirable to provide a pressure in the gap 30
lower than atmospheric pressure. A lower pressure in the gap 30
also increases thermal insulation effects, and the effects of heat
from the semiconductor light emitting element 20 on the fluorescent
material 10 can be suppressed more effectively.
[0037] By providing the reinforcing film 15 between the gap 30 and
the fluorescent material 10, the deterioration of the fluorescent
material 10 can be suppressed compared to the case where the
fluorescent material 10 directly defines the gap 30.
[0038] A method for manufacturing the semiconductor light emitting
apparatus device to this embodiment will now be described with
reference to FIG. 3A to FIG. 6C.
[0039] First, the mask 8 is selectively formed on the first major
surface of the substrate 3 as illustrated in FIG. 3A. Using the
mask 8 as a mask, anisotropic etching is performed to form the
recess 3b and the protrusion 3a. The mask 8 is formed by, for
example, forming a silicon oxide film with a thickness of about 5
.mu.m on the entire surface of the first major surface of the
silicon substrate 3 by thermal oxidation and then performing
patterning of the silicon oxide film using a resist.
[0040] After forming the mask 8, the recess 3b is made by
anisotropic etching of the portions where the mask 8 is not formed
using, for example, wet etching with KOH. The portions where the
etching does not occur below the mask 8 form the protrusions 3a in
cross-sectionally trapezoidal configurations. The difference in
levels between the protrusion 3a and the recess 3b (the depth of
the recess 3b) is, for example, about 100 .mu.m. The etching
selectivity for KOH of silicon to silicon oxide (SiO.sub.2) is
about 100:1. It may be necessary that the silicon oxide mask 8 has
a thickness of at least 1 .mu.m.
[0041] Then, as illustrated in FIG. 3B, the dielectric film 9 is
formed to cover the first major surface. The n-side interconnect
electrode 4 and the p-side interconnect electrode 5 are then formed
on the dielectric film 9. The dielectric film 9 is, for example, a
silicon oxide film formed by CVD (Chemical Vapor Deposition) with a
thickness of about 2 .mu.m. The n-side interconnect electrode 4 and
the p-side interconnect electrode 5 are, for example, aluminum
films formed by sputtering with a thickness of about 1 .mu.m. These
aluminum films are formed on the entire surface of the dielectric
film 9 and then are patterned into the desired electrode
configuration by removing the unnecessary portions by wet
etching.
[0042] Continuing, the entire surface of the second major surface
(the bottom face) of the substrate 3 on the side opposite to the
face where the semiconductor light emitting element is mounted is
then grinded to make the substrate 3 thin. Then, as illustrated in
FIG. 3C, a connection hole 22 is made in the second major surface
by, for example, RIE (Reactive Ion Etching). The connection hole 22
is made in the portion below the recess 3b from the second major
surface to reach the dielectric film 9.
[0043] Then, for example, a photosensitive polyimide film is coated
on the second major surface and into the connection hole 22. Then,
an opening (FIG. 3D) is made in a portion of the polyimide film
contacting the dielectric film 9. A connection hole 23 is made in
the dielectric film 9 exposed at the opening as illustrated in FIG.
4A. The connection hole 23 passes through the dielectric film 9
formed on the bottom face of the recess 3b to reach the n-side
interconnect electrode 4 and the p-side interconnect electrode
5.
[0044] Continuing as illustrated in FIG. 4B, the through-electrodes
18 are filled into the connection holes 22 and 23 and
simultaneously the n-side bottom face bonding electrode 11 and the
p-side bottom face bonding electrode 12 are formed on the second
major surface. These electrodes are made of, for example, copper
material formed by plating. Thereby, the n-side interconnect
electrode 4 on the first major surface is connected to the n-side
bottom face bonding electrode 11 on the second major surface via
the through-electrode 18; and the p-side interconnect electrode 5
on the first major surface is connected to the p-side bottom face
bonding electrode 12 on the second major surface via the
through-electrode 18.
[0045] Then, as illustrated in FIG. 4C, the n-side bonding metal 6
and the p-side bonding metal 7 are formed on the n-side
interconnect electrode 4 and the p-side interconnect electrode 5,
respectively, on the protrusion 3a. Then, the semiconductor light
emitting element 20 having a chip configuration is bonded by flip
chip bonding to the n-side bonding metal 6 and the p-side bonding
metal 7. This bond is performed by, for example, forming Au on the
n-side bonding metal 6 and the p-side bonding metal 7 side and Sn
on the semiconductor light emitting element 20 side beforehand,
performing positional alignment therebetween, and forming eutectic
AuSn by thermal fusion. Alternatively, AuSn eutectic solder may be
formed by plating beforehand on either the n-side bonding metal 6
and the p-side bonding metal 7 side or the semiconductor light
emitting element 20 side. Or, another solder material other than
eutectic solder may be used. A metal powder resin mixture such as
Ag paste also may be used.
[0046] The semiconductor light emitting element 20 is formed on a
light emitting element substrate 17 by epitaxial growth and the
like separately from the process described above for the substrate
3. To enable easier handling during mounting, the light emitting
element 20 is mounted for each of the relatively thick light
emitting element substrates 17.
[0047] Although the light emitting element substrates 17 are
mounted in a separated state for each of the light emitting element
20 in FIG. 4C, the light emitting element substrate 17 may be
formed without separating, and multiple light emitting element 20
may be formed as island-like shapes on the light emitting element
substrate 17.
[0048] After the mounting, because the light emitting element
substrate 17 is positioned on the light extraction surface side, a
process of removing the light emitting element substrate 17 is
performed (FIG. 5A) to reduce the chip thickness to the minimum
necessary thickness to reduce the light absorption of the light
emitting element substrate 17 and to allow the formation of the
reinforcing film 15 and the fluorescent material 10 via the gap 30
described above in a process described below. The light emitting
element substrate 17 may be removed by, for example, polishing,
etching, lift off by a spacer, laser lift off, and the like. After
removing the light emitting element substrate 17, the thickness of
the remaining semiconductor light emitting device 20 is about 5 to
10 .mu.m.
[0049] After removing the light emitting element substrate 17, the
AR coating 40 described above is formed on the entire surface of
the wafer. Then, the AR coating 40 on portions of the semiconductor
light emitting element 20 other than the light extraction surface
is removed. The AR coating 40 is, for example, a SiO.sub.2 film
formed by plasma CVD (Chemical Vapor Deposition) at 250.degree. C.
with a thickness of about 65 nm. The semiconductor light emitting
element 20 is bonded by, for example, AuSn solder at this time and
therefore can be prevented from shifting due to melting of the
solder.
[0050] Continuing as illustrated in FIG. 5B, a sacrificial layer 21
is selectively formed on the protrusion 3a of the substrate 3 to
cover the semiconductor light emitting element 20. Organic
materials are suitable as the material of the sacrificial layer 21;
and polyimide, for example, may be used.
[0051] The thickness of the sacrificial layer 21 from the top face
of the semiconductor light emitting element 20 (the n-type
semiconductor 1) is about 3 to 5 .mu.m considering the height of
the gap 30 made subsequently. The sacrificial layer 21 is formed on
the entire surface of the wafer. Then, patterning is performed to
remove the unnecessary portions of the sacrificial layer 21 by dry
etching by plasma processing, an alkaline developer, etc., to leave
only the portion to define the gap 30.
[0052] Then, as illustrated in FIG. 5C, the reinforcing film (e.g.,
the silicon oxide film) 15 is formed to cover the sacrificial layer
21, the n-side interconnect electrode 4, and the p-side
interconnect electrode 5. An opening is made in a portion of the
reinforcing film 15 on the sacrificial layer 21 for removing the
sacrificial layer 21. The opening may be multiply made, for
example, in a lattice configuration with diameters of 2 .mu.m at 10
.mu.m pitches by photolithography and dry etching.
[0053] The sacrificial layer 21 is removed from above the
semiconductor light emitting element 20 through the openings. For
example, the sacrificial layer 21 made of polyimide can be removed
by ashing by O.sub.2 plasma. To reduce the ashing time, the gas
introduced into the chamber may include a mixture of several
percent of CF.sub.4 added to O.sub.2 or a forming gas (a gas
mixture in which H.sub.2 is diluted by N.sub.2 to be not more than
3%) mixed with O.sub.2. However, it is desirable to make sure the
mixing ratio of the CF.sub.4 gas is not so high that a near-dry
etching state occurs. In other words, it is desirable to keep the
flow rate ratio of F to the main O.sub.2 gas not more than 3%
because the characteristics of the n-side interconnect electrode 4
and the p-side interconnect electrode 5 deteriorate when F bonds
with the Al forming the n-side interconnect electrode 4 and the
p-side interconnect electrode 5.
[0054] FIG. 6A illustrates the state after removing the sacrificial
layer 21. Removing the sacrificial layer 21 leaves the gap 30
enclosed by the reinforcing film 15 around and above the
semiconductor light emitting element 20.
[0055] The openings made to remove the sacrificial layer 21 may be
plugged by, for example, forming a silicon oxide film by CVD. The
openings are plugged by depositing the silicon oxide film to
overhang from the edges of the openings.
[0056] Although the fluorescent material is formed subsequently,
normally, the fluorescent material is formed by dispersing a fine
powder in a matrix resin to form a paste configuration; using
screen printing; and then subsequently performing curing by a
method such as heat treatment, ultraviolet curing, and the like.
Various resins such as acrylic, polyester, silicone, epoxy, and
polyimide may be used as the matrix resin. However, the use of a
resin shortens the life of the semiconductor light emitting element
itself because the life of the product is determined by the
resin.
[0057] However, to form a fluorescent material having the desired
fluorescent light emission without using a resin, it is necessary
to perform heat treatment at a high temperature of about
450.degree. C. Therefore, it is unfavorable from the aspect of
device characteristic deterioration for the fluorescent material to
cover the semiconductor light emitting element 20 in direct
contact.
[0058] Therefore, the fluorescent material 10 of this embodiment is
formed by the following method.
[0059] For example, the fluorescent material 10 is formed on the
reinforcing film 15 as illustrated in FIG. 6B by sputtering
multiple targets of Ba, Mn, Al, Eu, Sr, Ca, Ba, Mg, P, and C in an
Ar/O.sub.2 gas mixture atmosphere. Then, it is necessary to heat
the fluorescent material 10 to obtain the desired fluorescent light
emission characteristics. However, it is necessary to prevent the
deterioration of the semiconductor light emitting element 20
characteristics caused by the heating at this time.
[0060] Therefore, in this embodiment as illustrated in FIG. 6C,
only the fluorescent material 10 is locally heated from the top
face (the face on the side opposite to the face contacting the
reinforcing film 15) side of the fluorescent material 10 by laser
irradiation; the fluorescent material 10 is reformed to change the
characteristics thereof (crystallinity, dimensions, surface
morphology, etc.); and the desired fluorescent light emission is
obtained.
[0061] At this time, the heat of the fluorescent material 10 is not
easily conducted to the semiconductor light emitting element 20 due
to the gap 30 between the fluorescent material 10 and the
semiconductor light emitting element 20. Further, the laser
irradiation is from the fluorescent material 10 top face side and
does not heat the entire wafer. Therefore, the temperature increase
of the substrate 3 can be suppressed, and the temperature increase
of the semiconductor light emitting element 20 mounted on the
substrate 3 due to heat conducted from the substrate 3 to the
semiconductor light emitting element 20 also is prevented. Thus,
the temperature increase and characteristic deterioration of the
semiconductor light emitting element 20 are suppressed when heating
the fluorescent material 10.
[0062] The fluorescent material 10 does not directly define the gap
30 and is stabilized and maintained above the gap 30 by the
reinforcing film 15. The reinforcing film 15 is, for example, a
silicon oxide film and does not melt at the temperature (about 450
to 500.degree. C.) during the laser heating of the fluorescent
material 10. Accordingly, the gap 30 can be stabilized and
maintained even in the case where the fluorescent material 10 is in
a fluidic state due to the laser heating.
[0063] It is necessary for the openings made in the film covering
the sacrificial layer 21 for removing the sacrificial layer 21 to
be fine considering the plugging of the openings after removing the
sacrificial layer 21. Here, in the case where the fluorescent
material is directly formed on the sacrificial layer 21 without
forming the reinforcing film 15 after the process described above
in regard to FIG. 5B, it is necessary to make fine openings in the
fluorescent material for removing the sacrificial layer 21.
However, generally, it is difficult to make fine openings in the
fluorescent material. Conversely, fine openings can be made easily
in the reinforcing film 15 formed of, for example, a silicon oxide
film.
[0064] After laser annealing of the fluorescent material 10, the
lens 16 illustrated in FIG. 1 is formed on the fluorescent material
10. For example, methyl siloxane is coated onto the fluorescent
material 10 by spin coating; a template is brought into contact
with the coating film; and a recessed configuration is
patterned.
[0065] Thereafter, the external connection terminals 14 are formed,
dicing and the like is performed to separate the desired pieces
from the wafer form, and the structure illustrated in FIG. 1 is
obtained.
[0066] The processes of forming the components up to dicing
described above can be performed collectively in the wafer form,
enabling low-cost manufacturing.
[0067] The connection hole communicating from the first major
surface to the second major surface of the substrate can be made
from the first major surface side or from the second major surface
side.
[0068] Hereinabove, exemplary embodiments of the invention are
described with reference to specific examples. However, the
invention is not limited thereto, and various modifications are
possible based on the technical spirit of the invention. In other
words, materials, dimensions, and process conditions other than
those illustrated in the exemplary embodiments recited above are
implementable without departing from the purport of the
invention.
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