U.S. patent application number 13/288631 was filed with the patent office on 2012-05-31 for semiconductor device having plural memory chip.
This patent application is currently assigned to ELPIDA MEMORY, INC.. Invention is credited to Akira IDE.
Application Number | 20120134193 13/288631 |
Document ID | / |
Family ID | 46126567 |
Filed Date | 2012-05-31 |
United States Patent
Application |
20120134193 |
Kind Code |
A1 |
IDE; Akira |
May 31, 2012 |
SEMICONDUCTOR DEVICE HAVING PLURAL MEMORY CHIP
Abstract
A semiconductor device includes a stacked plurality of memory
chips. The memory chips each include a plurality of memory banks, a
plurality of read/write buses that are assigned to the respective
memory banks, and a plurality of penetration electrodes that are
assigned to the respective read/write buses and arranged through
the memory chip. Penetration electrodes arranged in the same
positions as seen in a stacking direction are connected in common
between the chips. In response to an access request, the memory
chips activate the memory banks that are arranged in respective
different positions as seen in the stacking direction, whereby data
is simultaneously input/output via the penetration electrodes that
lie in different planar positions.
Inventors: |
IDE; Akira; (Tokyo,
JP) |
Assignee: |
ELPIDA MEMORY, INC.
|
Family ID: |
46126567 |
Appl. No.: |
13/288631 |
Filed: |
November 3, 2011 |
Current U.S.
Class: |
365/51 |
Current CPC
Class: |
G11C 5/04 20130101; H01L
2224/16145 20130101; H01L 23/50 20130101; H01L 23/481 20130101;
H01L 2225/06544 20130101; G11C 11/408 20130101; H01L 25/0657
20130101 |
Class at
Publication: |
365/51 |
International
Class: |
G11C 5/02 20060101
G11C005/02 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 30, 2010 |
JP |
2010-266589 |
Claims
1. A semiconductor device comprising a plurality of memory chips
stacked to each other, each of the memory chips including a
plurality of memory banks, a plurality of read/write buses each
transferring data to/from an associated one of the memory banks,
and a plurality of penetration electrodes each transferring the
data to/from an associated one of the read/write buses and arranged
penetrating through the memory chip, the penetration electrodes
arranged in the same positions as seen in a stacking direction of
the memory chips being coupled in common between the memory chips,
and each one of the memory banks included in the memory chips being
activated in response to an access request so that the activated
memory banks are arranged in respective different positions as seen
in the stacking direction, thereby the data are simultaneously
transferred via the penetration electrodes in parallel.
2. The semiconductor device as claimed in claim 1, wherein the
access request is made by supplying an address signal and a command
signal to the memory chips in common.
3. The semiconductor device as claimed in claim 2, wherein each of
the chips has respective one of chip addresses different from each
other, the address signal includes a bank address that specifies
one of the memory banks, each of the memory chips further includes
a bank address generating circuit that performs a logical operation
using the bank address and the chip address to generate an internal
bank address, and each of the memory chips activates any one of the
memory banks based on the internal bank address.
4. The semiconductor device as claimed in claim 3, wherein each of
the memory chips further includes a chip address register that
retains the chip address, and the chip address registers included
in the memory chips are serially connected via other penetration
electrodes.
5. The semiconductor device as claimed in claim 1, further
comprising an interface chip that controls the memory chips,
wherein the interface chip converts the data supplied from the
memory chips via the penetration electrodes from parallel to serial
and outputs the data serial converted to outside, and the interface
chip converts the data supplied from outside from serial to
parallel and outputs the data parallel converted to the memory
chips via the penetration electrodes.
6. The semiconductor device as claimed in claim 5, wherein the
memory chips and the interface chip are stacked to one another.
7. The semiconductor device as claimed in claim 1, wherein the same
addresses are assigned to the memory chips so that all the memory
chips are accessed at the same time.
8. The semiconductor device as claimed in claim 1, wherein the
memory chips include a plurality of groups of memory chips, and the
same addresses are assigned to the memory chips belonging to the
same group so that all the memory chips belonging to the same group
are accessed at the same time.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device, and
more particularly to a semiconductor device includes a stacked
plurality of semiconductor memory chips.
[0003] 2. Description of Related Art
[0004] Storage capacities required to semiconductor memories such
as a dynamic random access memory (DRAM) have been increasing year
by year. To satisfy such a request, a semiconductor memory device
called multi-chip package has recently been proposed in which a
plurality of memory chips are stacked on each other. In a
multi-chip package, wirings for connecting a memory chip with the
package substrate need to be provided each memory chip. This makes
it difficult to stack a large number of memory chips.
[0005] In view of this, there has recently been proposed a type of
semiconductor device in which a plurality of memory chips having
through silicon vias are stacked (see Japanese Patent Application
Laid-Open Nos. 2002-305283 and 2003-110086). In such a type of
semiconductor device, through silicon vias that are located in the
same planar positions as seen in the stacking direction formed in
the memory chips are electrically short-circuited to one another.
This prevents the number of electrodes to be connected to the
package substrate from increasing even if the number of stacked
memory chips increases. It is therefore possible to stack a greater
number of memory chips.
[0006] In such a semiconductor device of stacked type using through
silicon vias, an address space may extend because of increasing a
storage capacity. For example, a stack of eight memory chips may be
handled as a large-capacity chip having an address space eight
times that of a single memory chip. In such a case, the through
silicon vias connected in common between the memory chips are used
in a time sharing manner since different memory chips are selected
by respective accesses. There occurs no data conflict on the
through silicon vias.
[0007] An increase in storage capacity due to stacking may also be
used to extend the data input/output width instead of address
extension. For example, eight memory chips each having eight data
input/output terminals can be stacked to implement a data
input/output width of 64 bits. Such a semiconductor device may be
handled as a single memory module.
[0008] When the data input/output width is extended, the memory
chips need to transfer data via respective different through
silicon vias since all the memory chips are selected for every
access. In this case, the same address signal is supplied to all
the memory chips. In a read operation, for example, read data
supplied from memory banks located in the same planar positions as
seen from the stacking direction therefore need to be distributed
so as to supply the read data to different through silicon vias
chip by chip. The read/write buses connected between the memory
banks and the through silicon vias need to be provided in equal
lengths with respect to each memory bank. Distributing the read
data to different through silicon vias chip by chip therefore has
the problem of not only increasing the number of read/write buses
required but also increasing the wiring lengths significantly.
SUMMARY
[0009] In one embodiment, there is provided a semiconductor device
that includes a plurality of memory chips stacked to each other,
each of the memory chips including a plurality of memory banks, a
plurality of read/write buses each transferring data to/from an
associated one of the memory banks, and a plurality of penetration
electrodes each transferring the data to/from an associated one of
the read/write buses and arranged penetrating through the memory
chip, the penetration electrodes arranged in the same positions as
seen in a stacking direction of the memory chips being coupled in
common between the memory chips, and each one of the memory banks
included in the memory chips being activated in response to an
access request so that the activated memory banks are arranged in
respective different positions as seen in the stacking direction,
thereby the data are simultaneously transferred via the penetration
electrodes in parallel.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The above and other features and advantages of the present
invention will be more apparent from the following description of
certain preferred embodiments taken in conjunction with the
accompanying drawings, in which:
[0011] FIG. 1 is a schematic cross-sectional view illustrating the
structure of a semiconductor memory device according to the
preferred embodiment of the present invention;
[0012] FIGS. 2A to 2C are diagram showing the various types of
through silicon vias TSV provided in a core chip;
[0013] FIG. 3 is a cross-sectional view illustrating the structure
of the through silicon via TSV1 of the type shown in FIG. 2A;
[0014] FIG. 4 is a cross-sectional view illustrating the structure
of the through silicon via TSV2 of the type shown in FIG. 2B;
[0015] FIG. 5 is a cross-sectional view illustrating the structure
of the through silicon vias TSV3 of the type shown in FIG. 2C;
[0016] FIG. 6 is a schematic diagram explaining the cyclic
connection of the through silicon vias TSV3;
[0017] FIG. 7 is a block diagram showing the configuration of
essential parts of the semiconductor device 10 according to the
embodiment of the present invention;
[0018] FIG. 8 is a circuit diagram of the bank address generating
circuit shown in FIG. 7;
[0019] FIG. 9 is a schematic diagram for explaining the
relationship between the memory banks, the read/write buses RWBS,
and the through silicon vias TSV1 (data) for data transfer;
[0020] FIG. 10 is a schematic diagram for explaining the operation
of the semiconductor device 10 according to the embodiment of the
present invention;
[0021] FIG. 11 is a schematic diagram for explaining the operation
of a semiconductor device according to a comparative example;
[0022] FIG. 12 is a schematic diagram for explaining the
configuration of the core chips CC0 to CC7 that is intended to
implement the function of FIG. 11;
[0023] FIG. 13 is a block diagram showing the configuration of a
semiconductor device 10a according to a second embodiment of the
present invention;
[0024] FIG. 14 is a circuit diagram of the bank address generating
circuit 42 shown in FIG. 13;
[0025] FIG. 15 is a circuit diagram of the layer address comparison
circuit 41a shown in FIG. 13; and
[0026] FIG. 16 is a schematic diagram for explaining the logical
arrangement of bank addresses in the core chips CC0 to CC3
according to the second embodiment.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0027] Preferred embodiments of the present invention will be
explained below in detail with reference to the accompanying
drawings.
[0028] Referring now to FIG. 1, the semiconductor device 10
according to this embodiment has the structure where eight core
chips (memory chips) CC0 to CC7 that have the same function and
structure and are manufactured using the same manufacture mask, an
interface chip IF that is manufactured using a manufacture mask
different from that of the core chips and an interposer IP are
laminated. The core chips CC0 to CC7 and the interface chip IF are
semiconductor chips using a silicon substrate and are electrically
connected to adjacent chips in a vertical direction through plural
Through Silicon Vias (TSV) penetrating the silicon substrate. The
through silicon vias may be referred to as penetration electrodes.
Meanwhile, the interposer IP is a circuit board that is made of a
resin, and plural external terminals (solder balls) SB are formed
in a back surface IPb of the interposer IP.
[0029] Each of the core chips CC0 to CC7 is a semiconductor chip
which consists of circuit blocks other than a so-called front end
unit having a front end function performing a function of an
interface with an external device through an external terminal
among circuit blocks included in an ordinary SDRAM (Synchronous
Dynamic Random Access Memory). The SDRAM operates even as a single
chip and is capable to communicate directly with a memory
controller. As the circuit blocks that are included in the front
end unit, a parallel-serial converting circuit having a data latch
circuit that performs parallel/serial conversion on input/output
data between a memory cell array and a data input/output terminal
and a DLL (Delay Locked Loop) circuit that controls input/output
timing of data are exemplified, which will be described in detail
below.
[0030] The interface chip IF is a semiconductor chip into which
only the front end unit included in an ordinary SDRAM is
integrated. The interface chip IF functions as a common front end
unit for the eight core chips CC0 to CC7. Accordingly, all external
accesses are performed through the interface chip IF and
inputs/outputs of data are also performed through the interface
chip IF.
[0031] In this embodiment, the interface chip IF is disposed
between the interposer IP and the core chips CC0 to CC7. However,
the position of the interface chip IF is not restricted in
particular, and the interface chip IF may be disposed on the core
chips CC0 to CC7 and may be disposed on the back surface IPb of the
interposer IP. When the interface chip IF is disposed on the core
chips CC0 to CC7 in a face-down manner or is disposed on the back
surface IPb of the interposer IP in a face-up manner, the through
silicon vias TSV does not need to be provided in the interface chip
IF. The interface chip IF may be disposed to be interposed between
the two interposers IP.
[0032] The interposer IP functions as a rewiring substrate to
increase an electrode pitch and secures mechanical strength of the
semiconductor device 10. That is, an electrode 91 that is formed on
a top surface IPa of the interposer IP is drawn to the back surface
IPb via a through-hole electrode 92 and the pitch of the external
terminals SB is enlarged by the rewiring layer 93 provided on the
back surface IPb. In FIG. 1, only the two external terminals SB are
shown. In actuality, however, three or more external terminals are
provided. The layout of the external terminals SB is the same as
that of the SDRAM that is determined by the regulation.
Accordingly, the semiconductor device 10 can be treated as one
SDRAM from the external controller.
[0033] As shown in FIG. 1, a top surface of the uppermost core chip
CC0 is covered by an NCF (Non-Conductive Film) 94 and a lead frame
95. Gaps between the core chips CC0 to CC7 and the interface chip
IF are filled with an underfill 96 and surrounding portions of the
gaps are covered by a sealing resin 97. Thereby, the individual
chips are physically protected.
[0034] When most of the through silicon vias TSV provided in the
core chips CC0 to CC7 viewed from a lamination direction, that is,
viewed from an arrow A shown in FIG. 1, are short-circuited from
the through silicon vias TSV of other layers provided at the same
position. That is, as shown in FIG. 2A, the vertically disposed
through silicon vias TSV1 that are provided at the same position in
plain view are short-circuited, and one wiring line is configured
by the through silicon vias TSV1. The through silicon vias TSV1
that are provided in each of the core chips CC0 to CC7 are
connected to internal circuits 4 in the core chips, respectively.
Accordingly, input signals (command signal, address signal, etc.)
that are supplied from the interface chip IF to the through silicon
vias TSV1 shown in FIG. 2A are commonly supplied to the internal
circuits 4 of the core chips CC0 to CC7. Output signals (data etc.)
that are supplied from the core chips CC0 to CC7 to the through
silicon vias TSV1 are wired-ORed and supplied to the interface chip
IF.
[0035] Meanwhile, as shown in FIG. 2B, another through silicon vias
TSV2 are not directly connected to the through silicon vias TSV2 of
other layers provided at the same position in plain view but are
connected to the through silicon vias TSV2 of other layers through
the internal circuits 5 provided in the core chips CC0 to CC7. That
is, the internal circuits that are provided in the core chips CC0
to CC7 are cascade-connected through the through silicon vias TSV2.
This kind of through silicon vias TSV2 are used to sequentially
transmit predetermined information to the internal circuits 5
provided in the core chips CC0 to CC7. As this information, chip
address information to be described below is exemplified.
[0036] Still another through silicon vias TSV3 are short-circuited
to the through silicon vias TSV3 of other layer provided at the
different position in plan view, as shown in FIG. 2C. With respect
to this kind of through silicon vias TSV3, internal circuits 6 of
the core chips CC0 to CC7 are connected to the TSV3a provided at
the predetermined position P in plain view. Thereby, information
can be selectively supplied to the internal circuits 6 provided in
the core chips. As this information, defective chip information is
exemplified.
[0037] As such, as types of the through silicon vias TSVs provided
in the core chips CC0 to CC7, three types (TSV1 to TSV3) shown in
FIGS. 2A to 2C exist. As described above, most of the through
silicon vias TSVs are of a type shown in FIG. 2A, and an address
signal, a command signal, and a clock signal are supplied from the
interface chip IF to the core chips CC0 to CC7, through the through
silicon vias TSV1 of the type shown in FIG. 2A. Read data and write
data are input to and output from the interface chip IF through the
through silicon vias TSV1 of the type shown in FIG. 2A. Meanwhile,
the through silicon vias TSV2 and TSV3 of the types shown in FIGS.
2B and 2C are used to provide individual information to the core
chips CC0 to CC7 having the same structure.
[0038] Turning to FIG. 3, the through silicon vias TSV1 is provided
to penetrate a silicon substrate 80 and an interlayer insulating
film 81 provided on a surface of the silicon substrate 80. Around
the through silicon vias TSV1, an insulating ring 82 is provided.
Thereby, the TSV1 and a transistor region are insulated from each
other. In an example shown in FIG. 3, the insulating ring 82 is
provided double. Thereby, capacitance between the through silicon
vias TSV1 and the silicon substrate 80 is reduced.
[0039] An end 83 of the through silicon vias TSV1 at the back
surface of the silicon substrate 80 is covered by a back surface
bump 84. The back surface bump 84 is an electrode that contacts a
surface bump 85 provided in a core chip of a lower layer. The
surface bump 85 is connected to an end 86 of the through silicon
vias TSV1, through plural pads P0 to P3 provided in wiring layers
L0 to L3 and plural through-hole electrodes TH1 to TH3 connecting
the pads to each other. Thereby, the surface bump 85 and the back
surface bump 84 that are provided at the same position in plain
view are short-circuited. Connection with internal circuits (not
shown in the drawings) is performed through internal wiring lines
(not shown in the drawings) drawn from the pads P0 to P3 provided
in the wiring layers L0 to L3.
[0040] Turning to FIG. 4, the through silicon via TSV2 differs from
the through silicon via TSV1 shown in FIG. 3 in the omission of the
through-hole electrodes TH2 which directly connect the pad P1 and
the pad P2 lying in the same planar position. The pad P1 is
connected to, for example, the output node of an internal circuit 5
shown in FIG. 2B. The pad P2 is connected to, for example, the
input node of the internal circuit 5 shown in FIG. 2B. The internal
circuits 5 arranged in the core chips CC0 to CC7 are thus cascaded
through the intervention of through silicon vias TSV2.
[0041] Turning to FIG. 5, the through silicon vias TSV3 are
configured not so that the pads P1 and P2 formed in the same planar
positions are connected by through-hole electrodes TH2, but so that
pads P1 and P2 formed in different planar positions are connected
by through-hole electrodes TH2. While FIG. 5 shows only three
through silicon vias TSV3, there are provided through silicon vias
TSV3 as many as the number of core chips CC0 to CC7 (eight) per
signal. The eight through silicon vias TSV3 are cyclically
connected as shown in FIG. 6. FIG. 6 shows surface bumps 85 in
solid lines and rear bumps 84 in broken lines. As shown in FIG. 6,
the cyclic connection of the through silicon vias TSV3 makes it
possible to supply individual data from the interface chip IF to
the respective core chips CC0 to CC7 with the core chips CC0 to CC7
identical in circuit configuration. For example, if internal
circuit 6 are connected to the positions of the rear bumps 84-7,
signals supplied from the interface chip IF to the rear bumps 84-0
to 84-7 of the lowermost core chip CC7 are selectively supplied to
the internal circuits 6 of the core chips CC0 to CC7,
respectively.
[0042] Turning to FIG. 7, the external terminals arranged on the
interposer IP include a clock terminal 11, a command terminal 12,
an address terminal 13, a bank address terminal 14, and data
input/output terminals 15. The interposer IP also has other
external terminals such as a data strobe terminal and power supply
terminals, which are omitted from the diagram. All the external
terminals excluding power supply terminals are connected to the
interface chip IF, not directly to the core chips CC0 to CC7.
[0043] The clock terminal 11 is supplied with an external clock
signal CK. The external clock signal CK is supplied to a clock
generating circuit 21. The clock generating circuit 21 generates an
internal clock signal ICLK. The internal clock signal ICLK is
supplied to various circuit blocks in the interface chip IF, as
well as to the core chips CC0 to CC7 through a TSV buffer 31.
[0044] The command terminal 12 is supplied with command signals CMD
including a row address strobe signal RASB, a column address strobe
signal CASB, and a write enable signal WEB. The command signals CMD
are supplied to a command decoder 22. The command decoder 22
decodes the command signals CMD to generate an internal command
signal ICMD. The internal command signal ICMD is supplied to the
core chips CC0 to CC7 through the TSV buffer 31.
[0045] The address terminal 13 is supplied with an address signal
ADD. The bank address terminal 14 is supplied with a bank address
BA. The address signal ADD and bank address BA are latched by
address latch circuits 23 and 24, respectively, and supplied to the
core chips CC0 to CC7 through the TSV buffer 31.
[0046] The data input/output terminals 15 are terminals for
outputting read data and inputting write data. In the present
embodiment, the data input/output terminals 15 include sixty-four
terminals DQ0 to DQ63. Each of the data input/output terminals 15
is connected to a parallel-to-serial conversion circuit P/S and a
serial-to-parallel conversion circuit S/P through a data
input/output circuit 25. In a read operation, parallel read data
output from the core chips CC0 to CC7 through the TSV buffer 31 is
converted into serial data by the parallel-to-serial conversion
circuits P/S, and burst out through the sixty-four data
input/output terminals 15. In a write operation, write data
serially burst in from the sixty-four data input/output terminals
15 is converted into parallel data by the serial-to-parallel
conversion circuits S/P, and output to the core chips CC0 to CC7
through the TSV buffer 31.
[0047] In the present embodiment, the core chips CC0 to CC7 are
composed of the back end sections of DDR3 (Double Data Rate 3)
DRAMs with a prefetch number of eight bits. More specifically, the
parallel-to-serial conversion circuits P/S perform
parallel-to-serial conversion of eight bits per data input/output
terminal 15. The serial-to-parallel conversion circuits S/P perform
serial-to-parallel conversion of eight bits per data input/output
terminal 15. The number of bits of data to be simultaneously
input/output between the interface chip IF and the core chips CC0
to CC7 is thus 512, and 512 through silicon vias TSV1 are used for
data transfer. The other through silicon vias TSV1 shown in FIG. 7
include ones that transmit the address signal ADD, the bank address
BA, the internal command signal ICMD, and the internal clock signal
ICLK. Such through silicon vias are through silicon vias TSV1 of
the type shown in FIG. 2A. This means that the address signal ADD,
the bank address BA, the internal command signal ICMD, and the like
are supplied from the interface chip IF to the core chips CC0 to
CC7 in common.
[0048] As shown in FIG. 7, the address signal ADD, the internal
command signal ICMD, and the internal clock signal ICLK are
supplied from the interface chip IF to an access control circuit 41
in each of the core chips CC0 to CC7 via through silicon vias TSV1
and a TSV buffer 32. Meanwhile, the bank address BA is not directly
supplied to the access control circuit 41, but is converted into an
internal bank address IBA by a bank address generating circuit 42
before supplied to the access control circuit 41. The bank address
generating circuit 42 generates the internal bank address IBA
through an operation using the bank address BA supplied from the
interface chip IF and a chip address SID retained in a chip address
register 43. A detailed example of the bank address generating
circuit 42 will be described later.
[0049] The chip address register 43 retains a chip address SID
which is different from one another to the respective core chips
CC0 to CC7. To assign different chip addresses SID to the
respective core chips CC0 to CC7, through silicon vias TSV2 of the
type shown in FIG. 2B or through silicon vias TSV3 of the type
shown in FIG. 2C need to be used. For example, through silicon vias
TSV2 of the type shown 2B may be used with a chip address setting
circuit 26 in the interface chip IF. Different data can be given to
the internal circuits 5 of the respective core chips CC0 to CC7 by
transferring 3-bit data from upper to lower layers (or lower to
upper layers) while incrementing the data by the internal circuits
5. The respective pieces of data can be latched by the chip address
registers 43 as the different chip addresses SID assigned to the
core chips CC0 to CC7.
[0050] The access control circuit 41 performs row access control
and column access control based on various types of signals
supplied thereto. Specifically, if the internal command signal ICMD
indicates an active command, the address signal ADD is supplied to
a row decoder 51. The row decoder 51 then selects a word line WL
specified by the address signal ADD, whereby a row access is
performed. If the internal command signal ICMD indicates a read
command or write command, the address signal ADD is supplied to a
column decoder 52. The column decoder 52 selects sense amplifiers
SA in a sense circuit 53 that are specified by the address signal
ADD, whereby a column access is performed.
[0051] A memory cell array 50 includes a plurality of word lines WL
and a plurality of bit lines BL. The memory cells MC are arranged
at the intersections of the word lines WL and the bit lines BL. The
bit lines BL are connected to respective corresponding sense
amplifiers SA. In a read operation, read data amplified by sense
amplifiers SA are further amplified by a data amplifier 54 and
supplied to the TSV buffer 32 through a read/write bus RWBS. In a
write operation, write data supplied through the TSV buffer 32 and
the read/write bus RWBS are supplied to selected bit lines BL
through the data amplifier 54.
[0052] In the present embodiment, the memory cell array 50 has an
eight-bank configuration. Which memory bank to access is specified
by the internal bank address IBA. A memory bank is the unit to be
issued commands. The memory banks are capable of interleaving
operations. In the present invention, it is important that the
memory banks are selected not by the bank address BA that is
supplied from outside, but by the internal bank address IBA that is
generated inside. Based on the internal bank address IBA, the
access control circuit 41 also supplies an enable signal EN to the
TSV buffer 32. The enable signal EN is a signal for activating any
one of TSV buffers B0 to B7 that are assigned to the through
silicon vias TSV1 for data transfer. The TSV buffers B0 to B7
correspond to the respective memory banks to be selected by the
internal bank address IBA.
[0053] Turning to FIG. 8, the bank address generating circuit 42
includes three exclusive OR circuits (EOR circuits) 42a to 42c. The
EOR circuit 42a receives a bit BA0 of the bank address BA and a bit
SID0 of the chip address SID to generate a bit IBA0 of the internal
bank address IBA. Similarly, the EOR circuit 42b receives a bit BA1
of the bank address BA and a bit SID1 of the chip address SID to
generate a bit IBA1 of the internal bank address IBA. The EOR
circuit 42c receives a bit BA2 of the bank address BA and a bit
SID2 of the chip address SID to generate a bit IBA2 of the internal
bank address IBA.
[0054] As described previously, the bank address BA is supplied to
the core chips CC0 to CC7 in common. The core chips CC0 to CC7 are
therefore given the same value. On the other hand, the chip address
SID is assigned so that the core chips CC0 to CC7 have respective
different values. The resulting internal bank address IBA therefore
has different values in the respective core chips CC0 to CC7. It
should be appreciated that the bits to be supplied to the EOR
circuits 42a to 42c are not limited to the foregoing combination.
Any bits of the bank address BA and any bits of the chip address
SID may be supplied to the EOR circuits 42a to 42c.
[0055] FIG. 9 shows the layout of the core chips CC0 to CC7 as seen
in the stacking direction. As shown in FIG. 9, the memory banks
Bank0 to Bank7 are laid out in respective different planar
positions, with respective dedicated read/write buses RWBS0 to
RWBS7 assigned thereto. In the present embodiment, eight data
input/output terminals 15 are assigned for each of the core chips
CC0 to CC7, with 8-bit prefetch operations. The number of bits of
data to be input/output into/from a single core chip CC0 to CC7 by
a single access is thus sixty-four. The read/write buses RWBS0 to
RWBS7 each have a data width of sixty-four bits, and input/output
sixty-four bits of data by a single access.
[0056] In a read operation, read data that is read from a selected
memory bank is then transferred to the interface chip IF through
the read/write bus RWBS dedicated to the memory bank and through
the through silicon vias TSV1 (data) for data transfer dedicated to
the memory bank. In a write operation, write data is transferred
from the interface chip IF to the selected memory bank through the
dedicated through silicon vias TSV1 (data) for data transfer. The
transferred write data are supplied to the selected memory bank
through the dedicated read/write bus RWBS.
[0057] In the core chips CC0 to CC7, respective different memory
banks are selected by the operation of the bank address generating
circuits 42. The eight core chips CC0 to CC7 therefore use
respective different through silicon vias TSV1 (data) for data
transfer to transfer read data or write data.
[0058] FIG. 10 shows a read operation where the bank address BA is
(000). As shown in FIG. 10, if the bank address BA is (000), the
core chips CC0 to CC7 generate internal bank addresses IBA of (000)
to (111), respectively. It follows that the memory banks to be
actually accessed in the core chips CC0 to CC7 are the memory banks
Bank0 to Bank7, respectively. The memory banks to be accessed are
shown shaded in FIG. 10.
[0059] Enable signals EN0 to EN7 are activated in the core chips
CC0 to CC7 according to the generated internal bank addresses IBA,
respectively, thereby read data is transferred via respective
different through silicon vias TSV1. There occurs no data conflict
on the through silicon vias TSV1, and the 512 bits of read data is
simultaneously transferred to the interface chip IF. The read data
transferred to the interface chip IF is converted into serial data
by the parallel-to-serial conversion circuits P/S before burst out
through the sixty-four data input/output terminals 15. A write
operation is performed in a reverse manner.
[0060] As described above, according to the present embodiment, a
bank address BA supplied from outside is converted into internal
bank addresses IBA in the respective core chips CC0 to CC7. The
internal bank addresses IBA are used as actual bank addresses.
Memory banks formed in respective different planar positions can
thus be accessed even with the same logical bank address as seen
from outside. This can prevent data conflict on the through silicon
vias TSV1 for data transfer. In addition, since the memory banks to
be accessed in the eight core chips CC0 to CC7 formed in respective
different planar positions, the heat-producing positions during
operation are two-dimensionally distributed to suppress a local
temperature increase.
[0061] Similar to FIG. 10, FIG. 11 shows a read operation where the
bank address BA is (000). In the example shown in FIG. 11, the bank
address BA supplied from the interface chip IF is simply used to
access the core chips CC0 to CC7. If the bank address BA is (000),
then the memory banks to be accessed in the core chips CC0 to CC7
are all Bank0. To avoid data conflict on the through silicon vias
TSV1 (data) for data transfer, the read data read from the memory
banks Bank0 need to be assigned to through silicon vias TSV1 (data)
that differ from one of the core chips CC0 to CC7 to another. In
the example shown in FIG. 11, enable signals EN are generated by
using the chip addresses SID, and the read data in the core chips
CC0 to CC7 are thereby distributed to different through silicon
vias TSV1.
[0062] FIG. 12 shows the layout of the core chips CC0 to CC7 as
seen in the stacking direction. As shown in FIG. 12, the
implementation of the function of FIG. 11 requires that read data
read from arbitrary memory banks Bank0 to Bank7 be able to be
supplied to arbitrary through silicon vias TSV1 (data). To match
the input and output timing of 512 bits of data, read/write buses
RWBS also need to be formed in equal wiring lengths regardless of
the planar relationship between the memory banks selected and the
through silicon vias TSV1 (data) selected. Consequently, as shown
in FIG. 12, read/write buses RWBS for collecting read data read
from the memory banks Bank0 to Bank7 to a chip center once and
read/write buses RWBS for distributing the read data collected to
the center to the through silicon vias TSV1 (data) are both needed.
This increases the number of lines of the wiring and the wiring
lengths as compared to the present embodiment.
[0063] In contrast, the present embodiment can minimize the number
of read/write buses RWBS and the wiring lengths without the
foregoing problem.
[0064] Turning to FIG. 13, the semiconductor device 10a according
to the second embodiment is different from the foregoing embodiment
in that the number of core chips stacked is four and two of the
core chips are simultaneously selected by a single access. With
such a difference, the access control circuit 41, the bank address
generating circuit 42, and the chip address register 43 are
accordingly modified in configuration. In the present embodiment,
the number of bits of data to be simultaneously input/output
into/from a core chip by a single access is 128 (=16.times.8). The
number of data input/output terminals 15 is thirty-two. In other
respects, the present embodiment is basically the same as the
foregoing embodiment. The same components will thus be designated
by like reference numerals, and redundant description will be
omitted.
[0065] In the present embodiment, the number of bits of the chip
address SID stored in the chip address register 43 is two since the
number of core chips stacked is four. The upper bit SID1 of the
chip address SID is supplied to a layer address comparison circuit
41a which is included in the access control circuit 41. The lower
bit SID0 of the chip address SID is supplied to the bank address
generating circuit 42.
[0066] Turning to FIG. 14, the bank address generating circuit 42
according to the present embodiment includes an EOR circuit 42d
which receives the bit BA2 of the bank address BA and the bit SID0
of the chip address SID to generate the bit IBA2 of the internal
bank address IBA. The other bits BA0 and BA1 of the bank address BA
are simply output as the bits IBA0 and IBA1 of the internal bank
address IBA. With such a configuration, the bank address BA is
simply output as the internal bank address IBA in the even-numbered
core chips CC0 and CC2. In the odd-numbered core chips CC1 and CC3,
the bank address BA is output as the internal bank address IBA with
only the most significant bit BA2 inverted.
[0067] Turning to FIG. 15, the layer address comparison circuit 41a
includes an ENOR circuit that receives one bit (X14) of the address
signal ADD and the bit SID1 of the chip address SID to generate a
hit signal HIT. The hit signal HIT is a signal for activating the
access control circuit 41. The access control circuit 41 is
activated only in core chips where the hit signal HIT is at a high
level. With such a configuration, the lower two core chips CC0 and
CC1 are selected when X14 is at a low level. The upper two core
chips CC2 and CC3 are selected when X14 is at a high level.
[0068] Turning to FIG. 16, according to the present embodiment, the
even-numbered core chips CC0 and CC2 have bank addresses of the
same logical arrangement. The odd-numbered core chips CC1 and CC3
have bank addresses of the same logical arrangement. The
even-numbered core chips CC0 and CC2 will not be simultaneously
selected, nor will the odd-numbered core chips CC1 and CC3 be
simultaneously selected. Instead, one of the even-numbered core
chips CC0 and CC2 and one of the odd-numbered core chips CC1 and
CC3 are always selected at the same time. In the example shown in
FIG. 16, the core chips CC0 and CC1 are accessed for Bank0. The
accessed core chips CC0 and CC1 each input/output 128 bits of data
at the same time. Since the memory banks of the two
simultaneously-selected core chips are located at respective
different planar positions, the data are input/output by the
intervention of through silicon vias TSV1 provided at different
planar positions.
[0069] According to the present embodiment, not all the stacked
core chips CC0 to CC3 are simultaneously selected, but only one
half the core chips are selected at a time. The memory banks to be
accessed in the two simultaneously-selected core chips are located
at different planar positions. It is therefore possible to provide
the same effect as in the foregoing embodiment.
[0070] As described above, the present invention is even applicable
to the case where all the increase in storage capacity due to the
stacking of memory chips is not allocated to extend the data
input/output width, but one half the increase in storage capacity
is allocated to extend the data input/output width and the
remaining half to address extension as in the second
embodiment.
[0071] It is apparent that the present invention is not limited to
the above embodiments, but may be modified and changed without
departing from the scope and spirit of the invention.
[0072] For example, in the present invention, the circuit
configuration of the bank address generating circuit 42 is not
limited to that of the circuit shown in FIG. 8. Other circuit
configurations may be employed as long as the core chips CC0 to CC7
can generate respective different internal bank addresses IBA based
on the bank address BA and the chip addresses SID. For example,
adders may be used instead of the exclusive OR circuits.
[0073] In the present invention, the interface chip IF is used to
perform parallel-to-serial conversions on read data and
serial-to-parallel conversions on write data. However, part or all
of the parallel-to-serial conversions and serial-to-parallel
conversions may be performed on the memory chip side. If all the
parallel-to-serial conversions and serial-to-parallel conversions
are performed on the memory chip side, the interface chip IF may be
omitted.
* * * * *