U.S. patent application number 13/343810 was filed with the patent office on 2012-05-03 for method for manufacturing light emitting device.
This patent application is currently assigned to KABUSHIKI KAISHA TOSHIBA. Invention is credited to Yasuhiko Akaike, Yoshinori Natsume, Ryo Saeki.
Application Number | 20120104446 13/343810 |
Document ID | / |
Family ID | 42102994 |
Filed Date | 2012-05-03 |
United States Patent
Application |
20120104446 |
Kind Code |
A1 |
Akaike; Yasuhiko ; et
al. |
May 3, 2012 |
METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE
Abstract
A method for manufacturing a light emitting device, includes:
forming a first multilayer body including a first substrate, a
first semiconductor layer provided on the first substrate and
having a light emitting layer, and a first metal layer provided on
the first semiconductor layer; forming a second multilayer body
including a second substrate having a thermal expansion coefficient
different from a thermal expansion coefficient of the first
substrate, and a second metal layer provided on the second
substrate; a first bonding step configured to heat the first metal
layer and the second metal layer being in contact with each other;
removing the first substrate after the first bonding step; and a
second bonding step configured to perform, after the removing,
heating at a temperature higher than a temperature of the first
bonding step.
Inventors: |
Akaike; Yasuhiko;
(Kanagawa-ken, JP) ; Saeki; Ryo; (Fukuoka-ken,
JP) ; Natsume; Yoshinori; (Kanagawa-ken, JP) |
Assignee: |
KABUSHIKI KAISHA TOSHIBA
Tokyo
JP
|
Family ID: |
42102994 |
Appl. No.: |
13/343810 |
Filed: |
January 5, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12544353 |
Aug 20, 2009 |
8110451 |
|
|
13343810 |
|
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Current U.S.
Class: |
257/98 ; 257/103;
257/E33.066 |
Current CPC
Class: |
H01L 33/0093
20200501 |
Class at
Publication: |
257/98 ; 257/103;
257/E33.066 |
International
Class: |
H01L 33/60 20100101
H01L033/60 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 10, 2009 |
JP |
2009-028908 |
Claims
1. A light emitting device comprising: a semiconductor layer
including a light emitting layer, the semiconductor layer having a
first surface and a second surface provided on a side opposed to
the first surface; a conductive substrate; a bonded metal layer
including a first Ti film provided on the first surface of the
semiconductor layer, a first Pt film provided on the first Ti film,
a first Au film provided on the first Pt film, and a solder layer
provided between the first Au film and the conductive substrate,
the solder layer including one of AuSn, AuGe, AuSi, and In; and an
electrode provided on the second surface of the semiconductor
layer.
2. The light emitting device according to claim 1, wherein the
bonded metal layer further includes a second Ti film provided on
the conductive substrate, a second Pt film provided on the second
Ti film and a second Au film provided between the second Pt film
and the solder layer.
3. The light emitting device according to claim 1, wherein the
conductive substrate includes one of Si, Ge, and SiC.
4. The light emitting device according to claim 1, wherein the
light emitting layer InGaAlP In.sub.x(Ga.sub.yAl.sub.1-y).sub.1-xP
(0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1).
5. The light emitting device according to claim 1, wherein the
light emitting layer includes In.sub.xGa.sub.yAl.sub.1-x-yN
(0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.1).
6. The light emitting device according to claim 5, further
comprising: a transparent electrode between the bonded metal layer
and the semiconductor layer.
7. The light emitting device according to claim 1, wherein a light
emitted from the light emitting layer is reflected by the bonded
metal layer.
8. A light emitting device comprising: a semiconductor layer having
a light emitting layer, the semiconductor layer having a first
surface and a second surface provided on a side opposed to the
first surface; a conductive substrate; a bonded metal layer
including a first Ni film provided on the first surface of the
semiconductor layer, a first Au film provided in the first Ni film
and a solder layer provided between the first Au layer and the
conductive substrate, the solder layer including one of AuSn, AuGe,
AuSi, and In; and an electrode provided on the second surface of
the semiconductor layer.
9. The light emitting device according to claim 8, wherein the
bonded metal layer further includes a second Ti film provided on
the conductive substrate, a second Pt film provided on the second
Ti film and a second Au film provided between the second Pt film
and the solder layer.
10. The light emitting device according to claim 8, wherein the
conductive substrate is one of Si, Ge, and SiC.
11. The light emitting device according to claim 8, wherein the
light emitting layer is made of InGaAlP
In.sub.x(Ga.sub.yAl.sub.1-y).sub.1-xP (0.ltoreq.x.ltoreq.1,
0.ltoreq.y.ltoreq.1).
12. The light emitting device according to claim 8, wherein the
light emitting layer is made of In.sub.xGa.sub.yAl.sub.1-x-yN
(0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.1).
13. The light emitting device according to claim 12, further
comprising: a transparent electrode provided between the bonded
metal layer and the semiconductor layer.
14. The light emitting device according to claim 8, wherein a light
emitted from the light emitting layer is reflected by the bonded
metal layer.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Division of application Ser. No.
12/544,353 filed Aug. 20, 2009; the entire contents of which are
incorporated herein by reference.
[0002] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No.
2009-028908, filed on Feb. 10, 2009; the entire contents of which
are incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0003] 1. Field of the Invention
[0004] This invention relates to a method for manufacturing a light
emitting device.
[0005] 2. Background Art
[0006] Semiconductor light emitting devices capable of emitting
visible light including blue to red light can be widely used in
such applications as illumination lamps, displays, and traffic
signals. Such light emitting devices with high brightness can find
wider application in light sources replacing fluorescent lamps and
incandescent bulbs. Furthermore, reduction of operating current
facilitates achieving low power consumption.
[0007] Here, in a light emitting device which uses a substrate made
of e.g. GaAs having a bandgap wavelength of generally 870 nm,
visible light emitted from the light emitting device and having
emission wavelengths of 700 nm or less is absorbed by the
substrate, causing the problem of decreased brightness.
[0008] If the substrate is made of e.g. GaP having a bandgap
wavelength of generally 550 nm, optical absorption by the substrate
can be reduced for visible light having longer wavelengths, which
facilitates increasing the brightness. However, the lattice
constant of InGaAlP-based semiconductors capable of emitting
visible light in the wavelength range from yellow-green to red
differs from the lattice constant of GaP by as large as several %,
which makes it difficult to directly form an InGaAlP-based light
emitting layer with low crystal defect density on a GaP
substrate.
[0009] JP-A 2005-019424 (Kokai) discloses a technique related to a
method for manufacturing a light emitting device by wafer bonding.
In this technique, a substrate and a light emitting layer section
are bonded via a metal layer. Here, a diffusion blocking
semiconductor layer is provided to prevent metal diffusion from the
metal layer into the light emitting layer, thereby preventing
decrease in light emission characteristics.
[0010] However, it is difficult to achieve good wafer bonding
characteristics while preventing cracking of the substrate in the
heat treatment step for substrate lamination.
SUMMARY OF THE INVENTION
[0011] According to an aspect of the invention, there is provided a
method for manufacturing a light emitting device, including:
forming a first multilayer body including a first substrate, a
first semiconductor layer provided on the first substrate and
having a light emitting layer, and a first metal layer provided on
the first semiconductor layer; forming a second multilayer body
including a second substrate having a thermal expansion coefficient
different from a thermal expansion coefficient of the first
substrate, and a second metal layer provided on the second
substrate; a first bonding step configured to heat the first metal
layer and the second metal layer being in contact with each other;
removing the first substrate after the first bonding step; and a
second bonding step configured to perform, after the removing,
heating at a temperature higher than a temperature of the first
bonding step.
[0012] According to an aspect of the invention, there is provided a
method for manufacturing a light emitting device, including:
forming a first multilayer body including a first substrate made of
one of GaAs, GaP, and SiC, a first semiconductor layer provided on
the first substrate and having a light emitting layer, and a first
metal layer provided on the first semiconductor layer; forming a
second multilayer body including a second substrate having a
thermal expansion coefficient different from a thermal expansion
coefficient of the first substrate and made of one of Si, Ge, and
SiC, and a second metal layer provided on the second substrate; a
first bonding step configured to heat the first metal layer and the
second metal layer being in contact with each other; removing the
first substrate after the first bonding step; and a second bonding
step configured to perform, after the removing, heating at a
temperature higher than a temperature of the first bonding
step.
[0013] According to an aspect of the invention, there is provided a
method for manufacturing a light emitting device, including:
forming a first multilayer body including a first substrate made of
sapphire, a first semiconductor layer provided on the first
substrate and having a light emitting layer, and a first metal
layer provided on the first semiconductor layer; forming a second
multilayer body including a second substrate having a thermal
expansion coefficient different from a thermal expansion
coefficient of the first substrate and made of one of Si, Ge, and
SiC, and a second metal layer provided on the second substrate; a
first bonding step configured to heat the first metal layer and the
second metal layer being in contact with each other; removing the
first substrate after the first bonding step; and a second bonding
step configured to perform, after the removing, heating at a
temperature higher than a temperature of the first bonding
step.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 is a schematic cross-sectional view of a light
emitting device according to a first embodiment;
[0015] FIGS. 2A to 2D are process cross-sectional views of a method
for manufacturing the light emitting device according to the first
embodiment;
[0016] FIGS. 3A to 3D are process cross-sectional views of a method
for manufacturing a light emitting device according to a
comparative example;
[0017] FIGS. 4A to 4D are process cross-sectional views showing a
method for manufacturing a light emitting device according to a
second embodiment
[0018] FIGS. 5A to 5D are process cross-sectional views of a light
emitting device according to a variation of the second
embodiment;
[0019] FIG. 6 is a schematic cross-sectional view of a light
emitting device according to a third embodiment;
[0020] FIGS. 7A to 7D are process cross-sectional views showing a
method for manufacturing the light emitting device of the third
embodiment; and
[0021] FIG. 8 is a schematic cross-sectional view showing a light
emitting device according to a variation of the third
embodiment.
DETAILED DESCRIPTION OF THE INVENTION
[0022] Embodiments of the invention will now be described with
reference to the drawings.
[0023] FIG. 1 is a schematic cross-sectional view of a light
emitting device according to a first embodiment of the
invention.
[0024] A second substrate 40 is illustratively made of p-type Si
and has a thickness of e.g. 250 .mu.m. However, the substrate is
not limited thereto, but can be made of other materials such as Ge
and SiC, and the conductivity type can be n-type. The second
substrate 40 and a second metal layer 42 provided thereon
constitute a second multilayer body 43.
[0025] A semiconductor layer 46 made of a compound semiconductor is
bonded to the second multilayer body 43 via a first metal layer 44.
That is, the first metal layer 44 and the second metal layer 42 are
bonded at a bonding interface 47. Here, the first metal layer 44
and the second metal layer 42 can be illustratively made of Ti, Pt,
and Au stacked in this order. In this case, the uppermost Au films
are bonded to each other.
[0026] An upper electrode 50 is provided on the semiconductor layer
46, and a lower electrode 52 is provided on the second substrate
40. The semiconductor layer 46 includes a light emitting layer 46a,
from which light is emitted upward and laterally. Light emitted
downward from the light emitting layer 46a can be reflected upward
or laterally by the first metal layer 44, which serves to increase
the brightness. If the light emitting layer 46a is made of
InGaAlP-based semiconductors, the emitted light can be in the
wavelength range of visible light.
[0027] In this specification, the InGaAlP-based semiconductor
refers to a material represented by a composition formula
In.sub.x(Ga.sub.yAl.sub.1-y).sub.1-xP (where 0.ltoreq.x.ltoreq.1,
0.ltoreq.y.ltoreq.1), and also includes those doped with p-type or
n-type impurities.
[0028] FIGS. 2A to 2D are process cross-sectional views of a method
for manufacturing the light emitting device according to the first
embodiment.
[0029] As shown in FIG. 2A, on a first substrate 48 illustratively
made of n-type GaAs, a semiconductor layer 46 including InGaAlP or
the like is formed by MOCVD (metal organic chemical vapor
deposition) method or MBE (molecular beam epitaxy) method, for
instance, and a first metal layer 44 is further formed to construct
a first multilayer body 49. If the light emitting layer 46a is made
of InGaAlP-based semiconductors, it can emit visible light in the
wavelength range from yellow-green to red. Thus, the semiconductor
layer 46 illustratively made of InGaAlP is readily lattice-matched
with GaAs, and hence can be formed as a good crystal. In contrast,
it is difficult to directly form an InGaAlP semiconductor layer on
a Si substrate, which has a different lattice constant.
[0030] The source material used in the MOCVD method can
illustratively be a metal-organic compound such as TMG
(trimethylgallium), TMA (trimethylaluminum), and TMI
(trimethylindium), or a hydride gas such as arsine (AsH.sub.3) and
phosphine (PH.sub.3). A p-type impurity can illustratively be Zn
derived from DMZ (dimethylzinc), and an n-type impurity can
illustratively be Si.
[0031] On the other hand, as shown in FIG. 2B, on the second
substrate 40 illustratively made of p-type Si, a second metal layer
42 is formed by vacuum evaporation method or the like to construct
a second multilayer body 43.
[0032] Next, as a first bonding step, the first metal layer 44 and
the second metal layer 42 are brought into contact at room
temperature, for instance, and heated for generally 30 minutes in
the temperature range of 100-200.degree. C., for instance. Thus, as
shown in FIG. 2C, the first multilayer body 49 and the second
multilayer body 43 are bonded at the bonding interface 47.
[0033] Here, the lamination is preferably performed in a vacuum or
under low pressure, for instance, because air and the like at the
lamination interface can be excluded to achieve closer contact.
Furthermore, heating in an inert gas atmosphere or vacuum is more
preferable because oxidation of the first and second metal layers
44, 42 can be prevented.
[0034] Subsequently, as shown in FIG. 2D, the first substrate 48 is
removed by at least one of mechanical polishing method and we
etching method. Here, the first substrate 48 can be completely
removed or partly left. Subsequently, as a second bonding step,
heating is performed for generally 30 minutes in the temperature
range of 300-500.degree. C., for instance, which is higher than the
temperature of the first bonding step. The second bonding step is
preferably performed in an inert gas atmosphere because oxidation
of the first and second metal layer 44, 42 can be prevented. More
preferably, the first and second metal layers 44, 42 have a
multilayer structure of Ti/Pt/Au, and the first and second bonding
steps are performed under a load, because the Au-Au bonding
strength can be increased.
[0035] Subsequently, an upper electrode 50 and a lower electrode 52
are formed, and ohmic contact is formed between the upper electrode
50 and the semiconductor layer 46, and between the lower electrode
52 and the second substrate 40. Here, the sintering temperature for
forming ohmic contact is 350.degree. C., for instance, which is
lower than the temperature of the second bonding step. In this
case, a stable ohmic contact can be formed between the upper
electrode 50 and the semiconductor layer 46, and between the lower
electrode 52 and the second substrate 40.
[0036] Alternatively, after the process of removing the first
substrate 48, an upper electrode 50 and a lower electrode 52 are
formed, and a second bonding step for heating to a temperature
higher than the temperature of the first bonding step can be
performed. In this case, if the temperature of the second bonding
step is in the range of 350-500.degree. C., for instance, ohmic
contact can be formed while increasing the bonding strength. Thus,
the light emitting device shown in FIG. 1 is completed.
[0037] Furthermore, in the first bonding step, if the Au or other
metal surface to be bonded is irradiated with ions, plasma and the
like, unwanted oxide film, organic matter and the like can be
removed, and active bonds of atoms can be exposed to the metal
surface. That is, the energy required for coupling can be reduced.
This is more preferable because it facilitates bonding at a lower
temperature. Bonding under an ultrahigh vacuum after the surface
activation may allow the wafer to be bonded at a temperature near
normal temperature.
[0038] In this manufacturing method, the first bonding step is
performed at a lower temperature than the second bonding step.
Here, it is easy to ensure bonding strength enough to avoid
delamination of the semiconductor layer 46, which is an epitaxial
layer, in the process of removing the first substrate 48.
Furthermore, the second bonding step is performed after the first
substrate 48 is removed. The absence of the second bonding step may
result in failing to ensure bonding strength enough to withstand
the chip separation process. In this embodiment, the second bonding
step performed at a higher temperature than the temperature of the
first bonding step further increases the bonding strength between
the first metal layer 44 and the second metal layer 42, and can
prevent chip breakage during the chip separation and assembly
process.
[0039] Furthermore, wafer cracks, dislocations and the like are
reduced at the bonding interface 47, which facilitates achieving
device characteristics with improved brightness and reliability.
Here, a higher temperature is required to bond a semiconductor
layer to a substrate made of a semiconductor, sapphire or the like
without the intermediary of a metal layer.
[0040] If the second substrate 40 is made of Si, the assembly
process can achieve high mass productivity because the substrate
has higher strength than that made of GaAs and the like and
facilitates chip separation.
[0041] FIGS. 3A to 3D are process cross-sectional views of a method
for manufacturing a light emitting device according to a
comparative example.
[0042] As shown in FIG. 3A, on a first substrate 148 illustratively
made of n-type GaAs, a semiconductor layer 146 illustratively made
of InGaAlP-based compound semiconductors and a first metal layer
144 are formed by vacuum evaporation method or the like. The first
metal layer 144 can be illustratively made of Ti, Pt, and Au
stacked in this order from the semiconductor layer 146 side.
[0043] On the other hand, as shown in FIG. 3B, on a second
substrate 140 illustratively made of p-type Si, a second metal
layer 142 illustratively made of Ti/Pt/Au is formed by vacuum
evaporation method or the like.
[0044] Next, as a bonding step, the first and second metal layers
144, 142 at the surface of these wafers are laminated in a vacuum,
for instance, and heated for generally 30 minutes in the
temperature range of 300-500.degree. C. in an inert gas atmosphere,
for instance. Thus, the two wafers are bonded at a bonding
interface 147 (FIG. 3C).
[0045] Subsequently, as shown in FIG. 3D, the first substrate 148
is removed by at least one of mechanical polishing and we etching.
Here, the first substrate 148 can be completely removed or partly
left. Subsequently, an upper electrode and a lower electrode are
formed, and separation into chips is performed.
[0046] By way of example, the first substrate 148 was made of GaAs
with a diameter of 3 inches and a thickness of 300 .mu.m, and the
second substrate 140 was made of Si with a diameter of inches and a
thickness of 250 .mu.m. Multilayer bodies including these
substrates were laminated together in a vacuum, and heat-treated at
generally 300.degree. C. under a load. A warpage of the bonded
wafer was measured using a dial gauge. This warpage was 100 .mu.m
or less, indicating avoidance of cracks. However, several ten voids
having a diameter of several mm occurred.
[0047] In general, because of the large thermal expansion
coefficient difference between Si and GaAs, a large stress acts
between the two substrates during the bonding step including
heating. Hence, dislocations and cracks are likely to occur in
regions 140a, 148a shown by dotted lines in FIG. 3C. Dislocations
and cracks decrease the mechanical strength of the chip, and hence
are likely to result in chip breakage during the assembly process.
Furthermore, if crystal defects due to dislocations and cracks
spread to a light emitting layer 146a, they may decrease the
optical output and the like. If the two substrates made of
different materials are bonded at a lower heating temperature, the
stress can be reduced, but the bonding strength is decreased. Thus,
there is a limit to the decrease of the temperature.
[0048] Thus, in the comparative example, the bonding temperature is
decreased to reduce stress, thereby avoiding cracks. However, voids
are difficult to avoid. Typically, to bond wafers made of
semiconductors or dielectrics containing no metal, they are heated
to e.g. 600.degree. C. or more, which is higher than the
temperature for bonding via a metal layer. In this case, impurity
atoms such as Zn penetrate into the light emitting layer and the
like, and degrade light emission characteristics. In contrast, this
embodiment is preferable because the wafers are bonded at
600.degree. C. or less via a metal layer, preventing
characteristics degradation. Furthermore, Si can be used for the
substrate, which facilitates increasing the mechanical strength.
Hence, the mass productivity of the assembly process can be
increased.
[0049] FIGS. 4A to 4D are process cross-sectional views showing a
method for manufacturing a light emitting device according to a
second embodiment.
[0050] More specifically, the first metal layer 44 of the first
multilayer body 49 includes a first metal film 44a illustratively
made of Ti/Pt/Au, a second metal film 44b illustratively made of
AuSn, and a third metal film 44c illustratively made of Au (FIG.
4A). The third metal film 44c can be omitted, but is preferably
provided because it can prevent evaporation of Sn and the like
during the lamination process in a vacuum or under low pressure,
thereby preventing contamination in the vacuum apparatus.
[0051] In FIG. 4A, in the case where the second metal film 44b is
made of AuSn eutectic solder (the melting point, which is minimized
near generally 270.degree. C., can be controlled by its composition
ratio), if the temperature of the first bonding step (FIG. 4C) is
e.g. 250.degree. C., which is not higher than the melting point,
then the bonding strength between the first multilayer body 49 and
the second multilayer body 43 is enough to withstand etching of the
first substrate 48 made of GaAs. In this case, the first substrate
48 is removed using, for instance, a liquid mixture of sulfuric
acid and hydrogen peroxide solution, or ammonia and hydrogen
peroxide solution (FIG. 4D).
[0052] Subsequently, when the AuSn eutectic solder is melted at
e.g. 300.degree. C., the third metal film 44c illustratively made
of a thin Au film is melted together with the AuSn eutectic solder,
or bonded to Au constituting the second metal layer 42. Thus, the
bonding interface 47 can achieve high bonding strength free from
voids. Here, if the first and second bonding steps are performed in
an inert gas atmosphere, oxidation of the first metal layer 44 and
the second metal layer 42 can be prevented. Furthermore, the
bonding strength can be further increased by applying a load. In
this embodiment, in the temperature decreasing process of the
second bonding step, the first substrate 48 illustratively made of
GaAs has already been removed. Hence, the second substrate 40
illustratively made of Si undergoes no stress from GaAs, which
facilitates avoiding cracks and dislocations.
[0053] By way of example, the second substrate 40 was a Si
substrate with a diameter of 3 inches and a thickness of 250 .mu.m,
and the first substrate 48 was a GaAs substrate with a diameter of
3 inches and a thickness of 300 .mu.m. The first multilayer body 49
and the second multilayer body 43 were bonded by heating to
300.degree. C. in the laminated state. A warpage of the wafer
measured in this case was as large as 300-400 .mu.m, and cracks
occurred in the Si wafer. This is attributed to the stress due to
the thermal expansion coefficient difference, caused by the
temperature difference between room temperature and approximately
300.degree. C. at which AuSn is melted. That is, in the bonding
process using AuSn eutectic solder, atoms at the bonding interface
are fixed at the melting point or a slightly lower temperature,
increasing the stress in the process of cooling to room
temperature. Thus, it was found that this bonding process is more
likely to cause cracks than Au--Au bonding.
[0054] The thermal expansion coefficient (or thermal expansion
rate) at 300 K is 2.4.times.10.sup.-6/K for Si, which is smaller
than 6.4.times.10.sup.-6/K for GaAs and 14.2.times.10.sup.-6/K for
Au. Hence, a compressive stress is applied to the Si substrate in
the temperature decreasing process from the melting point to room
temperature. That is, if the temperature of bonded substrates made
of different materials is decreased from generally 300.degree. C.
to room temperature, a compressive stress is applied to the
substrate having a smaller thermal expansion coefficient, which is
undesirable because cracks are likely to occur therein. In this
embodiment, the first bonding step is performed at a temperature
lower than generally 270.degree. C., which is the melting point of
AuSn solder. Then, after the GaAs substrate is removed to allow
stress reduction, the temperature is increased to above the melting
point. Hence, while the stress applied to the Si substrate is
reduced, melting of AuSn solder prevents voids, increasing the
bonding strength.
[0055] Examples of the eutectic solder include AuGe (melting point
generally 356.degree. C.) and AuSi (melting point generally
370.degree. C.), and examples of the low-melting-point metal
include In (melting point generally 156.degree. C.). These metals
can also be used.
[0056] Light directed downward from the light emitting layer can be
reflected upward or laterally by the first metal film 44a, which
facilitates increasing the brightness.
[0057] FIGS. 5A to 5D are process cross-sectional views of a light
emitting device according to a variation of the second
embodiment.
[0058] As shown in FIG. 5A, the first metal layer 44 on the
semiconductor layer 46 has a structure of, for instance, Ti/Pt/Au
stacked in this order. On the other hand, as shown in FIG. 5B, the
metal layer 42 on the second substrate 40 includes a first metal
film 42a illustratively made of Ti/Pt/Au, a second metal film 42b
illustratively made of AuSn, and a third metal film 42c
illustratively made of Au. As shown in FIG. 5C, these are laminated
and bonded at a bonding interface 57 by the first bonding step.
Subsequently, the first substrate 48 is removed, and the second
bonding step is further performed. As in this variation, a solder
layer illustratively made of AuSn can be provided on the second
substrate 40 side. Furthermore, a solder layer illustratively made
of AuSn can be provided on both the first and second substrates 48,
40 to bond them together.
[0059] FIG. 6 is a schematic cross-sectional view of a light
emitting device according to a third embodiment.
[0060] FIGS. 7A to 7D are process cross-sectional views showing a
method for manufacturing the light emitting device of the third
embodiment.
[0061] A second multilayer body 63 includes a second substrate 60
illustratively made of p-type Si and a second metal layer 62. A
first multilayer body 69 includes a first substrate 68
illustratively made of sapphire, a semiconductor layer 66 provided
on the first substrate 68, and a first metal layer 64. The second
metal layer 62 and the first metal layer 64 are bonded at a bonding
interface 67. The semiconductor layer 66 is made of InGaAlN-based
semiconductors, and a light emitting layer 66a can emit light
having a wavelength near blue, for instance.
[0062] In this specification, the InGaAlN-based semiconductor
refers to a semiconductor represented by a composition formula
In.sub.xGa.sub.yAl.sub.1-x-N (0.ltoreq.x.ltoreq.1,
0.ltoreq.y.ltoreq.1, x+y.ltoreq.1), and also includes those doped
with impurities for controlling the conductivity type.
[0063] An upper electrode 70 is provided on an upper surface of the
semiconductor layer 66, and a lower electrode 72 is provided on a
rear surface of the second substrate 60. Light from the light
emitting layer 66a can be emitted laterally, as well as from the
upper surface of the semiconductor layer 66 outside the upper
electrode 70.
[0064] In FIG. 7A, the semiconductor layer 66 is formed by MOCVD or
MBE method, for instance, on the first substrate 68 illustratively
made of sapphire with a thickness of e.g. 250 .mu.m. The material
used in the MOCVD method is a metal-organic compound such as TMG,
TMA, and TMI, or a gas such as ammonia. The p-type impurity can be
Mg, and the n-type impurity can be Si. The Mg source can be
bis(cyclopentadienyl)magnesium, and the Si source can be
silane.
[0065] In the semiconductor layer 66, a buffer layer made of AlN is
grown on the first substrate 68 at generally 500.degree. C.
Continuously, at generally 1000.degree. C., a GaN current block
layer 66d (0.2 .mu.m thick), an n-type GaN contact layer 66c (0.5
.mu.m thick), an n-type GaN current diffusion layer (1.5 .mu.m
thick), an n-type InGaAlN cladding layer (0.6 .mu.m thick), the
light emitting layer 66a (0.1 .mu.m thick), a p-type InGaAlN
cladding layer (0.3 .mu.m thick), and a p-type GaN contact layer
are formed by crystal growth in this order. The composition of the
light emitting layer 66a is suitably controlled so that the
emission wavelength falls within the range from blue to green. The
first metal layer 64 illustratively made of Ti/Pt/Au, Ni/Au, Al or
an alloy thereof, or Ag or an alloy thereof is formed by vacuum
evaporation or the like
[0066] On the other hand, the second substrate 60 illustratively
made of p-type Si is formed by vacuum evaporation method or the
like, and includes the second metal layer 62 illustratively made of
Ti/Pt/Au (FIG. 7B). The second metal layer 62 and the first metal
layer 64 are bonded at the bonding interface 67 by the first
bonding step in which they are laminated at room temperature, for
instance, and heated for 30 minutes at 100-200.degree. C. in an
inert gas (FIG. 7C).
[0067] Subsequently, the first substrate 68 is removed using at
least one of laser lift-off method and mechanical polishing method.
In the laser lift-off method, by irradiation with laser light from
the first substrate 68 side, GaN constituting the semiconductor
layer 66 is decomposed into Ga and N at the interface between the
first substrate 68 and the semiconductor layer 66. The decomposed N
is vaporized and increases its volume, allowing the first substrate
68 side to be removed (FIG. 7D). Subsequently, as the second
bonding step, heating is performed in an inert gas atmosphere for
30 minutes at 400-500.degree. C., which is higher than the
temperature of the first bonding step. More preferably, the first
and second bonding steps are performed under a load, because the
bonding strength can be increased. Furthermore, the upper electrode
70 and the lower electrode 72 are formed, and separation into chips
is performed. Thus, the light emitting device of FIG. 6 is
completed. Here, the upper electrode 70 includes a bonding
electrode 70a and a thin wire electrode 70b.
[0068] The bonding electrode 70a and the thin wire electrode 70b
are electrically connected, allowing a current to be injected into
the light emitting layer 66a through a bonding wire via the bonding
electrode 70a and the thin wire electrode 70b. On the other hand,
the GaN current block layer 66d is provided between the bonding
electrode 70a and the n-type GaN contact layer 66c, and hence no
current is injected therethrough. Hence, light emission is
prevented in the portion of the light emitting layer 66a below the
bonding electrode 70a. Thus, decrease in light extraction
efficiency due to light blocking by the bonding electrode 70a can
be prevented. Furthermore, light emitted downward from the light
emitting layer 66a can be reflected upward or laterally by the
first metal layer 64, which facilitates increasing the
brightness.
[0069] According to this embodiment, the temperature of the first
bonding step is as low as in the range of 100-200.degree. C. This
serves to reduce the stress applied to the substrate in the
temperature decreasing process, thereby avoiding cracks and
dislocations. Furthermore, in the second bonding step, the first
substrate 68 illustratively made of sapphire has been removed. This
serves to reduce voids and achieve high bonding strength while
avoiding cracks and dislocations in the temperature decreasing
process after bonding at a higher temperature. Thus, the
reliability of the light emitting device is improved. In this
embodiment, if the second substrate 60 is made of Si, chip
separation and the assembly process subsequent thereto are made
easier than those for the chip including a substrate made of
sapphire or GaN (for which the wafer diameter is difficult to
increase). Thus, the mass productivity of blue-green light emitting
devices can be increased.
[0070] FIG. 8 is a schematic cross-sectional view showing a light
emitting device according to a variation of the third
embodiment.
[0071] A transparent electrode 65 made of ITO (indium in oxide) or
ZnO and being conductive is provided between first metal layer 64
and the semiconductor layer 66. If the first metal layer 64
includes Au, AuGe and the like, it is likely to form an alloy layer
with the semiconductor layer 66. This alloy layer absorbs emitted
light and decreases the optical reflectance. In contrast, if the
transparent electrode 65 is provided, it can prevent alloying and
the decrease of optical reflectance associated therewith, and
facilitates maintaining high light extraction efficiency.
[0072] The first to third embodiments can provide methods for
manufacturing a light emitting device with reduced stress at the
wafer bonding interface and improved brightness and reliability.
These manufacturing methods can achieve high mass productivity in
providing a light emitting device being applicable to illumination
devices, display devices and the like, and having high brightness
and high reliability.
[0073] The embodiments of the invention have been described with
reference to the drawings. However, the invention is not limited to
these embodiments. Those skilled in the art can variously modify
the material, size, shape, layout, bonding condition and the like
of the substrate, semiconductor layer, metal layer, multilayer
body, electrode and the like constituting the embodiments of the
invention, and such modifications are also encompassed within the
scope of the invention unless they depart from the spirit of the
invention.
* * * * *