U.S. patent application number 13/225806 was filed with the patent office on 2012-03-22 for semiconductor device and manufacturing method thereof.
This patent application is currently assigned to Kabushiki Kaisha Toshiba. Invention is credited to Hirokazu Ezawa, Tatsuo MIGITA, Soichi Yamashita.
Application Number | 20120068334 13/225806 |
Document ID | / |
Family ID | 45817012 |
Filed Date | 2012-03-22 |
United States Patent
Application |
20120068334 |
Kind Code |
A1 |
MIGITA; Tatsuo ; et
al. |
March 22, 2012 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Abstract
Semiconductor devices of embodiments include a plurality of
solder bumps electrically connected on a plurality of electrode
pads disposed on a semiconductor substrate in parallel at a pitch
of 40 .mu.m or less via under bump metals. The ratio of the
diameter (the top diameter) of the portion of each solder bump most
away from the semiconductor substrate and the diameter (the bottom
diameter) of the bottom side of each solder bump is 1:1 to 1:4.
Inventors: |
MIGITA; Tatsuo; (Oita,
JP) ; Ezawa; Hirokazu; (Tokyo, JP) ;
Yamashita; Soichi; (Kanagawa, JP) |
Assignee: |
Kabushiki Kaisha Toshiba
Tokyo
JP
|
Family ID: |
45817012 |
Appl. No.: |
13/225806 |
Filed: |
September 6, 2011 |
Current U.S.
Class: |
257/737 ;
257/E21.159; 257/E21.16; 257/E21.174; 257/E23.023; 438/613 |
Current CPC
Class: |
H01L 2224/0401 20130101;
H01L 2224/05666 20130101; H01L 2224/0345 20130101; H01L 2224/13147
20130101; H01L 2924/01079 20130101; H01L 2924/01005 20130101; H01L
2224/13082 20130101; H01L 2924/01013 20130101; H01L 2224/11906
20130101; H01L 2224/13111 20130101; H01L 2924/01029 20130101; H01L
2224/13005 20130101; H01L 2224/05572 20130101; H01L 2924/01082
20130101; H01L 2224/03831 20130101; H01L 24/05 20130101; H01L
2224/05647 20130101; H01L 2224/13144 20130101; H01L 2924/01024
20130101; H01L 2224/13116 20130101; H01L 2224/11472 20130101; H01L
2224/03452 20130101; H01L 2224/0361 20130101; H01L 2924/00014
20130101; H01L 2224/03912 20130101; H01L 2224/11462 20130101; H01L
2924/014 20130101; H01L 24/11 20130101; H01L 2224/13155 20130101;
H01L 2924/01006 20130101; H01L 2924/01047 20130101; H01L 24/13
20130101; H01L 2224/0346 20130101; H01L 2224/13017 20130101; H01L
2224/13139 20130101; H01L 2224/13083 20130101; H01L 2224/131
20130101; H01L 2924/01033 20130101; H01L 2224/13171 20130101; H01L
24/03 20130101; H01L 2924/00014 20130101; H01L 2224/05552 20130101;
H01L 2224/13005 20130101; H01L 2924/206 20130101; H01L 2224/13005
20130101; H01L 2924/207 20130101 |
Class at
Publication: |
257/737 ;
438/613; 257/E23.023; 257/E21.159; 257/E21.16; 257/E21.174 |
International
Class: |
H01L 23/488 20060101
H01L023/488; H01L 21/285 20060101 H01L021/285; H01L 21/288 20060101
H01L021/288; H01L 21/283 20060101 H01L021/283 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 22, 2010 |
JP |
2010-212781 |
Claims
1. A semiconductor device comprising a plurality of solder bumps
electrically connected on a plurality of electrode pads disposed on
a semiconductor substrate in parallel at a pitch of 40 .mu.m or
less via under bump metals, wherein the ratio of the diameter (the
top diameter) of the portion of each solder bump most away from the
semiconductor substrate and the diameter (the bottom diameter) of
the bottom side of each solder bump is 1:1 to 1:4.
2. The semiconductor device according to claim 1, wherein the ratio
is 1:1 to 1:3.
3. The semiconductor device according to claim 1, wherein the
solder bumps are composed of Ni, Cu, Au, Sn, Ag, Pb, Cr, or a
combination thereof.
4. The semiconductor device according to claim 1, wherein the under
bump metals are composed of a Cu film or a laminated film of Cu and
Ti.
5. The semiconductor device according to claim 1, wherein the angle
between a bottom side and a side surface of each solder bump with
respect to a side of each solder bump is 45.degree. to
90.degree..
6. The semiconductor device according to claim 2, wherein the
solder bumps are composed of Ni, Cu, Au, Sn, Ag, Pb, Cr, or a
combination thereof.
7. The semiconductor device according to claim 2, wherein the under
bump metals are composed of a Cu film or a laminated film of Cu and
Ti.
8. A semiconductor device comprising a plurality of solder bumps
electrically connected on a plurality of electrode pads disposed on
a semiconductor substrate in parallel at a pitch of 40 .mu.m or
less via under bump metals, wherein the angle between a bottom side
and a side surface of each solder bump with respect to a side of
each solder bump is 45.degree. to 90.degree..
9. The semiconductor device according to claim 8, wherein the angle
is 55.degree. to 90.degree..
10. The semiconductor device according to claim 8, wherein the
solder bumps are composed of Ni, Cu, Au, Sn, Ag, Pb, Cr, or a
combination thereof.
11. The semiconductor device according to claim 8, wherein the
under bump metals are composed of a Cu film or a laminated film of
Cu and Ti.
12. The semiconductor device according to claim 8, wherein the
ratio of the diameter (the top diameter) of the portion of each
solder bump most away from the semiconductor substrate and the
diameter (the bottom diameter) of the bottom side of each solder
bump is 1:1 to 1:4.
13. The semiconductor device according to claim 9, wherein the
solder bumps are composed of Ni, Cu, Au, Sn, Ag, Pb, Cr, or a
combination thereof.
14. The semiconductor device according to claim 9, wherein the
under bump metals are composed of a Cu film or a laminated film of
Cu and Ti.
15. A manufacturing method of a semiconductor device comprising:
forming a resist film on a semiconductor substrate having a
plurality of electrode pads formed on the semiconductor substrate
at a pitch of 40 .mu.m or less and under bump metals laminated on
the electrode pads; and performing exposure to the surface of the
resist film at a first focus value larger than a focus value at
which a straight shape is exposed to the surface of the resist film
in a vertical direction.
16. The manufacturing method of the semiconductor device according
to claim 15, wherein exposure is further performed by a second
focus value at which a straight shape is exposed in a width larger
than the diameter (the top diameter) of the portion, which is most
away from the semiconductor substrate, of the bump-shaped portion
of the resist film which is made soluble by the exposure as well as
in a width smaller than the diameter (the bottom diameter) of a
bottom surface of the bump-shaped portion.
17. The manufacturing method of the semiconductor device according
to claim 15, wherein the resist film is composed of a positive
resist.
18. The manufacturing method of the semiconductor device according
to claim 15, wherein the resist film is composed of a negative
resist.
19. The manufacturing method of the semiconductor device according
to claim 15, wherein the under bump metals are formed by
sputtering, CVD, ALD (Atomic Layer Deposition), or plating.
20. The manufacturing method of the semiconductor device according
to claim 15, wherein the under bump metals are composed of a Cu
film or a laminated layer of Cu and Ti.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No.
2010-212781, filed on Sep. 22, 2010; the entire contents of which
are incorporated herein by reference.
FIELD
[0002] The embodiments relate in general to semiconductor devices
and manufacturing methods thereof.
BACKGROUND
[0003] Recently, it is required to improve an operation speed of a
device and to increase a capacity of a memory to achieve high
integration and sophisticated function of a semiconductor device.
In some devices, a chip, in which logic and a large capacity DRAM
are packaged by Chip on Chip (CoC) connection, has been developed
in place of one chip eDRAM.
[0004] When a minute bump for CoC connection is formed, a bump
having a high aspect ratio may be required in consideration of CoC
properties. At the time, a solder bump is formed via a pillar of
Cu, Ni, Au, and the like. In the CoC connection, the bump pitch is
recently more miniaturized and is becoming to 40 .mu.m,
30.mu.m.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1A is a view illustrating a semiconductor device and a
manufacturing method of the semiconductor device of a first
embodiment;
[0006] FIG. 1B is a view illustrating the semiconductor device and
a manufacturing method of the semiconductor device of the first
embodiment;
[0007] FIG. 1C is a view illustrating the semiconductor device and
a manufacturing method of the semiconductor device of the first
embodiment;
[0008] FIG. 2A is a view illustrating a semiconductor device and a
manufacturing method of the semiconductor device of a second
embodiment;
[0009] FIG. 2B is a view illustrating the semiconductor device and
a manufacturing method of the semiconductor device of the second
embodiment;
[0010] FIG. 2C is a view illustrating the semiconductor device and
a manufacturing method of the semiconductor device of the second
embodiment;
[0011] FIG. 3A is a view illustrating a semiconductor device and a
manufacturing method of the semiconductor device of a third
embodiment; and
[0012] FIG. 3B is a view illustrating the semiconductor device and
a manufacturing method of the semiconductor device of the third
embodiment.
DETAILED DESCRIPTION
[0013] Semiconductor devices of embodiments include a plurality of
solder bumps electrically connected on a plurality of electrode
pads disposed on a semiconductor substrate in parallel at a pitch
of 40 .mu.m or less via under bump metals. The ratio of the
diameter (the top diameter) of the portion of each solder bump most
away from the semiconductor substrate and the diameter (the bottom
diameter) of the bottom side of each solder bump is 1:1 to 1:4.
[0014] The semiconductor devices and manufacturing methods of the
semiconductor devices according to the embodiments will be
explained below in detail referring to the accompanying drawings.
The present invention is not limited to the following
embodiments.
First Embodiment
[0015] FIG. 1A to FIG. 1C are sectional views illustrating a
semiconductor device and a manufacturing method of the
semiconductor device of a first embodiment. In the embodiment, a
minute solder bump is formed on a silicon substrate made by a
conventional LSI forming technology.
[0016] First, as illustrated in FIG. 1A, for example, an aluminum
electrode pad 2 is formed on a substrate 1, and further, for
example, a SiN film 3 is formed as a passivation film so as to
cover an edge of the electrode pad 2 and the substrate 1 while
exposing a center of the electrode pad 2. In the embodiment, the
electrode pad 2 and not illustrated adjacent electrode pads are
disposed in parallel at an interval of 40 .mu.m or less. Cu films
or laminated films of Cu and Ti and the like are formed on the
electrode pads as under bump metals 4 (UBMs) of solder bumps using
sputtering, CVD, ALD (Atomic Layer Deposition), plating, and the
like.
[0017] Cu is used as uppermost layers of the under bump metals 4
and the uppermost layers function as power distribution layers in a
plating process which is a subsequent process. Next, to form a bump
pattern, a photosensitive resist 5 is applied, exposure is
performed using a photomask 6 as a mask, and a desired bump pattern
is formed using a photolithography technology. As the
photosensitive resist 5, for example, a negative resist is
used.
[0018] Since a special opening shape can be formed by mainly and
largely changing a focus condition in exposure of the
photolithography technology from an ordinary straight shape (FIG.
1A), a bump pattern is formed by setting a focus value to 16 .mu.m
(FIG. 1B).
[0019] Next, a Ni pillar 7 is formed by precipitating Ni on the
under bump metal 4 of a bump pattern portion by electrolytic
plating and subsequently a solder 8 is precipitated by electrolytic
plating. Subsequently, the photosensitive resist 5 is removed by a
stripping liquid, and the under bump metal 4 is removed by etching.
Thereafter, the solder 8 is melted and condensed again by a reflow
process, and a solder bump 8' is formed. At the time, since the
exposure is performed by greatly changing the photolithography
process from a focus value of 8 .mu.m at which the ordinary
straight shape can be obtained to the focus value of 16 .mu.m, a
bump shape which spreads toward a bottom can be obtained as
illustrated in FIG. 10.
[0020] In general, a shift of a focus value in exposure from a
small value to large value causes the angle between a bottom
surface and a side surface of a bump shape with respect to a bump
side (a of FIG. 10) to change from a large value (90.degree. or
more) to a small value (90.degree. or less). Even if any of a
negative resist and a positive resist is selected, a focus value at
which .alpha.=90.degree. is achieved is determined depending on the
resist. The focus value is a focus value at which exposure is
performed in the straight shape. In the embodiment, as illustrated
in FIG. 10, exposure is performed at a focus value larger than a
focus value at which the straight shape is exposed so that
.alpha.<90.degree. is achieved.
[0021] In a bump bottom diameter B at the time, a shape, which is
3.6 .mu.m larger than 20 .mu.m at which the straight shape is
exposed, is obtained. When the solder bump 8' having the above
shape is formed, since the bottom area of an interface between the
pillar 7 under the solder 8 and the under bump metal 4 of a ground
layer can be kept about 40 larger, an intimate contact property can
be improved. Further, since the top diameter T of the solder bump
8' can be kept smaller than the bottom diameter B with respect to
the bump pitch of 40 .mu.m or less, a short-circuit risk to an
adjacent bump can be reduced. As a result, even if a bump is
greatly miniaturized, a solder bump having high reliability can be
formed. As illustrated in FIGS. 1B and 1C, the top diameter T is
the diameter of the portion of the solder bump 8' most away from
the semiconductor the substrate 1, and the bottom diameter B is the
diameter of a bottom side of the solder bump 8' illustrated in FIG.
1B and FIG. 10 likewise.
[0022] Note that it is preferable that the ratio T:B of the top
diameter T and the bottom diameter B is 1:1 to 1:4 or the angle
.alpha. between the bottom surface and the side surface of the bump
shape with respect to the bump side is
45.degree.<.alpha.<90.degree.. Further, it is more preferable
that both the ratio T:B and the angle a are within the above
ranges.
[0023] This is because when the ratio T:B is out of the range and B
becomes smaller than T or when a is out of the range and becomes
90.degree. or more, the bottom diameter B of the bump becomes thin
and the intimate contact area of the bump with the interface of the
ground layer becomes small. Further, this is because a problem
arises in that the top diameter T of the bump becomes relatively
too large and a short-circuit risk increases when the bump is
connected.
[0024] Further, this is because when B becomes four times as large
as T or when a becomes 45.degree. or less on the contrary, since
the bottom diameter B of the bump becomes too thick, a
short-circuit risk to an adjacent bump becomes high. Further, this
is because a problem arises in that since the top diameter T of the
bump becomes too small, it becomes very difficult to connect the
bump.
[0025] Further, when a case, in which it is intended to increase
the degree of integration of the bump, and the like are also taken
into consideration, in order to reduce the short-circuit risk to
the adjacent bump, it is more preferable that the ratio T:B of the
top diameter T and the bottom diameter B is 1:1 to 1:3 or the angle
a between the bottom surface and the side surface of the bump shape
with respect to the bump side is
55.degree.<.alpha.<90.degree.. Further, it is more preferable
that both the ratio T:B and the angle a are within the above
range.
[0026] As described above, when the bump of the embodiment is
formed on a semiconductor substrate on which a semiconductor device
is formed, even if the pitch of the bump is formed in an
ultra-minute pattern, an intimate contact property of the bump with
the ground layer can be improved, a short-circuit risk between
solder bumps can be reduced, and the reliability of a semiconductor
package can be improved.
Second Embodiment
[0027] In a second embodiment of the invention, for example, a
positive resist is used as a photosensitive resist 5, a focus value
in exposure of a photolithography process is set to 28 .mu.m (a
first focus value) which is larger than the focus value in the
first embodiment (FIG. 2A), and further the focus value is set a
focus value (a second focus value) of 8 .mu.m of an ordinarily used
condition, and exposure is performed twice (FIG. 2B) to widen an
opening of an upper portion of a resist. With the operation, in
comparison with the first embodiment, a solder bump 8', in which
the bottom area of an interface between the solder bump 8'and an
under bump metal 4 of a ground layer is larger, can be formed.
[0028] As a bump bottom diameter B at the time, a shape 16.0 .mu.m
larger than 20 .mu.m when a straight shape is exposed can be
obtained. As illustrated in FIG. 2C, when the solder bump 8' having
the above shape is formed, since the bottom area of the interface
between the solder bump 8'and the under bump metal 4 of the ground
layer can be kept about 220, larger, an intimate contact property
can be more improved.
Third Embodiment
[0029] Different from the first embodiment in which Ni is
precipitated in the electrolytic plating on the under bump metal 4
of the bump pattern portion opened by the photoresist process, the
third embodiment of the invention precipitates Cu on an under bump
metal 4 of a bump pattern portion and forms a Cu pillar 9. Further,
a Ni pillar 7 is formed on the Cu pillar 9, and subsequently a
photosensitive resist is removed by a stripping liquid, and the
under bump metal 4 is removed by etching (not illustrated).
[0030] Since Cu is used as a plating power distribution material of
the under bump metal 4 here, when the Cu under bump metal 4 is
etched, the Cu pillar 9 is also etched at the same time (FIG. 3A).
In the focus value of 8 .mu.m in the ordinary lithography, although
the Cu pillar portion 9 becomes thin and an intimate contact
property is deteriorated, in the embodiment, a focus value is set
to 16 .mu.m which is larger than an ordinary value. Accordingly, a
solder bump having a large bottom diameter can be formed (FIG. 3B).
Further, top and bottom shapes can be arbitrarily set by performing
exposure twice as in the second embodiment.
[0031] Note that, in the embodiments, although explanation is made
using any resist of the negative and positive resists as the
photosensitive resist 5, any resist of the negative and positive
resists may be used in the respective embodiments. As described
above, even if any resist of the negative and positive resists is
selected, a focus value in which .alpha.=90.degree. is achieved is
determined depending on the resist. Further, a tendency that a
shift of a focus value in exposure from a small value to large
value causes the angle between a bottom surface and a side surface
of a bump shape with respect to a bump side (.alpha. of FIG. 1C) to
change from a large value (90.degree. or more) to a small value
(90.degree. or less) is also common. Accordingly, the same
advantage as that described above can be obtained by setting the
focus value larger than the value at the time of the straight
shape. Although a rubber resist, a resin resist such as an acrylic
resist, and the like may be used as the negative resist and a resin
resist such as a novolac resin resist and the like may be used as
the positive resist, the negative and positive resists are not
limited thereto. Further, Ni, Cu, Au, Sn, Ag, Pb, Cr or a
combination thereof can be optionally selected as material for
configuring the solder bump such as the solder, the pillar and the
like.
[0032] While certain embodiments have been described, these
embodiments have been presented by way of example only, and are not
intended to limit the scope of the inventions. Indeed, the novel
embodiments described herein may be embodied in a variety of other
forms; furthermore, various omissions, substitutions and changes in
the form of the embodiments described herein may be made without
departing from the spirit of the inventions. The accompanying
claims and their equivalents are intended to cover such forms or
modifications as would fall within the scope and spirit of the
inventions.
* * * * *