U.S. patent application number 13/052011 was filed with the patent office on 2012-03-22 for semiconductor device and method for manufacturing the same.
This patent application is currently assigned to Kabushiki Kaisha Toshiba. Invention is credited to Mitsuhiko KITAGAWA.
Application Number | 20120068222 13/052011 |
Document ID | / |
Family ID | 45816950 |
Filed Date | 2012-03-22 |
United States Patent
Application |
20120068222 |
Kind Code |
A1 |
KITAGAWA; Mitsuhiko |
March 22, 2012 |
Semiconductor Device and Method for Manufacturing the Same
Abstract
According to an embodiment, a semiconductor device includes a
first trench being provided in an N.sup.+ substrate. An N layer, an
N.sup.- layer, a P layer, and an N.sup.+ layer are formed in a
stacked manner to cover the first trench. The semiconductor device
includes second and third trenches. The P.sup.+ layer is formed to
cover the second trench. The trench gates are formed to cover the
third trenches.
Inventors: |
KITAGAWA; Mitsuhiko; (Tokyo,
JP) |
Assignee: |
Kabushiki Kaisha Toshiba
Tokyo
JP
|
Family ID: |
45816950 |
Appl. No.: |
13/052011 |
Filed: |
March 18, 2011 |
Current U.S.
Class: |
257/139 ;
257/334; 257/E21.41; 257/E29.197; 257/E29.262; 438/270 |
Current CPC
Class: |
H01L 29/0626 20130101;
H01L 29/0696 20130101; H01L 29/1095 20130101; H01L 29/7393
20130101; H01L 29/7821 20130101; H01L 29/4236 20130101; H01L
29/66704 20130101; H01L 29/7825 20130101 |
Class at
Publication: |
257/139 ;
257/334; 438/270; 257/E29.262; 257/E29.197; 257/E21.41 |
International
Class: |
H01L 29/739 20060101
H01L029/739; H01L 21/336 20060101 H01L021/336; H01L 29/78 20060101
H01L029/78 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 21, 2010 |
JP |
P2010-211036 |
Claims
1. A semiconductor device, comprising: a first trench provided in a
semiconductor substrate of a first conductivity type; a first
semiconductor layer of the first conductivity type having an
impurity concentration lower than that of the semiconductor
substrate, a second semiconductor layer of a second conductivity
type, and a third semiconductor layer of the first conductivity
type having an impurity concentration higher than that of the first
semiconductor layer, the first to third semiconductor layers being
formed in a stacked manner to cover the first trench; a second
trench provided in the third semiconductor layer in such a manner
that the second trench at least partially penetrates the third
semiconductor layer to expose the second semiconductor layer in a
vertical direction relative to a plane of the semiconductor
substrate, and at least partially penetrates the third
semiconductor layer to expose the second semiconductor layer in a
horizontal direction relative to the plane of the semiconductor
substrate; a fourth semiconductor layer of the second conductivity
type having an impurity concentration higher than that of the
second semiconductor layer, the fourth semiconductor layer being
formed to cover the second trench; third trenches arranged between
portions of the fourth semiconductor layer in such a manner as to
be spaced apart from the side of the fourth semiconductor layer,
the third trenches being provided so that each of the trenches
penetrates the third semiconductor layer to expose the second
semiconductor layer or penetrates the third and second
semiconductor layers to expose the first semiconductor layer in the
vertical direction relative to the plane of the semiconductor
substrate, and so that each of the trenches penetrates the second
semiconductor layer to expose the first semiconductor layer on one
end or penetrates the second and first semiconductor layers to
expose the semiconductor substrate on one end and to expose the
third semiconductor layer on the other end in the horizontal
direction relative to the plane of the semiconductor substrate; and
trench gates formed to cover the third trenches, each trench gate
including a gate insulating film and a gate electrode film formed
in a stacked manner.
2. The semiconductor device according to claim 1, wherein the third
and fourth semiconductor layers are connected to a source
electrode, the semiconductor substrate is connected to a drain
electrode, and when the semiconductor device is turned on, a
channel layer is formed on the side of the trench gate in the
vertical direction of the semiconductor substrate, and carriers
flow through the channel layer from a source toward a drain.
3. The semiconductor device according to claim 1, wherein carriers
are generated in the first semiconductor layer near the interface
of the first and second semiconductor layers when the semiconductor
device breaks down, the carriers are withdrawn to a source
electrode through the second and fourth semiconductor layers.
4. The semiconductor device according to claim 1, wherein the
semiconductor substrate is a first drain layer of an N type having
a high impurity concentration, the first semiconductor layer is a
second drain layer of the N type having an impurity concentration
lower than that of the first drain, and the third semiconductor
layer is a source layer of the N type having a high impurity
concentration.
5. The semiconductor device according to claim 1, wherein the
semiconductor substrate is a first drain layer of an N type having
a high impurity concentration, the first semiconductor layer
includes a second drain layer and a drift layer, the second drain
layer of the N type has an impurity concentration lower than that
of the first drain layer, the drift layer of the N type having an
impurity concentration lower than that of the second drain layer,
and the third semiconductor layer is a source layer of the N type
having a high impurity concentration.
6. The semiconductor device according to claim 1, wherein the
fourth semiconductor layer is a carrier withdrawal layer to
withdraw carriers generated by the breakdown of the semiconductor
device.
7. The semiconductor device according to claim 1, wherein the
semiconductor device is an N-channel power MOS transistor.
8. A semiconductor device, comprising: a first trench provided in a
semiconductor substrate of a first conductivity type; a first
semiconductor layer of a second conductivity type, a second
semiconductor layer of the second conductivity type having an
impurity concentration lower than that of the first semiconductor
layer, a third semiconductor layer of the first conductivity type
having an impurity concentration lower than that of the
semiconductor substrate, and a fourth semiconductor layer of the
second conductivity type having an impurity concentration higher
than that of the second semiconductor layer, the first to fourth
semiconductor layers being formed in a stacked manner to cover the
first trench; a second trench provided in the fourth semiconductor
layer in such a manner that the second trench at least partially
penetrates the fourth semiconductor layer to expose the third
semiconductor layer in a vertical direction relative to a plane of
the semiconductor substrate, and at least partially penetrates the
fourth semiconductor layer to expose the third semiconductor layer
in a horizontal direction relative to the plane of the
semiconductor substrate; a fifth semiconductor layer of the first
conductivity type having an impurity concentration higher than that
of the third semiconductor layer, the fifth semiconductor layer
being formed to cover the second trench; third trenches arranged
between portions of the fifth semiconductor layer in such a manner
as to be spaced apart from the side of the fifth semiconductor
layer, the third trenches being provided so that each of the
trenches penetrates the fourth semiconductor layer to expose the
third semiconductor layer or penetrates the fourth and third
semiconductor layers to expose the second semiconductor layer in
the vertical direction relative to the plane of the semiconductor
substrate, and so that each of the trenches penetrates the third
semiconductor layer to expose the second semiconductor layer on one
end or penetrates the third and second semiconductor layers to
expose the first semiconductor layer on one end and to expose the
fourth semiconductor layer on the other end in the horizontal
direction relative to the plane of the semiconductor substrate; and
trench gates formed to cover the third trenches, each trench gate
including a gate insulating film and a gate electrode film formed
in a stacked manner.
9. The semiconductor device according to claim 8, wherein the
fourth and fifth semiconductor layers are connected to an emitter
electrode, the semiconductor substrate is connected to a collector
electrode, and when the semiconductor device is turned on, a
channel layer is formed on the side of the trench gate in the
vertical direction of the semiconductor substrate, and carriers
flow through the channel layer from an emitter toward a
collector.
10. The semiconductor device according to claim 8, wherein carriers
are generated in the second semiconductor layer near the interface
of the second and third semiconductor layers when the semiconductor
device breaks down, the carriers are withdrawn to the emitter
electrode through the third and fifth semiconductor layers.
11. The semiconductor device according to claim 8, wherein the
semiconductor substrate is a first collector layer of a P type
having a high impurity concentration, the first semiconductor layer
is a second collector layer of an N type having a high impurity
concentration, the second semiconductor layer includes a buffer
layer and a first base layer, the buffer layer of the N type has an
impurity concentration lower than that of the second collector
layer, the first base layer of the N type has an impurity
concentration lower than that of the first collector layer, the
third semiconductor layer is a second base layer of the P type
having an impurity concentration lower than that of the first
collector layer, and the fourth semiconductor layer is an emitter
layer of the N type having a high impurity concentration.
12. The semiconductor device according to claim 8, wherein the
fifth semiconductor layer is a carrier withdrawal layer to withdraw
carriers generated by the breakdown of the semiconductor
device.
13. A method for manufacturing a semiconductor device, comprising
the steps of: forming a first trench in a semiconductor substrate
of a first conductivity type, the first trench having a
quadrangular prism shape elongated in a horizontal direction
relative to a plane of the semiconductor substrate; forming a first
semiconductor layer of the first conductivity type having an
impurity concentration lower than that of the semiconductor
substrate, a second semiconductor layer of a second conductivity
type, and a third semiconductor layer of the first conductivity
type having an impurity concentration higher than that of the first
semiconductor layer, the first to third semiconductor layers being
formed in a stacked manner to cover the first trench; polishing the
first to third semiconductor layers to be flattened so that the
semiconductor substrate is exposed; forming a second trench in the
third semiconductor layer in such a manner that the second trench
at least partially penetrates the third semiconductor layer to
expose the second semiconductor layer in a vertical direction
relative to the plane of the semiconductor substrate, and at least
partially penetrates the third semiconductor layer to expose the
second semiconductor layer in the horizontal direction relative to
the plane of the semiconductor substrate; forming a fourth
semiconductor layer of the second conductivity type having an
impurity concentration higher than that of the second semiconductor
layer, the fourth semiconductor layer being formed to cover the
second trench; polishing the fourth semiconductor layer to be
flattened so that the semiconductor substrate is exposed; forming
third trenches in such a manner that the third trenches are spaced
apart from the fourth semiconductor layer, the third trenches being
formed so that each of the trenches penetrates the third and second
semiconductor layers formed in the stacked manner to expose the
first semiconductor layer in the vertical direction relative to the
plane of the semiconductor substrate, and so that each of the
trenches penetrates the second semiconductor layer to expose the
first semiconductor layer or the semiconductor substrate on one end
and to expose the third semiconductor layer on the other end in the
horizontal direction relative to the plane of the semiconductor
substrate; and forming trench gates in such a manner that the
trench gates cover the third trenches, each trench gate including a
gate insulating film and a gate electrode film.
14. The method for manufacturing a semiconductor device, according
to claim 13, wherein the first to fourth semiconductor layers are
formed using an epitaxial method.
15. The method for manufacturing a semiconductor device, according
to claim 13, wherein the polishing for flattening is performed
using a CMP method.
16. The method for manufacturing a semiconductor device, according
to claim 13, wherein the first to third trenches are formed using
an RIE method.
17. The method according to claim 13, wherein the semiconductor
device is an N-channel power MOS transistor.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No.
2010-211036, filed on Sep. 21, 2010, the entire contents of which
are incorporated herein by reference.
FIELD
[0002] Embodiments described herein relate to a semiconductor
device and a method for manufacturing the same.
BACKGROUND
[0003] There have been developed a number of trench-type power MOS
transistors and IGBTs (Insulated Gate Bipolar Transistors) capable
of on-resistance reduction, speed-up, cell pitch reduction and the
like. To reduce the substrate resistance or to increase the density
of integration of unit elements, there have also been proposed
three-dimensional trench gate power MOS transistors and IGBTs
structured three-dimensionally.
[0004] The conventionally proposed three-dimensional trench gate
power MOS transistor structure or three-dimensional trench gate
IGBT structure requires complex control of internal carriers
attributable to the complicated element structure of the
three-dimensional trench gate. As a result, there arise problems
such as reduction in breakdown tolerance of the element, reduction
in an ASO (Area of Safe Operation: secondary breakdown tolerance of
the element) and difficult control of a threshold voltage
(Vth).
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1 is a plan view showing a trench power MOS transistor
according to a first embodiment;
[0006] FIG. 2 is a cross-sectional perspective view of region 1 in
FIG. 1;
[0007] FIG. 3 is a cross-sectional view taken along the line A-A in
FIG. 1;
[0008] FIG. 4 is a view explaining a flow of carriers during
operation of the trench power MOS transistor according to the first
embodiment;
[0009] FIG. 5 is a view explaining a flow of carriers induced by
breakdown of the trench power MOS transistor according to the first
embodiment;
[0010] FIG. 6 is a cross-sectional view showing a step of
manufacturing a trench power MOS transistor according to the first
embodiment;
[0011] FIG. 7 is a cross-sectional view showing a step of
manufacturing a trench power MOS transistor according to the first
embodiment;
[0012] FIG. 8 is a cross-sectional view showing a step of
manufacturing a trench power MOS transistor according to the first
embodiment;
[0013] FIG. 9 is a cross-sectional view showing a step of
manufacturing a trench power MOS transistor according to the first
embodiment;
[0014] FIG. 10 is a cross-sectional view showing a step of
manufacturing a trench power MOS transistor according to the first
embodiment;
[0015] FIG. 11 is a cross-sectional view showing a step of
manufacturing a trench power MOS transistor according to the first
embodiment;
[0016] FIG. 12 is a cross-sectional perspective view showing a step
of manufacturing a trench power MOS transistor according to the
first embodiment;
[0017] FIG. 13 is a plan view showing a modification of the trench
power MOS transistor according to the first embodiment;
[0018] FIG. 14 is a cross-sectional perspective view showing a
trench power MOS transistor according to a second embodiment;
[0019] FIG. 15 is a cross-sectional perspective view showing a
trench power MOS transistor according to a third embodiment;
[0020] FIG. 16 is a cross-sectional view showing a step of
manufacturing a trench power MOS transistor according to the third
embodiment; and
[0021] FIG. 17 is a cross-sectional perspective view showing an
IGBT according to a fourth embodiment.
DETAILED DESCRIPTION
[0022] According to an embodiment, a semiconductor device includes
a first trench, a first semiconductor layer, a second semiconductor
layer, a third semiconductor layer, a second trench, a fourth
semiconductor layer, third trenches and trench gates. The first
trench is provided in a semiconductor substrate of a first
conductivity type. The first semiconductor layer is of the first
conductivity type and has an impurity concentration lower than that
of the semiconductor substrate. The second semiconductor layer is
of a second conductivity type. The third semiconductor layer is of
the first conductivity type and has an impurity concentration
higher than that of the first semiconductor layer. The first to
third semiconductor layers are formed in a stacked manner to cover
the first trench. The second trench is provided in the third
semiconductor layer in such a manner that the second trench at
least partially penetrates the third semiconductor layer to expose
the second semiconductor layer in a vertical direction relative to
a plane of the semiconductor substrate, and at least partially
penetrates the third semiconductor layer to expose the second
semiconductor layer in a horizontal direction relative to the plane
of the semiconductor substrate. The fourth semiconductor layer is
of the second conductivity type, has an impurity concentration
higher than that of the second semiconductor layer, and is formed
to cover the second trench. The third trenches are arranged between
portions of the fourth semiconductor layer in such a manner as to
be spaced apart from the side of the fourth semiconductor layer.
The third trenches are provided so that each of the trenches
penetrates the third semiconductor layer to expose the second
semiconductor layer or penetrates the third and second
semiconductor layers to expose the first semiconductor layer in the
vertical direction relative to the plane of the semiconductor
substrate, and so that each of the trenches penetrates the second
semiconductor layer to expose the first semiconductor layer on one
end or penetrates the second and first semiconductor layers to
expose the semiconductor substrate on one end and to expose the
third semiconductor layer on the other end in the horizontal
direction relative to the plane of the semiconductor substrate. The
trench gates are formed to cover the third trenches, and each of
trench gates includes a gate insulating film and a gate electrode
film which are formed in a stacked manner.
[0023] According to another embodiment, a method for manufacturing
a semiconductor device includes first to eighth steps. The first
step is to form a first trench in a semiconductor substrate of a
first conductivity type, the first trench having a quadrangular
prism shape elongated in a horizontal direction relative to a plane
of the semiconductor substrate. The second step is to form a first
semiconductor layer of the first conductivity type having an
impurity concentration lower than that of the semiconductor
substrate, a second semiconductor layer of a second conductivity
type, and a third semiconductor layer of the first conductivity
type having an impurity concentration higher than that of the first
semiconductor layer, the first to third semiconductor layers being
formed in a stacked manner to cover the first trench. The third
step is to polish the first to third semiconductor layers to be
flattened so that the semiconductor substrate is exposed. The
fourth step is to form a second trench in the third semiconductor
layer so that the second trench at least partially penetrates the
third semiconductor layer to expose the second semiconductor layer
in a vertical direction relative to the plane of the semiconductor
substrate, and so that the second trench at least partially
penetrates the third semiconductor layer to expose the second
semiconductor layer in the horizontal direction relative to the
plane of the semiconductor substrate. The fifth step is to form a
fourth semiconductor layer of the second conductivity type having
an impurity concentration higher than that of the second
semiconductor layer so that the fourth semiconductor layer covers
the second trench. The sixth step is to polish the fourth
semiconductor layer to be flattened so that the semiconductor
substrate is exposed. The seventh step is to form third trenches to
be spaced apart from the fourth semiconductor layer so that each of
the trenches penetrates the third and second semiconductor layers
formed in the stacked manner to expose the first semiconductor
layer in the vertical direction relative to the plane of the
semiconductor substrate, and so that each of the trenches
penetrates the second semiconductor layer to expose the first
semiconductor layer or the semiconductor substrate on one end and
to expose the third semiconductor layer on the other end in the
horizontal direction relative to the plane of the semiconductor
substrate. The eighth step is to form trench gates each including a
gate insulating film and a gate electrode film so that the trench
gates cover the third trenches.
[0024] Further embodiments are described below with reference to
the drawings. In the drawings, the same reference numerals denote
the same or similar portions.
[0025] A semiconductor device and a method for manufacturing the
same according to a first embodiment are described with reference
to the drawings. FIG. 1 is a plan view showing a trench power MOS
transistor. FIG. 2 is a cross-sectional perspective view of region
1 in FIG. 1. FIG. 3 is a cross-sectional view taken along the line
A-A in FIG. 1. In the embodiment, a P.sup.+ carrier withdrawal
layer is provided around a trench gate to improve breakdown
tolerance of a three-dimensional N-channel trench power MOS
transistor to be operated in a lateral direction.
[0026] As shown in FIG. 1, in a trench power MOS transistor 80, a
stripe-shaped trench 21 (a first trench) is provided in an N.sup.+
substrate 1 that is a drain layer. An N layer 2 that is an N drain
layer, an N.sup.- layer 3 that is an N.sup.- drift layer, a P layer
4 to serve as a channel unit of the trench power MOS transistor 80,
and an N.sup.+ layer 5 that is a source layer are formed in a
stacked manner to cover the trench 21.
[0027] In the N.sup.+ layer 5, a trench 22 (a second trench) is
provided to partially penetrate the N.sup.+ layer 5 and reach the P
layer 4. The trench 22 is formed to be wider at end portions of
trench gates 11 (at left and right ends in FIG. 1) than in other
portions in such a manner as to reach the P layer 4. In the trench
22, a P.sup.+ layer 6 is provided to cover the trench 22.
[0028] In the P layer 4, rectangular trenches 23 (third trenches)
are provided to penetrate the P layer 4 and to have one ends reach
the N.sup.- layer 3 and the other ends reach the N.sup.+ layer 5.
The multiple trenches 23 (the third trenches) are arranged in two
parallel rows in a horizontal direction relative to the N.sup.+
substrate 1 that is the drain layer. The P.sup.+ layer 6 is
arranged between and on the side of the trenches 23 in such a
manner as to be spaced apart from the trenches 23 by the N.sup.+
layer 5.
[0029] In each of the trenches 23, the trench gate 11 including a
gate insulating film 7 and a gate electrode 8 is provided to cover
the trench 23.
[0030] The N.sup.+ layer 5 is provided between the trench gates 11
and the P.sup.+ layer 6. The P.sup.+ layer 6 is provided between
the N.sup.+ layers 5 provided around the trench gates 11 and on the
lateral side of the N.sup.+ layers 5 at the end portions of the
trench gates 11 (at the left and right ends in FIG. 1).
[0031] The trench power MOS transistor 80 is a 300-V
three-dimensional N-channel trench gate power MOS transistor, for
example. Here, the P.sup.+ layer 6 functions as a P.sup.+ carrier
withdrawal layer to withdraw carriers (holes). The P.sup.+ layer 6
as the P.sup.+ carrier withdrawal layer will be described in detail
later.
[0032] As shown in FIG. 2, in the N.sup.+ substrate 1, the trench
21 is formed having a quadrangular prism shape elongated in the
horizontal direction relative to the N.sup.+ substrate 1. A drain
electrode (not shown) is provided on the opposite side to the
trench 21 in the N.sup.+ substrate 1 that is the drain layer. The
drain electrode is connected to the N.sup.+ substrate 1.
[0033] In the trench 21 (the first trench), the N layer 2, the
N.sup.- layer 3, the P layer 4 and the N.sup.+ layer 5 are formed
in a stacked manner to cover the trench 21. An impurity
concentration of the N layer 2 that is the N drain layer is high on
the side of the N.sup.+ substrate 1, for example, and is set low on
the side of the N.sup.- layer 3 that is the N.sup.- drift layer.
The N.sup.- layer 3 that is the N.sup.- drift layer has a width set
wider than that of the N layer 2, for example.
[0034] In the N.sup.+ layer 5, the trench 22 (the second trench)
having protrusion portions 24 is formed. Specifically, the
protrusion portions 24 are formed in such a manner that the
protrusion portions 24 partially penetrate the N.sup.+ layer 5 to
expose the surface of the P layer 4 in a vertical direction
relative to a plane of the N.sup.+ substrate 1, and partially
penetrate the N.sup.+ layer 5 to expose the side of the P layer 4
in the horizontal direction relative to the plane of the N.sup.+
substrate 1.
[0035] In the trench 22, the P.sup.+ layer 6 is provided to cover
the trench 22. The P.sup.+ layer 6 has a higher impurity
concentration than the P layer 4.
[0036] In the P layer 4, the trenches 23 (the third trenches)
having a quadrangular prism shape are provided, each of the
trenches 23 formed in such a manner that the trench 23 penetrates
the P layer 4 to expose the side of the N.sup.- layer 3 on one end,
and to expose the side of the N.sup.+ layer 5 on the other end in
the horizontal direction relative to the plane of the N.sup.+
substrate 1. As shown in FIG. 3, the trenches 23 are provided in
such a manner that the trenches 23 penetrate the N.sup.+ layer 5 to
expose the surface of the P layer 4 in the vertical direction
relative to the plane of the N.sup.+ substrate 1. The trenches 23
are arranged between portions of the P.sup.+ layer 6 in such a
manner as to be spaced apart from the side of the P.sup.+ layer
6.
[0037] Although the trenches 23 are provided to expose the surface
of the P layer 4 in the vertical direction relative to the plane of
the N.sup.+ substrate 1, the trenches 23 may be provided in such a
manner that the trenches 23 penetrate the N.sup.+ layer 5 and the P
layer 4 to expose the surface of the N.sup.- layer 3. Furthermore,
although the trenches 23 are provided in such a manner that the
trances 23 penetrate the P layer 4 to expose the side of the
N.sup.- layer 3 on one end in the horizontal direction relative to
the plane of the N.sup.+ substrate 1, the trenches 23 may be
provided in such a manner that the trenches 23 penetrate the P
layer 4 and the N.sup.- layer 3 to expose the side of the N layer 2
on one end.
[0038] In each of the trenches 23, the trench gate 11 including the
gate insulating film 7 and the gate electrode 8 is provided to
cover the trench 23. Here, a source electrode (not shown) is
provided on the N.sup.+ layer 5 and the P.sup.+ layer 6. The source
electrode is connected to the N.sup.+ layer 5 and the P.sup.+ layer
6.
[0039] An operation of the trench power MOS transistor is described
with reference to FIGS. 4 and 5. FIG. 4 is a view explaining a flow
of carriers during operation of the trench power MOS
transistor.
[0040] As shown in FIG. 4, the trench power MOS transistor 80 is
turned on when a higher voltage source voltage (Vdd) is applied to
the drain electrode and a "High" level signal is applied to the
trench gate 11. In this event, an inversion layer is formed in a
side portion, of the trench gate 11, in contact with the P layer 4
in the vertical direction relative to the semiconductor substrate
1. Thus, carriers flow from the source electrode to the drain
electrode. The side portion is preferably set to be a {100} plane,
for example, in which electron mobility is higher than in other
plane directions.
[0041] The P layer 4 is provided immediately below the trench gate
11. Thus, although not shown, the inversion layer is also formed
immediately below the trench gate 11. The depth of the trench gate
11 in the vertical direction is larger than the width of the trench
gate 11 in the horizontal direction with respect to the N.sup.+
substrate 1. Accordingly, there is less influence (contribution to
the drain current) of the inversion layer immediately below the
trench gate 11.
[0042] FIG. 5 is a view explaining a flow of carriers induced by
breakdown of the trench power MOS transistor.
[0043] As shown in FIG. 5, when a high voltage is applied to the
drain side of the trench power MOS transistor 80, a junction
between the N.sup.- layer 3 that is the N.sup.- drift layer and the
P layer 4 breaks down. In this event, carriers are generated in the
side portion of the trench gate 11 (in the N.sup.- layer 3 near the
junction) in the vertical direction relative to the N.sup.+
substrate 1.
[0044] The holes which are the carriers generated by the breakdown
are discharged from the source electrode 11 after flowing in the
horizontal direction relative to the N.sup.+ substrate 1 from the P
layer 4 to the P.sup.+ layer 6 that is the P.sup.+ carrier
withdrawal layer for the protrusion portions 24, and then to the
source electrode.
[0045] As described above, the carriers generated by the breakdown
are quickly discharged from the source electrode through the
P.sup.+ layer 6. As a result, operation of a parasitic npn bipolar
transistor (the N.sup.- layer 3 side is a collector, the P layer 4
is a base, and the N.sup.+ layer 5 side is an emitter) can be
significantly suppressed. Therefore, reduction in an output
breakdown voltage (avalanche tolerance) is suppressed, thereby
enabling a high output breakdown voltage (avalanche tolerance) to
be secured.
[0046] As a result, reduction in breakdown tolerance of the trench
power MOS transistor 80 can be prevented. Moreover, reduction in an
ASO (Area of Safe Operation: secondary breakdown tolerance of the
element) of the trench power MOS transistor 80 can be prevented.
Furthermore, carriers not required for the operation are quickly
withdrawn, thereby facilitating the control of a threshold voltage
(Vth).
[0047] Next, a method for manufacturing the trench power MOS
transistor is described with reference to FIGS. 6 to 12. FIGS. 6 to
11 are cross-sectional views showing steps of manufacturing the
trench power MOS transistor. FIG. 12 is a cross-sectional
perspective view showing a step of manufacturing the trench power
MOS transistor.
[0048] As shown in FIG. 6, first, a resist film (not shown) is
formed, using a well-known lithography technique, on an N.sup.+
substrate 1 that is a silicon substrate heavily-doped with N-type
impurities. The resist film is used as a mask to form a trench 21
in the N.sup.+ substrate 1 using an RIE (Reactive Ion Etching)
method. After the resist film is peeled off, a damaged layer and
the like are removed by carrying out post-RIE treatment.
[0049] Next, as shown in FIG. 7, an N layer 2, an N.sup.- layer 3,
a P layer 4 and an N.sup.+ layer 5 are sequentially formed in a
stacked manner on the trench 21 and the N.sup.+ substrate 1 using a
silicon epitaxial growth method, for example.
[0050] For epitaxial growth of the N layer 2, a relatively low
temperature condition is preferably used, which hinders auto-doping
of the high concentration of impurities in the N.sup.+ substrate 1.
When the auto-doping occurs, the impurity concentration of the N
layer 2 on the N.sup.+ substrate 1 side is increased. Moreover, for
epitaxial growth of the N.sup.+ layer 5, a relatively low
temperature condition is preferably used, which hinders auto-doping
of the high concentration of impurities in the film. When the
auto-doping occurs, the impurity concentration of the P layer 4 on
the N.sup.+ substrate 1 side is reduced.
[0051] Subsequently, as shown in FIG. 8, the N.sup.+ layer 5, the P
layer 4, the N.sup.- layer 3 and the N layer 2 are polished to be
flattened, using a CMP (Chemical Mechanical Polishing) method, for
example, until the surface of the N.sup.+ substrate 1 is exposed.
After the CMP treatment, residues, a damaged layer and the like are
removed by carrying out post-CMP treatment.
[0052] Then, as shown in FIG. 9, a resist film (not shown) is
formed using a well-known lithography technique. The resist film is
used as a mask to form a trench 22 in the N.sup.+ substrate 5 using
the RIE method. After the resist film is removed, another resist
film (not shown) is formed again. The resist film is used as a mask
to form, using the RIE method, for example, protrusion portions 24
which penetrate the N.sup.+layer 5 to expose the surface of the P
layer 4. After the resist film is peeled off, a damaged layer and
the like are removed by carrying out post-RIE treatment.
[0053] Next, as shown in FIG. 10, a P.sup.+ layer 6 is formed on a
trench 22, the N.sup.+ layer 5, the P layer 4, the N.sup.- layer 3,
the N layer 2, and the N.sup.+ substrate 1 in such a manner as to
cover the trench 22 using the silicon epitaxial growth method, for
example.
[0054] Thereafter, as shown in FIG. 11, the P.sup.+ layer 6 is
polished to be flattened, using the CMP method, for example, until
the surface of the N.sup.+ substrate 1 is exposed. After the CMP
treatment, residues, a damaged layer and the like are removed by
carrying out post-CMP treatment.
[0055] Then, as shown in FIG. 12, a resist film (not shown) is
formed using a well-known lithography technique. The resist film is
used as a mask to form, using the RIE method, for example, trenches
23 in the P layer 4 so that each of the trenches penetrates the P
layer 4 to expose the side of the N.sup.- layer 3 on one end and to
expose the side of the N.sup.+ layer 5 on the other end in the
horizontal direction relative to the N.sup.+ substrate 1, and so
that an end portion of each of the trenches penetrates the N.sup.+
layer 5 to expose the surface of the P layer 4 in the vertical
direction relative to the N.sup.+ substrate 1. After the resist
film is peeled off, a damaged layer and the like are removed by
carrying out post-RIE treatment.
[0056] The subsequent steps of forming trench gates, insulating
films, contacts, metal wires, and the like are performed using
well-known techniques, thus completing a trench power MOS
transistor 80.
[0057] As described above, in the semiconductor device and the
method for manufacturing the same according to the embodiment, the
trench 21 is provided in the N.sup.+ substrate 1. In the trench 21,
the N layer 2, the N.sup.- layer 3, the P layer 4 and the N.sup.+
layer 5 are formed in a stacked manner to cover the trench 21. In
the N.sup.+ layer 5, the trench 22 is formed in such a manner that
the trench 22 partially penetrates the N.sup.+ layer 5 to expose
the surface of the P layer 4 in the vertical direction relative to
the N.sup.+ substrate 1, and partially penetrates the N.sup.+ layer
5 to expose the side of the P layer 4 in the horizontal direction
relative to the N.sup.+ substrate 1. In the trench 22, the P.sup.+
layer 6 is provided to cover the trench 22. The trenches 23
arranged between portions of the P.sup.+ layers 6 in such a manner
as to be spaced apart from the side of the P.sup.+ layer 6 are
provided so that each of the trenches penetrates the N.sup.+ layer
5 to expose the surface of the P layer 4 in the vertical direction
relative to the N.sup.+ substrate 1, and so that each of the
trenches penetrates the P layer 4 to expose the side of the N.sup.-
layer 3 on one end and to expose the side of the N.sup.+ layer 5 on
the other end in the horizontal direction relative to the N.sup.+
substrate 1. In each of the trenches 23, the trench gate 11 is
provided to cover the trench 23. The P.sup.+ layer 6 quickly
withdraws, to the source electrode side, the carriers generated by
the breakdown of the trench power MOS transistor 80.
[0058] Thus, the breakdown tolerance of the trench power MOS
transistor 80 can be improved. Moreover, the ASO of the trench
power MOS transistor 80 can be increased. Furthermore, carriers not
required for the operation are quickly withdrawn, thereby
facilitating the control of the threshold voltage (Vth) of the
trench power MOS transistor 80.
[0059] Note that, in the embodiment, the P.sup.+ layer 6 is
provided around the trench gate, the P.sup.+ layer 6 being the
P.sup.+ carrier withdrawal layer to withdraw to the source side the
holes generated in a three-dimensional N-channel trench gate power
MOS transistor. In the case of a three-dimensional P-channel trench
gate power MOS transistor, an N.sup.+ layer is preferably provided
around a trench gate, the N.sup.+ layer being an N.sup.+ carrier
withdrawal layer to withdraw electrons to be generated to the
source side. While the N layer 2 and the N.sup.- layer 3 are formed
in a stacked manner on the N.sup.+ substrate, only an N layer may
be provided in the case of a low-voltage three-dimensional
N-channel trench gate power MOS transistor, for example.
[0060] While the N.sup.+ layer 5 is provided between the trench
gate 11 and the P.sup.+ layer 6 (the plan view shown in FIG. 1),
the N.sup.+ layers 5 at the end side may be partially omitted as
shown in FIG. 13 to modify the shape of a trench 22aa so that a
P.sup.+ layer 6aa comes into contact with trench gates 11, thus
obtaining a trench power MOS transistor 80a having N.sup.+ layers
5aa provided at the end side.
[0061] A semiconductor device according to a second embodiment is
described with reference to the drawings. FIG. 14 is a
cross-sectional perspective view showing a trench power MOS
transistor. In the embodiment, a trench gate of a three-dimensional
N-channel trench power MOS transistor is provided between an
N.sup.+ source layer and an N.sup.+ drain layer.
[0062] The same constituent portions as those of the first
embodiment are denoted by the same reference numerals below. In the
following, description of the same constituent portions is omitted,
and only different portions are described.
[0063] As shown in FIG. 14, a trench power MOS transistor 81 is a
300-V three-dimensional N-channel trench gate power MOS transistor,
for example.
[0064] In a P layer 4, an N.sup.- layer 3 and an N layer 2,
trenches 23a (third trenches) having a quadrangular prism shape are
provided, each of the trenches 23a formed in such a manner that the
trench 23a penetrates the P layer 4, the N.sup.- layer 3 and the N
layer 2 to expose the side of an N.sup.+ substrate 1 on one end,
and to expose the side of an N.sup.+ layer 5 on the other end in
the horizontal direction relative to the plane of the N.sup.+
substrate 1. The trenches 23a are provided so that end portions
penetrate the N.sup.+ layer 5 to expose the surface of the P layer
4 in the vertical direction relative to the plane of the N.sup.+
substrate 1. The trenches 23a are arranged between portions of the
P.sup.+ layer 6 in such a manner as to be spaced apart from the
side of the P.sup.+ layer 6. The P.sup.+ layer 6 that is a P.sup.+
carrier withdrawal layer functions in the same manner as that of
the first embodiment.
[0065] Although the trenches 23a are provided to expose the surface
of the P layer 4 in the vertical direction relative to the plane of
the N.sup.+ substrate 1, the trenches 23a may be provided in such a
manner that the trenches 23a penetrates the N.sup.+ layer 5 and the
P layer 4 to expose the surface of the N.sup.- layer 3.
[0066] In each of the trenches 23a, a trench gate 11a including a
gate insulating film 7a and a gate electrode 8a is provided to
cover the trench 23a. The trench gate 11a is provided between the
N.sup.+ layer 5 that is an N.sup.+ source layer and the N.sup.+
substrate 1 that is an N.sup.+ drain layer.
[0067] Note that the trench power MOS transistor 81 is manufactured
using the same manufacturing method as that in the first
embodiment.
[0068] As described above, in the semiconductor device according to
the embodiment, the trench 21 is provided in the N.sup.+ substrate
1. In the trench 21, the N layer 2, the N.sup.- layer 3, the P
layer 4 and the N.sup.+ layer 5 are formed in a stacked manner to
cover the trench 21. In the N.sup.+ layer 5, the trench 22 is
formed in such a manner that the trench 22 partially penetrates the
N.sup.+ layer 5 to expose the surface of the P layer 4 in the
vertical direction relative to the N.sup.+ substrate 1, and
partially penetrates the N.sup.+ layer 5 to expose the side of the
P layer 4 in the horizontal direction relative to the N.sup.+
substrate 1. In the trench 22, the P.sup.+ layer 6 is provided to
cover the trench 22. The trenches 23a arranged between portions of
the P.sup.+ layer 6 in such a manner as to be spaced apart from the
side of the P.sup.+ layer 6 are provided so that each of the
trenches penetrates the N.sup.+ layer 5 to expose the surface of
the P layer 4 in the vertical direction relative to the N.sup.+
substrate 1, and so that each of the trenches penetrates the P
layer 4, the N.sup.- layer 3 and the N layer 2 to expose the side
of the N.sup.+ substrate 1 on one end and to expose the side of the
N.sup.+ layer 5 on the other end in the horizontal direction
relative to the N+substrate 1. In each of the trenches 23a, the
trench gate 11a is provided to cover the trench 23a. The P.sup.+
layer 6 quickly withdraws, to the source electrode side, the
carriers generated by the breakdown of the trench power MOS
transistor 81.
[0069] Thus, breakdown tolerance of the trench power MOS transistor
81 can be improved. Moreover, an ASO of the trench power MOS
transistor 81 can be increased. Furthermore, carriers not required
for the operation are quickly withdrawn, thereby facilitating the
control of a threshold voltage (Vth) of the trench power MOS
transistor 81.
[0070] A semiconductor device and a method for manufacturing the
same according to a third embodiment are described with reference
to the drawings. In the embodiment, the shape of a P.sup.+ carrier
withdrawal layer is modified.
[0071] The same constituent portions as those of the first
embodiment are denoted by the same reference numerals below. In the
following, description of the same constituent portions is omitted,
and only different portions are described.
[0072] As shown in FIG. 15, a trench power MOS transistor 82 is a
300-V three-dimensional N-channel trench gate power MOS transistor,
for example.
[0073] In an N.sup.+ layer 5, a trench 22a (a second trench) is
provided, which is formed in such a manner that the trench 22a
penetrates the N.sup.+ layer 5 to expose the surface of a P layer 4
in the vertical direction relative to the plane of the N.sup.+
substrate 1, and partially penetrates the N.sup.+ layer 5 to expose
the side of the P layer 4 in the horizontal direction relative to
the plane of the N.sup.+ substrate 1.
[0074] In the trench 22a, a P.sup.+ layer 6a that is the P.sup.+
carrier withdrawal layer is provided to cover the trench 22a. The
P.sup.+ layer 6a has a higher impurity concentration than the P
layer 4. The P.sup.+ layer 6a that is the P.sup.+carrier withdrawal
layer functions in the same manner as that of the first
embodiment.
[0075] Next, a method for manufacturing the trench power MOS
transistor is described with reference to FIG. 16. FIG. 16 is a
cross-sectional view showing a step of manufacturing a trench power
MOS transistor.
[0076] As shown in FIG. 16, a resist film (not shown) is formed
using a well-known lithography technique. The resist film is used
as a mask to form the trench 22a (the second trench) in such a
manner that the trenches 22a penetrates the N.sup.+ layer 5 to
expose the surface of a P layer 4, using an RIE method. After the
resist film is peeled off, a damaged layer and the like are removed
by carrying out post-RIE treatment. The subsequent manufacturing
steps are the same as those in the first embodiment, and thus
description of such manufacturing steps is omitted.
[0077] As described above, in the semiconductor device and the
method for manufacturing the same according to the embodiment, the
trench 21 is provided in the N.sup.+ substrate 1. In the trench 21,
the N layer 2, the N.sup.- layer 3, the P layer 4 and the N.sup.+
layer 5 are formed in a stacked manner to cover the trench 21. In
the N.sup.+ layer 5, the trench 22a is formed in such a manner that
the trench 22a penetrates the N.sup.+ layer 5 to expose the surface
of the P layer 4 in the vertical direction relative to the N.sup.+
substrate 1, and partially penetrates the N.sup.+ layer 5 to expose
the side of the P layer 4 in the horizontal direction relative to
the N.sup.+ substrate 1. In the trench 22a, the P.sup.+ layer 6a is
provided to cover the trench 22a. The trenches 23 arranged between
portions of the P.sup.+ layer 6 in such a manner as to be spaced
apart from the side of the P.sup.+ layer 6 are provided so that
each of the trenches penetrates the N.sup.+ layer 5 to expose the
surface of the P layer 4 in the vertical direction relative to the
N.sup.+ substrate 1, and so that each of the trenches penetrates
the P layer 4 to expose the side of the N.sup.- layer 3 on one end
and to expose the side of the N.sup.+ layer 5 on the other end in
the horizontal direction relative to the N.sup.+ substrate 1. In
each of the trenches 23, the trench gate 11 is provided to cover
the trench 23. The P.sup.+ layer 6a quickly withdraws, to the
source electrode side, the carriers generated by the breakdown of
the trench power MOS transistor 82.
[0078] Thus, breakdown tolerance of the trench power MOS transistor
82 can be improved. Moreover, an ASO of the trench power MOS
transistor 82 can be increased. Furthermore, carriers not required
for the operation are quickly withdrawn, thereby facilitating the
control of a threshold voltage (Vth) of the trench power MOS
transistor 82.
[0079] A semiconductor device according to a fourth embodiment is
described with reference to the drawings. FIG. 17 is a
cross-sectional perspective view showing an IGBT. In the
embodiment, a P.sup.+ carrier withdrawal layer is provided around a
trench gate to improve breakdown tolerance of a three-dimensional
IGBT to be operated in a lateral direction.
[0080] The same constituent portions as those of the first
embodiment are denoted by the same reference numerals below. In the
following, description of the same constituent portions is omitted,
and only different portions are described.
[0081] As shown in FIG. 17, an IGBT (Insulated Gate Bipolar
Transistor) 90 is a three-dimensional trench gate IGBT.
[0082] In a P.sup.+ substrate 31 that is a P.sup.+ collector layer,
a trench 21a is provided having a quadrangular prism shape
elongated in the horizontal direction relative to the P.sup.+
substrate 31. A collector electrode (not shown) is provided on the
opposite side to the trench 21a in the P.sup.+ substrate 31. The
collector electrode is connected to the P.sup.+ substrate 31.
[0083] In the trench 21a (the first trench), an N.sup.+ layer 32
that is an N.sup.+ collector, an N layer 2 that is an N buffer
layer, an N.sup.- layer 3 that is an N.sup.- base layer, a P layer
4 that is a first P base layer, and an N.sup.+ layer 5 that is an
emitter layer are formed in a stacked manner to cover the trench
21a.
[0084] In an N.sup.+ layer 5, a trench 22 (a second trench) having
protrusion portions 24 is provided, which is formed in such a
manner that the trench 22 partially penetrates the N.sup.+ layer 5
to expose the surface of a P layer 4 in the vertical direction
relative to the plane of the P.sup.+ substrate 31, and partially
penetrates the N.sup.+ layer 5 to expose the side of the P layer 4
in the horizontal direction relative to the plane of the P.sup.+
substrate 31.
[0085] In the trench 22, a P.sup.+ layer 6 that is a second P base
layer is provided to cover the trench 22. The P.sup.+ layer 6 has a
higher impurity concentration than the P layer 4. The P.sup.+ layer
6 that is the P.sup.+ carrier withdrawal layer functions in the
same manner as that of the first embodiment.
[0086] In the P layer 4, trenches 23 (third trenches) having a
quadrangular prism shape are provided, each of the trenches 23
formed in such a manner that the trench 23 penetrates the P layer 4
to expose the side of the N.sup.- layer 3 on one end, and to expose
the side of the N.sup.+ layer 5 on the other end in the horizontal
direction relative to the plane of the P.sup.+ substrate 31. The
trenches 23 are provided in such a manner that the trenches 23
penetrate the N.sup.+ layer 5 to expose the surface of the P layer
4 on an end in the vertical direction relative to the plane of the
P.sup.+ substrate 31. The trenches 23 are arranged between portions
of the P.sup.+ layer 6 in such a manner as to be spaced apart from
the side of the P.sup.+ layer 6.
[0087] Note that the trenches 23 may be provided so that each of
the trenches penetrates the N.sup.+ layer 5 and the P layer 4 to
expose the surface of the N.sup.- layer 3 in the vertical direction
relative to the plane of the P.sup.+ substrate 31, and so that each
of the trenches penetrates the P layer 4 and the N.sup.- layer 3 to
expose the side of the N layer 2 on one end, or penetrates the P
layer 4, the N.sup.- layer 3 and the N layer 2 to expose the side
of the N.sup.+ layer 32 on one end and to expose the side of the
N.sup.+ layer 5 on the other end in the horizontal direction
relative to the plane of the P.sup.+ substrate 31.
[0088] In each of the trenches 23, the trench gate 11 including the
gate insulating film 7 and the gate electrode 8 is provided to
cover the trench 23. Here, an emitter electrode (not shown) is
provided on the N.sup.+ layer 5 and the P.sup.+ layer 6. The
emitter electrode is connected to the N.sup.+ layer 5 and the
P.sup.+ layer 6.
[0089] As described above, in the semiconductor device according to
the embodiment, the trench 21a is provided in the P.sup.+ substrate
1. In the trench 21a, the N.sup.+ layer 32, the N layer 2, the
N.sup.- layer 3, the P layer 4 and the N.sup.+ layer 5 are formed
in a stacked manner to cover the trench 21a. In the N.sup.+ layer
5, the trench 22 is formed in such a manner that the trench 22a
partially penetrates the N.sup.+ layer 5 to expose the surface of
the P layer 4 in the vertical direction relative to the N.sup.+
substrate 1, and partially penetrates the N.sup.+ layer 5 to expose
the side of the P layer 4 in the horizontal direction relative to
the N.sup.+ substrate 1. In the trench 22, the P.sup.+ layer 6 is
provided to cover the trench 22. The trenches 23 arranged between
portions of the P.sup.+ layer 6 in such a manner as to be spaced
apart from the side of the P.sup.+ layer 6 are provided so that
each of the trenches penetrates the N.sup.+ layer 5 to expose the
surface of the P layer 4 in the vertical direction relative to the
N.sup.+ substrate 1, and so that each of the trenches penetrates
the P layer 4 to expose the side of the N.sup.- layer 3 on one end
and to expose the side of the N.sup.+ layer 5 on the other end in
the horizontal direction relative to the N.sup.+ substrate 1. In
each of the trenches 23, the trench gate 11 is provided to cover
the trench 23. The P.sup.+ layer 6 quickly withdraws, to the
emitter electrode side, the carriers generated by the breakdown of
the IGBT 90.
[0090] Thus, breakdown tolerance of the IGBT 90 that is a
three-dimensional trench gate IGBT can be improved. Moreover, an
ASO of the IGBT 90 can be increased.
[0091] The invention is not limited to the embodiments described
above, but various modifications may be made without departing from
the spirit of the invention.
[0092] In the first to third embodiments, the source electrode is
provided on the first trench 21 and the drain electrode is provided
on the N.sup.+ substrate 1 side. Instead, the drain electrode may
be provided on the first trench 21 and the source electrode may be
provided on the N.sup.+ substrate 1 side. In such a case, the
P.sup.+ layer 6 that is the P.sup.+ carrier withdrawal layer is
preferably provided on the N.sup.+ substrate 1 side. Meanwhile, the
N layer 2 and the N.sup.- layer 3 are preferably provided on the
drain electrode side.
[0093] Furthermore, while the P.sup.+ layer is buried in the second
trench in the first to fourth embodiments, a buried metal layer, a
buried metal silicide layer, or the like may be formed instead of
the P.sup.+ layer.
[0094] While certain embodiments have been described, these
embodiments have been presented by way of example only, and are not
intend to limit the scope of the inventions. Indeed, the novel
embodiments described herein may be embodied in a variety of the
other forms; furthermore, various omissions, substitutions and
changes in the form of the embodiments described herein may be made
without departing from the spirit of the inventions. The
accompanying claims and their equivalents are intended to cover
such forms or modifications as would fall within the scope and
spirit of the inventions.
* * * * *