U.S. patent application number 12/881663 was filed with the patent office on 2012-03-15 for resolution enhancement of video stream based on spatial and temporal correlation.
This patent application is currently assigned to Advanced Micro Devices, Inc.. Invention is credited to Philip J. Rogers, Greg SADOWSKI.
Application Number | 20120066444 12/881663 |
Document ID | / |
Family ID | 44658881 |
Filed Date | 2012-03-15 |
United States Patent
Application |
20120066444 |
Kind Code |
A1 |
SADOWSKI; Greg ; et
al. |
March 15, 2012 |
Resolution Enhancement of Video Stream Based on Spatial and
Temporal Correlation
Abstract
A method, computer program product, and system are provided for
associating one or more memory buffers in a computing system with a
plurality of memory channels. The method can include associating a
first memory buffer to a first plurality of memory banks, where the
first plurality of memory banks spans over a first set of one or
more memory channels. Similarly, the method can include associating
a second memory buffer to a second plurality of memory banks, where
the second plurality of memory banks spans over a second set of one
or more memory channels. The method can also include associating a
first sequence identifier and a second sequence identifier with the
first memory buffer and the second memory buffer, respectively.
Further, the method can include accessing the first and second
memory buffers based on the first and second sequence
identifiers.
Inventors: |
SADOWSKI; Greg; (Cambridge,
MA) ; Rogers; Philip J.; (Peppercell, MA) |
Assignee: |
Advanced Micro Devices,
Inc.
Sunnyvale
CA
|
Family ID: |
44658881 |
Appl. No.: |
12/881663 |
Filed: |
September 14, 2010 |
Current U.S.
Class: |
711/105 ;
711/154; 711/E12.001; 711/E12.008 |
Current CPC
Class: |
G06F 13/1673 20130101;
G06F 13/1684 20130101; Y02D 10/00 20180101 |
Class at
Publication: |
711/105 ;
711/154; 711/E12.001; 711/E12.008 |
International
Class: |
G06F 12/00 20060101
G06F012/00; G06F 12/02 20060101 G06F012/02 |
Claims
1. A method for associating one or more memory buffers in a
computing system with a plurality of memory channels, the method
comprising: associating a first memory buffer and a first sequence
identifier to a first plurality of memory banks, wherein the first
plurality of memory banks spans over a first set of one or more
memory channels; associating a second memory buffer and a second
sequence identifier to a second plurality of memory banks, wherein
the second plurality of memory banks spans over a second set of one
or more memory channels; and accessing the first and second memory
buffers based on the first and second sequence identifiers.
2. The method of claim 1, further comprising: executing a first
memory operation associated with the first memory buffer at a first
operating frequency; executing a second memory operation associated
with the second memory buffer at a second operating frequency,
wherein the first operating frequency is different from the second
operating frequency; and de-allocating the first and second memory
buffers from their respective first and second plurality of memory
banks, after the execution of the first and second memory
operations, respectively.
3. The method of claim 1, wherein the associating the first memory
buffer comprises allocating the first memory buffer to the first
plurality of memory banks.
4. The method of claim 1, wherein the associating the second memory
buffer comprises allocating the second memory buffer to the second
plurality of memory banks, the second plurality of memory banks
being different from the first plurality of memory banks.
5. The method of claim 1, wherein the associating the second memory
buffer comprises allocating the second memory buffer to the second
plurality of memory banks, the second plurality of memory banks
being the same as the first plurality of memory banks.
6. The method of claim 1, wherein the accessing the first and
second memory buffers comprises accessing the first and second
memory buffers in sequence to avoid memory bank contention and to
utilize a full bandwidth of the plurality of memory channels.
7. A computer program product comprising a computer-usable medium
having computer program logic recorded thereon that, when executed
by one or more processors, associates one or more memory buffers in
a computing system with a plurality of memory channels, the
computer program logic comprising: first computer readable program
code that enables a processor to associate a first memory buffer
and a first sequence identifier to a first plurality of memory
banks, wherein the first plurality of memory banks spans over a
first set of one or more memory channels; second computer readable
program code that enables a processor to associate a second memory
buffer and a second sequence identifier to a second plurality of
memory banks, wherein the second plurality of memory banks spans
over a second set of one or more memory channels; and third
computer readable program code that enables a processor to access
the first and second memory buffers based on the first and second
sequence identifiers.
8. The computer program product of claim 7, wherein the computer
program logic further comprises: fourth computer readable program
code that enables a processor to execute a first memory operation
associated with the first memory buffer at a first operating
frequency; fifth computer readable program code that enables a
processor to execute a second memory operation associated with the
second memory buffer at a second operating frequency, wherein the
first operating frequency is different from the second operating
frequency; and sixth computer readable program code that enables a
processor to de-allocate the first and second memory buffers from
their respective first and second plurality of memory banks, after
the execution of the first and second memory operations,
respectively.
9. The computer program product of claim 7, wherein the first
computer readable program code comprises: fourth computer readable
program code that enables a processor to allocate the first memory
buffer to the first plurality of memory banks.
10. The computer program product of claim 7, wherein the second
computer readable program code comprises: fourth computer readable
program code that enables a processor to allocate the second memory
buffer to the second plurality of memory banks, the second
plurality of memory banks being different from the first plurality
of memory banks.
11. The computer program product of claim 7, wherein the second
computer readable program code comprises: fourth computer readable
program code that enables a processor to allocate the second memory
buffer to the second plurality of memory banks, the second
plurality of memory banks being the same as the first plurality of
memory banks.
12. The computer program product of claim 7, wherein the third
computer readable program code comprises: fourth computer readable
program code that enables a processor to access the first and
second memory buffers in sequence to avoid memory bank contention
and to utilize a full bandwidth of the plurality of memory
channels.
13. A computing system, comprising: a first client device; a second
client device; a plurality of memory channels, wherein the
plurality of memory channels comprises a respective plurality of
memory devices; and a memory controller configured to
communicatively couple the first and second client devices to the
plurality of memory channels and configured to: allocate a first
memory buffer and a first sequence identifier to a first plurality
of memory banks, wherein the first plurality of memory banks spans
over a first set of one or more memory channels; allocate a second
memory buffer and a second sequence identifier to a second
plurality of memory banks, wherein the second plurality of memory
banks spans over a second set of one or more memory channels; and
access the first and second memory buffers based on the first and
second sequence identifiers.
14. The computing system of claim 13, further comprising: a
plurality of data buses that correspond to the plurality of memory
devices, wherein the plurality of data buses is configured to
transfer data between the memory controller and the respective
plurality of memory devices.
15. The computing system of claim 14, wherein the memory controller
is configured to control a transfer of data between the first
client device, or the second client device, and the plurality of
memory devices using an entire bandwidth of the plurality of data
buses.
16. The computing system of claim 13, wherein the first and second
client devices comprise at least one of a central processing unit,
a graphics processing unit, and an application-specific integrated
circuit.
17. The computing system of claim 13, wherein each of the plurality
of memory devices comprises a Dynamic Random Access Memory (DRAM)
device.
18. The computing system of claim 13, wherein the memory controller
is configured to: execute a first memory operation associated with
the first memory buffer at a first operating frequency; execute a
second memory operation associated with the second memory buffer at
a second operating frequency, wherein the first operating frequency
is different from the second operating frequency; and de-allocate
the first and second memory buffers from their respective first and
second plurality of memory banks, after the execution of the first
and second memory operations, respectively.
19. The computing system of claim 13, wherein the memory controller
is configured to allocate the second memory buffer to the second
plurality of memory banks, the second plurality of memory banks
being different from the first plurality of memory banks.
20. The computing system of claim 13, wherein the memory controller
is configured to allocate the second memory buffer to the second
plurality of memory banks, the second plurality of memory banks
being the same as the first plurality of memory banks.
21. The computing system of claim 13, wherein the memory controller
is configured to access the first and second memory buffers in
sequence to avoid memory bank contention and to utilize a full
bandwidth of the plurality of memory channels.
22. The computing system of claim 13, wherein the memory controller
is configured to associate the first memory buffer and the second
memory buffer to the first plurality of memory banks and to the
second plurality of memory banks, respectively.
Description
BACKGROUND
[0001] 1. Field
[0002] Embodiments of the present invention generally relate to
allocating one or more memory buffers in a computing system with a
plurality of memory channels.
[0003] 2. Background
[0004] Due to the demand for increasing processing speed and
volume, many computer systems employ multiple client devices (e.g.,
computing devices). In typical computer systems with multiple
client devices, each of the client devices can communicate with
multiple memory devices via a system bus. A source of inefficiency
in the system bus relates to a recovery time period of a memory
device when the client devices request successive data transfers
from the same memory bank of the memory device (also referred to
herein as "memory bank contention"). The recovery time period
refers to a delay time exhibited by the memory device between a
first access and an immediately subsequent second access to the
memory device. While the memory device accesses data, no data can
be transferred on the system bus during the recovery time period,
thus leading to inefficiency in the system bus.
[0005] Since the system bus can only be used by one client device
at a time, one approach to improve bus efficiency involves
interleaving memory addresses within the multiple memory devices on
the system bus. When the memory addresses are interleaved on the
system bus, successive memory storage locations (e.g., memory
locations having consecutive addresses) are placed in separate
memory devices. By placing successive memory locations in separate
memory devices, the effects from the recovery time period for a
given memory device, and thus memory bank contention, can be
reduced.
[0006] However, in a computer system with multiple client devices,
interleaving memory addresses within the multiple memory devices
may not lead to an optimal use of the system bus. In particular,
the system bus typically enters an arbitration state to determine
which of the client devices can access the system bus and
interleaved memory addresses within the multiple memory devices.
For instance, the arbitration state can allow a first client device
to access the system bus and successive memory locations within the
multiple memory devices prior to a second client device. However,
the arbitration state cannot guarantee that the second client
device will immediately access the same successive memory locations
as the first client device, thus compromising the benefits of the
interleaved memory architecture (e.g., reduction of memory bank
contention).
[0007] Methods and systems are needed to reduce, or eliminate,
memory bank contention in computer systems with multiple client
devices.
SUMMARY
[0008] Embodiments of the present invention include a method for
allocating one or more memory buffers in a computing system with a
plurality of memory channels. The method can include the following:
allocating a first memory buffer to a first plurality of memory
banks, where the first plurality of memory banks spans over a first
set of one or more memory channels; allocating a second memory
buffer to a second plurality of memory banks, where the second
plurality of memory banks spans over a second set of one or more
memory channels; associating a first sequence identifier and a
second sequence identifier with the first memory buffer and the
second memory buffer, respectively; and, accessing the first and
second memory buffers based on the first and second sequence
identifiers. The method can also include executing a first memory
operation associated with the first memory buffer at a first
operating frequency. Similarly, the method can include executing a
second memory operation associated with the second memory buffer at
a second operating frequency, where the first operating frequency
is different from the second operating frequency.
[0009] Embodiments of the present invention additionally include a
computer program product that includes a computer-usable medium
having computer program logic recorded thereon for enabling a
processor to allocate one or more memory buffers in a computing
system with a plurality of memory channels. The computer program
logic can include the following: first computer readable program
code that enables a processor to allocate a first memory buffer to
a first plurality of memory banks, where the first plurality of
memory banks spans over a first set of one or more memory channels;
second computer readable program code that enables a processor to
allocate a second memory buffer to a second plurality of memory
banks, where the second plurality of memory banks spans over a
second set of one or more memory channels; third computer readable
program code that enables a processor to associate a first sequence
identifier and a second sequence identifier with the first memory
buffer and the second memory buffer, respectively; and, fourth
computer readable program code that enables a processor to access
the first and second memory buffers based on the first and second
sequence identifiers. The computer program logic can also include
the following: fifth computer readable program code that enables a
processor to execute a first memory operation associated with the
first memory buffer at a first operating frequency; and, sixth
computer readable program code that enables a processor to execute
a second memory operation associated with the second memory buffer
at a second operating frequency, where the first operating
frequency is different from the second operating frequency.
[0010] Embodiments of the present invention further include a
computing system. The computing system can include a first client
device, a second client device, a plurality of memory channels, and
a memory controller. The plurality of memory channels can include a
plurality of memory devices (e.g., Dynamic Random Access Memory
(DRAM) devices). The memory controller is configured to
communicatively couple the first and second client devices to the
plurality of memory channels. The memory controller is also
configured to perform the following functions: allocate a first
memory buffer to a first plurality of memory banks, where the first
plurality of memory banks spans over a first set of one or more
memory channels; allocate a second memory buffer to a second
plurality of memory banks, where the second plurality of memory
banks spans over a second set of one or more memory channels;
associate a first sequence identifier and a second sequence
identifier with the first memory buffer and the second memory
buffer, respectively; and, access the first and second memory
buffers based on the first and second sequence identifiers.
Further, the memory controller is also configured to execute a
first memory operation associated with the first memory buffer at a
first operating frequency and to execute a second memory operation
associated with the second memory buffer at a second operating
frequency, where the first operating frequency is different from
the second operating frequency.
[0011] Further features and advantages of the invention, as well as
the structure and operation of various embodiments of the present
invention, are described in detail below with reference to the
accompanying drawings. It is noted that the invention is not
limited to the specific embodiments described herein. Such
embodiments are presented herein for illustrative purposes only.
Additional embodiments will be apparent to persons skilled in the
relevant art based on the teachings contained herein.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The accompanying drawings, which are incorporated herein and
form a part of the specification, illustrate embodiments of the
present invention and, together with the description, further serve
to explain the principles of the invention and to enable a person
skilled in the relevant art to make and use the invention.
[0013] FIG. 1 is an illustration of an exemplary system with
multiple client devices in which embodiments of the present
invention can be implemented.
[0014] FIG. 2 is an illustration of an embodiment of a plurality of
memory buffers that spans over a plurality of memory channels.
[0015] FIG. 3 is an illustration of an embodiment of a memory
controller.
[0016] FIG. 4 is an illustration of an example scenario in which an
available memory space is smaller than a memory buffer requested
from a computing device.
[0017] FIG. 5 is an illustration of an embodiment of a method for
allocating one or more memory buffers in a computing system with a
plurality of memory channels.
[0018] FIG. 6 is an illustration of an example computer system in
which embodiments of the present invention can be implemented.
DETAILED DESCRIPTION
[0019] The following detailed description refers to the
accompanying drawings that illustrate exemplary embodiments
consistent with this invention. Other embodiments are possible, and
modifications can be made to the embodiments within the spirit and
scope of the invention. Therefore, the detailed description is not
meant to limit the invention. Rather, the scope of the invention is
defined by the appended claims.
[0020] It would be apparent to one of skill in the art that the
present invention, as described below, can be implemented in many
different embodiments of software, hardware, firmware, and/or the
entities illustrated in the figures. Thus, the operational behavior
of embodiments of the present invention will be described with the
understanding that modifications and variations of the embodiments
are possible, given the level of detail presented herein.
[0021] FIG. 1 is an illustration of an embodiment of a multi-client
computing system 100. Multi-client computing system 100 includes a
first computing device 110, a second computing device 120, a memory
controller 130, and memory devices 140, 150, 160 and 170. First and
second computing devices 110 and 120 are communicatively coupled to
memory controller 130 via a system bus 180. Also, memory controller
130 is communicatively coupled to memory devices 140, 150, 160, and
170 via data buses 141, 151, 161, and 171, respectively. Memory
devices 140, 150, 160, and 170 are also referred to herein as
memory channels 140, 150, 160, and 170.
[0022] Based on the description herein, a person skilled in the
relevant art will recognize that multi-client computing system 100
can include more or less than two computing devices, more than one
memory controller, more or less than four memory devices, or a
combination thereof. These different configurations of multi-client
computing system 100 are within the scope and spirit of the
embodiments described herein. However, for ease of explanation, the
embodiments contained herein will be described in the context of
the system architecture depicted in FIG. 1.
[0023] In an embodiment, each of computing devices 110 and 120 can
be, for example and without limitation, a central processing unit
(CPU), a graphics processing unit (GPU), an application-specific
integrated circuit (ASIC) controller, other similar types of
processing units, or a combination thereof. Computing devices 110
and 120 are configured to execute instructions and to carry out
operations associated with multi-client computing system 100. For
instance, multi-client computing system 100 can be configured to
render and display graphics. Multi-client computing system 100 can
include a CPU (e.g., computing device 110) and a GPU (e.g.,
computing device 120), where the GPU can be configured to render
two- and three-dimensional graphics and the CPU can be configured
to coordinate the display of the rendered graphics onto a display
device (not shown in FIG. 1). Computing devices 110 and 120 can be
separate devices (e.g., separate semiconductor integrated circuits
or separate "chips"), separate devices in the same package,
combined devices on a single device (e.g., devices on a single
semiconductor device), or variants thereof.
[0024] In reference to FIG. 1, each of memory devices 140, 150,
160, and 170 is a Dynamic Random Access Memory (DRAM) device with
four memory banks (e.g., memory banks 0-3 in FIG. 2 below),
according to an embodiment of the present invention. Based on the
description herein, a person skilled in the relevant art will
recognize that memory devices 140, 150, 160, and 170 can be other
types of memory devices such as, for example and without
limitation, Static Random Access Memory devices (SRAMs), Static
DRAMs, Flash memory devices, or a combination thereof.
[0025] In an embodiment, one or more memory buffers are allocated
to, or associated with, a plurality of memory banks, where the
plurality of memory banks can span over one or more memory
channels. FIG. 2 is an illustration of an embodiment of a plurality
of memory buffers 210, 220, 230, 240, and 250 that spans over a
plurality of memory channels 140, 150, 160, and 170. For instance,
memory buffer 210 spans over memory banks 0-3 in memory channels
140, 150, 160, and 170, memory buffer 220 spans over memory banks
0-3 in memory channel 170, memory buffers 230 and 240 span over
memory banks 0-3 in memory channel 160, and memory buffer 250 spans
over memory banks 0-3 in memory channels 140 and 150. The plurality
of memory buffers 210-250 is interleaved over one or more memory
banks in memory channels 140-170, according to an embodiment of the
present invention. Methods and techniques for interleaving memory
addresses over a plurality of memory banks are known to a person of
ordinary skill in the relevant art.
[0026] In reference to FIG. 1, when executing instructions and
carrying out operations associated with multi-client computing
system 100, computing devices 110 and 120 can access information
stored in memory devices 140, 150, 160, and 170 via memory
controller 130. FIG. 3 is an illustration of an embodiment of
memory controller 130. Memory controller 130 includes a memory
management unit 310 and a scheduler 320.
[0027] A function of memory management unit 310, among others, is
to allocate, or associate, one or more memory buffers to operations
associated with computing devices 110 and 120. In an embodiment,
memory management unit 310 allocates (or associates) memory buffers
at a memory channel/memory bank granularity. This granularity
refers to a number of memory channels and a number of memory banks
(within the memory channels) that are allocated to the one or more
memory buffers. In an embodiment, the granularity can be dictated
by computing devices 110 and 120, as described in further detail
below.
[0028] In an embodiment, memory management unit 310 is configured
to allocate, or associate, a first memory buffer to a first
plurality of memory banks, where the first plurality of memory
banks spans over a first set of one or more memory channels. An
example of the first memory buffer is memory buffer 220 of FIG. 2.
Memory management unit 310 is also configured to allocate, or
associate, a second memory buffer to a second plurality of memory
banks, where the second plurality of memory banks spans over a
second set of one or more memory channels, according to an
embodiment of the present invention. An example of the second
memory buffer is memory buffer 250 of FIG. 2. In an embodiment, the
second plurality of memory banks is different from the first
plurality of memory banks. For instance, memory buffer 220 occupies
a different plurality of memory banks from memory buffer 250. In
another embodiment, the second plurality of memory banks is the
same as the first plurality of memory banks. For instance, memory
buffer 230 occupies the same plurality of memory banks as memory
buffer 240 of FIG. 2.
[0029] As would be understood by a person skilled in the relevant
art, memory buffers in computing systems (e.g., multi-client
computing system 100) are typically used when moving data between
operations or processes executed by computing devices (e.g.,
computing devices 110 and 120 of FIG. 1). In an embodiment,
computing device 110 is a CPU and the first plurality of memory
banks is allocated to the first memory buffer (e.g., memory buffer
220 of FIG. 2). Memory buffers required to execute
latency-sensitive CPU instruction code can be mapped to the first
memory buffer, according to an embodiment of the present invention.
A benefit, among others, of mapping latency-sensitive CPU
instruction code to the first memory buffer is that memory bank
contention issues can be reduced, or avoided, between computing
devices 110 and 120.
[0030] In an embodiment, computing device 120 is a GPU and the
second memory buffer (e.g., memory buffer 250 of FIG. 2) can be
used in the execution of operations by computing device 120. For
instance, frame memory buffers required to execute graphics
operations can be mapped to the second memory buffer. Since one or
more memory banks are dedicated to GPU operations, a benefit, among
others, of the second memory buffer is that memory bank contention
issues can be reduced, or avoided, between computing devices 110
and 120.
[0031] In another embodiment, the first and second memory buffers
can be used in the execution of operations by computing device 110
or computing device 120. In an embodiment, computing device 110 is
a GPU and the first and second memory buffers can be used in the
execution of operations by computing device 110. For instance,
memory buffer 210 of FIG. 2 can be allocated to GPU operations
associated with frame buffering, memory buffers 220, 230, and 240
can be allocated to GPU operations associated with video decoding,
and memory buffer 250 can be allocated to GPU operations associated
with a static screen state. Based on the description herein, a
person skilled in the relevant art will recognize that memory
buffers 210-250 of FIG. 2 can be allocated to other GPU operations,
which are within the scope and spirit of the embodiments described
herein. Also, based on the description herein, a person skilled in
the relevant art will recognize that memory buffers 210-250 can be
allocated to operations associated with other types of computing
devices (e.g., CPUs and ASIC controllers), which are within the
scope and spirit of the embodiments described herein.
[0032] A benefit, among others, in allocating memory buffers
210-250 across all of the memory channels in multi-computing system
100 of FIG. 1 (e.g., memory channels 140-170 of FIG. 2) is not only
that memory bank contention issues can be reduced, or avoided, but
also that the full bandwidth of the memory channels can be
utilized. In using the full bandwidth of the memory channels in
multi-client computing system 100, both power and efficiency in
multi-client computing system 100 are improved.
[0033] In reference to FIG. 3, memory management unit 310 is
configured to allocate one or more memory buffers to operations
associated with computing devices 110 and 120 of FIG. 1 in such a
manner as to minimize "holes" in the memory space. A "hole" refers
to a situation in which an available memory buffer is smaller than
requested by computing device 110 or computing device 120, and the
requested memory buffer is allocated to a higher address space.
This, as a result, leaves an available memory buffer space unused.
In an embodiment, memory management unit 310 is configured to
maintain an accounting and status of the memory buffers in order to
minimize, or avoid, the occurrence of holes in the memory space.
This accounting and status information is also referred to herein
as "tracking information." In an embodiment, the tracking
information can provide the following information: (1) whether an
allocated memory buffer is in use, free, or reserved; (2) the
memory channel/memory bank granularity of the allocated memory
buffer; (3) a sequence identifier associated with the allocated
memory buffer; and, (4) a performance parameter for the allocated
memory buffer. The sequence identifier and the performance
parameter associated with the allocated memory buffer are described
in further detail below.
[0034] FIG. 4 is an illustration of an example scenario in which an
available memory space 410 is smaller than a memory buffer 420
requested from computing device 110 or 120. In an embodiment, in
order to utilize the full bandwidth of all of the memory channels
(e.g., memory channels 140-170), it is desirable and optimal to
allocate memory buffer 420 into available memory space 410. Memory
management unit 310 of FIG. 3 is configured to track the allocation
of memory space to memory buffers associated with the operations of
computing devices 110 and 120 of FIG. 1 such that the tracking
information can be used in memory space allocations for future
operations, according to an embodiment of the present invention.
For instance, in the example scenario illustrated in FIG. 4, the
tracking information maintained by memory management unit 310 can
be used to adjust the memory space allocation of memory buffers
210, 230, 240, and 250 for future operations of the computing
device such that memory buffer 420 can be allocated across memory
banks 0-3 of memory channel 170 (e.g., similar to the memory buffer
arrangement illustrated in FIG. 2). As a result, the full bandwidth
of the memory channels in multi-client computing system 100 of FIG.
1 can be utilized, thus leading to an improvement in power and
efficiency in multi-client computing system 100.
[0035] In reference to FIG. 3, memory management unit 310 is also
configured to allocate one or more memory buffers to operations
associated with computing devices 110 and 120 of FIG. 1 based on a
workload expectation of computing devices 110 and 120. In an
embodiment, computing device 110 is a GPU and requests one or more
memory buffers to execute one or more GPU operations at a
particular bandwidth or rate. Based on the type of GPU operation
requested by computing device 110 (e.g., GPU), memory management
unit 310 can allocate an appropriate amount of memory space and
memory buffer for the GPU operations. For example, in reference to
FIG. 2, a video decode pipeline operation can be performed using
memory buffers 220, 230, 240, and 250. Memory buffer 250 can be
used, for example, in a static screen state of the video decode
pipeline. Memory buffers 230 and 240 can be used for internal use
by a video decoder in the pipeline. Further, memory buffer 220 can
be used, for example, in write operations by the video decoder and
read operations from one or more graphics blocks in the video
decode pipeline.
[0036] Each of memory buffers 220, 230, 240, and 250 can be
assigned a sequence identifier, according to an embodiment of the
present invention. In an embodiment, the sequence identifier
provides a reference for memory controller 130 and memory devices
140, 150, 160, and 170 of FIG. 1, in which the reference is an
indicator on an address/access sequence for the allocated memory
buffers. For example, in returning to the video decode pipeline
example above, a sequence identifier of `1` can be assigned to
memory buffer 250 and the static screen state operation of the
video decode pipeline. A sequence identifier of `2` can be assigned
to memory buffer 240 and the video decoder's internal operation. A
sequence identifier of `3` can be assigned to memory buffer 230 and
the write operations by the video decoder and the read operations
from the one or more graphics blocks. Further, a sequence
identifier of `4` can be assigned to memory buffer 220 and the
video decoder's internal operation.
[0037] For a portion of the video decode pipeline operation, memory
controller 130 and memory devices 140-170 may address/access memory
buffers 220, 230, 240, and 250 in a particular sequence, according
to an embodiment of the present invention. The sequence identifiers
of memory buffers 220, 230, 240, and 250 can be used as parameters
for the particular sequence. For example, if the particular
sequence is `1`, `2`, and `4`, memory buffer 250 will be
addressed/accessed first, memory buffer 240 will be
addressed/accessed second, and memory buffer 220 will be
addressed/accessed last. In another example, if the particular
sequence is `1`, `3`, and `4`, memory buffer 250 will be
addressed/accessed first, memory buffer 230 will be
addressed/accessed second, and memory buffer 220 will be
addressed/accessed last. In both of these examples, the particular
sequences do not have `2` and `3` occurring one after another. As a
result, memory bank contention issues are not only reduced, or
avoided, in memory channel 160, but the full bandwidth of the
memory channels in multi-client computing system 100 can also be
utilized.
[0038] In instances where memory management unit 310 does not have
information on the workload expectation of computing devices 110
and 120, a default memory buffer arrangement can be used for
operations associated with computing devices 110 and 120, according
to an embodiment of the present invention. In an embodiment, the
default memory buffer arrangement can span across all memory banks
of and across all memory channels. An example of this memory buffer
arrangement is illustrated as memory buffer 210 of FIG. 2, which
spans across all memory banks 0-3 and across all memory channels
140-170.
[0039] In addition to assessing the workload expectation of
computing devices 110 and 120, memory management unit 310 is
configured to operate each of memory channels 140, 150, 160, and
170 at a particular operating frequency. As a result, the bandwidth
per memory channel can be assessed based on the allocated memory
buffers across one or more of the memory channels. For instance,
based on a particular arrangement of memory buffers across memory
channels 140, 150, 160, and 170 (e.g., memory buffers 210, 220,
230, 240, and 250 of FIG. 2), the clock frequency of each of the
memory channels can either be increased or decreased to assess
whether the performance (e.g., throughput) of multi-client
computing system 100 of FIG. 1 improves based on the arrangement of
memory buffers. Based on this information, an optimal clock
frequency can be used for one or more memory channels associated
with one or more memory buffers such that memory operations
associated with the computing devices can be optimized. In an
embodiment, the performance parameter portion of the tracking
information (described above) includes the optimal clock frequency
for each of memory channels 140, 150, 160, and 170.
[0040] In reference to FIG. 3, scheduler 320 is configured to
process memory requests from memory management unit 310. In an
embodiment, scheduler 320 processes the memory requests based on
the tracking information provided by memory management unit 310. As
discussed above, in an embodiment, the tracking information can
provide the following information: (1) whether an allocated memory
buffer is in use, free, or reserved; (2) the memory channel/memory
bank granularity of the allocated memory buffer; (3) a sequence
identifier associated with the allocated memory buffer; and, (4) a
performance parameter for the allocated memory buffer. Based on
this tracking information, scheduler 320 generates an address,
command, and control signals necessary to send read and write
operations to memory channels 140, 150, 160, and 170 via data buses
141, 151, 161, and 171, respectively, of FIG. 1. The generation of
address, command, and control signals corresponding to read and
write memory requests from computing devices 110 and 120 of FIG. 1
is known to a person skilled in the relevant art.
[0041] In an embodiment, scheduler 320 operates in conjunction with
memory management unit 310 to sort threads of arbitration between
computing devices 110 and 120 of FIG. 1. In an embodiment, memory
controller 130 of FIG. 1 can manage two threads of arbitration--one
thread of arbitration allocated to memory requests from computing
device 110 and another thread of arbitration allocated to memory
requests from computing device 120. Scheduler 320 can be optimized
by processing the memory requests of one computing device before
the other computing device. For instance, if computing device 110
is a CPU and computing device 120 is a GPU, scheduler 320 can
process the CPU-related memory requests before GPU-related memory
requests since CPU performance is typically more sensitive to
memory delay than GPU performance. Here, scheduler 220 provides
control of system bus 180 of FIG. 1 to computing device 110 such
that the data transfer associated with the CPU-related memory
request takes priority over the data transfer associated with the
GPU-related memory request, according to an embodiment of the
present invention.
[0042] In an embodiment, after an operation associated with
computing devices 110 and 120 of FIG. 1 is executed (e.g., using
memory buffers 210-250 of FIG. 2), memory management unit 310 of
FIG. 3 de-allocates the one or more memory buffers associated with
the operation from the memory space. At this point, memory
management unit 310 can allocate the free memory space to other
memory buffers associated with operations of computing devices 110
and 120. Memory management unit 310 can allocate the free memory
space to the other memory buffers in the same arrangement as (e.g.,
same number of banks and channels allocated to memory buffers
associated with the previous operation) or in a different
arrangement from (e.g., different number of banks and channels
allocated to the other memory buffers associated with the previous
operation) as the previous operation. Memory management unit 310 is
configured to allocate the other memory buffers to the operations
of computing devices 110 and 120 in the same manner described above
with respect to FIG. 3.
[0043] FIG. 5 is an illustration of an embodiment of a method 500
for allocating one or more memory buffers in a computing system
with a plurality of memory channels. Method 500 can occur using,
for example and without limitation, multi-client computing system
100 of FIG. 1.
[0044] In step 510, a first memory buffer is allocated to, or
associated with, a first plurality of memory banks, where the first
plurality of memory banks spans over a first set of one or more
memory channels. Memory management unit 310 of FIG. 3 can be used,
for example, to perform step 510.
[0045] In step 520, a second memory buffer is allocated to, or
associated with, a second plurality of memory banks, where the
second plurality of memory banks spans over a second set of one or
more memory channels. In an embodiment, the second plurality of
memory banks is different from the first plurality of memory banks
(in step 510). In another embodiment, the second plurality of
memory banks is the same as the first plurality of memory banks.
Memory management unit 310 of FIG. 3 can be used, for example, to
perform step 520.
[0046] In step 530, a first sequence identifier and a second
sequence identifier are associated with the first memory buffer and
the second memory buffer, respectively. Memory management unit 310
of FIG. 3 can be used, for example, to perform step 530.
[0047] In step 540, the first and second memory buffers are
accessed based on the first and second sequence identifiers. In an
embodiment, the first and second memory buffers are accessed in
sequence to avoid memory bank contention and to utilize a full
bandwidth of the plurality of memory channels. Memory management
unit 310 and scheduler 320 of FIG. 3 can be used, for example, to
perform step 540.
[0048] Further, in an embodiment, when executing a first memory
operation associated with the first memory buffer and a second
memory operation associated with the second memory buffer, the
first and second memory operations are executed at a first
operating frequency and a second operating frequency, respectively.
The first and second operating frequencies are different from one
another, according to an embodiment of the present invention.
[0049] In step 550, after the first and second memory operations
associated with the first and second memory buffers, respectively,
are executed, the first and second memory buffers are de-allocated
from their respective memory spaces. With the de-allocation of the
first and second memory buffers, memory buffers associated with
other memory operations can be allocated to the free memory
space.
[0050] Various aspects of the present invention may be implemented
in software, firmware, hardware, or a combination thereof. FIG. 6
is an illustration of an example computer system 600 in which
embodiments of the present invention, or portions thereof, can be
implemented as computer-readable code. For example, the method
illustrated by flowchart 500 of FIG. 5 can be implemented in system
600. Various embodiments of the present invention are described in
terms of this example computer system 600. After reading this
description, it will become apparent to a person skilled in the
relevant art how to implement embodiments of the present invention
using other computer systems and/or computer architectures.
[0051] It should be noted that the simulation, synthesis and/or
manufacture of various embodiments of this invention may be
accomplished, in part, through the use of computer readable code,
including general programming languages (such as C or C++),
hardware description languages (HDL) such as, for example, Verilog
HDL, VHDL, Altera HDL (AHDL), or other available programming and/or
schematic capture tools (such as circuit capture tools). This
computer readable code can be disposed in any known computer-usable
medium including a semiconductor, magnetic disk, optical disk (such
as CD-ROM, DVD-ROM). As such, the code can be transmitted over
communication networks including the Internet. It is understood
that the functions accomplished and/or structure provided by the
systems and techniques described above can be represented in a core
(such as a GPU core) that is embodied in program code and can be
transformed to hardware as part of the production of integrated
circuits.
[0052] Computer system 600 includes one or more processors, such as
processor 604. Processor 604 may be a special purpose or a general
purpose processor. Processor 604 is connected to a communication
infrastructure 606 (e.g., a bus or network).
[0053] Computer system 600 also includes a main memory 608,
preferably random access memory (RAM), and may also include a
secondary memory 610. Secondary memory 610 can include, for
example, a hard disk drive 612, a removable storage drive 614,
and/or a memory stick. Removable storage drive 614 can include a
floppy disk drive, a magnetic tape drive, an optical disk drive, a
flash memory, or the like. The removable storage drive 614 reads
from and/or writes to a removable storage unit 618 in a well known
manner. Removable storage unit 618 can comprise a floppy disk,
magnetic tape, optical disk, etc. which is read by and written to
by removable storage drive 614. As will be appreciated by persons
skilled in the relevant art, removable storage unit 618 includes a
computer-usable storage medium having stored therein computer
software and/or data.
[0054] In alternative implementations, secondary memory 610 can
include other similar devices for allowing computer programs or
other instructions to be loaded into computer system 600. Such
devices can include, for example, a removable storage unit 622 and
an interface 620. Examples of such devices can include a program
cartridge and cartridge interface (such as those found in video
game devices), a removable memory chip (e.g., EPROM or PROM) and
associated socket, and other removable storage units 622 and
interfaces 620 which allow software and data to be transferred from
the removable storage unit 622 to computer system 600.
[0055] Computer system 600 can also include a communications
interface 624. Communications interface 624 allows software and
data to be transferred between computer system 600 and external
devices. Communications interface 624 can include a modem, a
network interface (such as an Ethernet card), a communications
port, a PCMCIA slot and card, or the like. Software and data
transferred via communications interface 624 are in the form of
signals which may be electronic, electromagnetic, optical, or other
signals capable of being received by communications interface 624.
These signals are provided to communications interface 624 via a
communications path 626. Communications path 626 carries signals
and can be implemented using wire or cable, fiber optics, a phone
line, a cellular phone link, a RF link or other communications
channels.
[0056] In this document, the terms "computer program medium" and
"computer-usable medium" are used to generally refer to media such
as removable storage unit 618, removable storage unit 622, and a
hard disk installed in hard disk drive 612. Computer program medium
and computer-usable medium can also refer to memories, such as main
memory 608 and secondary memory 610, which can be memory
semiconductors (e.g., DRAMs, etc.). These computer program products
provide software to computer system 600.
[0057] Computer programs (also called computer control logic) are
stored in main memory 608 and/or secondary memory 610. Computer
programs may also be received via communications interface 624.
Such computer programs, when executed, enable computer system 600
to implement embodiments of the present invention as discussed
herein. In particular, the computer programs, when executed, enable
processor 604 to implement processes of embodiments of the present
invention, such as the steps in the methods illustrated by
flowchart 500 of FIG. 5, discussed above. Accordingly, such
computer programs represent controllers of the computer system 600.
Where embodiments of the present invention are implemented using
software, the software can be stored in a computer program product
and loaded into computer system 600 using removable storage drive
614, interface 620, hard drive 612, or communications interface
624.
[0058] Embodiments of the present invention are also directed to
computer program products including software stored on any
computer-usable medium. Such software, when executed in one or more
data processing device, causes a data processing device(s) to
operate as described herein. Embodiments of the present invention
employ any computer-usable or -readable medium, known now or in the
future. Examples of computer-usable mediums include, but are not
limited to, primary storage devices (e.g., any type of random
access memory), secondary storage devices (e.g., hard drives,
floppy disks, CD ROMS, ZIP disks, tapes, magnetic storage devices,
optical storage devices, MEMS, nanotechnological storage devices,
etc.), and communication mediums (e.g., wired and wireless
communications networks, local area networks, wide area networks,
intranets, etc.).
[0059] While various embodiments of the present invention have been
described above, it should be understood that they have been
presented by way of example only, and not limitation. It will be
understood by persons skilled in the relevant art that various
changes in form and details can be made therein without departing
from the spirit and scope of the invention as defined in the
appended claims. It should be understood that the invention is not
limited to these examples. The invention is applicable to any
elements operating as described herein. Accordingly, the breadth
and scope of the present invention should not be limited by any of
the above-described exemplary embodiments, but should be defined
only in accordance with the following claims and their
equivalents.
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