U.S. patent application number 13/221252 was filed with the patent office on 2012-03-08 for sputtering target and method for manufacturing semiconductor device.
This patent application is currently assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD.. Invention is credited to Shunpei Yamazaki.
Application Number | 20120056176 13/221252 |
Document ID | / |
Family ID | 45770024 |
Filed Date | 2012-03-08 |
United States Patent
Application |
20120056176 |
Kind Code |
A1 |
Yamazaki; Shunpei |
March 8, 2012 |
SPUTTERING TARGET AND METHOD FOR MANUFACTURING SEMICONDUCTOR
DEVICE
Abstract
An object is to provide a deposition technique for depositing an
oxide semiconductor film. Another object is to provide a method for
manufacturing a highly reliable semiconductor element using the
oxide semiconductor film. A novel sputtering target obtained by
removing an alkali metal, an alkaline earth metal, and hydrogen
that are impurities in a sputtering target used for deposition is
used, whereby an oxide semiconductor film containing a small amount
of those impurities can be deposited.
Inventors: |
Yamazaki; Shunpei; (Tokyo,
JP) |
Assignee: |
SEMICONDUCTOR ENERGY LABORATORY
CO., LTD.
Atsugi-shi
JP
|
Family ID: |
45770024 |
Appl. No.: |
13/221252 |
Filed: |
August 30, 2011 |
Current U.S.
Class: |
257/43 ;
257/E21.462; 257/E29.098; 257/E29.1; 438/104 |
Current CPC
Class: |
C23C 14/086 20130101;
C23C 14/081 20130101; H01L 29/66969 20130101; H01L 29/7869
20130101; C23C 14/3414 20130101; H01L 21/02631 20130101; H01L
29/66742 20130101; H01L 21/02565 20130101 |
Class at
Publication: |
257/43 ; 438/104;
257/E29.1; 257/E29.098; 257/E21.462 |
International
Class: |
H01L 29/227 20060101
H01L029/227; H01L 21/363 20060101 H01L021/363; H01L 29/24 20060101
H01L029/24 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 3, 2010 |
JP |
2010-197509 |
Claims
1. A sputtering target for forming an oxide semiconductor film,
comprising a sintered body of at least one oxide selected from zinc
oxide, aluminum oxide, gallium oxide, indium oxide, and tin oxide,
wherein concentration of each of alkali metals contained in the
sintered body by SIMS is 5.times.10.sup.16 cm.sup.-3 or lower.
2. The sputtering target according to claim 1, wherein
concentration of hydrogen contained in the sintered body by SIMS is
1.times.10.sup.19 cm.sup.-3 or lower.
3. The sputtering target according to claim 1, wherein
concentration of sodium contained in the sintered body by SIMS is
1.times.10.sup.16 cm.sup.-3 or lower.
4. The sputtering target according to claim 1, wherein
concentration of sodium contained in the sintered body by SIMS is
1.times.10.sup.15 cm.sup.-3 or lower.
5. The sputtering target according to claim 1, wherein
concentration of lithium contained in the sintered body by SIMS is
5.times.10.sup.15 cm.sup.-3 or lower.
6. The sputtering target according to claim 1, wherein
concentration of lithium contained in the sintered body by SIMS is
1.times.10.sup.15 cm.sup.-3 or lower.
7. The sputtering target according to claim 1, wherein
concentration of potassium contained in the sintered body by SIMS
is 5.times.10.sup.15 cm.sup.-3 or lower.
8. The sputtering target according to claim 1, wherein
concentration of potassium contained in the sintered body by SIMS
is 1.times.10.sup.15 cm.sup.-3 or lower.
9. A method for manufacturing a semiconductor device, the method
comprising the steps of: forming a conductive film over a
substrate; etching the conductive film to form a gate electrode;
forming a gate insulating layer over the gate electrode; and
forming an oxide semiconductor film over the gate insulating layer
by a sputtering method using a sputtering target, wherein the
sputtering target comprises a sintered body of at least one oxide
selected from zinc oxide, aluminum oxide, gallium oxide, indium
oxide, and tin oxide, wherein concentration of each of alkali
metals contained in the sintered body by SIMS is 5.times.10.sup.16
cm.sup.-3 or lower.
10. The method according to claim 9, wherein concentration of
hydrogen contained in the sintered body by SIMS is
1.times.10.sup.19 cm.sup.-3 or lower.
11. The method according to claim 9, wherein concentration of
sodium contained in the sintered body by SIMS is 1.times.10.sup.16
cm.sup.-3 or lower.
12. The method according to claim 9, wherein concentration of
sodium contained in the sintered body by SIMS is 1.times.10.sup.15
cm.sup.-3 or lower.
13. The method according to claim 9, wherein concentration of
lithium contained in the sintered body by SIMS is 5.times.10.sup.15
cm.sup.-3 or lower.
14. The method according to claim 9, wherein concentration of
lithium contained in the sintered body by SIMS is 1.times.10.sup.15
cm.sup.-3 or lower.
15. The method according to claim 9, wherein concentration of
potassium contained in the sintered body by SIMS is
5.times.10.sup.15 cm.sup.-3 or lower.
16. The method according to claim 9, wherein concentration of
potassium contained in the sintered body by SIMS is
1.times.10.sup.15 cm.sup.-3 or lower.
Description
TECHNICAL FIELD
[0001] The present invention relates to a sputtering target and a
method for manufacturing the sputtering target. Further, the
present invention relates to a method for manufacturing a
semiconductor device which is manufactured with the use of the
sputtering target and uses an oxide semiconductor.
[0002] In this specification, a semiconductor device means a
general device which can function by utilizing semiconductor
characteristics, and an electro-optic device, a semiconductor
circuit, and an electronic device are all semiconductor
devices.
BACKGROUND ART
[0003] A transistor formed over a flat plate such as a glass
substrate, which is typically used in a liquid crystal display
device, is generally formed using a semiconductor material such as
amorphous silicon or polycrystalline silicon. A transistor
manufactured using amorphous silicon has low field effect mobility,
but can be formed over a larger glass substrate. In contrast, a
transistor manufactured using polycrystalline silicon has high
field effect mobility, but needs a crystallization step such as
laser annealing and is not always suitable for a larger glass
substrate.
[0004] Thus, a technique in which a transistor is manufactured
using an oxide semiconductor as a semiconductor material and
applied to an electronic device or an optical device has attracted
attention. For example, Patent Document 1 and Patent Document 2
disclose a technique by which a transistor is formed using zinc
oxide or an In--Ga--Zn-based oxide semiconductor as a semiconductor
material and such a transistor is used as a switching element or
the like of an image display device.
[0005] A transistor in which a channel formation region (also
referred to as a channel region) is provided in an oxide
semiconductor can have higher field effect mobility than a
transistor using amorphous silicon. An oxide semiconductor film can
be formed by a sputtering method or the like at a relatively low
temperature. Its manufacturing process is easier than that of a
transistor using polycrystalline silicon.
[0006] Transistors which are formed using such an oxide
semiconductor over a glass substrate, a plastic substrate, or the
like are expected to be applied to display devices such as a liquid
crystal display, an electroluminescent display (also referred to as
an EL display), and electronic paper.
REFERENCE
[0007] [Patent Document 1] Japanese Published Patent Application
No. 2007-123861 [0008] [Patent Document 2] Japanese Published
Patent Application No. 2007-96055
DISCLOSURE OF INVENTION
[0009] However, characteristics of a semiconductor element which is
manufactured using an oxide semiconductor are not yet sufficient.
For example, controlled threshold voltage, high operation speed,
and sufficient reliability are required for a transistor including
an oxide semiconductor film.
[0010] An object of one embodiment of the present invention is to
provide a deposition technique for forming an oxide semiconductor
film. In addition, an object of one embodiment of the present
invention is to provide a method for manufacturing a highly
reliable semiconductor element using the oxide semiconductor
film.
[0011] The density of carriers in an oxide semiconductor film has
influence on the threshold voltage of a transistor including the
oxide semiconductor. The carriers in the oxide semiconductor film
are generated due to impurities contained in the oxide
semiconductor film. For example, impurities such as a compound
containing a hydrogen atom typified by H.sub.2O, a compound
containing an alkali metal, or a compound containing an alkaline
earth metal contained in the deposited oxide semiconductor film
increase the carrier density of the oxide semiconductor film.
[0012] In order to achieve the above objects, impurities contained
in the oxide semiconductor film which have influence on the carrier
density, for example, a compound containing a hydrogen atom
typified by H.sub.2O, a compound containing an alkali metal, or a
compound containing an alkaline earth metal may be removed.
Specifically, a novel sputtering target obtained by removing an
alkali metal, an alkaline earth metal, and hydrogen that are
impurities in a sputtering target used for deposition is used,
whereby an oxide semiconductor film containing a small amount of
those impurities can be deposited.
[0013] A sputtering target of one embodiment of the present
invention is a sputtering target for forming an oxide semiconductor
film and includes a sintered body of at least one oxide selected
from zinc oxide, aluminum oxide, gallium oxide, indium oxide, and
tin oxide. When observed by SIMS, the concentration of each of
alkali metals contained in the sintered body is 5.times.10.sup.16
cm.sup.-3 or lower. Further, when observed by SIMS, the
concentration of hydrogen contained in the sintered body is
1.times.10.sup.19 cm.sup.--3 or lower, preferably 1.times.10.sup.18
cm.sup.-3 or lower, more preferably lower than 1.times.10.sup.16
cm.sup.-3.
[0014] More specifically, the concentration of sodium (Na) observed
by SIMS is 5.times.10.sup.16 cm.sup.-3 or lower, preferably
1.times.10.sup.16 cm.sup.-3 or lower, more preferably
1.times.10.sup.15 cm.sup.-3 or lower. The concentration of lithium
(Li) observed by SIMS is 5.times.10.sup.15 cm.sup.-3 or lower,
preferably 1.times.10.sup.15 cm.sup.-3 or lower. The concentration
of potassium (K) observed by SIMS is 5.times.10.sup.15 cm.sup.-3 or
lower, preferably 1.times.10.sup.15 cm.sup.-3 or lower.
[0015] It has been pointed out that an oxide semiconductor is
insensitive to impurities, there is no problem when a considerable
amount of metal impurities is contained in the film, and therefore,
soda-lime glass which contains a large amount of an alkali metal
such as sodium and is inexpensive can also be used (Kamiya, Nomura,
and Hosono, "Carrier Transport Properties and Electronic Structures
of Amorphous Oxide Semiconductors: The present status", KOTAI
BUTSURI (SOLID STATE PHYSICS), 2009, Vol. 44, pp. 621-633). But
such consideration is not appropriate.
[0016] An alkali metal and an alkaline earth metal are adverse
impurities for a transistor using an oxide semiconductor layer and
are preferably contained as little as possible. An alkali metal, in
particular, Na diffuses into an oxide and becomes Na.sup.+ when an
insulating film in contact with the oxide semiconductor layer is an
oxide. In addition, Na cuts a bond between metal and oxygen or
enters the bond in the oxide semiconductor layer. As a result,
transistor characteristics deteriorate (e.g., the transistor
becomes normally-on (the shift of threshold voltage to a negative
side) or the mobility is decreased). In addition, this also causes
variation in the characteristics. Such a problem is significant
especially in the case where the hydrogen concentration in the
oxide semiconductor layer is sufficiently low. Thus, the
concentration of an alkali metal is required to be set to the above
value in the case where the concentration of hydrogen in the oxide
semiconductor layer is 5.times.10.sup.19 cm.sup.-3 or lower,
particularly 5.times.10.sup.18 cm.sup.-3 or lower.
[0017] Note that in this specification, a measurement value
obtained by secondary ion mass spectrometry (SIMS) is used as the
impurity concentration in the sputtering target or the oxide
semiconductor film. It is known that it is difficult to obtain
accurate data in the proximity of a surface of a sample or in the
proximity of an interface between stacked films formed using
different materials by the SIMS analysis in principle. Thus, in the
case where distributions of the impurity concentrations in the
films in thickness directions are analyzed by SIMS, the smallest
value in a region where the films are provided, the value is not
greatly changed, and almost constant level of strength can be
obtained is employed as the impurity concentration. Further, in the
case where the thickness of the film is small, a region where
almost constant level of strength can be obtained cannot be found
in some cases due to the influence of the impurity concentration in
the films adjacent to each other. In this case, the smallest value
of the impurity concentration in a region where the films are
provided is employed as the impurity concentration in the film.
[0018] In one embodiment of the present invention, a sputtering
target containing a small amount of impurities such as a hydrogen
atom, an alkali metal, and an alkaline earth metal can be provided.
An oxide semiconductor film in which impurities are reduced can be
formed using the sputtering target. A method for manufacturing a
highly reliable semiconductor element including the oxide
semiconductor film containing a small amount of impurities can be
provided.
BRIEF DESCRIPTION OF DRAWINGS
[0019] In the accompanying drawings:
[0020] FIG. 1 is a flow chart illustrating a method for
manufacturing a sputtering target;
[0021] FIGS. 2A and 2B are top views illustrating a sputtering
target; and
[0022] FIGS. 3A to 3E are cross-sectional views illustrating an
example of a method for manufacturing a transistor.
BEST MODE FOR CARRYING OUT THE INVENTION
[0023] An embodiment of the present invention will be described in
detail below with reference to drawings. Note that the present
invention is not limited to the following description and it will
be easily understood by those skilled in the art that modes and
details can be modified in various ways. In addition, the present
invention is not construed as being limited to description of the
embodiment.
Embodiment 1
[0024] In this embodiment, a method for manufacturing a sputtering
target which is one embodiment of the present invention will be
described with reference to FIG. 1. FIG. 1 is a flow chart
illustrating an example of a method for manufacturing a sputtering
target according to this embodiment.
[0025] First, plural kinds of single metals (Zn, In, Al, Sn, and
the like) that are materials of the sputtering target are each
purified by repeating distillation, sublimation, or
recrystallization (S101). After that, purified metals are each
processed into a powder form. Note that in the case of using Ga or
Si as the material of the sputtering target, a single crystal is
obtained by a zone melt method or a Czochralski method and then
processing into a powder form is performed. Then, each of the
sputtering target materials is baked in a high-purity oxygen
atmosphere so as to be oxidized (S102). Subsequently, each of the
oxide powders is weighed as appropriate, and the weighed oxide
powders are mixed (S103).
[0026] The purity of the high-purity oxygen atmosphere is, for
example, 6N (99.9999%) or higher, preferably 7N (99.99999%) or
higher (i.e., the concentration of impurities is 1 ppm or lower,
preferably 0.1 ppm or lower).
[0027] In this embodiment, a sputtering target for an
In--Ga--Zn-based oxide semiconductor is to be manufactured. For
example, In.sub.2O.sub.3, Ga.sub.2O.sub.3, and ZnO are weighed so
that the composition ratio of In.sub.2O.sub.3:Ga.sub.2O.sub.3:ZnO
is 1:1:1 [molar ratio].
[0028] As examples of the sputtering target for an oxide
semiconductor which is manufactured in this embodiment, without
being limited to a sputtering target for an In--Ga--Zn-based oxide
semiconductor, the following can be given: a sputtering target for
an In--Sn--Ga--Zn-based oxide semiconductor, a sputtering target
for an In--Sn--Zn-based oxide semiconductor, a sputtering target
for an In--Al--Zn-based oxide semiconductor, a sputtering target
for a Sn--Ga--Zn-based oxide semiconductor, a sputtering target for
an Al--Ga--Zn-based oxide semiconductor, a sputtering target for a
Sn--Al--Zn-based oxide semiconductor, a sputtering target for an
In--Zn-based oxide semiconductor, a sputtering target for a
Sn--Zn-based oxide semiconductor, a sputtering target for an
Al--Zn-based oxide semiconductor, a sputtering target for an
In-based oxide semiconductor, a sputtering target for a Sn-based
oxide semiconductor, a sputtering target for a Zn-based oxide
semiconductor, and the like.
[0029] Next, the mixture is shaped into a predetermined shape and
baked, whereby a sintered body of the metal oxide is obtained
(S104). By baking the sputtering target material, hydrogen,
moisture, hydrocarbon, and the like can be prevented from being
mixed into the sputtering target. The baking can be performed in an
inert gas atmosphere (a nitrogen atmosphere or a rare gas
atmosphere), in vacuum, or in a high-pressure atmosphere, and
further, may be performed with application of mechanical pressure.
As a baking method, an atmospheric sintering method, a pressure
sintering method, or the like can be used as appropriate. As the
pressure sintering method, a hot pressing method, a hot isostatic
pressing (HIP) method, a discharge plasma sintering method, or an
impact method is preferably used. Although the maximum temperature
at which baking is performed is selected depending on the sintering
temperature of the sputtering target material, it is preferably set
to approximately 1000.degree. C. to 2000.degree. C., or more
preferably, 1200.degree. C. to 1500.degree. C. Although the holding
time of the maximum temperature is selected depending on the
sputtering target material, 0.5 hours to 3 hours is preferable.
[0030] Note that the filling rate of the sputtering target for an
oxide semiconductor in this embodiment is preferably higher than or
equal to 90% and lower than or equal to 100%, or more preferably,
higher than or equal to 95% and lower than or equal to 99.9%
inclusive.
[0031] Next, mechanical processing is performed in order to form a
sputtering target having desired dimensions, a desired shape, and
desired surface roughness (S105). As a processing means, for
example, mechanical polishing, chemical mechanical polishing (CMP),
or a combination of these can be used.
[0032] Then, in order to remove minute dust generated by the
mechanical processing and components of a grinding solution, the
sputtering target may be cleaned. Note that, in the case where the
sputtering target is cleaned by ultrasonic cleaning in which the
target is soaked in water or an organic solvent, cleaning with
running water, or the like, it is preferable that heat treatment be
subsequently performed for sufficiently reducing the concentration
of hydrogen in the target or on a surface thereof.
[0033] Then, heat treatment is performed on the sputtering target
(S106). The heat treatment is preferably performed in an inert gas
atmosphere (a nitrogen atmosphere or a rare gas atmosphere).
Although the temperature of the heat treatment differs depending on
the sputtering target material, it is set to a temperature at which
the sputtering target is not changed in property. Specifically, the
temperature is higher than or equal to 150.degree. C. and lower
than or equal to 750.degree. C., preferably, higher than or equal
to 425.degree. C. and lower than or equal to 750.degree. C. Heating
time is, specifically, 0.5 hours or longer, preferably, for an hour
or longer. The heat treatment may be performed in vacuum or in a
high-pressure atmosphere.
[0034] After that, the sputtering target is attached to a metal
plate called a backing plate (S107). A backing plate has functions
of cooling the sputtering target material and being a sputtering
electrode and thus is preferably formed using copper, which is
excellent in thermal conductivity and electric conductivity.
Alternatively, titanium, a copper alloy, a stainless steel alloy,
or the like can be used other than copper.
[0035] Further, at the time of attaching the sputtering target to
the backing plate, the sputtering target may be divided and
attached to one backing plate. FIGS. 2A and 2B illustrate examples
in which the sputtering target is divided and attached (bonded) to
one backing plate.
[0036] FIG. 2A illustrates an example in which a sputtering target
851 is divided into four pieces of sputtering targets 851a, 851b,
851c, and 851d and they are attached to a backing plate 850. FIG.
2B illustrates an example in which a sputtering target is divided
to a larger number of sputtering targets; that is, a sputtering
target 852 is divided into nine pieces of sputtering targets 852a,
852b, 852c, 852d, 852e, 852f, 852g, 852h, and 852i, and they are
attached to the backing plate 850. Note that the number of pieces
of divided sputtering targets and the shape of the target are not
limited to the number and the shape in the case of FIG. 2A or FIG.
2B. When the sputtering target is divided, warpage of the
sputtering target can be relaxed in the attachment of the
sputtering target to the backing plate. In particular, when a film
is formed over a large substrate, such divided sputtering targets
can be suitably used for a sputtering target which is upsized in
accordance with the size of the large substrate. Needless to say,
one sputtering target may be attached to one backing plate.
[0037] It is preferable that the sputtering target which has been
subjected to the heat treatment be transferred, stored, and the
like in a high-purity oxygen gas atmosphere, a high-purity N.sub.2O
gas atmosphere, or an ultra dry air (having a dew point of
-40.degree. C. or lower, preferably -60.degree. C. or lower)
atmosphere, in order to prevent entry of impurities such as
moisture, hydrogen, or an alkali metal. The target may be covered
with a protective material formed of a material with low water
permeability such as a stainless steel alloy, and the above gas may
be introduced into a gap between the protective material and the
target. It is preferable that the oxygen gas and the N.sub.2O gas
do not contain water, hydrogen, and the like. Alternatively, the
purity of an oxygen gas or a N.sub.2O gas is preferably 6N
(99.9999%) or higher, more preferably 7N (99.99999%) or higher
(that is, the impurity concentration in the oxygen gas or the
N.sub.2O gas is 1 ppm or lower, preferably 0.1 ppm or lower).
[0038] Through the above process, the sputtering target described
in this embodiment can be manufactured. The sputtering target in
this embodiment can contain a small amount of impurities by using
the materials each of which is purified to have high purity in the
manufacturing process. Further, the concentration of impurities
contained in the oxide semiconductor film which is formed using the
target can also be reduced.
[0039] The above-described manufacture of the sputtering target is
preferably conducted in an inert gas atmosphere (a nitrogen
atmosphere or a rare gas atmosphere) without exposure to air.
[0040] Similarly, the sputtering target is set in a sputtering
apparatus in an inert gas atmosphere (a nitrogen atmosphere or a
rare gas atmosphere) without exposure to air. Accordingly,
hydrogen, moisture, an alkali metal, or the like can be prevented
from attaching to the sputtering target.
[0041] In addition, after the sputtering target is set in the
sputtering apparatus, dehydrogenation treatment is preferably
performed to remove hydrogen which remains on a surface of or
inside the target material. As the dehydrogenation treatment, a
method in which the inside of the film formation chamber is heated
to 200.degree. C. to 600.degree. C. under reduced pressure, a
method in which introduction and removal of nitrogen or an inert
gas are repeated while the inside of the film formation chamber is
heated, and the like can be given.
[0042] Moreover, in the sputtering apparatus in which the
sputtering target is set, it is preferable that the leakage rate be
set to 1.times.10.sup.-10 Pam.sup.3/sec or lower, entry of water as
an impurity be reduced with the use of, specifically, a cryopump as
an evacuation unit, and counter flow be also prevented.
[0043] With reference to FIGS. 3A to 3E, an example will be
described below in which a transistor is manufactured with the use
of a sputtering apparatus in which a sputtering target manufactured
in the above-described process is set. Also in a manufacturing
process of the transistor, it is preferable that impurities such as
a compound containing a hydrogen atom typified by H.sub.2O, a
compound containing an alkali metal, and a compound containing an
alkaline earth metal be prevented from entering an oxide
semiconductor film formed in the sputtering apparatus.
[0044] First, a conductive film is formed over a substrate 100
having an insulating surface, and then, a gate electrode layer 112
is formed through a first photolithography process and an etching
step.
[0045] An insulating film serving as a base film may be formed
between the substrate 100 and the gate electrode layer 112; in this
embodiment, a base film 101 is provided. The base film 101 has a
function of preventing diffusion of impurity elements (e.g., Na)
from the substrate 100 and can be formed from a film selected from
a silicon oxide film, a silicon oxynitride film, a silicon nitride
film, a hafnium oxide film, an aluminum oxide film, a gallium oxide
film, and a gallium aluminum oxide (Ga.sub.xAl.sub.2-xO.sub.3-y
(where x is greater than or equal to 0 and less than or equal to 2,
and y is greater than 0 and less than 1)) film. By provision of the
base film 101, impurity elements (e.g., Na) from the substrate 100
can be prevented from diffusing into an oxide semiconductor film
that is formed later. The structure of the base film is not limited
to a single-layer structure, and may be a layered structure of a
plurality of the above films.
[0046] Then, a gate insulating layer 102 is formed over the gate
electrode layer 112 by a sputtering method or a PCVD method (see
FIG. 3A). Also at the time of formation of the gate insulating
layer 102, it is preferable that entry of impurities such as a
compound containing an alkali metal and a compound containing an
alkaline earth metal be prevented, and the gate insulating layer
102 is formed without exposure to air after the base film 101 is
formed.
[0047] Then, after the gate insulating layer 102 is formed, a first
oxide semiconductor film having a thickness of greater than or
equal to 1 nm and less than or equal to 10 nm is formed over the
gate insulating layer 102 by a sputtering method without exposure
to air. In this embodiment, the first oxide semiconductor film is
formed to a thickness of 5 nm in an oxygen atmosphere, an argon
atmosphere, or a mixed atmosphere of argon and oxygen under
conditions where a target for an oxide semiconductor (a target for
an In--Ga--Zn-based oxide semiconductor containing In.sub.2O.sub.3,
Ga.sub.2O.sub.3, and ZnO at 1:1:2 [molar ratio]) is used, the
distance between the substrate and the target is 170 mm, the
substrate temperature is 250.degree. C., the pressure is 0.4 Pa,
and the direct current (DC) power source is 0.5 kW. The target for
an oxide semiconductor includes a sintered body of at least one
oxide selected from zinc oxide, aluminum oxide, gallium oxide,
indium oxide, and tin oxide, and the concentration of each of
alkali metals contained in the sintered body by SIMS is
5.times.10.sup.16 cm.sup.-3 or lower. In addition, the
concentration of Na contained in the sintered body by SIMS is
5.times.10.sup.16 cm.sup.-3 or lower, preferably 1.times.10.sup.16
cm.sup.-3 or lower, further preferably 1.times.10.sup.15 cm.sup.-3
or lower. In addition, the concentration of Li contained in the
sintered body by SIMS is 5.times.10.sup.15 cm.sup.-3 or lower,
preferably 1.times.10.sup.15 cm.sup.-3 or lower. In addition, the
concentration of K contained in the sintered body by SIMS is
5.times.10.sup.15 cm.sup.-3 or lower, preferably 1.times.10.sup.15
cm.sup.-3 or lower.
[0048] After the first oxide semiconductor film is formed, without
exposure to air, first heat treatment is performed by setting an
atmosphere where the substrate is placed to a nitrogen atmosphere
or dry air. The temperature of the first heat treatment is higher
than or equal to 400.degree. C. and lower than or equal to
750.degree. C. In addition, heating time of the first heat
treatment is longer than or equal to one minute and shorter than or
equal to 24 hours. By the first heat treatment, a first crystalline
oxide semiconductor film 108a is formed (see FIG. 3B).
[0049] Subsequently, after the first heat treatment, without
exposure to air, a second oxide semiconductor film having a
thickness greater than 10 nm is formed over the first crystalline
oxide semiconductor film 108a by a sputtering method. In this
embodiment, the second oxide semiconductor film is formed to a
thickness of 25 nm in an oxygen atmosphere, an argon atmosphere, or
a mixed atmosphere of argon and oxygen under conditions where a
target for an oxide semiconductor (a target for an In--Ga--Zn-based
oxide semiconductor containing In.sub.2O.sub.3, Ga.sub.2O.sub.3,
and ZnO at 1:1:2 [molar ratio]) is used, the distance between the
substrate and the target is 170 mm, the substrate temperature is
400.degree. C., the pressure is 0.4 Pa, and the direct current (DC)
power source is 0.5 kW. The target for an oxide semiconductor
includes a sintered body of at least one oxide selected from zinc
oxide, aluminum oxide, gallium oxide, indium oxide, and tin oxide,
and the concentration of each of alkali metals contained in the
sintered body by SIMS is 5.times.10.sup.16 cm.sup.-3 or lower. In
addition, the concentration of Na contained in the sintered body by
SIMS is 5.times.10.sup.16 cm.sup.-3 or lower, preferably
1.times.10.sup.16 cm.sup.-3 or lower, further preferably
1.times.10.sup.15 cm.sup.-3 or lower. In addition, the
concentration of Li contained in the sintered body by SIMS is
5.times.10.sup.15 cm.sup.-3 or lower, preferably 1.times.10.sup.15
cm.sup.-3 or lower. In addition, the concentration of K contained
in the sintered body by SIMS is 5.times.10.sup.15 cm.sup.-3 or
lower, preferably 1.times.10.sup.15 cm.sup.-3 or lower.
[0050] Note that it is preferable that entry of impurities such as
a compound containing a hydrogen atom typified by H.sub.2O, a
compound containing an alkali metal, and a compound containing an
alkaline earth metal be prevented at the time of deposition of the
first oxide semiconductor film and the second oxide semiconductor
film. Specifically, the distance (also called a TS distance)
between the substrate and the target is made large, in which case a
high-mass impurity element is eliminated and entry thereof at the
time of deposition is reduced; alternatively, the film formation
chamber is set to a high vacuum state, in which case H.sub.2O or
the like which is attached to the substrate is evaporated from a
surface on which the film is formed. Further, it is preferable that
impurities such as a compound containing a hydrogen atom typified
by H.sub.2O, a compound containing an alkali metal, and a compound
containing an alkaline earth metal be prevented from entering the
oxide semiconductor film by setting the substrate temperature at
the tune of deposition to higher than or equal to 250.degree. C.
and lower than or equal to 450.degree. C.
[0051] After the second oxide semiconductor film is formed, without
exposure to air, second heat treatment is performed by setting an
atmosphere where the substrate is placed to a nitrogen atmosphere
or dry air. The temperature of the second heat treatment is higher
than or equal to 400.degree. C. and lower than or equal to
750.degree. C. In addition, heating time of the second heat
treatment is longer than or equal to one minute and shorter than or
equal to 24 hours. By the second heat treatment, a second
crystalline oxide semiconductor film 108b is formed (see FIG.
3C).
[0052] Then, an oxide semiconductor stack of the first crystalline
oxide semiconductor film 108a and the second crystalline oxide
semiconductor film 108b is processed into an island-shaped oxide
semiconductor stack (see FIG. 3D).
[0053] The oxide semiconductor stack can be processed by etching
after a mask having a desired shape is formed over the oxide
semiconductor stack. The above mask can be formed by a method such
as photolithography. Alternatively, a method such as an inkjet
method may be used to form the mask.
[0054] For the etching of the oxide semiconductor stack, either wet
etching or dry etching may be employed. It is needless to say that
these may be combined.
[0055] After that, a conductive film for forming a source electrode
layer and a drain electrode layer (including a wiring formed in the
same layer as the source electrode layer and the drain electrode
layer) is formed over the oxide semiconductor stack and is
processed to form a source electrode layer 104a and a drain
electrode layer 104b.
[0056] Next, an insulating film 110a and an insulating film 110b
which cover the oxide semiconductor stack, the source electrode
layer 104a, and the drain electrode layer 104b are formed (see FIG.
3E). The insulating film 110a is formed using an oxide insulating
material, and after deposition, third heat treatment is preferably
performed. By the third heat treatment, oxygen is supplied from the
insulating film 110a to the oxide semiconductor stack. The third
heat treatment is performed in an inert atmosphere, an oxygen
atmosphere, a mixed atmosphere of oxygen and nitrogen, at a
temperature higher than or equal to 200.degree. C. and lower than
or equal to 400.degree. C., preferably higher than or equal to
250.degree. C. and lower than or equal to 320.degree. C. In
addition, heating time of the third heat treatment is longer than
or equal to one minute and shorter than or equal to 24 hours.
[0057] Through the above process, a bottom-gate transistor 150 is
formed.
[0058] The transistor 150 includes the base film 101, the gate
electrode layer 112, the gate insulating layer 102, the oxide
semiconductor stack including a channel formation region, the
source electrode layer 104a, the drain electrode layer 104b, and
the insulating film 110a, which are formed over the substrate 100
having the insulating surface. The source electrode layer 104a and
the drain electrode layer 104b are provided to cover the oxide
semiconductor stack. A region functioning as the channel formation
region is part of the oxide semiconductor stack which overlaps with
the gate electrode layer 112 with the gate insulating layer 102
interposed therebetween.
[0059] In a semiconductor layer (which refers to the above oxide
semiconductor stack) including the channel formation region of the
transistor 150 which is illustrated in FIG. 3E, the concentration
of Na observed by SIMS is 5.times.10.sup.16 cm.sup.-3 or lower,
preferably 1.times.10.sup.16 cm.sup.-3 or lower, further preferably
1.times.10.sup.15 cm.sup.-3 or lower. In the semiconductor layer
including the channel formation region of the transistor 150, the
concentration of Li observed by SIMS is 5.times.10.sup.15 cm.sup.-3
or lower, preferably 1.times.10.sup.15 cm.sup.-3 or lower. In the
semiconductor layer including the channel formation region of the
transistor 150, the concentration of K observed by SIMS is
5.times.10.sup.15 cm.sup.-3 or lower, preferably 1.times.10.sup.15
cm.sup.-3 or lower.
[0060] In the semiconductor layer including the channel formation
region of the transistor 150 illustrated in FIG. 3E, it is
preferable that the concentration of hydrogen observed by SIMS be
5.times.10.sup.19 cm.sup.-3 or lower, specifically
5.times.10.sup.18 cm.sup.-3 or lower.
[0061] The semiconductor layer including the channel formation
region of in the transistor 150 illustrated in FIG. 3E is a stack
of the first crystalline oxide semiconductor film 108a and the
second crystalline oxide semiconductor film 108b. The first
crystalline oxide semiconductor film 108a and the second
crystalline oxide semiconductor film 108b are c-axis aligned. Note
that the first crystalline oxide semiconductor film 108a and the
second crystalline oxide semiconductor film 108b comprise an oxide
including crystals with c-axis alignment (also referred to as
C-Axis Aligned Crystal (CAAC)), which has neither a single crystal
structure nor an amorphous structure. The first crystalline oxide
semiconductor film 108a and the second crystalline oxide
semiconductor film 108b partly include a crystal grain boundary and
are apparently different from an amorphous oxide semiconductor
film.
[0062] In the case of the transistor including a stack of a first
crystalline oxide semiconductor film and a second crystalline oxide
semiconductor film, the amount of change in threshold voltage of
the transistor between before and after a bias-temperature (BT)
stress test can be reduced even when the transistor is irradiated
with light; thus, such a transistor has stable electric
characteristics.
[0063] Note that although an example of a bottom-gate transistor is
illustrated in FIGS. 3A to 3E, the present invention is not limited
thereto and a top-gate transistor can also be manufactured, for
example.
REFERENCE NUMERALS
[0064] 100: substrate, 101: base film, 102: gate insulating layer,
104a: source electrode layer, 104b: drain electrode layer, 108a:
first crystalline oxide semiconductor film, 108b: second
crystalline oxide semiconductor film, 110a: insulating film, 110b:
insulating film, 112: gate electrode layer, 150: transistor, 850:
backing plate, 851: sputtering target, 851a: sputtering target,
851b: sputtering target, 851c: sputtering target, 851d: sputtering
target, 852: sputtering target, 852a: sputtering target, 852b:
sputtering target, 852c: sputtering target, 852d: sputtering
target, 852e: sputtering target, 852f: sputtering target, 852g:
sputtering target, 852h: sputtering target, and 852i: sputtering
target
[0065] This application is based on Japanese Patent Application
serial no. 2010-197509 filed with Japan Patent Office on Sep. 3,
2010, the entire contents of which are hereby incorporated by
reference.
* * * * *