U.S. patent application number 13/026852 was filed with the patent office on 2012-02-23 for reversible resistive memory using diodes formed in cmos processes as program selectors.
Invention is credited to Shine C. Chung.
Application Number | 20120044747 13/026852 |
Document ID | / |
Family ID | 45593990 |
Filed Date | 2012-02-23 |
United States Patent
Application |
20120044747 |
Kind Code |
A1 |
Chung; Shine C. |
February 23, 2012 |
REVERSIBLE RESISTIVE MEMORY USING DIODES FORMED IN CMOS PROCESSES
AS PROGRAM SELECTORS
Abstract
Junction diodes fabricated in standard CMOS logic processes can
be used as program selectors for reversible resistive memory cells
that can be programmed based on magnitude, duration, voltage-limit,
or current-limit of a supply voltage or current. These cells are
PCM, RRAM, CBRAM, or other memory cells that have a reversible
resistive element coupled to a diode. The diode can be constructed
by P+ and N+ active regions on an N well as the P and N terminals
of the diode. The memory cells can be used to construct a
two-dimensional memory array with the N terminals of the diodes in
a row connected as a wordline and the reversible resistive elements
in a column connected as a bitline. By applying a voltage or a
current to a selected bitline and to a selected wordline to turn on
the diode, a selected cell can be programmed into different states
reversibly based on magnitude, duration, voltage-limit, or
current-limit. The data in the reversible resistive memory can also
be read by turning on a selected wordline to couple a selected
bitline to a sense amplifier. The wordlines may have
high-resistivity local wordlines coupled to low-resistive global
wordlines through conductive contact(s) or via(s).
Inventors: |
Chung; Shine C.; (San Jose,
CA) |
Family ID: |
45593990 |
Appl. No.: |
13/026852 |
Filed: |
February 14, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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61375660 |
Aug 20, 2010 |
|
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61375660 |
Aug 20, 2010 |
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Current U.S.
Class: |
365/148 ; 257/4;
257/E45.001; 365/163 |
Current CPC
Class: |
G11C 13/0028 20130101;
H01L 27/2409 20130101; H01L 29/785 20130101; G11C 13/004 20130101;
G11C 11/1675 20130101; H01L 45/1233 20130101; G11C 13/0004
20130101; G11C 13/0002 20130101; G11C 2213/74 20130101; G11C
11/1659 20130101; H01L 45/144 20130101; G11C 13/0011 20130101; H01L
27/224 20130101; G11C 11/161 20130101; G11C 17/06 20130101; G11C
2013/0073 20130101; G11C 13/0007 20130101; G11C 13/0069 20130101;
H01L 45/06 20130101; G11C 13/003 20130101; G11C 2213/72
20130101 |
Class at
Publication: |
365/148 ;
365/163; 257/4; 257/E45.001 |
International
Class: |
G11C 11/00 20060101
G11C011/00; H01L 45/00 20060101 H01L045/00 |
Claims
1. A reversible resistive memory, comprising: a plurality of
reversible resistive cells, each of the reversible resistive cells
including a reversible resistive film and a diode as program
selector having at least a first active region with a first type of
dopant for a first terminal of the diode, and a second active
region with a second type of dopant for a second terminal of the
diode, both active regions being fabricated from sources or drains
of CMOS devices and residing in a common CMOS well, the first
terminal of the diode being coupled to a first terminal of the
reversible resistive film, the reversible resistive film being
programmable reversibly by conducting a current flowing through the
reversible resistive film, wherein the current is high and/or short
duration for programming one state and low and/or long duration for
programming another state; a plurality of local wordlines, each
coupled to a plurality of the reversible resistive cells via the
second terminal of the diodes and having a first resistivity; a
plurality of global wordlines, each coupled to at least one of the
local wordlines and having a second resistivity; and a plurality of
bitlines, each coupled to a plurality of the reversible resistive
cells via the second terminal of reversible resistive film.
2. A reversible resistive cell as recited in claim 1, wherein the
reversible resistive film is a phase-change film that has chemical
composition of Germanium (Ge), Antimony (Sb), and Tellurium
(Te).
3. A reversible resistive cell as recited in claim 2, wherein the
phase-change film has the chemical composition of Germanium (Ge),
Antimony (Sb), and Tellurium (Te) as GexSbyTez, where x+y+z=9, and
x=2+/-10%, y=2+/-10%, and z=5+-10%.
4. A reversible resistive cell as recited in claim 1, wherein the
reversible resistive film comprises a metal oxide between metal or
metal alloy electrodes.
5. A reversible resistive cell as recited in claim 1, wherein the
reversible resistive film comprises a solid-state electrolyte
between metal or metal alloy electrodes.
6. A reversible resistive memory as recited in claim 1, wherein the
local wordline is constructed at least in part of CMOS well.
7. A reversible resistive memory as recited in claim 1, wherein the
global wordline is constructed of metal.
8. A reversible resistive memory as recited in claim 1, wherein the
global wordline is coupled to the local wordline through at least
one of conductive via or contact.
9. A reversible resistive memory as recited in claim 1, wherein the
bitline is coupled to a first supply voltage line and the global
wordline is coupled to a second supply voltage line during program
or read, wherein the voltage between the first and second supply
voltages has larger magnitude or longer duration for program than
read.
10. A reversible resistive memory as recited in claim 1, wherein
the bitline is coupled to a first supply voltage line and the
global wordline is coupled to a second supply voltage line during
program, and wherein the voltage between the first and second
supply voltage lines has larger magnitude or longer duration for
programming into the one state than the another state.
11. A reversible resistive memory as recited in claim 1, wherein
the bitline is coupled to a first supply voltage line and the
global wordline is coupled to a second supply voltage line during
program, and wherein the voltage between the first and second
supply voltage lines has voltage-limit or current-limit to program
into one state.
12. A reversible resistive memory as recited in claim 1, wherein
the reversible resistive memory further comprising a plurality of
write bitline selectors to select a bitline coupled to a first
supply voltage line, and a plurality of wordline drivers to select
a local wordline coupled to a second supply voltage line to conduct
a current during program.
13. A reversible resistive memory as recited in claim 1, wherein
the reversible resistive memory further comprises a plurality of
read bitline selectors to select a bitline coupled to a sense
amplifier, and a plurality of wordline drivers to select a local
wordline coupled to a supply voltage line to conduct a current
through the sense amplifier during read.
14. An electronics system, comprising: a processor; and a
reversible resistive memory operatively connected to the processor,
the reversible resistive memory including at least: a plurality of
reversible resistive cells, each including a reversible resistive
film and a diode as program selector having at least a first active
region with a first type of dopant for a first terminal of the
diode, and a second active region with a second type of dopant for
a second terminal of the diode, both active regions being
fabricated from sources or drains of CMOS devices and residing in a
common CMOS well, the first terminal of the diode being coupled to
a first terminal of the reversible resistive film, the reversible
resistive film being programmable by conducting a current flowing
through the reversible resistive film and the program selector,
wherein the current is high and/or short duration for one state and
low and/or long duration for another state; a plurality of local
wordlines, each coupled to a plurality of the reversible resistive
cells via the second terminal of the diodes and having a first
resistivity; a plurality of global wordlines, each coupled to at
least one of the local wordlines and having a second resistivity;
and a plurality of bitlines, each coupled to a plurality of the
reversible resistive cells via the second terminal of reversible
resistive film.
15. An electronics system as recited in claim 14, wherein the
reversible resistive film is a phase-change film that has chemical
composition of Germanium (Ge), Antimony (Sb), and Tellurium
(Te).
16. An electronics system as recited in claim 14, wherein the
reversible resistive film comprises a metal oxide between metal or
metal alloy electrodes.
17. An electronics system as recited in claim 14, wherein the
reversible resistive film comprises a solid-state electrolyte
between metal or metal alloy electrodes.
18. An electronics system as recited in claim 14, wherein the local
wordline is constructed at least in part of CMOS well.
19. An electronics system as recited in claim 14, wherein the
global wordline is constructed of metal.
20. An electronics system as recited in claim 14, wherein the
electronics system is configured to periodically read content of
every cell and writes the content back.
21. A method for programming a reversible resistive memory,
comprising: providing a plurality of reversible resistive cells,
each including an reversible resistive film and a diode, the diode
serving as a program selector and having at least a first active
region with a first type of dopant for a first terminal of the
diode, and having a second active region with a second type of
dopant for a second terminal of the diode, both active regions
being fabricated from sources or drains of CMOS devices and
residing in a common CMOS well, the first terminal of the diode
being coupled to a first terminal of the reversible resistive film,
the reversible resistive film being programmable reversibly by
conducting a current flowing through the reversible resistive film;
providing a plurality of local wordlines, each coupled to a
plurality of the reversible resistive cells via the second terminal
of the diodes and having a first resistivity; providing a plurality
of global wordlines, each coupled to at least one of the local
wordlines and having a second resistivity; providing a plurality of
bitlines, each coupled to a plurality of the reversible resistive
cells via a second terminal of reversible resistive film; and
programming at least one of the reversible resistive cells by
applying voltages to a selected one of the global wordlines and to
a selected one of the bitlines, and generating a high and/or
short-duration current to reversibly program into one state and a
low and/or long-duration current to reversibly program into another
state.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority benefit of U.S. Provisional
Patent Application No. 61/375,653, filed on Aug. 20, 2010 and
entitled "Circuit and System of Using Junction Diode As Program
Selector for Resistive Devices in CMOS Logic Processes," which is
hereby incorporated herein by reference; and U.S. Provisional
Patent Application No. 61/375,660, filed on Aug. 20, 2010 and
entitled "Circuit and System of Using Polysilicon Diode As Program
Selector for Resistive Devices in CMOS Logic Processes," which is
hereby incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to programmable memory
devices, such as programmable resistive devices for use in memory
arrays.
[0004] 2. Description of the Related Art
[0005] A programmable resistive device is generally referred to a
device's resistance states that may change after means of
programming. Resistance states can also be determined by resistance
values. For example, a resistive device can be a One-Time
Programmable (OTP) device, such as electrical fuse, and the
programming means can apply a high voltage to induce a high current
to flow through the OTP element. When a high current flows through
an OTP element by turning on a program selector, the OTP element
can be programmed, or burned into a high or low resistance state
(depending on either fuse or anti-fuse).
[0006] An electrical fuse is a common OTP which is a programmable
resistive device that can be constructed from a segment of
interconnect, such as polysilicon, silicided polysilicon, silicide,
metal, metal alloy, or some combination thereof. The metal can be
aluminum, copper, or other transition metals. One of the most
commonly used electrical fuses is a CMOS gate, fabricated in
silicided polysilicon, used as interconnect. The electrical fuse
can also be one or more contacts or vias instead of a segment of
interconnect. A high current may blow the contact(s) or via(s) into
a very high resistance state. The electrical fuse can be an
anti-fuse, where a high voltage makes the resistance lower, instead
of higher. The anti-fuse can consist of one or more contacts or
vias with an insulator in between. The anti-fuse can also be a CMOS
gate coupled to a CMOS body with a thin gate oxide as
insulator.
[0007] The programmable resistive device can be a reversible
resistive device that can be programmed into a digital logic value
"0" or "1" repetitively and reversibly. The programmable resistive
device can be fabricated from phase change material, such as
Germanium(Ge), Antimony(Sb), and Tellurium(Te) with composition
Ge.sub.2Sb.sub.2Te.sub.5 (GST-225) or GeSbTe-like materials
including compositions of Indium (In), Tin (Sn), or Selenium (Se).
The phase change material can be programmed into a high resistance
amorphous state or a low resistance crystalline state by applying a
short and high voltage pulse or a long and low voltage pulse,
respectively. The reversible resistive device can be a Resistive
RAM (RRAM) with cells fabricated from metal oxides between
electrodes, such as Pt/NiO/Pt, TiN/TiOx/HfO2/TiN, TiN/ZnO/Pt. The
resistance states can be changed reversibly and determined by
polarity, magnitude, duration, or voltage/current-limit of pulse(s)
to generate or annihilate conductive filaments. Another
programmable resistive device similar to RRAM is a Conductive
Bridge RAM (CBRAM) that is based on electro-chemical deposition and
removal of metal ions in a thin solid-state electrolyte film. The
electrodes can be an oxidizable anode and an inert cathode and the
electrolyte can be Ag- or Cu-doped chalcogenide glass such as GeSe
or GeS, etc. The resistance states can be changed reversibly and
determined by polarity, magnitude, duration, or
voltage/current-limit of pulse(s) to generate or annihilate
conductive bridges. The programmable resistive device can be an
MRAM (Magnetic RAM) with cells fabricated from magnetic multi-layer
stacks that construct a Magnetic Tunnel Junction (MTJ). In a Spin
Transfer Torque MRAM (STT-MRAM) the direction of currents applied
to an MTJ determines parallel or anti-parallel states, and hence
low or high resistance states.
[0008] A conventional programmable resistive memory cell is shown
in FIG. 1. The cell 10 consists of a resistive element 11 and an
NMOS program selector 12. The resistive element 11 is coupled to
the drain of the NMOS 12 at one end, and to a positive voltage V+
at the other end. The gate of the NMOS 12 is coupled to a select
signal (Sel), and the source is coupled to a negative voltage V-.
When a high voltage is applied to V+ and a low voltage to V-, the
resistive device 10 can be programmed by raising the select signal
(Sel) to turn on the NMOS 12. One of the most common resistive
elements is a silicided polysilicon, the same material and
fabricated at the same time as a MOS gate. The size of the NMOS 12,
as program selector, needs to be large enough to deliver the
required program current for a few microseconds. The program
current for a silicided polysilicon is normally between a few
milliamps for a fuse with width of 40 nm to about 20 mA for a fuse
with width about 0.6 um. As a result, the cell size of an
electrical fuse using silicided polysilicon tends to be very
large.
[0009] Another conventional programmable resistive device 20 for
Phase Change Memory (PCM) is shown in FIG. 2(a). The PCM cell 20
has a phase change film 21 and a bipolar transistor 22 as program
selector with P+ emitter 23, N-base 27, and P-sub collector 25. The
phase change film 21 is coupled to the emitter 23 of the bipolar
transistor 22 at one end, and to a positive voltage V+ at the
other. The N-type base 27 of bipolar transistor 22 is coupled to a
negative voltage V-. The collector 25 is coupled to ground. By
applying a proper voltage between V+ and V- for a proper duration
of time, the phase change film 21 can be programmed into high or
low resistance states, depending on voltage and duration.
Conventionally, to program a phase-change memory to a high
resistance state (or reset state) requires about 3V for 50 ns and
consumes about 300 uA of current, or to program a phase-change
memory to a low resistance state (or set state) requires about 2V
for 300 ns and consumes about 100 uA of current.
[0010] FIG. 2(b) shows a cross section of a conventional bipolar
transistor 22. The bipolar transistor 22 includes a P+ active
region 23, a shallow N well 24, an N+ active region 27, a P-type
substrate 25, and a Shallow Trench Isolation (STI) 26 for device
isolation. The P+ active region 23 and N+ active region 27 couple
to the N well 24 are the P and N terminals of the emitter-base
diode of the bipolar transistor 22, while the P-type substrate 25
is the collector of the bipolar transistor 22. This cell
configuration requires an N well 24 be shallower than the STI 26 to
properly isolate cells from each other and needs 3-4 more masking
steps over the standard CMOS logic processes which makes it more
costly to fabricate.
[0011] Another programmable resistive device 20' for Phase Change
Memory (PCM) is shown in FIG. 2(c). The PCM cell 20' has a phase
change film 21' and a diode 22'. The phase change film 21' is
coupled between an anode of the diode 22' and a positive voltage
V+. A cathode of the diode 22' is coupled to a negative voltage V-.
By applying a proper voltage between V+ and V- for a proper
duration of time, the phase change film 21' can be programmed into
high or low resistance states, depending on voltage and duration.
As an example of use of a diode as program selector for each PCM
cell as shown in FIG. 2(c), see Kwang-Jin Lee et al., "A 90 nm 1.8V
512 Mb Diode-Switch PRAM with 266 MB/s Read Throughput,"
International Solid-State Circuit Conference, 2007, pp. 472-273.
Though this technology can reduce the PCM cell size to only 6.8
F.sup.2 (F stands for feature size), the diode requires very
complicated process steps, such as Selective Epitaxial Growth
(SEG), to fabricate, which would be very costly for embedded PCM
applications.
[0012] FIGS. 3(a) and 3(b) show several embodiments of an
electrical fuse element 80 and 84, respectively, fabricated from an
interconnect. The interconnect serves as a particular type of
resistive element. The resistive element has three parts: anode,
cathode, and body. The anode and cathode provide contacts for the
resistive element to be connected to other parts of circuits so
that a current can flow from the anode to cathode through the body.
The body width determines the current density and hence the
electro-migration threshold for a program current. FIG. 3(a) shows
a conventional electrical fuse element 80 with an anode 81, a
cathode 82, and a body 83. This embodiment has a large symmetrical
anode and cathode. FIG. 3(b) shows another conventional electrical
fuse element 84 with an anode 85, a cathode 86, and a body 87. This
embodiment has an asymmetrical shape with a large anode and a small
cathode to enhance the electro-migration effect based on polarity
and reservoir effects. The polarity effect means that the
electro-migration always starts from the cathode. The reservoir
effect means that a smaller cathode makes electro-migration easier
because the smaller area has lesser ions to replenish voids when
the electro-migration occurs. The fuse elements 80, 84 in FIGS.
3(a) and 3(b) are relatively large structures which makes them
unsuitable for some applications.
[0013] FIGS. 4(a) and 4(b) show programming a conventional MRAM
cell 210 into parallel (or state 0) and anti-parallel (or state 1)
by current directions. The MRAM cell 210 consists of a Magnetic
Tunnel Junction (MTJ) 211 and an NMOS program selector 218. The MTJ
211 has multiple layers of ferromagnetic or anti-ferromagnetic
stacks with metal oxide, such as Al.sub.2O.sub.3 or MgO, as an
insulator in between. The MTJ 211 includes a free layer stack 212
on top and a fixed layer stack 213 underneath. By applying a proper
current to the MTJ 211 with the program selector CMOS 218 turned
on, the free layer stack 212 can be aligned into parallel or
anti-parallel to the fixed layer stack 213 depending on the current
flowing into or out of the fixed layer stack 213, respectively.
Thus, the magnetic states can be programmed and the resultant
states can be determined by resistance values, lower resistance for
parallel and higher resistance for anti-parallel states. The
resistances in state 0 or 1 are about 5K.OMEGA. or 10K.OMEGA.,
respectively, and the program currents are about +/-100-200 .mu.A.
One example of programming an MRAM cell is described in T.
Kawahara, "2 Mb Spin-Transfer Torque RAM with Bit-by-Bit
Bidirectional Current Write and Parallelizing-Direction Current
Read," International Solid-State Circuit Conference, 2007, pp.
480-481.
SUMMARY OF THE INVENTION
[0014] Embodiments of programmable resistive device cells using
junction diodes as program selectors are disclosed. The
programmable resistive devices can be fabricated using standard
CMOS logic processes to reduce cell size and cost.
[0015] In one embodiment, a programmable resistive device and
memory can use P+/N well diodes as program selectors, where the P
and N terminals of the diode are P+ and N+ active regions residing
in an N well. The same P+ and N+ active regions are used to create
sources or drains of PMOS and NMOS devices, respectively.
Advantageously, the same N well can be used to house PMOS in
standard CMOS logic processes. By using P+/N well diodes in
standard CMOS processes, a small cell size can be achieved, without
incurring any special processing or masks. Thus, costs can be
reduced substantially for variously applications, such as embedded
applications.
[0016] The invention can be implemented in numerous ways, including
as a method, system, device, or apparatus (including graphical user
interface and computer readable medium). Several embodiments of the
invention are discussed below.
[0017] As a reversible resistive memory, one embodiment can, for
example, include at least a plurality of reversible resistive
cells. Each of the reversible resistive cells can include a
reversible resistive film and a diode as program selector. The
diode can have at least a first active region with a first type of
dopant for a first terminal of the diode, and a second active
region with a second type of dopant for a second terminal of the
diode, and both active regions being fabricated from sources or
drains of CMOS devices and residing in a common CMOS well. The
first terminal of the diode can be coupled to a first terminal of
the reversible resistive film, and the reversible resistive film
can be programmed reversibly by conducting a current flowing
through the reversible resistive film, wherein the current is high
and/or short duration for programming one state and low and/or long
duration for programming another state. The embodiment of the
reversible resistive memory can further include: a plurality of
local wordlines, each coupled to a plurality of the reversible
resistive cells via the second terminal of the diodes and having a
first resistivity; a plurality of global wordlines, each coupled to
at least one of the local wordlines and having a second
resistivity; and a plurality of bitlines, each coupled to a
plurality of the reversible resistive cells via the second terminal
of reversible resistive film.
[0018] As an electronics system, one embodiment can, for example,
include at least a processor; and a reversible resistive memory
operatively connected to the processor. The reversible resistive
memory can include at least a plurality of reversible resistive
cells. Each of the reversible resistive cells can include a
reversible resistive film and a diode as program selector. The
diode can have at least a first active region with a first type of
dopant for a first terminal of the diode, and a second active
region with a second type of dopant for a second terminal of the
diode, and both active regions being fabricated from sources or
drains of CMOS devices and residing in a common CMOS well. The
first terminal of the diode can be coupled to a first terminal of
the reversible resistive film. The reversible resistive film can be
programmable by conducting a current flowing through the reversible
resistive film and the program selector, wherein the current is
high and/or short duration for one state and low and/or long
duration for another state. The reversible resistive cells can also
include at least: a plurality of local wordlines, each coupled to a
plurality of the reversible resistive cells via the second terminal
of the diodes and having a first resistivity; a plurality of global
wordlines, each coupled to at least one of the local wordlines and
having a second resistivity; and a plurality of bitlines, each
coupled to a plurality of the reversible resistive cells via the
second terminal of reversible resistive film.
[0019] As a method for programming a reversible resistive memory,
one embodiment can, for example, include at least providing a
plurality of reversible resistive cells, each including an
reversible resistive film and a diode The diode can serve as a
program selector and can have at least a first active region with a
first type of dopant for a first terminal of the diode, and having
a second active region with a second type of dopant for a second
terminal of the diode. Both active regions can be fabricated from
sources or drains of CMOS devices and can reside in a common CMOS
well. The first terminal of the diode can be coupled to a first
terminal of the reversible resistive film, the reversible resistive
film can be programmable reversibly by conducting a current flowing
through the reversible resistive film. The embodiment of the method
can also include at least: providing a plurality of local
wordlines, each coupled to a plurality of the reversible resistive
cells via the second terminal of the diodes and having a first
resistivity; providing a plurality of global wordlines, each
coupled to at least one of the local wordlines and having a second
resistivity; providing a plurality of bitlines, each coupled to a
plurality of the reversible resistive cells via a second terminal
of reversible resistive film; and programming at least one of the
reversible resistive cells by applying voltages to a selected one
of the global wordlines and to a selected one of the bitlines, and
generating a high and/or short-duration current to reversibly
program into one state and a low and/or long-duration current to
reversibly program into another state.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The present invention will be readily understood by the
following detailed descriptions in conjunction with the
accompanying drawings, wherein like reference numerals designate
like structural elements, and in which:
[0021] FIG. 1 shows a conventional programmable resistive memory
cell.
[0022] FIG. 2(a) shows another conventional programmable resistive
device for Phase Change Memory (PCM) using bipolar transistor as
program selector.
[0023] FIG. 2(b) shows a cross section of a conventional Phase
Change Memory (PCM) using bipolar transistor as program
selector.
[0024] FIG. 2(c) shows another conventional Phase Change Memory
(PCM) cell using diode as program selector.
[0025] FIGS. 3(a) and 3(b) show several embodiments of an
electrical fuse element, respectively, fabricated from an
interconnect.
[0026] FIGS. 4(a) and 4(b) show programming a conventional MRAM
cell into parallel (or state 0) and anti-parallel (or state 1) by
current directions.
[0027] FIG. 5(a) shows a block diagram of a memory cell using a
junction diode according to the invention.
[0028] FIG. 5(b) shows a cross section of a junction diode as
program selector with STI isolation according to one
embodiment.
[0029] FIG. 5(c) shows a cross section of a junction diode as
program selector with CMOS gate isolation according to one
embodiment.
[0030] FIG. 5(d) shows a cross section of a junction diode as
program selector with SBL isolation according to one
embodiment.
[0031] FIG. 6(a) shows a cross section of a junction diode as
program selector with dummy CMOS gate isolation in SOI technologies
according to one embodiment.
[0032] FIG. 6(b) shows a cross section of a junction diode as
program selector with dummy CMOS gate isolation in FINFET
technologies according to one embodiment.
[0033] FIG. 7(a) shows an electrical fuse element according to one
embodiment.
[0034] FIG. 7(b) shows a top view of an electrical fuse coupled to
a junction diode with STI isolation in four sides.
[0035] FIG. 7(c) shows a top view of an electrical fuse coupled to
a junction diode with STI isolation in two sides and dummy CMOS
isolation in another two sides.
[0036] FIG. 7(d) shows a top view of an electrical fuse coupled to
a junction diode with dummy CMOS isolation in four sides.
[0037] FIG. 7(e) shows a top view of an electrical fuse coupled to
a junction diode with Silicide Block Layer isolation in four
sides.
[0038] FIG. 7(f) shows an abutted contact coupled between a
resistive element, P terminal of a junction diode, and metal in a
single contact.
[0039] FIG. 8(a) shows a top view of a metal fuse coupled to a
junction diode with dummy CMOS gate isolation.
[0040] FIG. 8(b) shows a top view of a metal fuse coupled to a
junction diode with 4 cells sharing one N well contact in each
side.
[0041] FIG. 8(c) shows a top view of a via1 fuse coupled to a
junction diode with 4 cells sharing one N well contact in each
side.
[0042] FIG. 8(d) shows a top view of a two-dimensional array of
via1 fuses using P+/N well diodes.
[0043] FIG. 9(a) shows a cross section of a programmable resistive
device cell using phase-change material as a resistive element,
with buffer metals and a P+/N well junction diode, according to one
embodiment.
[0044] FIG. 9(b) shows a top view of a PCM cell using a P+/N well
junction diode as program selector in accordance with one
embodiment.
[0045] FIG. 10 shows one embodiment of an MRAM cell using diodes as
program selectors in accordance with one embodiment.
[0046] FIG. 11(a) shows a top view of an MRAM cell with an MTJ as a
resistive element and with P+/N well diodes as program selectors in
standard CMOS processes in accordance with one embodiment.
[0047] FIG. 11(b) shows another top view of an MRAM cell with an
MTJ as a resistive element and with P+/N well diodes as program
selectors in a shallow well CMOS process in accordance with another
embodiment.
[0048] FIG. 12(a) shows one embodiment of a three-terminal
2.times.2 MRAM cell array using junction diodes as program
selectors and the condition to program the upper-right cell into 1
in accordance with one embodiment.
[0049] FIG. 12(b) shows alternative conditions to program the
upper-right cell into 1 in a 2.times.2 MRAM array in accordance
with one embodiment.
[0050] FIG. 13(a) shows one embodiment of a three-terminal
2.times.2 MRAM cell array using junction diodes as program
selectors and the condition to program the upper-right cell into 0
in accordance with one embodiment.
[0051] FIG. 13(b) shows alternative conditions to program the
upper-right cell into 0 in a 2.times.2 MRAM array in accordance
with one embodiment.
[0052] FIGS. 14(a) and 14(b) show one embodiment of programming 1
and 0 into the upper-right cell, respectively, in a two-terminal
2.times.2 MRAM cell array in accordance with one embodiment.
[0053] FIG. 15 shows a portion of a programmable resistive memory
constructed by an array of n-row by (m+1)-column non-MRAM cells and
n wordline drivers in accordance with one embodiment.
[0054] FIG. 16(a) shows a portion of a programmable resistive
memory constructed by an array of 3-terminal MRAM cells according
to one embodiment.
[0055] FIG. 16(b) shows another embodiment of constructing a
portion of MRAM memory with 2-terminal MRAM cells.
[0056] FIGS. 17(a), 17(b), and 17(c) show three other embodiments
of constructing reference cells for differential sensing.
[0057] FIG. 18(a) shows a schematic of a wordline driver circuit
according to one embodiment.
[0058] FIG. 18(b) shows a schematic of a bitline circuit according
to one embodiment.
[0059] FIG. 18(c) shows a portion of memory with an internal power
supply VDDP coupled to an external supply VDDPP and a core logic
supply VDD through power selectors.
[0060] FIG. 19(a) shows one embodiment of a schematic of a
pre-amplifier according to one embodiment.
[0061] FIG. 19(b) shows one embodiment of a schematic of an
amplifier according to one embodiment.
[0062] FIG. 19(c) shows a timing diagram of the pre-amplifier and
the amplifier in FIGS. 19(a) and 19(b), respectively.
[0063] FIG. 20(a) shows another embodiment of a pre-amplifier,
similar to the pre-amplifier in FIG. 18(a).
[0064] FIG. 20(b) shows level shifters according to one
embodiment.
[0065] FIG. 20(c) shows another embodiment of an amplifier with
current-mirror loads.
[0066] FIG. 21(a) depicts a method of programming a programmable
resistive memory in a flow chart according to one embodiment.
[0067] FIG. 21(b) depicts a method of reading a programmable
resistive memory in a flow chart according to one embodiment.
[0068] FIG. 22 shows a processor system according to one
embodiment.
DETAILED DESCRIPTION OF THE INVENTION
[0069] Embodiments disclosed herein use a P+/N well junction diode
as program selector for a programmable resistive device. The diode
can comprise P+ and N+ active regions on an N well. Since the P+
and N+ active regions and N well are readily available in standard
CMOS logic processes, these devices can be formed in an efficient
and cost effective manner. There are no additional masks or process
steps to save costs. The programmable resistive device can also be
included within an electronic system.
[0070] FIG. 5(a) shows a block diagram of a memory cell 30 using a
junction diode according to one embodiment. In particular, the
memory cell 30 includes a resistive element 30a and a junction
diode 30b. The resistive element 30a can be coupled between an
anode of the junction diode 30b and a positive voltage V+. A
cathode of the junction diode 30b can be coupled to a negative
voltage V-. In one implementation, the memory cell 30 can be a fuse
cell with the resistive element 30a operating as an electrical
fuse. The junction diode 30b can serve as a program selector. The
junction diode can be constructed from a P+/N well in standard CMOS
processes using a P-type substrate. The P+ and N+ active regions
serve as the anode and cathode of the diode are the sources or
drains of CMOS devices. The N well is a CMOS well to house PMOS
devices. Alternatively, the junction diode can be constructed from
N+/P well in triple-well or CMOS processes using an N-type
substrate. The coupling of the resistive element 30a and the
junction diode 30b between the supply voltages V+ and V- can be
interchanged. By applying a proper voltage between V+ and V- for a
proper duration of time, the resistive element 30a can be
programmed into high or low resistance states, depending on voltage
and duration, thereby programming the memory cell 30 to store a
data value (e.g., bit of data). The P+ and N+ active regions of the
diode can be isolated by using a dummy CMOS gate, Shallow Trench
Isolation (STI) or Local Oxidation (LOCOS), or Silicide Block Layer
(SBL).
[0071] Electrical fuse cell can be used as an example to illustrate
the key concepts according to one embodiment. FIG. 5(b) shows a
cross section of a diode 32 using a P+/N well diode as program
selector with Shallow Trench Isolation (STI) isolation in a
programmable resistive device. P+ active region 33 and N+ active
region 37, constituting the P and N terminals of the diode 32
respectively, are sources or drains of PMOS and NMOS in standard
CMOS logic processes. The N+ active region 37 is coupled to an N
well 34, which houses PMOS in standard CMOS logic processes.
P-substrate 35 is a P-type silicon substrate. STI 36 isolates
active regions for different devices. A resistive element (not
shown in FIG. 5(b)), such as electrical fuse, can be coupled to the
P+ region 33 at one end and to a high voltage supply V+ at the
other end. To program this programmable resistive device, a high
voltage is applied to V+, and a low voltage or ground is applied to
the N+ region 37. As a result, a high current flows through the
fuse element and the diode 32 to program the resistive device
accordingly.
[0072] FIG. 5(c) shows a cross section of another embodiment of a
junction diode 32' as program selector with dummy CMOS gate
isolation. Shallow Trench Isolation (STI) 36' provides isolation
among active regions. An active region 31' is defined between STI
36', where the N+ and P+ active regions 37' and 33' are further
defined by a combination of a dummy CMOS gate 39', P+ implant layer
38', and N+ implant (the complement of the P+ implant 38'),
respectively, to constitute the N and P terminals of the diode 32'.
The diode 32' is fabricated as a PMOS-like device with 37', 39',
33', and 34' as source, gate, drain, and N well, except that the
source 37' is covered by an N+ implant, rather than a P+ implant
38'. The dummy MOS gate 39', preferably biased at a fixed voltage,
only serves for isolation between P+ active region 33' and N+
active region 37' during fabrication. The N+ active 37' is coupled
to an N well 34', which houses PMOS in standard CMOS logic
processes. P-substrate 35' is a P-type silicon substrate. A
resistive element (not shown in FIG. 5(c)), such as electrical
fuse, can be coupled to the P+ region 33' at one end and to a high
voltage supply V+ at the other end. To program this programmable
resistive device, a high voltage is applied to V+, and a low
voltage or ground is applied to the N+ active region 37'. As a
result, a high current flows through the fuse element and the diode
32' to program the resistive device accordingly. This embodiment is
desirable for isolation for small size and low resistance.
[0073] FIG. 5(d) shows a cross section of another embodiment of a
junction diode 32'' as program selector with Silicide Block Layer
(SBL) isolation. FIG. 5(d) is similar to 5(c), except that the
dummy CMOS gate 39' in FIG. 5(c) is replaced by SBL 39'' in FIG.
5(d) to block a silicide grown on the top of active region 31''.
Without a dummy MOS gate or a SBL, the N+ and P+ active regions
would be undesirably electrically shorted by a silicide on the
surface of the active region 31''.
[0074] FIG. 6(a) shows a cross section of another embodiment of a
junction diode 32'' as a program selector in Silicon-On-Insulator
(SOI) technologies. In SOI technologies, the substrate 35'' is an
insulator such as SiO.sub.2 or similar material with a thin layer
of silicon grown on top. All NMOS and PMOS are in silicon wells
isolated by SiO.sub.2 or similar material to each other and to the
substrate 35''. One-piece active region 31'' is divided into an N+
active region 37'', P+ active region 33'', and body 34'' by a
combination of a dummy CMOS gate 39'', P+ implant 38'', and N+
implant (the complement of P+ implant 38''). Consequently, the N+
active region 37'' and P+ active region 33'' constitute the N and P
terminals of the junction diode 32''. The N+ active region 37'' and
P+ active region 33'' can be the same as sources or drains of NMOS
and PMOS devices, respectively, in standard CMOS processes.
Similarly, the dummy CMOS gate 39'' can be the same CMOS gate
fabricated in standard CMOS processes. The dummy MOS gate 39'',
which can be biased at a fixed voltage, only serves for isolation
between P+ active region 33'' and N+ active region 37'' during
fabrication. The N+ active region 37'' can be coupled to a low
voltage supply V- and to an N well 34'' that houses PMOS in
standard CMOS SOI processes. A resistive element (not shown in FIG.
6(a)), such as an electrical fuse, can be coupled to the P+ active
region 33'' at one end and to a high voltage supply V+ at the other
end. To program the electrical fuse cell, a high and low voltages
are applied to V+ and V-, respectively, to conduct a high current
flowing through the fuse element and the junction diode 32'' to
program the resistive device accordingly. Other embodiments of
isolations in CMOS bulk technologies, such as STI, dummy MOS gate,
or SBL in one to four (1-4) or any sides, can be readily applied to
CMOS SOI technologies accordingly.
[0075] FIG. 6(b) shows a cross section of another embodiment of a
junction diode 45 as a program selector in FinFET technologies.
FinFET refers to a fin-based, multigate transistor. FinFET
technologies are similar to the conventional CMOS except that thin
and tall silicon islands can be raised above the silicon substrate
to serve as the bulks of CMOS devices. The bulks are divided into
source, drain, and channel regions by polysilicon or non-aluminum
metal gates like in the conventional CMOS. The primary difference
is that the MOS devices are raised above the substrate so that
channel widths are the height of the islands, though the direction
of current flow is still in parallel to the surface. In an example
of FinFET technology shown in FIG. 6(b), the silicon substrate 35
is an epitaxial layer built on top of an insulator like SOI or
other high resistivity silicon substrate. The silicon substrate 35
can then be etched into several tall rectangular islands 31-1,
31-2, and 31-3. With proper gate oxide grown, the islands 31-1,
31-2, and 31-3 can be patterned with MOS gates 39-1, 39-2, and
39-3, respectively, to cover both sides of raised islands 31-1,
31-2, and 31-3 and to define source and drain regions. The source
and drain regions formed at the islands 31-1, 31-2, and 31-3 are
then filled with silicon, such as fill 40-1 and 40-2, so that the
combined source or drain areas are large enough to allow contacts.
The fill 40-1 and 40-2 areas in FIG. 6(b) are for illustrative
purpose to reveal the cross section and can, for example, be filled
up to the surface of the islands 31-1, 31-2, and 31-3. In this
embodiment, active regions 33-1,2,3 and 37-1,2,3 are covered by a
P+ implant 38 and N+ implant (the complement of P+ implant 38),
respectively, rather than all covered by P+ implant 38 as PMOS in
the conventional FinFET, to constitute the P and N terminals of the
junction diode 45. The N+ active region 37-1,2,3 is coupled to a
low voltage supply V-. A resistive element (not shown in FIG.
6(b)), such as an electrical fuse, is coupled to the P+ active
region 33-1,2,3 at one end and to a high voltage supply V+ at the
other end. To program the electrical fuse, high and low voltages
are applied between V+ and V-, respectively, to conduct a high
current flowing through the resistive element and the junction
diode 45 to program the resistive device accordingly. Other
embodiments of isolations in CMOS bulk technologies, such as STI,
dummy MOS gate or SBL, can be readily applied to FinFET
technologies accordingly.
[0076] FIG. 7(a) shows a top view of an electrical fuse element 88
according to one embodiment. The electrical fuse element 88 can,
for example, by used as the resistive element 31a illustrated in
FIGS. 5(a). The electrical fuse element 88 includes an anode 89, a
cathode 90, and a body 91. In this embodiment, the electrical fuse
element 88 is a bar shape with a small anode 89 and cathode 90 to
reduce area. The anode 89 and cathode 90 may protrude from the body
91 to make contacts. The contact number can be one (1) for both the
anode 89 and the cathode 90 so that the area can be very small.
However, the contact area for anode 89 is often made larger so that
the anode 89 can resist electro-migration more than the cathode 90.
The fuse body 91 can have about 1-5 squares, namely, the length to
width ratio is about 1-to-5, to optimize cell area and program
current. The fuse element 88 has a P+ implant 92 covering half of
the body 91 and the cathode 90, while an N+ implant over the rest
of area. This embodiment makes the fuse element 88 behave like a
reverse biased diode to increase resistance after being programmed,
when silicide on top is depleted by electro-migration, ion
diffusion, silicide decomposition, and other effects.
[0077] The above scheme can be realized for those fuse elements
consisting of polysilicon, silicided polysilicon, or other CMOS
gate material so that P+ and N+ implants can create a diode. For
example, if a metal-gate CMOS has a sandwich structure of
polysilicon between metal alloy layers, the metal alloy layers may
be blocked by masks generated from layout database to create a
diode in the fuse elements.
[0078] FIGS. 7(b), 7(c), 7(d), 7(e), and 7(f) show top views of
P+/N well diodes constructed with different embodiments of
isolation and fuse elements. Without isolation, P+ and N+ active
regions would be shorted together by silicide grown on top. The
isolation can be provided by STI, dummy CMOS gate, SBL, or some
combination thereof from one to four (1-4) or any sides. The P+ and
N+ active regions that act as P and N terminals of the diodes are
sources or drains of CMOS devices. Both the P+ and N+ active
regions reside in an N well, which is the same N well that can be
used to house PMOS in standard CMOS processes. The N+ active region
of the diodes in multiple cells can be shared, though for
simplicity FIGS. 7(b)-7(f) show only one N+ active region for one
P+ active region.
[0079] FIG. 7(b) shows a top view of one embodiment of a P+/N well
diode 40 in an electrical fuse cell having active regions 43 and 44
with STI 49 isolation in four sides. A fuse element 42 is coupled
to the active region 43 through a metal 46. The active regions 43
and 44 are covered by a P+ implant 47 and N+ implant (the
complement of P+ implant 47), respectively, to constitute the P and
N terminals of the diode 40. The active regions 43 and 44 of the
diode 40 reside in an N well 45, the same N well can be used to
house PMOS in standard CMOS processes. In this embodiment, the P+
active region 43 and N+ active region 44 are surrounded by an STI
49 in four (4) sides. Since the STI 49 is much deeper than either
the N+ or P+ active region, the resistance of the diode 40 between
the P+ active region 43 and N+ active region 44 is high.
[0080] FIG. 7(c) shows a top view of another embodiment of a P+/N
well diode 50 in an electrical fuse cell having active regions 53
and 54 with an STI 59 isolation in two sides and a dummy MOS gate
58 in another two sides. One-piece active region 51 with two STI
slots 59 in the right and left is divided into a peripheral 54 and
a central 53 regions by two MOS gates 58 on top and bottom. The
central active region 53 is covered by a P+ implant 57, while the
peripheral active region 54 is covered by an N+ implant layer (the
complement of the P+ implant), which constitute the P and N
terminals of the diode 50. The active region 51 resides in an N
well 55, the same N well can be used to house PMOS in standard CMOS
processes. A fuse element 52 is coupled to the P+ active region 53.
The dummy MOS gate 58 is preferably biased to a fixed voltage. In
this embodiment, the P+ active region 53 and N+ active region 54
are surrounded by STI 59 in left and right sides and the dummy MOS
gate 58 on top and bottom. The isolation provided by the dummy MOS
gate 58 can provide lower resistance than the STI isolation,
because the space between the P+ active region 53 and N+ active
region 54 may be narrower and there is no oxide to block the
current path underneath the silicon surface.
[0081] FIG. 7(d) shows a top view of yet another embodiment of P+/N
well diode 60 in an electrical fuse cell with dummy MOS gate 68
providing isolation in four sides. One-piece active region 61 is
divided into a center active region 63 and a peripheral active
region 64 by a ring-shape MOS gate 68. The center active region 63
is covered by a P+ implant 67 and the peripheral active region 64
is covered by an N+ implant (the complement of the P+ implant 67),
respectively, to constitute the P and N terminals of the diode 60.
The active region 61 resides in an N well, the same N well can be
used to house PMOS in standard CMOS processes. A fuse element 62 is
coupled to the P+ active region 63 through a metal 66. The dummy
MOS gate 68, which can be biased at a fixed voltage, provides
isolation between P+ active region 63 and N+ active region 64
regions on four sides. This embodiment offers low resistance
between P and N terminals of the diode 60.
[0082] FIG. 7(e) shows a top view of yet another embodiment of a
P+/N well diode 60' in an electrical fuse cell having active
regions 63' and 64' with Silicide Block Layer (SBL) 68' providing
isolation in four sides. One-piece active region 61' is divided
into a center active region 63' and a peripheral active region 64'
by an SBL ring 68'. The center active region 63' and the peripheral
active region 64' are covered by a P+ implant 67' and an N+ implant
(the complement of P+ implant 67'), respectively, to constitute the
P and N terminals of the diode 60'. The boundaries between the P+
implant 67' and N+ implants are about in the middle of the SBL ring
68'. The active region 61' resides in an N well 65'. A fuse element
62' is coupled to the P+ active region 63' through a metal 66'. The
SBL ring 68' blocks silicide formation on the top of the active
regions between P+ active region 63' and N+ active region 64'. In
this embodiment, the P+ active region 63' and N+ active region 64'
are isolated in four sides by P/N junctions. This embodiment has
low resistance between the P and N terminals of the diode 60',
though the SBL may be wider than a MOS gate. In another embodiment,
there is a space between the P+ implant 67' and the N+ implant that
is covered by the SBL ring 68'.
[0083] FIG. 7(f) shows a top view of another embodiment of a P+/N
well diode 70 in an electrical fuse cell with an abutted contact.
Active regions 73 and 74, which are isolated by an STI 79, are
covered by a P+ implant 77 and an N+ implant (the complement of the
P+ implant 77), respectively, to constitute the P and N terminals
of the diode 70. Both of the active regions 73 and 74 reside in an
N well 75, the same N well can be used to house PMOS in standard
CMOS processes. A fuse element 72 is coupled to the P+ active
region 73 through a metal 76 in a single contact 71. This contact
71 is quite different from the contacts in FIGS. 7(b), (c), (d),
and (e) where a contact can be used to connect a fuse element with
a metal and then another contact is used to connect the metal with
a P+ active region. By connecting a fuse element directly to an
active region through a metal in a single contact, the cell area
can be reduced substantially. This embodiment for a fuse element
can be constructed by a CMOS gate, including polysilicon, silicided
polysilicon, or non-aluminum metal CMOS gate, that allows an
abutted contact.
[0084] In general, a polysilicon or silicide polysilicon fuse is
more commonly used as an electrical fuse because of its lower
program current than metal or contact/via fuses. However, a metal
fuse has some advantages such as smaller size and wide resistance
ratio after being programmed. Metal as a fuse element allows making
contacts directly to a P+ active region thus eliminating one
additional contact as compared to using a polysilicon fuse. In
advanced CMOS technologies with feature size less than 65 nm, the
program voltage for metal fuses can be lower than 3.3V, which makes
metal fuse a viable solution.
[0085] FIG. 8(a) shows a top view of P+/N well diode 60'' having a
metal1 fuse with dummy CMOS gate isolation. One-piece active region
61 is divided into a center active region 63 and a peripheral
active region 64 by a ring-shape MOS gate 68. The center active
region 63 is covered by a P+ implant 67 and the peripheral active
region 64 is covered by an N+ implant (the complement of the P+
implant 67), respectively, to constitute the P and N terminals of
the diode 60''. The active region 61 resides in an N well 65, the
same N well can be used to house PMOS in standard CMOS processes. A
metal1 fuse element 62'' is coupled to the P+ region 63 directly.
The ring-shape MOS gate 68, which provides dummy CMOS gate
isolation, can be biased at a fixed voltage, and can provide
isolation between P+ active 63 and N+ active 64 regions in four
sides. In one embodiment, the length to width ratio of a metal fuse
is about 1-5.
[0086] The size of the metal fuse cell in FIG. 8(a) can be further
reduced, if the turn-on resistance of the diode is not crucial.
FIG. 8(b) shows a top view of a row of metal fuse cells 60'''
having four metal fuse cells that share one N well contact in each
side in accordance with one embodiment. Metal1 fuse 69 has an anode
62', a metal1 body 66', and a cathode coupled to an active region
64' covered by a P+ implant 67' that acts as the P terminal of a
diode. The active region 61' resides in an N well 65'. Another
active region 63' covered by an N+ implant (complement of P+
implant 67') acts as N terminal of the diode. Four diodes are
isolated by STI 68' and share one N+ active region 63' each side.
The N+ active regions 63' are connected by a metal2 running
horizontally, and the anode of the diode is connected by a metal3
running vertically. If metal1 is intended to be programmed, other
types of metals in the conduction path should be wider. Similarly,
more contacts and vias should be put in the conduction path to
resist programming. It should be noted metal1 as a metal fuse in
FIG. 8(b) is for illustrative purposes, those skilled in the art
understand that the above description can be applied to any metals,
such as metal2, metal3, or metal4 in other embodiments. Similarly,
those skilled in the art understand that the isolation, metal
scheme, and the number of cells sharing one N+ active may vary in
other embodiments.
[0087] Contact or via fuses may become more viable for advanced
CMOS technologies with feature size less than 65 nm, because small
contact/via size makes program current rather low. FIG. 8(c) shows
a top view of a row of four via1 fuse cells 70 sharing N-type well
contacts 73a and 73b in accordance with one embodiment. Via1 fuse
cell 79 has a via1 79a coupled to a metal1 76 and a metal2 72.
Metal2 72 is coupled to a metal3 through via2 89 running vertically
as a bitline. Metal1 76 is coupled to an active region 74 covered
by a P+ implant 77 that acts as the P terminal of a diode 71.
Active regions 73a and 73b covered by an N+ implant (complement of
P+ implant 77) serves as the N terminal of the diode 71 in via1
fuse cell 79. Moreover, the active regions 73a and 73b serve as the
common N terminal of the diodes in the four-fuse cell 70. They are
further coupled to a metal4 running horizontally as a wordline. The
active regions 74, 73a, and 73b reside in the same N well 75. Four
diodes in via1 fuse cells 70 have STI 78 isolation between each
other. If via1 is intended to be programmed, more contacts and more
other kinds of vias should be put in the conduction path. And
metals in the conduction path should be wider and contain large
contact/via enclosures to resist programming. Via1 as a via fuse in
FIG. 8(c) is for illustrative purpose, those skilled in the art
understand that the above description can be applied to any kinds
of contacts or vias, such as via2, via3, or via4, etc. Similarly,
those skilled in the art understand that the isolation, metal
scheme, and the number of cells sharing one N+ active may vary in
other embodiments.
[0088] FIG. 8(d) shows a top view of an array of 4.times.5 via1
fuses with dummy CMOS gate isolation in accordance with one
embodiment. The one-row via fuse shown in FIG. 8(c) can be extended
into a two-dimensional array 90 as shown in FIG. 8(d). The array 90
has four rows of active regions 91, each residing in a separate N
well, and five columns of via fuse cells 96, isolated by dummy CMOS
gates 92 between active regions. Each via fuse cell 96 has one
contact 99 on an active region covered by a P+ implant 94 that acts
as the P terminal of a diode, which is further coupled to a metal2
bitline running vertically. Active regions in two sides of the
array 90 are covered by N+ implant 97 to serve as the N terminals
of the diodes in the same row, which is further coupled to metal3
as wordlines running horizontally. To program a via fuse, select
and apply voltages to the desired wordline and bitline to conduct a
current from metal2 bitline, via1, metal1 , contact, P+ active, N+
active, to metal3 wordline. To ensure only via1 is programmed,
metals can be made wider and the numbers of other types of vias or
contact can be more than one. To simplify the drawing,
metal1-via1-metal2 connection can be referred to FIG. 8(c) and,
therefore, is not shown in each cell in FIG. 8(d). Those skilled in
the art understand that various types of contact or vias can be
used as resistive elements and the metal schemes may change in
other embodiments. Similarly, the number of cells in rows and
columns, the numbers of rows or columns in an array, and the
numbers of cells between N+ active may vary in other
embodiments.
[0089] FIG. 9(a) shows a cross section of a programmable resistive
device cell 40 using phase-change material as a resistive element
42, with buffer metals 41 and 43, and a P+/N well diode 32,
according to one embodiment. The P+/N well diode 32 has a P+ active
region 33 and N+ active region 37 on an N well 34 as P and N
terminals. The isolation between the P+ active region 33 and N+
active region 37 is an STI 36. The P+ active region 33 of the diode
32 is coupled to a lower metal 41 as a buffer layer through a
contact plug 40-1. The lower metal 41 is then coupled to a thin
film of phase change material 42 (e.g., GST film). An upper metal
43 also couples to the thin film of the phase-change material 42
through a contact plug 40-2. The upper metal 43 is coupled to
another metal 44 to act as a bitline (BL) through a plug 40-3. The
phase-change film 42 can have a chemical composition of Germanium
(Ge), Antimony (Sb), and Tellurium (Te), such as
Ge.sub.xSb.sub.yTe.sub.z (x, y and z are any arbitrary numbers), or
as one example Ge.sub.2Sb.sub.2Te.sub.5 (GST-225). The GST film can
be doped with at least one or more of Indium (In), Tin (Sn), or
Selenium (Se) to enhance performance. The phase-change cell
structure can be substantially planar, which means the phase-change
film 42 has an area that is larger than the film contact area
coupled to the program selector, or the height from the surface of
the silicon substrate to the phase-change film 42 is much smaller
than the dimensions of the film parallel to silicon substrate. In
this embodiment, the active area of phase-change film 42 is much
larger than the contact area so that the programming
characteristics can be more uniform and reproducible. The
phase-change film 42 is not a vertical structure and does not sit
on top of a tall contact, which can be more suitable for embedded
phase-change memory applications, especially when the diode 32
(i.e., junction diode) is used as program selector to make the cell
size very small. For those skilled in the art understand that the
structure and fabrication processes may vary and that the
structures of phase-change film (e.g., GST film) and buffer metals
described above are for illustrative purpose.
[0090] FIG. 9(b) shows a top view of a PCM cell using a junction
diode as program selector having a cell boundary 80 in accordance
with one embodiment. The PCM cell has a P+/N well diode and a
phase-change material 85, which can be a GST film. The P+/N well
diode has active regions 83 and 81 covered by a P+ implant 86 and
an N+ implant (complement of P+ implant 86), respectively, to serve
as the anode and cathode. Both active regions 81 and 83 reside on
an N well 84, the same N well can be used to house PMOS in standard
CMOS processes. The anode is coupled to the phase-change material
85 through a metal1 82. The phase-change material 85 is further
coupled to a metal3 bitline (BL) 88 running vertically. The cathode
of the P+/N well diode (i.e., active region 81) is connected by a
metal2 wordline (WL) 87 running horizontally. By applying a proper
voltage between the bitline 88 and the wordline 87 for a suitable
duration, the phase-change material 85 can be programmed into a 0
or 1 state accordingly. Since programming the PCM cell is based on
raising the temperature rather than electro-migration as with an
electrical fuse, the phase-change film (e.g., GST film) can be
symmetrical in area for both anode and cathode. Those skilled in
the art understand that the phase-change film, structure, layout
style, and metal schemes may vary in other embodiments.
[0091] Programming a phase-change memory (PCM), such as a
phase-change film, depends on the physical properties of the
phase-change film, such as glass transition and melting
temperatures. To reset, the phase-change film needs to be heated up
beyond the melting temperature and then quenched. To set, the
phase-change film needs to be heated up between melting and glass
transition temperatures and then annealed. A typical PCM film has
glass transition temperature of about 200.degree. C. and melting
temperature of about 600.degree. C. These temperatures determine
the operation temperature of a PCM memory because the resistance
state may change after staying in a particular temperature for a
long time. However, most applications require retaining data for 10
years for the operation temperature from 0 to 85.degree. C. or even
from -40 to 125.degree. C. To maintain cell stability over the
device's lifetime and over such a wide temperature range, periodic
reading and then writing back data into the same cells can be
performed. The refresh period can be quite long, such as longer
than a second (e.g., minutes, hours, days, weeks, or even months).
The refresh mechanism can be generated inside the memory or
triggered from outside the memory. The long refresh period to
maintain cell stability can also be applied to other emerging
memories such as RRAM, CBRAM, and MRAM, etc.
[0092] FIG. 10 shows one embodiment of an MRAM cell 310 using
diodes 317 and 318 as program selectors in accordance with one
embodiment. The MRAM cell 310 in FIG. 10 is a three-terminal MRAM
cell. The MRAM cell 310 has an MTJ 311, including a free layer
stack 312, a fixed layer stack 313, and a dielectric film in
between, and the two diodes 317 and 318. The free layer stack 312
is coupled to a supply voltage V, and coupled to the fixed layer
stack 313 through a metal oxide such as Al.sub.2O.sub.3 or MgO. The
diode 317 has the N terminal coupled to the fixed layer stack 313
and the P terminal coupled to V+ for programming a 1. The diode 318
has the P terminal coupled to the fixed layer stack 313 and the N
terminal coupled to V- for programming a 0. If V+ voltage is higher
than V, a current flows from V+ to V to program the MTJ 311 into
state 1. Similarly, if V- voltage is lower than V, a current flows
from V to V- to program the MTJ 311 into state 0. During
programming, the other diode is supposedly cutoff. For reading, V+
and V- can be both set to 0V and the resistance between node V and
V+/V- can be sensed to determine whether the MTJ 311 is in state 0
or 1.
[0093] FIG. 11(a) shows a cross section of one embodiment of an
MRAM cell 310 with MTJ 311 and junction diodes 317 and 318 as
program selectors in accordance with one embodiment. MTJ 311 has a
free layer stack 312 on top and a fixed layer stack 313 underneath
with a dielectric in between to constitute a magnetic tunneling
junction. Diode 317 is used to program 1 and diode 318 is used to
program 0. Diodes 317 and 318 have P+ and N+ active regions on N
wells 321 and 320, respectively, the same N wells to house PMOS in
standard CMOS processes. Diode 317 has a P+ active region 315 and
N+ active region 314 to constitute the P and N terminals of the
program-1 diode 317. Similarly, diode 318 has a P+ active 316 and
N+ active 319 to constitute the P and N terminals of the program-0
diode 318. FIG. 11(a) shows STI 330 isolation for the P and N
terminals of diodes 317 and 318. For those skilled in the art
understand that different isolation schemes, such as dummy MOS gate
or SBL, can alternatively be applied.
[0094] The free stacks 312 of the MTJ 311 can be coupled to a
supply voltage V, while the N terminal of the diode 318 can be
coupled to a supply voltage V- and the P terminal of the diode 317
can be coupled to another supply voltage V+. Programming a 1 in
FIG. 11(a) can be achieved by applying a high voltage, i.e., 2V to
V+ and V-, while keeping V at ground, or 0V. To program a 1, a
current flows from diode 317 through the MTJ 311 while the diode
318 is cutoff. Similarly, programming a 0 can be achieved by
applying a high voltage to V, i.e., 2V, and keeping V+and V- at
ground. In this case. a current flows from MTJ 311 through diode
318 while the diode 317 is cutoff.
[0095] FIG. 11(b) shows a cross section of another embodiment of an
MRAM cell 310' with MTJ 311' and junction diodes 317' and 318' as
program selectors in accordance with one embodiment. MTJ 311' has a
free layer stack 312' on top and a fixed layer stack 313'
underneath with a dielectric in between to constitute a magnetic
tunneling junction. Diode 317' is used to program 1 and diode 318'
is used to program 0. Diodes 317' and 318' have P+ and N+ active
regions on N wells 321' and 320', respectively, which are
fabricated by shallow N wells with additional process steps. Though
more process steps are needed, the cell size can be smaller. Diode
317' has P+ active region 315' and N+ active region 314' to
constitute the P and N terminals of the program-1 diode 317'.
Similarly, diode 318' has P+ active 316' and N+ active 319' to
constitute the P and N terminals of the program-0 diode 318'. STI
330' isolates different active regions.
[0096] The free stacks 312' of the MTJ 311' can be coupled to a
supply voltage V, while the N terminal of the diode 318' can be
coupled to a supply voltage V- and the P terminal of the diode 317'
is coupled to another supply voltage V+. Programming a 1 in FIG.
11(b) can be achieved by applying a high voltage, i.e., 2V to V+and
V-, while keeping V at ground, or 0V. To program a 1, a current
will flow from diode 317' through the MTJ 311' while the diode 318'
is cutoff. Similarly, programming 0 can be achieved by applying a
high voltage to V, i.e., 2V, and keeping V+ and V- at ground. In
this case, a current will flow from MTJ 311' through diode 318'
while the diode 317' is cutoff.
[0097] FIG. 12(a) shows one embodiment of a three-terminal
2.times.2 MRAM cell array using junction diodes 317 and 318 as
program selectors and the condition to program 1 in a cell in
accordance with one embodiment. Cells 310-00, 310-01, 310-10, and
310-11 are organized as a two-dimensional array. The cell 310-00
has a MTJ 311-00, a program-1 diode 317-00, and a program-0 diode
318-00. The MTJ 311-00 is coupled to a supply voltage V at one end,
to the N terminal of the program-1 diode 317-00 and to the P
terminal of the program-0 diode 318-00 at the other end. The P
terminal of the program-1 diode 317-00 is coupled to a supply
voltage V+. The N terminal of the program-0 diode 318-00 is coupled
to another supply voltage V-. The other cells 310-01, 310-10, and
310-11 are similarly coupled. The voltage Vs of the cells 310-00
and 310-10 in the same columns are connected to BL0. The voltage Vs
of the cells 310-01 and 310-11 in the same column are connected to
BL1. The voltages V+ and V- of the cells 310-00 and 310-01 in the
same row are connected to WL0P and WL0N, respectively. The voltages
V+ and V- of the cells 310-10 and 310-11 in the same row are
connected to WL1P and WL1N, respectively. To program a 1 into the
cell 310-01, WL0P is set high and BL1 is set low, while setting the
other BL and WLs at proper voltages as shown in FIG. 12(a) to
disable the other program-1 and program-0 diodes. The bold line in
FIG. 12(a) shows the direction of current flow.
[0098] FIG. 12(b) shows alternative program-1 conditions for the
cell 310-01 in a 2.times.2 MRAM array in accordance with one
embodiment. For example, to program a 1 into cell 310-01, set BL1
and WL0P to low and high, respectively. If BL0 is set to high in
condition 1, the WL0N and WL1N can be either high or floating, and
WL1P can be either low or floating. The high and low voltages of an
MRAM in today's technologies are about 2-3V for high voltage and 0
for low voltage, respectively. If BL0 is floating in condition 2,
WL0N and WL1N can be high, low, or floating, and WL1P can be either
low or floating. In a practical implementation, the floating nodes
are usually coupled to very weak devices to a fixed voltage to
prevent leakage. One embodiment of the program-1 condition is shown
in FIG. 12(a) without any nodes floating.
[0099] FIG. 13(a) shows one embodiment of a three-terminal
2.times.2 MRAM cell array with MTJ 311 and junction diodes 317 and
318 as program selectors and the condition to program 0 in a cell
in accordance with one embodiment. The cells 310-00, 310-01,
310-10, and 310-11 are organized as a two-dimensional array. The
cell 310-00 has a MTJ 311-00, a program-1 diode 317-00, and a
program-0 diode 318-00. The MTJ 311-00 is coupled to a supply
voltage V at one end, to the N terminal of program-1 diode 317-00
and to the P terminal of program-0 diode 318-00 at the other end.
The P terminal of the program-1 diode 317-00 is coupled to a supply
voltage V+. The N terminal of the program-0 diode 318-00 is coupled
to another supply voltage V-. The other cells 310-01, 310-10, and
310-11 are similarly coupled. The voltage Vs of the cells 310-00
and 310-10 in the same columns are connected to BL0. The voltage Vs
of the cells 310-01 and 310-11 in the same column are connected to
BL1. The voltages V+ and V-of the cells 310-00 and 310-01 in the
same row are connected to WL0P and WL0N, respectively. The voltages
V+ and V- of the cells 310-10 and 310-11 in the same row are
connected to WL1P and WL1N, respectively. To program a 0 into the
cell 310-01, WL0N is set low and BL1 is set high, while setting the
other BL and WLs at proper voltages as shown in FIG. 13(a) to
disable the other program-1 and program-0 diodes. The bold line in
FIG. 13(a) shows the direction of current flow.
[0100] FIG. 13(b) shows alternative program-0 conditions for the
cell 310-01 in a 2.times.2 MRAM array in accordance with one
embodiment. For example, to program a 0 into cell 310-01, set BL1
and WL0N to high and low, respectively. If BL0 is set to low in
condition 1, the WL0P and WL1P can be either low or floating, and
WL1N can be either high or floating. The high and low voltages of
an MRAM in today's technologies are about 2-3V for high voltage and
0 for low voltage, respectively. If BL0 is floating in condition 2,
WL0P and WL1P can be high, low, or floating, and WL1N can be either
high or floating. In a practical implementation, the floating nodes
are usually coupled to very weak devices to a fixed voltage to
prevent leakage. One embodiment of the program-0 condition is as
shown in FIG. 13(a) without any nodes floating.
[0101] The cells in 2.times.2 MRAM arrays in FIGS. 12(a), 12(b),
13(a) and 13(b) are three-terminal cells, namely, cells with V, V+,
and V- nodes. However, if the program voltage VDDP is less than
twice a diode's threshold voltage Vd, i.e. VDDP<2*Vd, the V+ and
V- nodes of the same cell can be connected together as a
two-terminal cell. Since Vd is about 0.6-0.7V at room temperature,
this two-terminal cell works if the program high voltage is less
than 1.2V and low voltage is 0V. This is a common voltage
configuration of MRAM arrays for advanced CMOS technologies that
has supply voltage of about 1.0V. FIGS. 14(a) and 14(b) show
schematics for programming a 1 and 0, respectively, in a
two-terminal 2.times.2 MRAM array.
[0102] FIGS. 14(a) and 14(b) show one embodiment of programming 1
and 0, respectively, in a two-terminal 2.times.2 MRAM cell array in
accordance with one embodiment. The cells 310-00, 310-01, 310-10,
and 310-11 are organized in a two-dimensional array. The cell
310-00 has the MTJ 311-00, the program-1 diode 317-00, and the
program-0 diode 318-00. The MTJ 311-00 is coupled to a supply
voltage V at one end, to the N terminal of program-1 diode 317-00
and the P terminal of program-0 diode 318-00 at the other end. The
P terminal of the program-1 diode 317-00 is coupled to a supply
voltage V+. The N terminal of the program-0 diode 318-00 is coupled
to another supply voltage V-. The voltages V+ and V- are connected
together in the cell level if VDDP<2*Vd can be met. The other
cells 310-01, 310-10 and 310-11 are similarly coupled. The voltages
Vs of the cells 310-00 and 310-10 in the same columns are connected
to BL0. The voltage Vs of the cells 310-01 and 310-11 in the same
column are connected to BL1. The voltages V+ and V- of the cells
310-00 and 310-01 in the same row are connected to WL0. The
voltages V+ and V- of the cells 310-10 and 310-11 in the same row
are connected to WL1.
[0103] To program a 1 into the cell 310-01, WL0 is set high and BL1
is set low, while setting the other BL and WLs at proper voltages
as shown in FIG. 14(a) to disable other program-1 and program-0
diodes. The bold line in FIG. 14(a) shows the direction of current
flow. To program a 0 into the cell 310-01, WL0 is set low and BL1
is set high, while setting the other BL and WLs at proper voltages
as shown in FIG. 14(b) to disable the other program-1 and program-0
diodes. The bold line in FIG. 14(b) shows the direction of current
flow.
[0104] The embodiments of constructing MRAM cells in a 2.times.2
array as shown in FIGS. 12(a)-14(b) are for illustrative purposes.
Those skilled in the art understand that the number of cells, rows,
or columns in a memory can be constructed arbitrarily and rows and
columns are interchangeable.
[0105] The programmable resistive devices can be used to construct
a memory in accordance with one embodiment. FIG. 15 shows a portion
of a programmable resistive memory 100 constructed by an array 101
of n-row by (m+1)-column non-MRAM cells 110 and n wordline drivers
150-i, where i=0, 1, . . . , n-1, in accordance with one
embodiment. The memory array 101 has m normal columns and one
reference column for one shared sense amplifier 140 for
differential sensing. Each of the memory cells 110 has a resistive
element 111 coupled to the P terminal of a diode 112 as program
selector and to a bitline BLj 170-j (j=0, 1, . . . m-1) or
reference bitline BLR0 175-0 for those of the memory cells 110 in
the same column. The N terminal of the diode 112 is coupled to a
wordline WLBi 152-i through a local wordline LWLBi 154-i, where
i=0, 1, . . . , n-1, for those of the memory cells 110 in the same
row. Each wordline WLBi is coupled to at least one local wordline
LWLBi, where i=0, 1, . . . , n-1. The LWLBi 154-i is generally
constructed by a high resistivity material, such as N well or
polysilicon, to connect cells, and then coupled to the WLBi (e.g.,
a low-resistivity metal WLBi) through conductive contacts or vias,
buffers, or post-decoders 172-i, where i=0, 1, . . . , n-1. Buffers
or post-decoders 172-i may be needed when using diodes as program
selectors because there are currents flowing through the WLBi,
especially when one WLBi drives multiple cells for program or read
simultaneously in other embodiments. The wordline WLBi is driven by
the wordline driver 150-i with a supply voltage vddi that can be
switched between different voltages for program and read. Each BLj
170-j or BLR0 175-0 is coupled to a supply voltage VDDP through a
Y-write pass gate 120-j or 125 for programming, where each BLj
170-j or BLR0 175-0 is selected by YSWBj (j=0, 1, . . . , m-1) or
YSWRB0, respectively. The Y-write pass gate 120-j (j=0, 1, . . . ,
m-1) or 125 can be built by PMOS, though NMOS, diode, or bipolar
devices can be employed in some embodiments. Each BL or BLR0 is
coupled to a dataline DL or DLR0 through a Y-read pass gate 130-j
or 135 selected by YSRj (j=0, 1, . . . , m-1) or YSRR0,
respectively. In this portion of memory array 101, m normal
datalines DLj (j=0, 1, . . . , m-1) are connected to an input 160
of a sense amplifier 140. The reference dataline DLR0 provides
another input 161 for the sense amplifier 140 (no multiplex is
generally needed in the reference branch). The output of the sense
amplifiers 140 is Q0.
[0106] To program a cell, the specific WLBi and YSWBj are turned on
and a high voltage is supplied to VDDP, where i=0, 1, . . . n-1 and
j=0, 1, . . . , m-1. In some embodiments, the reference cells can
be programmed to 0 or 1 by turning on WLRBi, and YSWRB0, where i=0,
1, . . . , n-1. To read a cell, a data column 160 can be selected
by turning on the specific WLBi and YSRj, where i=0, 1, . . . ,
n-1, and j=0, 1, . . . , m-1, and a reference cell coupled to the
reference dataline DLR0 161 for the sense amplifier 140 can be
selected to sense and compare the resistance difference between BLs
and ground, while disabling all YSWBj and YSWRB0 where j=0, 1, . .
. , m-1.
[0107] The programmable resistive devices can be used to construct
a memory in accordance with one embodiment. FIG. 16(a) shows a
portion of a programmable resistive memory 100 constructed by an
array 101 of 3-terminal MRAM cells 110 in n rows and m+1 columns
and n pairs of wordline drivers 150-i and 151-i, where i=0, 1, . .
. , n-1, according to one embodiment. The memory array 101 has m
normal columns and one reference column for one shared sense
amplifier 140 for differential sensing. Each of the memory cells
110 has a resistive element 111 coupled to the P terminal of a
program-0 diode 112 and N terminal of a program-1 diode 113. The
program-0 diode 112 and the program-1 diode 113 serve as program
selectors. Each resistive element 111 is also coupled to a bitline
BLj 1701 (j=0, 1, . . . m-1) or reference bitline BLR0 175-0 for
those of the memory cells 110 in the same column. The N terminal of
the diode 112 is coupled to a wordline WLNi 152-i through a local
wordline LWLNi 154-i, where i=0, 1, . . . , n-1, for those of the
memory cells 110 in the same row. The P terminal of the diode 113
is coupled to a wordline WLPi 153-i through a local wordline LWLPi
155-i, where i=0, 1, . . . , n-1, for those cells in the same row.
Each wordline WLNi or WLPi is coupled to at least one local
wordline LWLNi or LWLPi, respectively, where i=0, 1, . . . , n-1.
The LWLNi 154-i and LWLPi 155-i are generally constructed by a high
resistivity material, such as N well or polysilicon, to connect
cells, and then coupled to the WLNi or WLPi (e.g., low-resistivity
metal WLNi or WLPi) through conductive contacts or vias, buffers,
or post-decoders 172-i or 173-i respectively, where i=0, 1, . . . ,
n-1. Buffers or post-decoders 172-i or 173-i may be needed when
using diodes as program selectors because there are currents
flowing through WLNi or WLPi, especially when one WLNi or WLPi
drivers multiple cells for program or read simultaneously in some
embodiments. The wordlines WLNi and WLPi are driven by wordline
drivers 150-i and 151-i, respectively, with a supply voltage vddi
that can be switched between different voltages for program and
read. Each BLj 170-j or BLR0 175-0 is coupled to a supply voltage
VDDP through a Y-write-0 pass gate 120-0 or 125 to program 0, where
each BLj 1701 or BLR0 175-0 is selected by YS0WBj (j=0, 1, . . . ,
m-1) or YS0WRB0, respectively. Y-write-0 pass gate 120-j or 125 can
be built by PMOS, though NMOS, diode, or bipolar devices can be
employed in other embodiments. Similarly, each BLj 170-j or BLR0
175-0 is coupled to a supply voltage 0V through a Y-write-1 pass
gate 121-j or 126 to program 1, where each BLj 170-j or BLR0 175-0
is selected by YS1Wj (j=0, 1, . . . , m-1) or YS1WR0, respectively.
Y-write-1 pass gate 121-j or 126 is can be built by NMOS, though
PMOS, diode, or bipolar devices can be employed in other
embodiments. Each BL or BLR0 is coupled to a dataline DL or DLR0
through a Y-read pass gate 130-j or 135 selected by YSRj (j=0, 1, .
. . , m-1) or YSRR0, respectively. In this portion of memory array
101, m normal datalines DLj (j=0, 1, . . . , m-1) are connected to
an input 160 of a sense amplifier 140. Reference dataline DLR0
provides another input 161 for the sense amplifier 140, except that
no multiplex is generally needed in a reference branch. The output
of the sense amplifier 140 is Q0.
[0108] To program a 0 into a cell, the specific WLNi, WLPi and BLj
are selected as shown in FIG. 13(a) or 13(b) by wordline drivers
150-i, 151-i, and Y-pass gate 120-j by YS0WBj, respectively, where
i=0, 1, . . . n-1 and j=0, 1, . . . , m-1, while the other
wordlines and bitlines are also properly set. A high voltage is
applied to VDDP. In some embodiments, the reference cells can be
programmed into 0 by setting proper voltages to WLRNi 158-i, WLRPi
159-i and YS0WRB0, where i=0, 1, . . . , n-1. To program a 1 to a
cell, the specific WLNi, WLPi and BLj are selected as shown in FIG.
12(a) or 12(b) by wordline driver 150-i, 151-i, and Y-pass gate
121-j by YS1Wj, respectively, where i=0, 1, . . . n-1 and j=0, 1, .
. . , m-1, while the other wordlines and bitlines are also properly
set. In some embodiments, the reference cells can be programmed to
1 by setting proper voltages to WLRNi 158-i, WLRPi 159-i and
YS1WR0, where i=0, 1, . . . , n-1. To read a cell, a data column
160 can be selected by turning on the specific WLNi, WLPi and YSRj,
where i=0, 1, . . . , n-1, and j=0, 1, . . . , m-1, and a reference
cell coupled to the reference dataline DLR 161 for the sense
amplifier 140 to sense and compare the resistance difference
between BLs and ground, while disabling all YS0WBj, YS0WRB0, YS1Wj
and YS1WR0, where j=0, 1, . . . , m-1.
[0109] Another embodiment of constructing an MRAM memory with
2-terminal MRAM cells is shown in FIG. 16(b), provided the voltage
difference VDDP, between high and low states, is less than twice of
the diode's threshold voltage Vd, i.e., VDDP<2*Vd. As shown in
FIG. 16(b), two wordlines per row WLNi 152-i and WLPi 153-i in FIG.
16(a) can be merged into one wordline driver WLNi 152-i, where i=0,
1, . . . , n-1. Also, the local wordlines LWLNi 154-i and LWLP
155-i per row in FIG. 16(a) can be merged into one local wordline
LWLNi 154-i, where i=0, 1, . . . , n-1, as shown in FIG. 16(b).
Still further, two wordline drivers 150-i and 151-i in FIG. 16(a)
can be merged into one, i.e., wordline driver 150-i. The BLs and
WLNs of the unselected cells are applied with proper program 1 and
0 conditions as shown in FIGS. 14(a) and 14(b), respectively. Since
half of wordlines, local wordlines, and wordline drivers can be
eliminated in this embodiment, cell and macro areas can be reduced
substantially.
[0110] Differential sensing is a common for programmable resistive
memory, though single-end sensing can be used in other embodiments.
FIGS. 17(a), 17(b), and 17(c) show three other embodiments of
constructing reference cells for differential sensing. In FIG.
17(a), a portion of memory 400 has a normal array 180 of n.times.m
cells, two reference columns 150-0 and 150-1 of n.times.1 cells
each storing all data 0 and 1 respectively, m+1 Y-read pass gates
130, and a sense amplifier 140. As an example, n=8 and m=8 are used
to illustrate the concept. There are n wordlines WLBi and n
reference wordlines WLRBi for each row, where i=0, 1, . . . , n-1.
When a wordline WLBi is turned on to access a row, a corresponding
reference wordline WLRBi (i=0, 1, . . . , n-1) is also turned on to
activate two reference cells 170-0 and 170-1 in the same row to
provide mid-level resistance after proper scaling in the sense
amplifier. The selected dataline 160 along with the reference
dataline 161 are input to a sense amplifier 140 to generate an
output Q0. In this embodiment, each WLRBi and WLBi (i=0, 1, . . . ,
n-1) are hardwired together and every cells in the reference
columns need to be pre-programmed before read.
[0111] FIG. 17(b) shows another embodiment of using a reference
cell external to a reference column. In FIG. 17(b), a portion of
memory 400 has a normal array 180 of n.times.m cells, a reference
column 150 of n.times.1 cells, m+1 Y-read pass gates 130, and a
sense amplifier 140. When a wordline WLBi (i=0, 1, . . . , n-1) is
turned on, none of the cells in the reference column 150 are turned
on. An external reference cell 170 with a pre-determined resistance
is turned on instead by an external reference wordline WLRB. The
selected dataline 160 and the reference dataline 161 are input to a
sense amplifier 140 to generate an output Q0. In this embodiment,
all internal reference wordlines WLRBi (i=0, 1, . . . , n-1) in
each row are tied together to a high voltage to disable the diodes
in the reference column. The reference column 150 provides a
loading to match with that of the normal columns.
[0112] FIG. 17(c) shows another embodiment of constructing
reference cells for differential sensing. In FIG. 17(c), a portion
of memory 400 has a normal array 180 of n.times.m cells, one
reference column 150 of n.times.1, two reference rows 175-0 and
175-1 of 1.times.m cells, m+1 Y-read pass gates 130, and a sense
amplifier 140. As an example, n=8 and m=8 are used to illustrate
the approach. There are n wordlines WLBi and 2 reference wordlines
WLRB0 175-0 and WLRB1 175-1 on top and bottom of the array, where
i=0, 1, . . . , n-1. When a wordline WLBi (i=0, 1, . . . , n-1) is
turned on to access a row, the reference wordline WLRB0 and WLRB1
are also turned on to activate two reference cells 170-0 and 170-1
in the upper and lower right corners of the array 180, which store
data 0 and 1 respectively. The selected dataline 160 along with the
reference dataline 161 are input to a sense amplifier 140 to
generate an output Q0. In this embodiment, all cells in the
reference column 150 are disabled except that the cells 170-0 and
170-1 on top and bottom of the reference column 150. Only two
reference cells are used for the entire n x m array that needs to
be pre-programmed before read.
[0113] For those programmable resistive devices that have a very
small resistance ratio between states 1 and 0, such as 2:1 ratio in
MRAM, FIGS. 17(a) and 17(c) are desirable embodiments, depending on
how many cells are suitable for one pair of reference cells.
Otherwise, FIG. 17(b) is a desirable embodiment for electrical fuse
or PCM that has resistance ratio of more than about 10.
[0114] FIGS. 15, 16(a), 16(b), 17(a), 17(b), and 17(c) show only a
few embodiments of a portion of programmable resistive memory in a
simplified manner. The memory array 101 in FIGS. 15, 16(a), and
16(b) can be replicated s times to read or program s-cells at the
same time. In the case of differential sensing, the number of
reference columns to normal columns may vary and the physical
location can also vary relative to the normal data columns. Rows
and columns are interchangeable. The numbers of rows, columns, or
cells likewise may vary. For those skilled in the art understand
that the above descriptions are for illustrative purpose. Various
embodiments of array structures, configurations, and circuits are
possible and are still within the scope of this invention.
[0115] The portions of programmable resistive memories shown in
FIGS. 15, 16(a), 16(b), 17(a), 17(b) and 17(c) can include
different types of resistive elements. The resistive element can be
an electrical fuse including a fuse fabricated from an
interconnect, contact/via fuse, contact/via anti-fuse, or gate
oxide breakdown anti-fuse. The interconnect fuse can be formed from
silicide, metal, metal alloy, or some combination thereof, or can
be constructed from a CMOS gate. The resistive element can also be
fabricated from phase-change material, MTJ, etc. For the electrical
fuse fabricated from an interconnect, contact, or via fuse,
programming requirement is to provide a sufficiently high current,
about 4-20 mA range, for a few microseconds to blow the fuse by
electro-migration, heat, ion diffusion, or some combination
thereof. For anti-fuse, programming requirement is to provide a
sufficiently high voltage to breakdown the dielectrics between two
ends of a contact, via or CMOS gate. The required voltage is about
6-7V for a few millisecond to consume about 10 uA of current in
today's technologies. Programming Phase-Change Memory (PCM)
requires different voltages and durations for 0 and 1. Programming
to a 1 (or to reset) requires a high and short voltage pulse
applied to the phase-change film. Alternatively, programming to a 0
(or to set) requires a low and long voltage pulse applied to the
phase change film. The reset needs about 3V for 50 ns and consumes
about 300 uA, while set needs about 2V for 300 ns and consumes
about 100 uA. For MRAM, the high and low program voltages are about
2-3V and 0V, respectively, and the current is about +/-100-200
uA.
[0116] Most programmable resistive devices have a higher voltage
VDDP (.about.2-3V) for programming than the core logic supply
voltage VDD (.about.1.0V) for reading. FIG. 18(a) shows a schematic
of a wordline driver circuit 60 according to one embodiment. The
wordline driver includes devices 62 and 61, as shown as the
wordline driver 150 in FIGS. 15, 16(a) and 16(b). The supply
voltage vddi is further coupled to either VDDP or VDD through power
selectors 63 and 64 (e.g., PMOS power selectors) respectively. The
input of the wordline driver Vin is from an output of an X-decoder.
In some embodiments, the power selectors 63 and 64 are implemented
as thick oxide I/O devices to sustain high voltage. The bodies of
power selector 63 and 64 can be tied to vddi to prevent
latchup.
[0117] Similarly, bitlines tend to have a higher voltage VDDP
(.about.2-3V) for programming than the core logic supply voltage
VDD (.about.1.0V) for reading. FIG. 18(b) shows a schematic of a
bitline circuit 70 according to one embodiment. The bitline circuit
70 includes a bitline (BL) coupled to VDDP and VDD through power
selectors 73 and 74 (e.g., PMOS power selectors), respectively. If
the bitline needs to sink a current such as in an MRAM, an NMOS
pulldown device 71 can be provided. In some embodiments, the power
selectors 73 and 74 as well as the pulldown device 71 can be
implemented as thick-oxide I/O devices to sustain high voltage. The
bodies of power selector 73 and 74 can be tied to vddi to prevent
latchup.
[0118] Using junction diodes as program selectors may have high
leakage current if a memory size is very large. Power selectors for
a memory can help reducing leakage current by switching to a lower
supply voltage or even turning off when a portion of memory is not
in use. FIG. 18(c) shows a portion of memory 85 with an internal
power supply VDDP coupled to an external supply VDDPP and a core
logic supply VDD through power selectors 83 and 84. VDDP can even
be coupled to ground by an NMOS pulldown device 81 to disable this
portion of memory 85, if this portion of memory is temporarily not
in use.
[0119] FIGS. 19(a) and 20(a) only show two of many pre-amplifier
embodiments. Similarly, FIGS. 19(b), 20(b) and 20(c) only show
several of many amplifier and level shifter embodiments. Various
combinations of pre-amplifiers, level shifters, and amplifiers in
core logic or I/O devices can be constructed differently,
separately or mixed.
[0120] FIG. 19(a) shows one embodiment of a schematic of a
pre-amplifier 100 according to one embodiment. The pre-amplifier
100 needs special considerations because the supply voltage VDD for
core logic devices is about 1.0V that does not have enough head
room to turn on a diode to make sense amplifiers functional,
considering a diode's threshold is about 0.7V. One embodiment is to
use another supply VDDR, higher than VDD, to power at least the
first stage of sense amplifiers. The programmable resistive cell
110 shown in FIG. 19(a) has a resistive element 111 and a diode 112
as program selector, and can be selected for read by asserting YSR'
to turn on a gate of a NMOS 130 (NMOS device) and wordline bar WLB.
The pre-amplifier 100 also has a reference cell 115 including a
reference resistive element 116 and a reference diode 117. The
reference cell 115 can be selected for differential sensing by
asserting YSR' to turn on a gate of a NMOS 131 and reference
wordline WLRB. The resistance Ref of the reference resistive
element 116 can be set at a resistance half-way between minimum of
state 1 and maximum of state 0 resistance.
[0121] The drains of NMOS 130 and 131 are coupled to sources of
NMOS 132 and 134, respectively. The gates of 132 and 134 are biased
at a fixed voltage Vbias. The channel width to length ratios of
NMOS 132 and 134 can be relatively large to clamp the voltage
swings of bitline BL and reference bitline BLR, respectively. The
drain of NMOS 132 and 134 are coupled to drains of PMOS 170 and
171, respectively. The drain of PMOS 170 is coupled to the gate of
PMOS 171 and the drain of PMOS 171 is coupled to the gate of PMOS
170. The outputs V+ and V- of the pre-amplifier 100 are drains of
PMOS 170 and PMOS 171 respectively. The sources of PMOS 170 and
PMOS 171 are coupled to a read supply voltage VDDR. The outputs V+
and V- are pulled up by a pair of PMOS 175 to VDDR when the
pre-amplifier 100 is disabled. VDDR is about 2-3V (which is higher
than about 1.0V VDD of core logic devices) to turn on the diode
selectors 112 and 117 in the programmable resistive cell 110 and
the reference cell 115, respectively. The CMOS 130, 131, 132, 134,
170, 171, and 175 can be embodied as thick-oxide I/O devices to
sustain high voltage VDDR. In another embodiment, the read
selectors 130 and 131 can be PMOS devices.
[0122] FIG. 19(b) shows one embodiment of a schematic of an
amplifier 200 according to one embodiment. In another embodiment,
the outputs V+ and V- of the pre-amplifier 100 in FIG. 19(a) can be
coupled to gates of NMOS 234 and 232, respectively, of the
amplifier 200. The NMOS 234 and 232 can be relatively thick oxide
I/O devices to sustain the high input voltage V+ and V- from a
pre-amplifier. The sources of NMOS 234 and 232 are coupled to
drains of NMOS 231 and 230, respectively. The sources of NMOS 231
and 230 are coupled to a drain of an NMOS 211. The gate of NMOS 211
is coupled to a clock .phi. to turn on the amplifier 200, while the
source of NMOS 211 is coupled to ground. The drains of NMOS 234 and
232 are coupled to drains of PMOS 271 and 270, respectively. The
sources of PMOS 271 and 270 are coupled to a core logic supply VDD.
The gates of PMOS 271 and NMOS 231 are connected and coupled to the
drain of PMOS 270, as a node Vp. Similarly, the gates of PMOS 270
and NMOS 230 are connected and coupled to the drain of PMOS 271, as
a node Vn. The nodes Vp and Vn are pulled up by a pair of PMOS 275
to VDD when the amplifier 200 is disabled when .phi. goes low. The
output nodes Vout+ and Vout- are coupled to nodes Vn and Vp through
a pair of inverters as buffers.
[0123] FIG. 19(c) shows a timing diagram of the pre-amplifier 100
and the amplifier 200 in FIGS. 19(a) and 19(b), respectively. The
X- and Y-addresses AX/AY are selected to read a cell. After some
propagation delays, a cell is selected for read by turning WLB low
and YSR high to thereby select a row and a column, respectively.
Before activating the pre-amplifier 100, a pulse Vpc is generated
to precharge DL and DLR to ground. The pre-amplifier 100 would be
very slow if the DL and DLR voltages are high enough to turn off
the cascode devices (e.g., NMOS 132 and 134). After the
pre-amplifier outputs V+ and V- are stabilized, the clock .phi. is
set high to turn on the amplifier 200 and to amplify the final
output Vout+ and Vout- into full logic levels.
[0124] FIG. 20(a) shows another embodiment of a pre-amplifier 100',
similar to the pre-amplifier 100 in FIG. 18(a). The reference
branch is turned on by a level signal to enable a sense amplifier,
SAEN, rather than cycle by cycle in FIG. 19(a). The PMOS pull-ups
171 and 170 in FIG. 20(a) are configured as current mirror loads,
rather than a pair of cross-coupled PMOS in FIG. 19(a). In this
embodiment, the number of the reference branches can be shared at
the expense of increasing power consumption.
[0125] FIG. 20(b) shows level shifters 300 according to one
embodiment. The V+ and V- from the pre-amplifier 100, 100' outputs
in FIG. 19(a) or FIG. 20(a) are coupled to gates of NMOS 301 and
302, respectively. The drains of NMOS 301 and 302 are coupled to a
supply voltage VDDR. The sources of NMOS 301 and 302 are coupled to
drains of NMOS 303 and 304, respectively, which have gates and
drains connected as diodes to shift the voltage level down by one
Vtn, the threshold voltage of an NMOS. The sources of NMOS 303 and
304 are coupled to pulldown devices NMOS 305 and 306, respectively.
The gates of NMOS 305 and 306 can be turned on by a clock .phi..
The NMOS 301, 302, 303 and 304 can be thick-oxide I/O devices to
sustain high voltage VDDR. The NMOS 303 and 304 can be cascaded
more than once to shift V+ and V- further to proper voltage levels
Vp and Vn. In another embodiment, the level shifting devices 303
and 304 can be built using PMOS devices.
[0126] FIG. 20(c) shows another embodiment of an amplifier 200'
with current-mirror loads having PMOS 270 and 271. The inputs Vp
and Vn of the amplifier 200' are from the outputs Vp and Vn of the
level shifter 300 in FIG. 20(b) can be coupled to gates of NMOS 231
and 230, respectively. The drains of NMOS 231 and 230 are coupled
to drains of NMOS 271 and 270 which provide current-mirror loads.
The drain and gate of PMOS 271 are connected and coupled to the
gate of PMOS 270. The sources of NMOS 231 and 230 are coupled to
the drain of an NMOS 211, which has the gate coupled to a clock
signal .phi. and the source to ground. The clock signal .phi.
enables the amplifier 200. The drain of PMOS 270 provides an output
Vout+. The PMOS pullup 275 keeps the output Vout+ at logic high
level when the amplifier 200' is disabled.
[0127] FIGS. 21(a) and 21(b) show a flow chart depicting
embodiments of a program method 700 and a read method 800,
respectively, for a programmable resistive memory in accordance
with certain embodiments. The methods 700 and 800 are described in
the context a programmable resistive memory, such as the
programmable resistive memory 100 in FIGS. 15, 16(a) and 16(c). In
addition, although described as a flow of steps, one of ordinary
skilled in the art will recognize that at least some of the steps
may be performed in a different order, including simultaneously, or
skipped.
[0128] FIG. 21(a) depicts a method 700 of programming a
programmable resistive memory in a flow chart according to one
embodiment. In the first step 710, proper power selectors can be
selected so that high voltages can be applied to the power supplies
of wordline drivers and bitlines. In the second step 720, the data
to be programmed in a control logic (not shown in FIGS. 15, 16(a),
and 16(b)) can be analyzed, depending on what types of programmable
resistive devices. For electrical fuse, this is a
One-Time-Programmable (OTP) device such that programming always
means blowing fuses into a non-virgin state and is irreversible.
Program voltage and duration tend to be determined by external
control signals, rather than generated internally from the memory.
For PCM, programming into a 1 (to reset) and programming into a 0
(to set) require different voltages and durations such that a
control logic determines the input data and select proper power
selectors and assert control signals with proper timings. For MRAM,
the directions of current flowing through MTJs are more important
than time duration. A control logic determines proper power
selectors for wordlines and bitlines and assert control signals to
ensure a current flowing in the desired direction for desired time.
In the third step 730, a cell in a row can be selected and the
corresponding local wordline can be turned on. In the fourth step
740, sense amplifiers can be disabled to save power and prevent
interference with the program operations. In the fifth step 750, a
cell in a column can be selected and the corresponding Y-write pass
gate can be turned on to couple the selected bitline to a supply
voltage. In the last step 760, a desired current can be driven for
a desired time in an established conduction path to complete the
program operations. For most programmable resistive memories, this
conduction path is from a high voltage supply through a bitline
select, resistive element, diode as program selector, and an NMOS
pulldown of a local wordline driver to ground. Particularly, for
programming a 1 to an MRAM, the conduction path is from a high
voltage supply through a PMOS pullup of a local wordline driver,
diode as program selector, resistive element, and bitline select to
ground.
[0129] FIG. 21(b) depicts a method 800 of reading a programmable
resistive memory in a flow chart according to one embodiment. In
the first step 810, proper power selectors can be selected to
provide supply voltages for local wordline drivers, sense
amplifiers, and other circuits. In the second step 820, all Y-write
pass gates, i.e. bitline program selectors, can be disabled. In the
third step 830, desired local wordline(s) can be selected so that
the diode(s) as program selector(s) have a conduction path to
ground. In the fourth step 840, sense amplifiers can be enabled and
prepared for sensing incoming signals. In the fifth step 850, the
dataline and the reference dataline can be pre-charged to the V-
voltage of the programmable resistive device cell. In the sixth
step 860, the desired Y-read pass gate can be selected so that the
desired bitline is coupled to an input of the sense amplifier. A
conduction path is thus established from the bitline to the
resistive element in the desired cell, diode(s) as program
selector(s), and the pulldown of the local wordline driver(s) to
ground. The same applies for the reference branch. In the last step
870, the sense amplifiers can compare the read current with the
reference current to determine a logic output of 0 or 1 to complete
the read operations.
[0130] FIG. 22 shows a processor system 700 according to one
embodiment. The processor system 700 can include a programmable
resistive device 744, such as in a cell array 742, in memory 740,
according to one embodiment. The processor system 700 can, for
example, pertain to a computer system. The computer system can
include a Central Process Unit (CPU) 710, which communicate through
a common bus 715 to various memory and peripheral devices such as
I/O 720, hard disk drive 730, CDROM 750, memory 740, and other
memory 760. Other memory 760 is a conventional memory such as SRAM,
DRAM, or flash, typically interfaces to CPU 710 through a memory
controller. CPU 710 generally is a microprocessor, a digital signal
processor, or other programmable digital logic devices. Memory 740
is preferably constructed as an integrated circuit, which includes
the memory array 742 having at least one programmable resistive
device 744. The memory 740 typically interfaces to CPU 710 through
a memory controller. If desired, the memory 740 may be combined
with the processor, for example CPU 710, in a single integrated
circuit.
[0131] The invention can be implemented in a part or all of an
integrated circuit in a Printed Circuit Board (PCB), or in a
system. The programmable resistive device can be fuse, anti-fuse,
or emerging nonvolatile memory. The fuse can be silicided or
non-silicided polysilicon fuse, metal fuse, contact fuse, or via
fuse. The anti-fuse can be a gate-oxide breakdown anti-fuse,
contact or via anti-fuse with dielectrics in-between. The emerging
nonvolatile memory can be Magnetic RAM (MRAM), Phase Change Memory
(PCM), Conductive Bridge RAM (CBRAM), or Resistive RAM (RRAM).
Though the program mechanisms are different, their logic states can
be distinguished by different resistance values.
[0132] The above description and drawings are only to be considered
illustrative of exemplary embodiments, which achieve the features
and advantages of the present invention. Modifications and
substitutions of specific process conditions and structures can be
made without departing from the spirit and scope of the present
invention.
[0133] The many features and advantages of the present invention
are apparent from the written description and, thus, it is intended
by the appended claims to cover all such features and advantages of
the invention. Further, since numerous modifications and changes
will readily occur to those skilled in the art, it is not desired
to limit the invention to the exact construction and operation as
illustrated and described. Hence, all suitable modifications and
equivalents may be resorted to as falling within the scope of the
invention.
* * * * *