U.S. patent application number 12/958408 was filed with the patent office on 2012-02-09 for pixel array substrate.
Invention is credited to Kai-Hung Huang, Li-Wen Wang.
Application Number | 20120033166 12/958408 |
Document ID | / |
Family ID | 45555917 |
Filed Date | 2012-02-09 |
United States Patent
Application |
20120033166 |
Kind Code |
A1 |
Huang; Kai-Hung ; et
al. |
February 9, 2012 |
PIXEL ARRAY SUBSTRATE
Abstract
A pixel array substrate is disclosed. The reflective pixel array
substrate can be made by utilizing five photo masks only. The
reflective pixel array substrate includes a substrate, a thin film
transistor, a reflective electrode, an insulating layer and
numerous protruding bumps. The step between the protrusion bump and
the substrate cause the reflective electrode thereon to have a
corrugated structure. The gate electrode of the thin film
transistor and the protruding bumps are made of a same conductive
layer. The drain electrode connects the reflective electrode, and
the drain electrode and the reflective electrode are made of a same
conductive layer.
Inventors: |
Huang; Kai-Hung; (Taipei
County, TW) ; Wang; Li-Wen; (Taoyuan County,
TW) |
Family ID: |
45555917 |
Appl. No.: |
12/958408 |
Filed: |
December 2, 2010 |
Current U.S.
Class: |
349/113 |
Current CPC
Class: |
G02F 2203/03 20130101;
G02F 1/13439 20130101; G02F 1/133553 20130101 |
Class at
Publication: |
349/113 |
International
Class: |
G02F 1/1335 20060101
G02F001/1335 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 3, 2010 |
TW |
099125805 |
Claims
1. A reflective pixel array substrate, comprising: a substrate
having at least a pixel region, the pixel region having a
reflective region and an element region; a thin film transistor
disposed within the element region, wherein the thin film
transistor comprises: a gate electrode disposed on the substrate; a
gate insulating layer covering the gate electrode and extending to
the reflective region; a semiconductive layer disposed on the gate
insulating layer and overlapping the gate electrode; a source
electrode and a drain electrode disposed on the semiconductive
layer and the gate insulating layer; and a plurality of protruding
bumps disposed on the substrate within the reflective region and
the gate insulating layer covering the protruding bumps, wherein
the protruding bumps are floating; a reflective electrode disposed
on the gate insulating layer, and connecting to the drain
electrode, the reflective electrode extending from the drain
electrode to the reflective region, wherein the reflective
electrode within the reflective region overlaps with the protruding
bumps so that the surface of the reflective electrode forms a
corrugated structure; an insulating layer covering the reflective
region; and a plurality of first openings disposed in the
insulating layer, wherein the reflective electrode disposed
directly above each of the protruding bumps is exposed through the
first openings.
2. The reflective pixel array substrate of claim 1, wherein the
gate electrode and the protruding bumps are formed by a same layer
of a conductive layer.
3. The reflective pixel array substrate of claim 1, wherein the
substrate further comprises: a peripheral circuit region; a gate
line connecting to the gate electrode, the gate line extending from
the element region to the peripheral circuit region, wherein the
gate insulating layer and the insulating layer cover the gate line
in sequence; a second opening disposed in the gate insulating layer
and the insulating layer, wherein the gate line within the
peripheral circuit region is exposed through the second opening;
and a conductive layer filling in the second opening and covering
the insulating layer within the peripheral circuit region and
covering the gate line exposed through the second opening.
4. The reflective pixel array substrate of claim 1, wherein the
shape of each of the protruding bumps comprises polygonal, circular
or oval-shaped.
5. The reflective pixel array substrate of claim 1, wherein the
protruding bumps are floating.
6. The reflective pixel array substrate of claim 1, wherein each of
the protruding bumps is separate from each other.
7. The reflective pixel array substrate of claim 1, wherein the
reflective electrode connects to the drain electrode
electrically.
8. The reflective pixel array substrate of claim 1, wherein light
illuminates the corrugated structure, and is reflected in a
plurality of reflective angles.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a pixel array substrate,
and more particularly to a reflective pixel array substrate.
[0003] 2. Description of the Prior Art
[0004] Reflection liquid crystal display devices are commonly used
for portable cellular phones or intelligent terminals. In a
reflection liquid crystal display, an externally entered incident
light is reflected by a reflector disposed within the back light
module and the reflected light is used as a display illumination
light. As a result, reflection type liquid crystal display devices
are more effective at achieving reduction in power consumption,
thickness and weight compared with a transmitting type liquid
crystal display device.
[0005] A reflection liquid crystal display device should have a
display performance for displaying a bright and white display when
the liquid crystal is in the light transmitting state. In order to
realize this display performance, it is necessary to effectively
reflect back the incident light from various directions. To achieve
this, the reflection electrode on the reflective pixel array
substrate is formed with a convex/concave structure.
[0006] To form a reflective pixel array substrate in the reflection
liquid crystal display device requires too many fabricating steps,
however. A simplified production procedure is required in order to
reduce the production cost and production time.
SUMMARY OF THE INVENTION
[0007] It is therefore an objective of the present invention to
provide a reflective pixel array substrate to solve the above
mentioned problems.
[0008] According to a preferred embodiment of the present
invention, a reflective pixel array substrate is provided. The
reflective pixel array substrate includes a substrate having at
least a pixel region, the pixel region having a reflective region
and an element region, a thin film transistor disposed within the
element region, wherein the thin film transistor comprises: a gate
electrode disposed on the substrate, a gate insulating layer
covering the gate electrode and extending to the reflective region,
a semiconductive layer disposed on the gate insulating layer and
overlapping the gate electrode, a source electrode and a drain
electrode disposed on the semiconductive layer and the gate
insulating layer and a plurality of protruding bumps disposed on
the substrate within the reflective region and the gate insulating
layer covering the protruding bumps, wherein the protruding bumps
are floating, a reflective electrode disposed on the gate
insulating layer, and connecting to the drain electrode, the
reflective electrode extending from the drain electrode to the
reflective region, wherein the reflective electrode within the
reflective region overlaps with the protruding bumps so that the
surface of the reflective electrode forms a corrugated structure,
an insulating layer covering the reflective region and a plurality
of first openings disposed in the insulating layer, wherein the
reflective electrode disposed directly above each of the protruding
bumps is exposed through the first openings.
[0009] The reflective pixel array substrate of the present
invention is compatible with current processes. Furthermore, the
reflective pixel array substrate has protruding bumps to make
corrugated structure on the surface of the reflective electrode.
Therefore, the light reflected from the reflective electrode can
become uniform.
[0010] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1A to FIG. 4C show a method of fabricating a reflective
pixel array substrate according to a preferred embodiment of the
present invention.
DETAILED DESCRIPTION
[0012] FIGS. 1A to 4C show a method of fabricating a reflective
pixel array substrate according to a first preferred embodiment of
the present invention. FIG. 1A shows a top view of a first
preferred embodiment of the present invention. FIG. 1B is a
sectional view of FIG. 1A taken along the line G-G'. FIG. 1C is a
sectional view of FIG. 1A taken along the line K-K'.
[0013] As shown in FIGS. 1A, 1B and 1C, first a substrate 10 having
an active region 12 and at least one peripheral circuit region 14
is provided. The peripheral circuit region 14 is disposed at an
edge of the active region 12. At least one pixel region 16 is
disposed in the active region 12. The pixel region 16 can be
divided into a reflective region 18 and an element region 20. For
the sake of brevity, only one pixel region 16 is described in the
detailed description. Please note, however, that there could be
numerous pixel regions in the active region 12, and each of the
pixel regions can be divided into an element region and a
reflective region. The substrate 10 can be glass, plastic, quartz
or other suitable materials.
[0014] Next, a conductive layer 22 is formed on the substrate 10.
Then, a first photo mask (not shown) is utilized to perform a
lithography and development process and the conductive layer 22 is
patterned to form a gate line 24, a gate electrode 26, a common
line 28, and protruding bumps 30 on the substrate 10. The gate
electrode 26 and the common line 28 are disposed within the element
region 20 of the pixel region 16. The protruding bumps 30 are
disposed within the reflective region 18 of the pixel region 16.
Additionally, the gate line 24 extends from the element region 20
to the peripheral circuit region 14.
[0015] The conductive layer 22 may be a metal layer made of Al, Cr,
Mo, W, Ta, Cu or an alloy of the combination thereof. The
conductive layer 22 may be a non metal layer such as indium tin
oxide (ITO) or zinc oxide (ZnO). Furthermore, each of the
protruding bumps 30 is individual and separate from each other.
Each of the protruding bumps 30 is floating. Moreover, the shape of
each of the protruding bumps 30 may be polygonal, circular or
oval-shaped, but is not limited to these shapes. It is noteworthy
that the gate line 24, the gate electrode 26, the common line 28
and the protruding bumps 30 are formed by utilizing one photo
mask.
[0016] Please refer to FIGS. 2A, 2B and 2C. FIG. 2A shows a top
view of a first preferred embodiment of the present invention. FIG.
2B is a sectional view of FIG. 2A taken along the line G-G'. FIG.
2C is a sectional view of FIG. 2A taken along the line K-K'. As
shown in FIGS. 2A, 2B, and 2C, a gate insulating layer 32 is formed
to cover the element region 20, the reflective region 18, and the
peripheral circuit region 14 entirely. The gate insulating layer 32
conformally covers the substrate 10, the gate line 24, the gate
electrode 26, the common line 28 and each of the protruding bumps
30. Because the gate insulating layer 32 covers each protruding
bump 30 conformally, the surface of the gate insulating layer 32
will go up and down with the protruding bumps 30. The gate
insulating layer 32 may be silicon oxide, silicon nitride, or
silicon oxynitride, but is not limited to these materials. Then, a
semiconductive layer 34 is formed on the gate insulating layer 32.
After that, a second photo mask (not shown) is utilized during a
lithographic and development process, and is followed by an etching
process to pattern the semiconductive layer 34. After these
processes, the patterned semiconductive layer 34 is positioned
corresponds to the gate electrode 26.
[0017] Please refer to FIGS. 3A to 3B. FIG. 3A shows a top view of
a first preferred embodiment of the present invention. FIG. 3B is a
sectional view of FIG. 3A taken along the line G-G'. As shown in
FIG. 3A to FIG. 3B. a conductive layer 36 is formed on the
substrate 10 to cover the active region 12 and the peripheral
circuit region 14. The conductive layer 36 covers the
semiconductive layer 34 and the gate insulating layer 32
conformally. Then, a third photo mask (not shown) is utilized
during a lithographic and development process, which is followed by
an etching process to pattern the conductive layer 36. After the
etching process, the conductive layer 36 within the peripheral
region 14 is removed, and a source line 38, a source electrode 40,
a drain electrode 42 and a reflective electrode 44 are formed. The
source line 38, the source electrode 40 and the drain electrode 42
are disposed within the element region 20. The reflective electrode
44 connects to the drain electrode 42 and the reflective electrode
44 extends from the element region 20 to the reflective region
18.
[0018] It is noteworthy that the reflective electrode 44 within the
reflective region 18 overlaps with each of the protruding bumps 30.
The surface of the gate insulating layer 32 below the reflective
electrode 44 goes up and down because a step is between each of the
protruding bumps 30 and the substrate 10. Therefore, the surface of
the reflective electrode 44 in the reflective region 18 forms a
corrugated structure 46, or a convex/concave structure. The
corrugated structure 46 can thereby reflect an incident light
illuminating the corrugated structure in a plurality of reflective
angles. This allows the reflected light to be a uniform light
source for a back light module. In addition, the reflective
electrode 44, the source line 38, the source electrode 40 and the
drain electrode 42 are formed by the same photo mask.
[0019] Please refer to FIGS. 4A, 4B and 4C. FIG. 4A shows a top
view of a first preferred embodiment of the present invention. FIG.
4B is a sectional view of FIG. 4A taken along the line G-G'. FIG.
4C is a sectional view of FIG. 4A taken along the line K-K'. As
shown in FIGS. 4A, 4B and 4C, an insulating layer 48 is formed to
cover the pixel region 16 and the peripheral circuit region 14.
That is, the insulating layer 48 covers the entire substrate 10.
Then, a fourth photo mask (not shown) is utilized during a
lithographic and development process, which is followed by an
etching process to pattern the insulating layer 48 within the
reflective region 18 so as to form numerous openings 52. The
reflective layer 44 directly above each protruding bump 30 within
the reflective region 18 is exposed through the openings 52. After
utilizing the fourth photo mask, the insulating layer 32 and the
gate insulating layer 48 are patterned to form an opening 54
exposing part of the gate line 24.
[0020] According to a preferred embodiment, the insulating layer 48
may be silicon nitride. Additionally, the insulating layer 48
surrounding the reflective electrode 44 within the reflective
region 18 can reflect the light illuminating the insulating layer
48 toward the reflective electrode 44. Next, a conductive layer 56
is formed entirely within the active region 12 and the peripheral
region 14. Then, a fifth photo mask (not shown) is utilized during
a lithographic and development process, and followed by an etching
process to pattern the conductive layer 56 for removing the
conductive layer 56 within the active region 12 and removing part
of the conductive layer 56 within the peripheral circuit region 14.
Only the conductive layer 56 in the opening 54 and around the
opening 54 remains. This enables the conductive layer 56 within the
peripheral region 14 to connect to the gate line 24 electrically.
Moreover, the gate line 24 covered by the conductive layer 56 can
be kept from being oxidized. The conductive layer 56 preferably is
ITO. At this point, the reflective pixel array substrate is
completed.
[0021] The present invention also provides a reflective pixel array
substrate. Please refer to FIGS. 4A and 4B, FIG. 4A depicts a top
view of a reflective pixel array substrate according to a second
preferred embodiment of the present invention. FIG. 4B is a
sectional view of FIG. 4A taken along the line G-G'. FIG. 4C is a
sectional view of FIG. 4A taken along the line K-K'. As shown in
FIGS. 4A, 4B and 4C, the reflective pixel array substrate 100
includes a substrate 10 having an active region 12 and at least one
peripheral circuit region 14. The peripheral circuit region 14 is
disposed on at least one edge of the active region 12. At least one
pixel region 16 is disposed in the active region 12. The pixel
region 16 is divided into a reflective region 18 and an element
region 20. For the sake of brevity, only one pixel region 16 is
described in the detailed description. Please note, however, that
there could be numerous pixel regions in the active region 12, and
each of the pixel regions 16 can be divided into an element region
20 and a reflective region 18. The substrate 10 can be glass,
plastic, quartz or other suitable material.
[0022] In addition, a thin film transistor 58 is disposed within
the element region 20, wherein the thin film transistor 58 includes
a gate electrode 26 disposed on the substrate 10. A gate insulating
layer 32 covers the gate electrode 26 and extends from the element
region 20 to the reflective region 18 and the peripheral circuit
region 14. A semiconductive layer 34 is disposed on the gate
insulating layer 32 and overlaps with the gate electrode 26. A
source electrode 40 and a drain electrode 42 are both disposed on
the semiconductive layer 34 and on the gate insulating layer 32.
Moreover, a gate line 24 connects to the gate electrode 26 and
extends from the element region 20 to the peripheral circuit region
14. The gate insulating layer 32 extends from the element region 20
to the peripheral region 14 and covers the gate line 24. A common
line 28 is disposed in the element region 20.
[0023] The reflective pixel array substrate 100 further includes
numerous protruding bumps 30 disposed within the reflective region
18 of the substrate 10. The gate insulating layer 32 extends from
the element region 20 to the reflective region 18 and covers each
of the protruding bumps 30. Each of the protruding bumps 30 is
floating and is disposed individually. That is, the protruding
bumps 30 do not connect with each other. A reflective electrode 44
is disposed on the gate insulating layer 32 and connects to the
drain electrode 42. The reflective electrode 44 extends from the
element region 20 to the reflective region 18. It is noteworthy
that a step is between each protruding bump 30 and the substrate 10
so that the gate insulating layer 32 on the protruding bumps 30 and
the substrate 10 goes up and down with the step profile. The
reflective electrode 44 covering on the gate insulating layer 32
therefore forms a corrugated structure 46. The light illuminated on
the corrugated structure 46 can be reflected into numerous
reflective angles so the reflected light can form a uniform light
source. Additionally, please refer to FIG. 1A, which shows each of
the protruding bumps 30, the gate line 24, the gate electrode 26
and the common line 28 are formed by the same conductive layer 22.
Moreover, please refer to FIGS. 4A and 4B, which shows an
insulating layer 48 covers the pixel region 16 including the thin
film transistor 58 and the reflective electrode 44 therein. The
insulating layer 48 also covers the peripheral circuit region 14
including the gate insulating layer 32 therein. The insulating
layer 48 within the reflective region 18 has numerous openings 52
that expose the reflective electrode 44 directly above each
protruding bump 30. At least one opening 54 is disposed in the gate
insulating layer 32 and the insulating layer 48 within the
peripheral circuit region 14. Part of the gate line 24 is exposed
through the opening 54. A conductive layer 56 fills in the opening
54. The conductive layer 56 also covers the insulating layer 48
within the peripheral circuit region 14 and covers the gate line 24
exposed through the opening 54. The conductive layer 56 could be
ITO.
[0024] To sum up, the method of fabricating the reflective pixel
array substrate is compatible with current fabricating processes.
The gate electrode and the protruding bumps of the reflective pixel
array substrate are formed by utilizing the same photo mask. The
reflective electrode, the source electrode, and the drain electrode
are formed by using the same photo mask. Therefore, the fabricating
process of the reflective pixel array substrate only needs five
photo masks so the process is simplified and the production cost
can be reduced.
[0025] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention.
* * * * *