Radio Frequency Signal Processing Circuit And Quadrature Power Amplifier

Abstract

A quadrature power amplifier capable of operating in a single-output mode and a multiple-output mode. When operating in the single-output mode, a first quadrature coupler receives a first input signal, and splits and phase-shifts the first input signal into two first split signals. A first power amplifier receives and amplifies one of the two first split signals to generate a first amplified signal. The second power amplifier receives and amplifies the other one of the two first split signals to generate a second amplified signal. The second quadrature coupler receives the first amplified signal and the second amplified signal, and phase-shifts and combines the first amplified signal and the second amplified signal into a first output signal.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 61/367,732 filed Jul. 26, 2010 and entitled "Transmit Antenna Diversity for MIMO System". The entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The invention relates to a power amplifier, and more particularly to a power amplifier capable of operating in a single-output mode and a multiple-output mode. When operating in the single-output mode, an extra 3 dB output power is gained as compared to the multiple-output mode.

[0004] 2. Description of the Related Art

[0005] Portable battery powered wireless communications devices, such as mobile terminals, cell phones, personal digital assistant, tablet computer, and the like, often have requirements to efficiently transmit information at different output power levels. As a result, RF transmitter power amplifiers need to transmit using a wide range of output power levels, while maintaining efficiency throughout operating ranges. Conventionally, in the single uplink path designs, when higher output power is required, a power amplifier having larger gain is utilized. However, the power amplifier having larger gain requires larger chip area. There is a trade off between the chip area and the output power level required.

[0006] Meanwhile, for the multiple uplink path designs in a Multiple-Input-Multiple-Output (MIMO) system, the signal power may be increased (for example, doubled) when using antenna diversity. However, when signal loss in one signal path is serious, the benefits of using multiple power amplifiers cannot be gained.

[0007] Therefore, a novel power amplifier capable of supporting both single-output and multiple-output systems while maintaining amplifying efficiency is highly required.

BRIEF SUMMARY OF THE INVENTION

[0008] A radio frequency signal processing circuit and a quadrature power amplifier are provided. An embodiment of a quadrature power amplifier capable of operating in a single-output mode and a multiple-output mode comprises a first quadrature coupler, a first power amplifier, a second power amplifier and a second quadrature coupler. When operating in the single-output mode, the first quadrature coupler receives a first input signal, and splits and phase-shifts the first input signal into two first split signals, which are phase-shifted substantially 90 degrees from each other. The first power amplifier receives and amplifies one of the two first split signals to generate a first amplified signal. The second power amplifier receives and amplifies the other one of the two first split signals to generate a second amplified signal. The second quadrature coupler receives the first amplified signal and the second amplified signal, and phase-shifts and combines the first amplified signal and the second amplified signal into a first output signal.

[0009] An embodiment of a radio frequency (RF) signal processing circuit coupled between a transceiver module and at least a first antenna and a second antenna comprises a quadrature power amplifier. The quadrature power amplifier is capable of operating in a single-output mode and a multiple-output mode, and comprises a first input terminal and a second input terminal coupled to the transceiver, and a first output terminal coupled to the first antenna and a second output terminal coupled to the second antenna. When operating in the single-output mode, the quadrature power amplifier receives a first input signal from the transceiver module via the first input terminal, splits and phase-shifts the first input signal into two first split signals, and further amplifies and combines the two first split signals to generate a first output signal, which is an amplified version of the first input signal with a predetermined phase difference and is output to one of the first and the second antennas.

[0010] Another embodiment of a radio frequency (RF) signal processing circuit coupled between a transceiver module and at least a first antenna and a second antenna comprises a quadrature power amplifier. The quadrature power amplifier comprises a first input terminal and a second input terminal coupled to the transceiver, and a first output terminal coupled to the first antenna and a second output terminal coupled to the second antenna. When the quadrature power amplifier receives a first input signal and a second input signal from the transceiver module respectively via the first input terminal and the second input terminal, the quadrature power amplifier splits, and phase-shifts the first input signal and the second input signal into two first split signals and two second split signals, respectively, and further amplifies and combines the two first split signals and the two second split signals to respectively generate a first output signal, which is an amplified version of the first input signal with a first predetermined phase difference, and a second output signal, which is an amplified version of the second input signal with a second predetermined phase difference, and outputs the first output signal to the second antenna and the second output signal to the first antenna.

[0011] A detailed description is given in the following embodiments with reference to the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0012] The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

[0013] FIG. 1 shows a simplified block diagram of a communications apparatus according to an embodiment of the invention;

[0014] FIG. 2 shows a simplified block diagram of a quadrature power amplifier according to an embodiment of the invention;

[0015] FIG. 3a shows a simplified block diagram of a communications apparatus operating in TDD system with a quadrature power amplifier coupled therein according to an embodiment of the invention;

[0016] FIG. 3b shows a simplified block diagram of a communications apparatus operating in FDD system with a quadrature power amplifier coupled therein according to another embodiment of the invention;

[0017] FIG. 4a shows a simplified block diagram of a communications apparatus operating in TDD system with a quadrature power amplifier coupled therein according to another embodiment of the invention;

[0018] FIG. 4b shows a simplified block diagram of a communications apparatus operating in FDD system with a quadrature power amplifier coupled therein according to yet another embodiment of the invention;

[0019] FIG. 5 is a schematic diagram showing the power and phases of the signals generated by the quadrature power amplifier when operating in the single-output mode according to an embodiment of the invention;

[0020] FIG. 6 is a schematic diagram showing the power and phases of the signals generated by the quadrature power amplifier when operating in the single-output mode according to another embodiment of the invention;

[0021] FIG. 7 is a schematic diagram showing the power and phases of the signals generated by the quadrature power amplifier when operating in the multiple-output mode according to another embodiment of the invention; and

[0022] FIG. 8 is a schematic diagram showing the power and phases of the signals generated by the quadrature power amplifier when operating in the multiple-output mode according to yet another embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

[0024] FIG. 1 shows a simplified block diagram of a communications apparatus according to an embodiment of the invention. The communications apparatus 100 may comprise a baseband module 101, a transceiver module 102, a radio frequency (RF) signal processing circuit 103 and multiple antennas 104 and 105. The baseband module 101 may comprise multiple hardware devices to perform baseband signal processing, including Analog to Digital Conversion (ADC)/Digital to Analog Conversion (DAC), gain adjusting, modulation/demodulation, encoding/decoding, and so on. The transceiver module 102 may receive RF signals, convert the received RF signals to baseband signals, which are processed by the baseband module 101, or receive baseband signals from the baseband module 101 and convert the received baseband signals to RF signals, which are later transmitted. The transceiver module 102 may also comprise multiple hardware devices to perform radio frequency conversion. For example, the transceiver module 102 may comprise a mixer to multiply the baseband signals with a carrier oscillated in the radio frequency of the wireless communications system.

[0025] The RF signal processing circuit 103 may comprise one or more T/R (transmit/receive) switches for switching the downlink and uplink paths between the transceiver module 102 and the antennas 104 and 105 when operate in TDD system or may comprise one or more T/R (transmit/receive) duplexer to separate the downlink and uplink path signals between transceiver module 102 and the antennas 104 and 105 when operate in FDD system, and one or more power amplifiers for amplifying the RF signals to be later transmitted to the air interface or amplifying the RF signals that have been received from the antennas. According to an embodiment of the invention, the RF signal processing circuit 103 may further comprise a quadrature power amplifier, which is capable of amplifying and outputting one or more signals to the antennas, depending on whether antenna diversity is required.

[0026] FIG. 2 shows a simplified block diagram of a quadrature power amplifier according to an embodiment of the invention. The quadrature power amplifier 200 may comprise quadrature couplers 201 and 202, and power amplifiers 203 and 204. According to an embodiment of the invention, the quadrature power amplifier 200 is capable of operating in a single-output mode and a multiple-output mode. When operating in the single-output mode, the quadrature power amplifier 200 receives a first input signal from the transceiver module via one of the input terminals TX1 and TX2, and generates a first output signal, which is an amplified version of the first input signal with a predetermined phase difference, at one of the output terminals ANT1 and ANT2. The first output signal is then transmitted by one of the antennas 104 and 105 to the air interface.

[0027] Meanwhile, when operating in the multiple-output mode, the quadrature power amplifier 200 receives a first input signal and a second input signal from the transceiver module respectively via the input terminals TX1 and TX2, and generates a first output signal at one of the output terminals ANT1 and ANT2 and a second output signal at the other one of the output terminals ANT1 and ANT2. The first output signal is an amplified version of the first input signal with a first predetermined phase difference, and the second output signal is an amplified version of the second input signal with a second predetermined phase difference. The first predetermined phase difference and the second predetermined phase difference may be the same or different, depending on the phases of the first and second input signals. The first and second output signals are then transmitted by the antennas 104 and 105, respectively.

[0028] FIG. 3a shows a simplified block diagram of a communications apparatus operating in TDD (Time Division Duplex) system with a quadrature power amplifier coupled therein according to an embodiment of the invention. As shown in FIG. 3a, the RF signal processing circuit 303 may comprise low noise amplifiers 333 and 334 in the downlink paths, a quadrature power amplifier 335 in the uplink paths and T/R switches 331 and 332. The T/R switches 331 and 332 are arranged to selectively connect the antennas 104 and 105 to the down link paths or the uplink paths when operate in TDD system. The low noise amplifiers 333 and 334 in the downlink paths are arranged to amplify the RF signals that have been received from the antennas 104 and 105, and the quadrature power amplifier 335 is arranged to amplify the RF signals to be later transmitted. The nodes BBRX1 and BBRX2 of the transceiver module 102 are coupled to the baseband module 101 for transmitting the received downlink signals thereto, and the nodes BBTX1 and BBTX2 of the transceiver module 102 are coupled to the baseband module 101 for receiving the uplink signals to be later transmitted therefrom. In the embodiment, the quadrature power amplifier 335 is capable of operating in the single-output mode and the multiple-output mode (which will be discussed in detail in the following paragraphs). When operating in the single-output mode, an extra 3 dB output power in the output signal is gained as compared to the multiple-output mode.

[0029] FIG. 3b shows a simplified block diagram of a communications apparatus operating in FDD (Frequency Division Duplex) system with a quadrature power amplifier coupled therein according to an embodiment of the invention. As shown in FIG. 3b, the RF signal processing circuit 303 may comprise low noise amplifiers 333 and 334 in the downlink paths, a quadrature power amplifier 335 in the uplink paths and duplexers 336 and 337. The duplexers 336 and 337 are arranged to connect the antennas 104 and 105 to the downlink paths or the uplink paths and separate the downlink signal and uplink signal when operate in FDD system. The low noise amplifiers 333 and 334 in the downlink paths are arranged to amplify the RF signals that have been received from the antennas 104 and 105, and the quadrature power amplifier 335 is arranged to amplify the RF signals to be later transmitted. In the embodiment, the quadrature power amplifier 335 is capable of operating in the single-output mode and the multiple-output mode (which will be discussed in detail in the following paragraphs). When operating in the single-output mode, an extra 3 dB output power in the output signal is gained as compared to the multiple-output mode.

[0030] FIG. 4a shows a simplified block diagram of a communications apparatus operating in TDD system with a quadrature power amplifier coupled therein according to another embodiment of the invention. As shown in FIG. 4a, the RF signal processing circuit 303 may further comprise a switch 436 coupled between the quadrature power amplifier 435 and the transceiver module 102. In the embodiment, the quadrature power amplifier 435 is capable of operating in the single-output mode, and the switch 436 is arranged to selectively pass the signal received from the transceiver module 102 to one of the input terminals TX1 and TX2 in response to an antennal selection signal S.sub.SEL. The nodes BBRX1 and BBRX2 of the transceiver module 102 are coupled to the baseband module 101 for transmitting the received downlink signals thereto, and the node BBTX of the transceiver module 102 is coupled to the baseband module 101 for receiving the uplink signals to be later transmitted therefrom. The antennal selection signal S.sub.SEL may be generated by the baseband module 101 to indicate which antenna is selected to transmit the output signal. Thereafter, the amplified output signal is transmitted to one of the corresponding antennas 104 and 105.

[0031] FIG. 4b shows a simplified block diagram of a communications apparatus operating in FDD system with a quadrature power amplifier coupled therein according to another embodiment of the invention. As shown in FIG. 4b, the RF signal processing circuit 303 may further comprise a switch 436 coupled between the quadrature power amplifier 435 and the transceiver module 102. One or more duplexer as shown to separate the downlink and uplink signal from and to antennas when operate in FDD system. In the embodiment, the quadrature power amplifier 435 is capable of operating in the single-output mode, and the switch 436 is arranged to selectively pass the signal received from the transceiver module 102 to one of the input terminals TX1 and TX2 in response to an antennal selection signal S.sub.SEL. The antennal selection signal S.sub.SEL may be generated by the baseband module 101 to indicate which antenna is selected to transmit the output signal. Thereafter, the amplified output signal is transmitted to one of the corresponding antennas 104 and 105.

[0032] FIG. 5 is a schematic diagram showing the power and phases of the signals generated by the quadrature power amplifier when operating in the single-output mode according to an embodiment of the invention. In the embodiment, the input terminal TX2 is terminated (for example, terminated when the switch does not connect the input terminal TX2 to the transceiver module 102). Therefore, the quadrature power amplifier can only receive signals from the transceiver module 102 via the input terminal TX1. The quadrature power amplifier receives the input signal S.sub.1 with -5 dBm of power and a 0 degree phase (labeled by S.sub.1(-5 dBm, 0.degree. as shown) from the input terminal TX1. The quadrature coupler 201 splits and phase-shifts the input signal S.sub.1(-5 dBm, 0.degree. into two split signals S.sub.11(-8 dBm, -90.degree. and S.sub.12(-8 dBm, -180.degree.. Because the input signal S.sub.1 is split, a 3 dB power drop is presented in the split signals.

[0033] The power amplifier 203 having a predetermined gain (for example, 35 dB) receives and amplifies the split signal S.sub.11(-8 dBm, -90.degree.) to generate an amplified signal S'.sub.11(27 dBm, -90.degree.). The power amplifier 204 having a predetermined gain (for example, 35 dB) receives and amplifies another split signals S.sub.12(-8 dBm, -180.degree.) to generate another amplified signal S'.sub.12(27 dBm, -180.degree.). The quadrature coupler 202 receives and phase-shifts the amplified signals S'.sub.11(27 dBm, -90.degree. and S'.sub.12(27 dBm, -180.degree.), so as to generate the phase-shifted signals S''.sub.11(27 dBm, -180.degree.) and the S''.sub.12(27 dBm, 0.degree.) at the output terminal ANT1, and generates the phase-shifted signals S''.sub.11(27 dBm, -270.degree.) and S''.sub.12(27 dBm, -270.degree.) at the output terminal ANT2, respectively. Because -180.degree. and 0.degree. are complementary phases, after the phase-shifted signals S''.sub.11(27 dBm, -180.degree.) and the S''.sub.12(27 dBm, 0.degree.) are combined at the output terminal ANT1, the amplitude of the combined signal at the output terminal ANT1 is zero. Meanwhile, because the phase-shifted signals S''.sub.11(27 dBm, -270.degree.) and S''.sub.12(27 dBm, -270.degree.) at the output terminal ANT2 have the same phase, an output signal S'.sub.1(30 dBm, -270.degree.) is generated after the phase-shifted signals S''.sub.11(27 dBm, -270.degree.) and S''.sub.12(27 dBm, -270.degree.) are combined at the output terminal ANT2. Therefore, the output signal S'.sub.1(30 dBm, -270.degree.), which is an amplified version of the input signal S.sub.1(-5 dBm, 0.degree.) with a predetermined phase difference, is generated at the output terminal ANT2.

[0034] FIG. 6 is a schematic diagram showing the power and phases of the signals generated by the quadrature power amplifier when operating in the single-output mode according to another embodiment of the invention. In the embodiment, the input terminal TX1 is terminated (for example, terminated when the switch does not connect the input terminal TX1 to the transceiver module 102). Therefore, the quadrature power amplifier can only receive signals from the transceiver module 102 via the input terminal TX2. The quadrature power amplifier receives the input signal S.sub.2 with -5 dBm of power and a 0 degree phase (labeled by S.sub.2(-5 dBm, 0.degree.) as shown) from the input terminal TX2. The quadrature coupler 201 splits and phase-shifts the input signal S.sub.2(-5 dBm, 0.degree.) into two split signals S.sub.21(-8 dBm, -180.degree.) and S.sub.22(-8 dBm, -90.degree.). Because the input signal S.sub.2 is split, a 3 dB power drop is presented in the split signals.

[0035] The power amplifier 203 receives and amplifies the split signal S.sub.21(-8 dBm, -180.degree.) to generate an amplified signal S'.sub.21(27 dBm, -180.degree.). The power amplifier 204 receives and amplifies another split signals S.sub.22(-8 dBm, -90.degree.) to generate another amplified signal S'22(27 dBm, -90.degree.). The quadrature coupler 202 receives and phase-shifts the amplified signals S'.sub.21(27 dBm, -180.degree. and S'.sub.22(27 dBm, -90.degree.), so as to generate the phase-shifted signals S''.sub.21(27 dBm, -270.degree.) and the S''.sub.22(27 dBm, -270.degree.) at the output terminal ANT1, and generates the phase-shifted signals S''.sub.21(27 dBm, 0.degree.) and S''.sub.22 (27 dBm, -180.degree.) at the output terminal ANT2, respectively. Similarly, because -180.degree. and 0.degree. are complementary phases, the amplitude of the combined signal at the output terminal ANT2 is zero after the phase-shifted signals S''.sub.21(27 dBm, 0.degree.) and S''.sub.22 (27 dBm, -180.degree.) are combined at the output terminal ANT2. Meanwhile, because the phase-shifted signals S''.sub.21(27 dBm, -270.degree.) and the S''.sub.22(27 dBm, -270.degree.) at the output terminal ANT1 have the same phase, an output signal S'.sub.2(30 dBm, -270.degree.) is generated after the phase-shifted signals S''.sub.21(27 dBm, -270.degree.) and the S''.sub.22(27 dBm, -270.degree.) are combined at the output terminal ANT1. Therefore, the output signal S'.sub.2(30 dBm, -270.degree.), which is an amplified version of the input signal S.sub.2(-5 dBm, 0.degree.) with a predetermined phase difference, is generated at the output terminal ANT1.

[0036] FIG. 7 is a schematic diagram showing the power and phases of the signals generated by the quadrature power amplifier when operating in the multiple-output mode according to another embodiment of the invention. In the embodiment, the quadrature power amplifier receives the input signal S.sub.1(-8 dBm, 0.degree.) from the input terminal TX1 and the input signal S.sub.2(-8 dBm, 0.degree.) from the input terminal TX2. The quadrature coupler 201 splits and phase-shifts the input signal S.sub.1(-8 dBm, 0.degree.) into two split signals S.sub.11(-11 dBm, -90.degree.) and S.sub.12(-11 dBm, -180.degree.), and splits and phase-shifts the input signal S.sub.2(-8 dBm, 0.degree.) into two split signals S.sub.21(-11 dBm, -180.degree.) and S.sub.22(-11 dBm, -90.degree.), respectively.

[0037] The power amplifier 203 receives and amplifies the split signals S.sub.11(-11 dBm, -90.degree.) and S.sub.21(-11 dBm, -180.degree.) to generate the amplified signals S'.sub.11(24 dBm, -90.degree.) and S'.sub.21(24 dBm, -180.degree.). Similarly, the power amplifier 204 receives and amplifies the split signals S.sub.12(-11 dBm, -180.degree.) and S.sub.22(-11 dBm, -90.degree.) to generate the amplified signals S'.sub.12(24 dBm, -180.degree.) and 5'.sub.22(24 dBm, -90.degree.). The quadrature coupler 202 receives and phase-shifts the amplified signals S'.sub.11(24 dBm, -90.degree.) and S'.sub.21(24 dBm, -180.degree.), so as to generate the phase-shifted signals S''.sub.11(24 dBm, -180.degree.) and the S''.sub.21(24 dBm, -270.degree.) at the output terminal ANT1 and generates the phase-shifted signals S''.sub.11(24 dBm, -270.degree.) and the S''.sub.21(24 dBm, 0.degree.) at the output terminal ANT2.

[0038] The quadrature coupler 202 further receives and phase-shifts the amplified signals S'12(24 dBm, -180.degree.) and S'.sub.22(24 dBm, -90.degree.) and generates the phase-shifted signals S''.sub.12 (24 dBm, 0.degree.) and S''.sub.22(24 dBm, -270.degree.) at the output terminal ANT1, and generates the phase-shifted signals S''.sub.12 (24 dBm, -270.degree.) and S''.sub.22(24 dBm, -180.degree.) at the output terminal ANT2. Because the phase-shifted signals S''.sub.21(24 dBm, -270.degree.) and the S''.sub.22(24 dBm, -270.degree.) at the output terminal ANT1 have the same phase, they are combined as an output signal S'2(27 dBm, -270.degree.) at the output terminal ANT1. Similarly, because the phase-shifted signals S''.sub.11 (24 dBm, -270.degree.) and S''.sub.12(24 dBm, -270.degree.) at the output terminal ANT2 have the same phase, they are combined as an output signal S'.sub.1(27 dBm, -270.degree.) at the output terminal ANT2. Note that the remaining phase-shifted signals at the output terminals ANT1 and ANT2 are cancelled due to being complementary phases. Therefore, the output signal S'.sub.1(27 dBm, -270.degree.), which is an amplified version of the input signal S.sub.1(-8 dBm, 0.degree.) with a predetermined phase difference, and S'.sub.2(27 dBm, -270.degree.), which is an amplified version of the input signal S.sub.2(-8 dBm, 0.degree.) with a predetermined phase difference are finally generated at the output terminals. Note that in the embodiment, the input signals S.sub.1 and S.sub.2 have substantially the same phase, and the output signals S'.sub.1 and S'.sub.2 have substantially the same phase.

[0039] FIG. 8 is a schematic diagram showing the power and phases of the signals generated by the quadrature power amplifier when operating in the multiple-output mode according to yet another embodiment of the invention. In the embodiment, the quadrature power amplifier receives the input signal S.sub.1(-8 dBm, 0.degree.) from the input terminal TX1 and the input signal S.sub.2(-8 dBm, -180.degree.) from the input terminal TX2. Note that the input signals S.sub.1 and S.sub.2 have different phases. The quadrature coupler 201 splits and phase-shifts the input signal S.sub.1(-8 dBm, 0.degree.) into two split signals S.sub.11(-11 dBm, -90.degree.) and S.sub.12(-11 dBm, -180.degree.), and splits and phase-shifts the input signal S.sub.2(-8 dBm, -180.degree.) into two split signals S.sub.21(-11 dBm, 0.degree.) and S.sub.22(-11 dBm, -270.degree.), respectively.

[0040] The power amplifier 203 receives and amplifies the split signals S.sub.11(-11 dBm, -90.degree.) and S.sub.21(-11 dBm, 0.degree.) to generate the amplified signals S'.sub.11(24 dBm, -90.degree.) and S'.sub.21(24 dBm, 0.degree.). Similarly, the power amplifier 204 receives and amplifies the split signals S.sub.12(-11 dBm, -180.degree.) and S.sub.22(-11 dBm, -270.degree.) to generate the amplified signals S'.sub.12(24 dBm, -180.degree.) and S'.sub.22(24 dBm, -270.degree.). The quadrature coupler 202 receives and phase-shifts the amplified signals S'.sub.11(24 dBm, -90.degree.) and S'.sub.21(24 dBm, 0.degree.), so as to generate the phase-shifted signals S''.sub.11(24 dBm, -180.degree.) and the S''.sub.21(24 dBm, -90.degree.) at the output terminal ANT1 and generates the phase-shifted signals S''.sub.11(24 dBm, -270.degree.) and the S''.sub.21(24 dBm, -180.degree.) at the output terminal ANT2.

[0041] The quadrature coupler 202 further receives and phase-shifts the amplified signals S'.sub.12(24 dBm, -180.degree.) and S'.sub.22(24 dBm, -270.degree.) and generates the phase-shifted signals S''.sub.12 (24 dBm, 0.degree.) and S''.sub.22(24 dBm, -90.degree.) at the output terminal ANT1, and generates the phase-shifted signals S''.sub.12 (24 dBm, -270.degree.) and S''.sub.22(24 dBm, 0.degree.) at the output terminal ANT2. Because the phase-shifted signals S''.sub.21(24 dBm, -90.degree.) and the S''.sub.22(24 dBm, -90.degree.) at the output terminal ANT1 have the same phase, they are combined as an output signal S'.sub.2(27 dBm, -90.degree.) at the output terminal ANT1. Similarly, because the phase-shifted signals S''.sub.11 (24 dBm, -270.degree.) and S''.sub.12(24 dBm, -270.degree.) at the output terminal ANT2 have the same phase, they are combined as an output signal S'.sub.1(27 dBm, -270.degree.) at the output terminal ANT2. Note that the remaining phase-shifted signals at the output terminals ANT1 and ANT2 are cancelled due to being complementary phases. Therefore, the output signal S'.sub.1(2'7 dBm, -270.degree.), which is an amplified version of the input signal S.sub.1(-8 dBm, 0.degree.) with a first predetermined phase difference, and S'.sub.2(27 dBm, -90.degree.), which is an amplified version of the input signal S.sub.2(-8 dBm, -180.degree.) with a second predetermined phase difference are finally generated at the output terminals. Note that in the embodiment, the input signals S.sub.1 and S.sub.2 have different phases, and the output signals S'.sub.1 and S'.sub.2 have different phases. Note also that in the embodiment, the first predetermined phase difference is different from the second predetermined phase difference.

[0042] By using the quadrature couplers, the output of two power amplifiers can be automatically combined and thus, higher power can be output. When operating in the single-output mode, an extra 3 dB output power in the output signal is gained as compared to the multiple-output mode. In addition, because the proposed quadrature power amplifier is capable of operating in a single-output mode and a multiple-output mode, the proposed architecture may be applied in either the single-input-single-output (SISO) system or the multiple-input-multiple-output (MIMO) system, such as the single antenna system, the intelligent transmit antenna selection (i-TAS) system, the MIMO matrix A system, the MIMO matrix B system, the cyclic delay diversity system (CCD), and the likes. When operating in the multiple-output mode, benefits of using antenna diversity can be gained. The operation modes is activated according to the demand from the baseband to combat with the variation on the uplink channel conditions to achieve the performance target such as coverage, throughput, efficiency etc.

[0043] Use of ordinal terms such as "first", "second", "third", etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

[0044] While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.

Claims

1. A quadrature power amplifier, capable of operating in a single-output mode and a multiple-output mode, comprising: a first quadrature coupler, when operating in the single-output mode, receiving a first input signal, splitting and phase-shifting the first input signal into two first split signals, which are phase-shifted substantially 90 degrees from each other; a first power amplifier, coupled to the first quadrature coupler for receiving and amplifying one of the two first split signals to generate a first amplified signal; a second power amplifier, coupled to the first quadrature coupler for receiving and amplifying the other one of the two first split signals to generate a second amplified signal; and a second quadrature coupler, receiving the first amplified signal and the second amplified signal, and phase-shifting and combining the first amplified signal and the second amplified signal into a first output signal.

2. The quadrature power amplifier as claimed in claim 1, wherein when operating in the multiple-output mode, the first quadrature coupler further receives a second input signal, and splits and phase-shifts the second input signal into two second split signals, which are phase-shifted substantially 90 degrees from each other; the first power amplifier further receives and amplifies one of the two second split signals to generate a third amplified signal; the second power amplifier further receives and amplifies the other one of the two second split signals to generate a fourth amplified signal; and the second quadrature coupler further receives the third amplified signal and the fourth amplified signal, and phase-shifts and combines the third amplified signal and the fourth amplified signal into a second output signal.

3. The quadrature power amplifier as claimed in claim 1, wherein the first output signal is an amplified version of the first input signal with a predetermined phase difference.

4. The quadrature power amplifier as claimed in claim 2, wherein the first output signal is an amplified version of the first input signal with a first predetermined phase difference, and the second output signal is an amplified version of the second input signal with a second predetermined phase difference.

5. The quadrature power amplifier as claimed in claim 4, wherein the first predetermined phase difference equals to the second predetermined phase difference.

6. The quadrature power amplifier as claimed in claim 2, wherein when the first input signal and the second input signal have substantially the same phase, the first output signal and the second output signal have substantially the same phase, and when the first input signal and the second input signal have different phases, the first output signal and the second output signal have different phases.

7. A radio frequency (RF) signal processing circuit, coupled between a transceiver module and at least a first antenna and a second antenna, comprising: a quadrature power amplifier, capable of operating in a single-output mode and a multiple-output mode, and comprising a first input terminal and a second input terminal coupled to the transceiver, and a first output terminal coupled to the first antenna and a second output terminal coupled to the second antenna, wherein when operating in the single-output mode, the quadrature power amplifier receives a first input signal from the transceiver module via the first input terminal, splits and phase-shifts the first input signal into two first split signals, and further amplifies and combines the two first split signals to generate a first output signal, which is an amplified version of the first input signal with a predetermined phase difference and is output to one of the first and the second antennas.

8. The RF signal processing circuit as claimed in claim 7, wherein when operating in the multiple-output mode, the quadrature power amplifier further receives a second input signal from the transceiver module via the second input terminal, splits and phase-shifts the second input signal into two second split signals, and further amplifies and combines the two second split signals to generate a second output signal, which is an amplified version of the second input signal with the predetermined phase difference, and outputs the second output signal to the other one of the first and the second antennas.

9. The RF signal processing circuit as claimed in claim 7, further comprising: a switch device, coupled between the quadrature power amplifier and the transceiver module, for selectively passing the first input signal to the first input terminal or the second input terminal in response to an antennal selection signal indicating which antenna is selected when operating in the single-output mode.

10. The RF signal processing circuit as claimed in claim 8, wherein the quadrature power amplifier further comprises: a first quadrature coupler, coupled to the first input terminal and the second input terminal; a first power amplifier, coupled to the first quadrature coupler; a second power amplifier, coupled to the first quadrature coupler; and a second quadrature coupler, coupled between to the first power amplifier, second power amplifier, the first output terminal and the second output terminal.

11. The RF signal processing circuit as claimed in claim 10, wherein when operating in the single-output mode, the first quadrature coupler receives the first input signal, and splits and phase-shifts the first input signal into the two first split signals, which are phase-shifted substantially 90 degrees from each other; and when operating in the multiple-output mode, the first quadrature coupler further receives the second input signal, and splits and phase-shifts the second input signal into the two second split signals, which are phase-shifted substantially 90 degrees from each other.

12. The RF signal processing circuit as claimed in claim 11, wherein when operating in the single-output mode, the first power amplifier receives and amplifies one of the two first split signals to generate a first amplified signal, and the second power amplifier receives and amplifies the other one of the two first split signals to generate a second amplified signal; and when operating in the multiple-output mode, the first power amplifier further receives and amplifies one of the two second split signals to generate a third amplified signal, and the second power amplifier further receives and amplifies the other one of the two second split signals to generate a fourth amplified signal.

13. The RF signal processing circuit as claimed in claim 12, wherein when operating in the single-output mode, the second quadrature coupler receives the first amplified signal and the second amplified signal, and phase-shifts and combines the first amplified signal and the second amplified signal into the first output signal; and when operating in the multiple-output mode, the second quadrature coupler further receives the third amplified signal and the fourth amplified signal, and phase-shifts and combines the third amplified signal and the fourth amplified signal into the second output signal.

14. A radio frequency (RF) signal processing circuit, coupled between a transceiver module and at least a first antenna and a second antenna, comprising: a quadrature power amplifier, comprising a first input terminal and a second input terminal coupled to the transceiver, and a first output terminal coupled to the first antenna and a second output terminal coupled to the second antenna, wherein when the quadrature power amplifier receives a first input signal and a second input signal from the transceiver module respectively via the first input terminal and the second input terminal, the quadrature power amplifier splits, and phase-shifts the first input signal and the second input signal into two first split signals and two second split signals, respectively, and further amplifies and combines the two first split signals and the two second split signals to respectively generate a first output signal, which is an amplified version of the first input signal with a first predetermined phase difference, and a second output signal, which is an amplified version of the second input signal with a second predetermined phase difference, and outputs the first output signal to the second antenna and the second output signal to the first antenna.

15. The RF signal processing circuit as claimed in claim 14, wherein when the quadrature power amplifier receives only the first input signal from the transceiver module via one of the first input terminal and the second input terminal, the quadrature power amplifier outputs only the first output signal to one of the first and the second antennas.

16. The RF signal processing circuit as claimed in claim 15, further comprising: a switch device, coupled between the quadrature power amplifier and the transceiver module, for selectively passing the first input signal to the first input terminal or the second input terminal in response to an antennal selection signal indicating which antenna is selected to transmit the first output signal.

17. The RF signal processing circuit as claimed in claim 14, wherein when the first input signal and the second input signal have substantially the same phase, the first output signal and the second output signal have substantially the same phase, and when the first input signal and the second input signal have different phases, the first output signal and the second output signal have different phases.