U.S. patent application number 13/137918 was filed with the patent office on 2012-01-19 for stacked gate nonvolatile semiconductor memory and method for manufacturing the same.
This patent application is currently assigned to Kabushiki Kaisha Toshiba. Invention is credited to Kenji Aoyama, Satoshi Nagashima.
Application Number | 20120012916 13/137918 |
Document ID | / |
Family ID | 39675402 |
Filed Date | 2012-01-19 |
United States Patent
Application |
20120012916 |
Kind Code |
A1 |
Aoyama; Kenji ; et
al. |
January 19, 2012 |
Stacked gate nonvolatile semiconductor memory and method for
manufacturing the same
Abstract
A stacked gate nonvolatile semiconductor memory includes at
least a memory cell transistor and a selective gate transistor
which are formed on a semiconductor substrate. The memory cell
transistor includes a floating gate made of a semiconductor
material below an interlayer insulating layer and a control gate
made of a silicide above the interlayer insulating layer. The
selective gate transistor includes a semiconductor layer made of
the semiconductor material, a silicide layer made of the silicide
and a conductive layer made of a conductive material not subject to
silicide process which is formed through the interlayer insulating
film so as to electrically connect the semiconductor layer and the
silicide layer.
Inventors: |
Aoyama; Kenji;
(Yokohama-shi, JP) ; Nagashima; Satoshi;
(Yokohama-shi, JP) |
Assignee: |
Kabushiki Kaisha Toshiba
Tokyo
JP
|
Family ID: |
39675402 |
Appl. No.: |
13/137918 |
Filed: |
September 21, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11927799 |
Oct 30, 2007 |
8053825 |
|
|
13137918 |
|
|
|
|
Current U.S.
Class: |
257/316 ;
257/E29.3 |
Current CPC
Class: |
H01L 27/11521 20130101;
H01L 27/115 20130101; H01L 27/11524 20130101 |
Class at
Publication: |
257/316 ;
257/E29.3 |
International
Class: |
H01L 29/788 20060101
H01L029/788 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 6, 2007 |
JP |
P2007-026868 |
Claims
1.-3. (canceled)
4. A stacked gate nonvolatile semiconductor memory comprising at
least a memory cell transistor and a selective gate transistor
which are formed on a semiconductor substrate; the memory cell
transistor including: a first floating gate made of a semiconductor
material; a first interlayer insulating layer made of an insulating
material above the first floating gate; and a first control gate
made of a silicide material above the first interlayer insulating
layer, and the selective gate transistor including: a second
floating gate made of the semiconductor material; a second
interlayer insulating layer made of the insulating material above
the second floating gate; and a second control gate made of the
silicide material above the second interlayer insulating layer; a
trench formed from a top of the second control gate into the second
floating gate through the second interlayer insulating layer; and a
silicide conductive layer in the trench made of a silicide
conductive material, and electrically connecting the second
floating gate and the second control gate.
5. The stacked gate nonvolatile semiconductor memory as set forth
in claim 4, wherein said silicide conductive layer is made of at
least one selected from the group consisting of WSi, CoSi and
TiSi.sub.2.
6.-20. (canceled)
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No. 2007-026868
filed on Feb. 6, 2007; the entire contents which are incorporated
herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a stacked gate nonvolatile
semiconductor memory and a method for manufacturing the stack gate
nonvolatile semiconductor memory.
[0004] 2. Description of the Related Art
[0005] As one of nonvolatile semiconductor memories, a NAND flush
memory is well known. With the NAND flush memory, a plurality of
memory cell transistors and a plurality of selective gate
transistors are provided and in addition, the peripheral circuitry
is provided so as to operate the NAND flush memory. The memory cell
transistors, the selective gate transistors and the peripheral
circuitry are formed on a given semiconductor substrate. Each
memory cell transistor includes a floating gate made of a first
semiconductor material such as polysilicon and a control gate made
of a second semiconductor material such as polysilicon which is
formed on the floating gate via an interlayer insulating layer.
[0006] Each selective gate transistor can be formed in the same
manner as the memory cell transistor. Namely, the selective gate
transistors and the memory cell transistors are formed
simultaneously. In this case, each selective gate transistor is
configured such that a first semiconductor layer made of the first
semiconductor material and a second semiconductor layer made of the
second semiconductor material are stacked via the interlayer
insulating film. In this point of view, the NAND flush memory is
structured as a stacked gate nonvolatile semiconductor memory.
[0007] With the stacked gate nonvolatile semiconductor memory,
particularly, the second semiconductor material constituting the
control gate of the memory cell transistor is silicified so as to
reduce the resistance of the control gate and thus, reduce the
contact resistance for a contact plug. In this case, the operation
voltage of the nonvolatile semiconductor memory can be reduced and
the operationality of the nonvolatile semiconductor memory can be
enhanced (refer to Reference 1).
[0008] In the stack gate nonvolatile semiconductor memory, in
contrast, the selective gate transistor functions only as a
transistor, not a memory. As described above, if the selective gate
transistor is made of the first semiconductor layer and the second
semiconductor layer via the interlayer insulating film in
accordance with the formation of the memory cell transistor as it
is, the selective gate transistor can not exhibit the inherent
function because the first semiconductor layer and the second
semiconductor layer is electrically separated from one another via
the interlayer insulating film. In this point of view, it is
required to form a conductive layer so as to penetrate through the
interlayer insulating film.
[0009] Generally, the conductive layer composing the selective gate
transistor is made of a silicide through the silicide process for
the control gate of the memory cell transistor. In the silicide
process for the conductive layer, the intended silicide is formed
too deep into the first semiconductor layer not to maintain the
stable transistor operation originated from the change in operation
performance of the selective gate transistor such as threshold
value.
[0010] [Reference 1] JP-A 2006-310454 (KOKAI)
BRIEF SUMMARY OF THE INVENTION
[0011] An aspect of the present invention relates to a stacked gate
nonvolatile semiconductor memory including at least a memory cell
transistor and a selective gate transistor which are formed on a
semiconductor substrate; wherein the memory cell transistor
includes a floating gate made of a semiconductor material below an
interlayer insulating layer and a control gate made of a silicide
above the interlayer insulating layer; wherein the selective gate
transistor includes a semiconductor layer made of the semiconductor
material, a silicide layer made of the silicide and a conductive
layer made of a conductive material not subject to silicide process
which is formed through the interlayer insulating film so as to
electrically connect the semiconductor layer and the silicide
layer.
[0012] Another aspect of the present invention relates to a stacked
gate nonvolatile semiconductor memory including at least a memory
cell transistor and a selective gate transistor which are formed on
a semiconductor substrate; wherein the memory cell transistor
includes a floating gate made of a semiconductor material below an
interlayer insulating layer and a control gate made of a silicide
above the interlayer insulating layer; wherein the selective gate
transistor includes a semiconductor layer made of the semiconductor
material, a silicide layer made of the silicide and a silicide
conductive layer made of an additional silicide material which is
formed through the interlayer insulating film so as to electrically
connect the semiconductor layer and the silicide layer.
[0013] Still another aspect of the present invention relates to a
stacked gate nonvolatile semiconductor memory including at least a
memory cell transistor and a selective gate transistor which are
formed on a semiconductor substrate; wherein the memory cell
transistor includes a floating gate made of a semiconductor
material below an interlayer insulating layer and a control gate
made of a silicide above the interlayer insulating layer; wherein
the selective gate transistor includes a semiconductor layer made
of the semiconductor material and a conductive layer made of a
conductive material not subject to silicide process which is formed
on the semiconductor layer.
[0014] A further aspect of the present invention relates to a
stacked gate nonvolatile semiconductor memory including at least a
memory cell transistor and a selective gate transistor which are
formed on a semiconductor substrate; wherein the memory cell
transistor includes a floating gate made of a semiconductor
material below an interlayer insulating layer and a control gate
made of a silicide above the interlayer insulating layer; wherein
the selective gate transistor includes a semiconductor layer made
of the semiconductor material and a silicide conductive layer made
of an additional silicide material.
[0015] A still further aspect of the present invention relates to a
method for manufacturing a stacked gate nonvolatile semiconductor
memory, including: forming, on a semiconductor substrate, a memory
cell transistor including a floating gate made of a semiconductor
material located below an interlayer insulating film and a control
gate made of a silicide located above the interlayer insulating
film; subsequently forming a semiconductor layer of the
semiconductor material and a silicide layer of the silicide via the
interlayer insulating film, and partially removing at least the
semiconductor layer and the interlayer insulating film to form an
opening, and forming a conductive layer made of a conductive
material not subject to silicide process in the opening to form a
selective gate transistor.
[0016] Still another aspect of the present invention relates to a
method for manufacturing a stacked gate nonvolatile semiconductor
memory, including: forming, on a semiconductor substrate, a memory
cell transistor including a floating gate made of a semiconductor
material located below an interlayer insulating film and a control
gate made of a silicide located above the interlayer insulating
film; and subsequently forming a semiconductor layer of the
semiconductor material and a silicide layer of the silicide via the
interlayer insulating film, and partially removing at least the
semiconductor layer and the interlayer insulating film to form an
opening, and forming a silicide conductive layer made of an
additional silicide in the opening to form a selective gate
transistor.
[0017] A further aspect of the present invention relates to a
method for manufacturing a stacked gate nonvolatile semiconductor
memory, including: forming, on a semiconductor substrate, a memory
cell transistor including a floating gate made of a semiconductor
material located below an interlayer insulating film and a control
gate made of a silicide located above the interlayer insulating
film; and subsequently forming a semiconductor layer of the
semiconductor material and a pre-semiconductor layer via interlayer
insulating film, and removing the pre-semiconductor layer, the
interlayer insulating film and a portion of the semiconductor layer
in the stacking direction thereof, and forming, on the remaining
semiconductor layer, a conductive layer made of a conductive
material not subject to silicide process to form a selective gate
transistor.
[0018] A still further aspect of the present invention relates to a
method for manufacturing a stacked gate nonvolatile semiconductor
memory, including: forming, on a semiconductor substrate, a memory
cell transistor including a floating gate made of a semiconductor
material located below an interlayer insulating film and a control
gate made of a silicide located above the interlayer insulating
film; and subsequently forming a semiconductor layer of the
semiconductor material and a pre-semiconductor layer via interlayer
insulating film, and removing the pre-semiconductor layer, the
interlayer insulating film and a portion of the semiconductor layer
in the stacking direction thereof, and forming, on the remaining
semiconductor layer, a silicide conductive layer made of an
additional silicide to form a selective gate transistor.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] FIG. 1 is a perspective view schematically showing an
essential part of a stacked gate nonvolatile semiconductor memory
according to a first embodiment.
[0020] FIG. 2 is a cross sectional view of the stacked gate
nonvolatile semiconductor memory shown in FIG. 1, as viewed from
the direction designated by the arrow "A".
[0021] FIG. 3 is a cross sectional view showing a step in a method
for manufacturing the stacked gate nonvolatile semiconductor memory
in the first embodiment (third embodiment).
[0022] FIG. 4 is a cross sectional view showing another step in a
method for manufacturing the stacked gate nonvolatile semiconductor
memory in the first embodiment.
[0023] FIG. 5 is a cross sectional view showing still another step
in a method for manufacturing the stacked gate nonvolatile
semiconductor memory in the first embodiment.
[0024] FIG. 6 is a cross sectional view showing a further step in a
method for manufacturing the stacked gate nonvolatile semiconductor
memory in the first embodiment.
[0025] FIG. 7 is a perspective view schematically showing an
essential part of a stacked gate nonvolatile semiconductor memory
according to a second embodiment.
[0026] FIG. 8 is a perspective view schematically showing an
essential part of a stacked gate nonvolatile semiconductor memory
according to a third embodiment.
[0027] FIG. 9 is a cross sectional view showing another step in a
method for manufacturing the stacked gate nonvolatile semiconductor
memory in the third embodiment.
[0028] FIG. 10 is a cross sectional view showing still another step
in a method for manufacturing the stacked gate nonvolatile
semiconductor memory in the third embodiment.
[0029] FIG. 11 is a cross sectional view showing a further step in
a method for manufacturing the stacked gate nonvolatile
semiconductor memory in the third embodiment.
[0030] FIG. 12 is a perspective view schematically showing an
essential part of a stacked gate nonvolatile semiconductor memory
according to a fourth embodiment.
DETAILED DESCRIPTION OF THE INVENTION
[0031] Then, some embodiments will be described with reference to
the drawings.
First Embodiment
[0032] FIG. 1 is a perspective view schematically showing an
essential part of a stacked gate nonvolatile semiconductor memory
according to a first embodiment. FIG. 2 is a cross sectional view
of the stacked gate nonvolatile semiconductor memory shown in FIG.
1, as viewed from the direction designated by the arrow "A". For
clarifying the distinctive feature of the present embodiment, some
components may be different from the real ones in size and the
like.
[0033] As shown in FIGS. 1 and 2, in the stacked gate nonvolatile
semiconductor memory 10 of this embodiment, a plurality of memory
cell transistors 12 and a plurality of selective gate transistors
13 are provided on a semiconductor substrate 11 made of, e.g., Si
via corresponding tunnel insulating films 111. The memory cell
transistors 12 are separated from one another via corresponding
element isolation insulating films 14. Then, each memory cell
transistor 12 and each selective gate transistor 13 are also
separated from one another via corresponding element isolation
insulating film 14. Then, the adjacent selective gate transistors
13 are separated from one another via corresponding element
isolation insulating film 15. The tunnel insulating film 111 may be
made of a silicon oxynitride film with a thickness of 85 nm.
However, the thickness of the silicon oxynitride film is
exemplified in the present technological level of the nonvolatile
semiconductor memory, but may be varied in accordance with the
development of the technological level of the nonvolatile
semiconductor memory.
[0034] The element isolation insulating films 14 and 15 may be
formed in various structures commensurate with the manufacturing
process of the nonvolatile semiconductor memory 10 and in view of
the development in characteristic of the nonvolatile semiconductor
memory 10. In this embodiment, the detail description relating to
the element isolation insulating films 14 and 15 will be omitted
for convenience so that the element isolation insulating films 14
and 15 are considered as single layers, respectively.
[0035] The memory cell transistor 12 includes a floating gate 121
made of, e.g., phosphor-doped silicon (P-doped Si), an interlayer
insulating film 122 and a control gate 123 made of silicide from
the bottom to the top thereof. The interlayer insulating film 122
may be made of an NONON film of silicon (N: nitrogen, O: oxygen).
The thickness of the interlayer insulating film 122 may be set to
85 nm. Since the control gate 123 is made of the silicide which is
formed by reacting a Ni, NiPt ot Co film with a silicon film, the
resistance of the control gate 123 is reduced in comparison with a
control gate made of polysilicon.
[0036] The selective gate transistor 13 includes a semiconductor
layer 131 made of the same semiconductor material such as
phosphor-doped silicon (P-doped Si), an interlayer insulating film
132 and a silicide layer 133 from the bottom to the top thereof.
The interlayer insulating film 132 may be formed in the same
structure as the interlayer insulating film 122 originated from the
manufacturing method of the nonvolatile semiconductor memory 10.
Then, a conductive layer 18 is formed from the top of the silicide
layer 133 into the semiconductor layer 131 through the interlayer
insulating film 132 so as to embed the opening 13A formed at the
silicide layer 133. The conductive layer 18 is made of a material
not to be reacted with silicon (Si) such as tungsten (W). Then, a
barrier film 17 is formed of titanium (Ti) or titanium nitride
(TiN) on the inner wall of each opening 13A so that the conductive
layer 18 is not contacted directly with the silicide layer 133.
[0037] With the selective gate transistor 13, the semiconductor
layer 131 and the silicide layer 133 are electrically connected
with the conductive layer 18 via the interlayer insulating film
132. As a result, the selective gate transistor 13 can exhibit the
inherent performance as it is. Then, in the annealing process to
silicify the floating gate 123 in the memory cell transistor 12,
the conductive layer 18 can not be reacted with silicon (Si) so as
not to be converted into the corresponding silicide layer. In the
selective gate transistor 13, therefore, since the area in the
vicinity of the semiconductor substrate 11 is not made of the
silicide, various characteristics of the selective gate transistor
13 such as threshold value can be maintained as they are because
the silicide can not affect the selective gate transistor 13. The
annealing process for forming the silicide floating gate 123 will
be described in detail hereinafter.
[0038] With the memory cell transistor 12, the floating gate 121 is
located below the interlayer insulating layer 122 and the control
gate 123 is located above the interlayer insulating layer 122 so as
to exhibit the inherent function as a memory cell. Since the
control gate 123 is made of silicide, the contact resistance of the
control gate 123 for a contact plug or the like can be reduced. As
a result, the nonvolatile semiconductor memory 10 can be operated
stably under the condition that the operational voltage is reduced
on the stable operation of the selective gate transistor 13.
[0039] The conductive layer 18 may be made of TiN, aluminum (Al)
and copper (Cu) in addition to W as described above. These
materials are unlikely to be reacted with silicon (Si) so as not to
form the corresponding silicide.
[0040] Then, a method for manufacturing the stacked gate
nonvolatile semiconductor memory will be described. FIGS. 3 to 6
are cross sectional views relating to the manufacturing method of
the nonvolatile semiconductor memory. In the manufacturing method
of this embodiment, attention is paid to a part relating to one
memory unit of the nonvolatile semiconductor memory. First of all,
as shown in FIG. 3, the semiconductor substrate 11 is prepared as a
Si substrate, and the tunnel insulating film 111 is formed of
silicon oxynitride or the like on the semiconductor substrate 11 by
means of oxynitriding treatment for the surface of the
semiconductor substrate 11. Then, the semiconductor layers 121;
131, the interlayer insulating films 122; 123 and the
pre-semiconductor layers 123A; 133A are formed on the semiconductor
substrate 11 via the tunnel insulating film 111. The semiconductor
layers 121 and 131 are made of the first semiconductor material
such as phosphor-doped silicon (P-doped Si). The pre-semiconductor
layers 123A and 133A are also made of, e.g., phosphor-doped silicon
(P-doped Si). The semiconductor layers and the pre-semiconductor
layers are formed by means of normal film forming technique such as
chemical vapor deposition (CVD).
[0041] Then, a prescribed etching treatment is carried out for the
thus obtained laminated structure via a mask to form some openings.
Then, the element isolation insulating films 14 and 15 are formed
into the openings. The element isolation insulating films 14
insulate the adjacent memory cell transistors 12, and the memory
cell transistor 12 and the selective gate transistor 13 adjacent to
the memory cell transistor 12 as described above. The element
isolation insulating films 15 insulate the adjacent selective gate
transistors 13 to be formed later.
[0042] Then, as shown in FIG. 4, the pre-semiconductor layers 123A
and 133A are nitrided to form the silicon nitride films 16. Then, a
predetermined resist pattern 19 is formed on the silicon nitride 16
and a dry etching process is carried out so that the openings 13A
are formed at the laminated structure formed by the step shown in
FIG. 3 in the thickness direction of the laminated structure. In
this case, the openings 13A are formed from the pre-semiconductor
layers 133A to the semiconductor layers 131 through the interlayer
insulating layers 132.
[0043] Then, as shown in FIG. 5, the resist pattern 19 is removed
by means of ashing, and then, the barrier films 17 are formed of
titanium (Ti), titanium nitride (TiN) or the like over the
laminated structure formed by the step shown in FIG. 4 so as to be
also formed on the inner wall of the openings 13A by mean of
sputtering. Then, the conductive layers 18 are formed of tungsten
(W) or the like on the conductive layer 17 so as to embed the
openings 13A by means of chemical vapor deposition (CVD) or the
like. Then, as shown in FIG. 6, portions of the conductive layers
18 and the barrier film 17 remaining on the laminated structure are
etched and removed, and then, a film (not shown) made of platinum
(Pt), nickel-platinum (NiPt) or cobalt (Co) is formed on the
laminated structure. Then, a predetermined annealing treatment is
carried out for the film by means of lamp heating so that the
constituent elements of the film such as nickel elements can be
diffused into the pre-semiconductor layers 123A and 133A, thereby
forming the respective silicide layers.
[0044] As a result, in the memory cell transistor 12, the silicide
layer functions as the control gate, and in the selective gate
transistor 13, the silicide layer 133 is electrically connected
with the semiconductor layer 131 via the conductive layer 18 so
that the selective gate transistor 13 can operate as a single
transistor as described in FIGS. 1 and 2.
Second Embodiment
[0045] FIG. 7 is a perspective view schematically showing an
essential part of a stacked gate nonvolatile semiconductor memory
according to a second embodiment. For clarifying the distinctive
feature of the present embodiment, some components maybe different
from the real ones in size and the like. Moreover, like or
corresponding components may be designated by the same reference
numerals throughout the drawings.
[0046] As shown in FIG. 7, the stacked gate nonvolatile
semiconductor memory 20 in this embodiment is different from the
one in the first embodiment in that the semiconductor layer 131 and
the silicide layer 133 are electrically connected with one another
directly via the silicide conductive layer 28, instead of the
conductive layer 18 not made of silicide, through the interlayer
insulating film 132 so that the selective gate transistor 13 can
function as a single transistor.
[0047] In this embodiment, since the semiconductor layer 131 and
the silicide layer 133 are electrically connected with one another
by the silicide conductive layer 28, the silicide conductive layer
28 cannot be reacted with silicon at the annealing process for
silicifying the floating gate 123 in the memory cell transistor 12.
As a result, there is not such a disadvantage as the area in the
vicinity of the semiconductor substrate 11 is made of silicide to
deteriorate some characteristics such as threshold value of the
selective gate transistor 13.
[0048] The silicide conductive layer 28 can exhibit the inherent
barrier performance to some degrees. As is apparent from FIG. 7,
therefore, no barrier film made of titanium (Ti) or the like is
required to be formed so that the manufacturing process of the
nonvolatile semiconductor memory 20 can be simplified.
[0049] In this embodiment, the conductive layer 28 may be made of
tungsten silicide (WSi), cobalt silicide (CoSi), titanium silicide
(TiSi.sub.2) and the like.
[0050] The nonvolatile semiconductor memory 20 can be manufactured
in the same manner as the nonvolatile semiconductor memory 10 in
the first embodiment except that the corresponding conductive
layers are different from one another and whether the barrier film
is formed or not.
[0051] The silicide conductive layer 28 may be formed by means of
chemical vapor deposition (CVD) using (a) prescribed raw material
gas(es). In the case of the formation of the WSi conductive layer
48, for example, a WF.sub.6 raw material gas and a
SiH.sub.2Cl.sub.2 (dichlorosilane) raw material gas are
employed.
Third Embodiment
[0052] FIG. 8 is a perspective view schematically showing an
essential part of a stacked gate nonvolatile semiconductor memory
according to a third embodiment. For clarifying the distinctive
feature of the present embodiment, some components may be different
from the real ones in size and the like. Moreover, like or
corresponding components may be designated by the same reference
numerals throughout the drawings. In this embodiment, attention is
paid to a part relating to one memory unit of the nonvolatile
semiconductor memory.
[0053] As shown in FIG. 8, in the stacked gate nonvolatile
semiconductor memory 30 of this embodiment, a plurality of memory
cell transistors 12 and a plurality of selective gate transistors
13 are provided on a semiconductor substrate 11 made of, e.g., Si
via corresponding tunnel insulating films 111. The memory cell
transistors 12 are separated from one another via corresponding
element isolation insulating films 14. Then, each memory cell
transistor 12 and each selective gate transistor 13 are also
separated from one another via corresponding element isolation
insulating film 14. Then, the adjacent selective gate transistors
13 are separated from one another via corresponding element
isolation insulating films 15. The tunnel insulating film 111 may
be made of a silicon oxynitride film with a thickness of 85 nm.
However, the thickness of the silicon oxynitride film is
exemplified in the present technological level of the nonvolatile
semiconductor memory, but may be varied in accordance with the
development of the technological level of the nonvolatile
semiconductor memory.
[0054] The element isolation insulating films 14 and 15 may be
formed in various structures commensurate with the manufacturing
process of the nonvolatile semiconductor memory 30 and in view of
the development in characteristic of the nonvolatile semiconductor
memory 30. In this embodiment, the detail description relating to
the element isolation insulating films 14 and 15 will be omitted
for convenience so that the element isolation insulating films 14
and 15 are considered as single layers, respectively.
[0055] The memory cell transistor 12 includes a floating gate 121
made of, e.g., phosphor-doped silicon (P-doped Si), an interlayer
insulating film 122 and a control gate 123 made of silicide from
the bottom to the top thereof. The interlayer insulating film 122
may be made of an NONON film of silicon (N: nitrogen, O: oxygen).
The thickness of the interlayer insulating film 122 may be set to
85 nm. Since the control gate 123 is made of the silicide which is
formed by reacting a Ni, NiPt ot Co film with a silicon film, the
resistance of the control gate 123 is reduced in comparison with a
control gate made of polysilicon.
[0056] The selective gate transistor 23 includes a semiconductor
layer 231, a barrier film 232 and a conductive layer 38 made of,
e.g., tungsten (W) not subject to the silicide process. In the
selective gate transistor 23, since the conductive layer 38 is
formed directly on the semiconductor layer 231 via the barrier
layer 232, the conductive layer 38 is electrically connected with
the semiconductor layer 231. As a result, the selective gate
transistor 23 can function as a single transistor. Then, in the
annealing process to silicify the floating gate 123 in the memory
cell transistor 12, the conductive layer 38 can not be reacted with
silicon (Si) so as not to be converted into the corresponding
silicide layer. In the selective gate transistor 23, therefore,
since the area in the vicinity of the semiconductor substrate 11 is
not made of the silicide, various characteristics of the selective
gate transistor 23 such as threshold value can be maintained as
they are because the silicide can not affect the selective gate
transistor 23. The annealing process for forming the silicide
floating gate 123 will be described in detail hereinafter.
[0057] The barrier film 232 prevents the interdiffusion between the
constituent elements of the semiconductor layer 231 and the
constituent elements of the conductive layer 38 and thus, the
formation of the intermixed layer of the semiconductor layer 231
and the conductive layer 28.
[0058] With the memory cell transistor 12, the floating gate 121 is
located below the interlayer insulating layer 122 and the control
gate 123 is located above the interlayer insulating layer 122 so as
to exhibit the inherent function as a memory cell. Since the
control gate 123 is made of silicide, the contact resistance of the
control gate 123 for a contact plug or the like can be reduced. As
a result, the nonvolatile semiconductor memory 30 can be operated
stably under the condition that the operational voltage is reduced
on the stable operation of the selective gate transistor 23.
[0059] The conductive layer 38 may be made of TiN, aluminum (Al)
and copper (Cu) in addition to W as described above. These
materials are unlikely to be reacted with silicon (Si) so as not to
form the corresponding silicide.
[0060] Then, a method for manufacturing the stacked gate
nonvolatile semiconductor memory will be described. FIGS. 3 and 9
to 11 are cross sectional views relating to the manufacturing
method of the nonvolatile semiconductor memory. First of all, as
shown in FIG. 3, the semiconductor substrate 11 is prepared as a Si
substrate, and the tunnel insulating film 111 is formed of silicon
oxynitride or the like on the semiconductor substrate 11 by means
of oxynitriding treatment for the surface of the semiconductor
substrate 11. Then, the semiconductor layers 121; 131, the
interlayer insulating films 122; 123 and the pre-semiconductor
layers 123A; 133A are formed on the semiconductor substrate 11 via
the tunnel insulating film 111. The semiconductor layers 121 and
131 are made of the first semiconductor material such as
phosphor-doped silicon (P-doped Si). The pre-semiconductor layers
123A and 133A are also made of, e.g., phosphor-doped silicon
(P-doped Si). The semiconductor layers and the pre-semiconductor
layers are formed by means of normal film forming technique such as
chemical vapor deposition (CVD).
[0061] Then, a prescribed etching treatment is carried out for the
thus obtained laminated structure via a mask to form some openings.
Then, the element isolation insulating films 14 and 15 are formed
into the openings. The element isolation insulating films 14
insulate the adjacent memory cell transistors 12, and the memory
cell transistor 12 and the selective gate transistor 23 adjacent to
the memory cell transistor 12 as described above. The element
isolation insulating films 15 insulate the adjacent selective gate
transistors 23 to be formed later.
[0062] Then, as shown in FIG. 9, the pre-semiconductor layers 123A
and 133A are nitrided to form the silicon nitride films 16. Then, a
predetermined resist pattern 19 is formed on the silicon nitride 16
and a dry etching process is carried out via the resist pattern 19
so that an area for the selective gate transistor 13 to be formed
can be formed by partially removing the pre-semiconductor layer
133A, the interlayer insulating film 132 and the semiconductor
layer 131 in the thickness direction of the laminated
structure.
[0063] Then, as shown in FIG. 10, the resist pattern 19 is removed
by means of ashing, and then, the barrier layer 232 is formed of
titanium (Ti), titanium nitride (TiN) or the like over the
laminated structure. Then, the conductive layer 38 is formed over
the laminated structure so as to embed the area for forming the
selective gate transistor 13 by means of chemical vapor deposition
(CVD). Then, as shown in FIG. 11, portions of the conductive layers
38 and the barrier layer 23 remaining on the laminated structure
are etched and removed, and then, a film (not shown) made of
platinum (Pt), nickel-platinum (NiPt) or cobalt (Co) is formed on
the laminated structure. Then, a predetermined annealing treatment
is carried out for the film by means of lamp heating so that the
constituent elements of the film such as nickel elements can be
diffused into the pre-semiconductor layer 123A, thereby forming the
corresponding silicide layer. As a result, in the memory cell
transistor 12, the silicide layer functions as the control gate
123.
[0064] In the selective gate transistor 23, the conductive layer 38
is not subject to the silicide process so as to be electrically
connected with the semiconductor layer 231 via the barrier layer
232. As a result, the selective gate transistor 23 can function
Fourth Embodiment
[0065] FIG. 12 is a perspective view schematically showing an
essential part of a stacked gate nonvolatile semiconductor memory
according to a fourth embodiment. For clarifying the distinctive
feature of the present embodiment, some components may be different
from the real ones in size and the like. Moreover, like or
corresponding components may be designated by the same reference
numerals throughout the drawings.
[0066] As shown in FIG. 12, the stacked gate nonvolatile
semiconductor memory 40 in this embodiment is different from the
one in the third embodiment in that the selective gate transistor
23 includes a silicide conductive layer 48, instead of the
conductive layer 38, so as to function as a single transistor.
[0067] In this embodiment, since the silicide conductive layer 48
is formed directly on the semiconductor layer 231, the silicide
conductive layer 48 is electrically connected with the
semiconductor layer 231 so that the selective gate transistor 23
can function as a single transistor. Then, the silicide conductive
layer 48 can not be reacted with silicon any more at the annealing
process for silicify the floating gate 123 in the memory cell
transistor 12 because the silicide conductive layer 48 is already
reacted with the silicon. As a result, there is not such a
disadvantage as the area in the vicinity of the semiconductor
substrate 11 is made of silicide to deteriorate some
characteristics such as threshold value of the selective gate
transistor 23.
[0068] The silicide conductive layer 48 can exhibit the inherent
barrier performance to some degrees. As is apparent from FIG. 12,
therefore, no barrier film made of titanium (Ti) or the like is
required to be formed so that the manufacturing process of the
nonvolatile semiconductor memory 40 can be simplified.
[0069] In this embodiment, the conductive layer 48 may be made of
tungsten silicide (WSi), cobalt silicide (CoSi), titanium silicide
(TiSi.sub.2) and the like.
[0070] The nonvolatile semiconductor memory 40 can be manufactured
in the same manner as the nonvolatile semiconductor memory 30 in
the third embodiment except that the silicide conductive layer 48
is formed instead of the conductive layer 38 and whether the
barrier layer 232 is formed or not.
[0071] The silicide conductive layer 48 may be formed by means of
chemical vapor deposition (CVD) using (a) prescribed raw material
gas(es). In the case of the formation of the WSi conductive layer
48, for example, a WF.sub.6 raw material gas and a
SiH.sub.2Cl.sub.2 (dichlorosilane) raw material gas are
employed.
[0072] Although the present invention was described in detail with
reference to the above examples, this invention is not limited to
the above disclosure and every kind of variation and modification
may be made without departing from the scope of the present
invention.
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