U.S. patent application number 13/176189 was filed with the patent office on 2012-01-05 for frequency converting circuit, signal processing circuit and receiver.
This patent application is currently assigned to KABUSHIKI KAISHA TOSHIBA. Invention is credited to Toshiya Mitomo, Yuta Tsubouchi, Tong Wang.
Application Number | 20120001667 13/176189 |
Document ID | / |
Family ID | 45399240 |
Filed Date | 2012-01-05 |
United States Patent
Application |
20120001667 |
Kind Code |
A1 |
Tsubouchi; Yuta ; et
al. |
January 5, 2012 |
FREQUENCY CONVERTING CIRCUIT, SIGNAL PROCESSING CIRCUIT AND
RECEIVER
Abstract
A frequency converting apparatus according to one embodiment is
a frequency converting circuit which generates a multiplied signal
obtained by multiplying a local signal by an amplified signal
generated by an amplifying portion comprising a first transistor
having a drain terminal connected to a first power source
potential, the frequency converting circuit comprising: a converter
which comprises a second transistor of which gate terminal is
connected to the amplifying portion and which converts the
amplified signal inputted to the gate terminal into a current
signal; a switching circuit which comprises two third-transistors
of which a source terminal is connected each other and which
multiplies the current signal by the local signal and generates the
multiplied signal; and an impedance element which comprises a first
terminal connected to a source terminal of the first transistor, a
second terminal connected to a drain terminal of the second
transistor and a third terminal connected to the source terminal of
the third transistor, which inputs a first direct current inputted
from the source terminal of the first transistor and a second
direct current inputted from the source terminal of the third
transistor into the drain terminal of the second transistor, of
which impedance is an ACwise high impedance between the first
terminal and the second terminal.
Inventors: |
Tsubouchi; Yuta;
(Kanagawa-ken, JP) ; Mitomo; Toshiya;
(Kanagawa-ken, JP) ; Wang; Tong; (Kanagawa-ken,
JP) |
Assignee: |
KABUSHIKI KAISHA TOSHIBA
Tokyo
JP
|
Family ID: |
45399240 |
Appl. No.: |
13/176189 |
Filed: |
July 5, 2011 |
Current U.S.
Class: |
327/119 |
Current CPC
Class: |
H03D 7/1441 20130101;
H03D 7/1491 20130101; H03D 7/1458 20130101; H03D 2200/0084
20130101 |
Class at
Publication: |
327/119 |
International
Class: |
H03B 19/00 20060101
H03B019/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 5, 2010 |
JP |
2010-153151 |
Claims
1. A frequency converting circuit which generates a multiplied
signal obtained by multiplying a local signal by an amplified
signal generated by an amplifying portion comprising a first
transistor having a drain terminal connected to a first power
source potential, the frequency converting circuit comprising: a
converter which comprises a second transistor of which gate
terminal is connected to the amplifying portion and which converts
the amplified signal inputted to the gate terminal into a current
signal; a switching circuit which comprises two third-transistors
of which a source terminal is connected each other and which
multiplies the current signal by the local signal and generates the
multiplied signal; and an impedance element which comprises a first
terminal connected to a source terminal of the first transistor, a
second terminal connected to a drain terminal of the second
transistor and a third terminal connected to the source terminal of
the third transistor, which inputs a first direct current inputted
from the source terminal of the first transistor and a second
direct current inputted from the source terminal of the third
transistor into the drain terminal of the second transistor, of
which impedance is an ACwise high impedance between the first
terminal and the second terminal.
2. The frequency converting circuit according to claim 1, further
comprising a controlling portion which controls the second direct
current such that a first potential of a connecting portion between
the amplifying portion and the first terminal of the impedance
element becomes a desired potential.
3. The frequency converting circuit according to claim 1, further
comprising a controlling portion which compares a first potential
of a connecting portion between the amplifying portion and the
first terminal of the impedance element with a predetermined
reference voltage, and inputs a voltage in the third transistor
such that the first potential matches the predetermined reference
voltage.
4. The frequency converting circuit according to claim 1, wherein:
the amplified signal comprises a normal phase signal and a reverse
amplified signal; a second transistor of the converter comprises: a
second normal phase transistor which generates a normal phase
current signal from the normal phase amplifying signal; and a
second reverse phase transistor which generates a reverse phase
current signal from the reverse phase amplified signal, and
generates a current signal comprising the normal phase current
signal and the reverse phase current signal; and the switching
circuit comprises: two third-normal-phase-transistors which
generate normal phase multiplied signals from the normal phase
current signal and which are connected in parallel; and two
third-reverse-phase-transistors which generate reverse multiplied
signals from the reverse phase current signal and which are
connected in parallel, and generates a multiplied signal comprising
the normal phase multiplied signal and the reverse phase multiplied
signal.
5. A receiver comprising: an antenna which receives an input
signal; an amplifying portion which amplifies the input signal and
generates an amplified signal; and a frequency converting circuit
according to claim 1 which multiplies the amplified signal by a
local signal and generates a multiplied signal.
6. A signal processing circuit comprising: an amplifying portion
which comprises: M (where M is an integer equal to or more than 2
and equal to or less than N) amplifiers which comprise a first
transistor having source terminals connected with each other and
having drain terminals connected to a first power source potential,
and which generate an amplified alternate current signal by
amplifying an alternate current signal; and N-M (N is an integer
equal to or more than 3) amplifiers which comprise a second
transistor having drain terminals connected to the source terminals
of the M amplifiers and with each other, the amplifiers having
source terminals connected to a second power source potential and
which generate an amplified alternate current signal by amplifying
an alternate current signal, and which generates an amplified
signal by amplifying an input signal by the amplifiers; a converter
which comprises a third transistor of which gate terminal is
connected to the amplifying portion and which converts the
amplified signal inputted to the gate terminal; a switching circuit
which comprises two fourth-transistors of which a source terminal
is connected each other and which multiplies the current signal by
the local signal and generates the multiplied signal; and an
impedance element which comprises a first terminal connected to a
source terminal of the first transistor, a second terminal
connected to a drain terminal of the third transistor and a third
terminal connected to the source terminal of the fourth-transistor,
which inputs a first direct current inputted from the source
terminal of the first transistor and a second direct current
inputted from the source terminal of the fourth transistor into the
drain terminal of the second transistor, of which impedance is an
ACwise high impedance between the first terminal and the second
terminal.
7. The signal processing circuit according to claim 6, wherein a
drain terminal of a kth (k is an integer of 0<k<N) amplifier
of the amplifying portion is connected to a gate terminal of a
(k+1)th amplifier; and the (k+1)th amplifier amplifies an amplified
alternate current signal amplified by the kth amplifier.
8. A receiver comprising: an antenna which receives an input
signal; the amplifying portion which amplifies the input signal and
generates the amplified signal; and a frequency converting circuit
according to claim 6 which multiplies the amplified signal with a
local signal and generates a multiplied signal.
9. A frequency converting circuit comprising: an amplifying portion
which amplifies an input signal; a converter which converts an
amplified signal, which is amplified by the amplifying portion,
into a current signal; an impedance element which not only connects
the amplifying portion and the converter with an ACwise high
impedance but also supplies to the converter a direct current
inputted from the amplifying portion; and a switching circuit which
comprises a pair of transistors connected in parallel, which is
connected with the converter through the impedance element, and
which generates a multiplied signal by multiplying a local signal
by the current signal converted into the converter.
10. The frequency converting circuit according to claim 9, wherein
the amplifying portion comprises a transistor having a drain
terminal connected to a first power source.
11. The frequency converting circuit according to claim 9, wherein
the amplifying portion comprises two amplifiers connected in
cascade for high frequency signal.
12. The frequency converting circuit according to claim 11, wherein
the amplifying portion, the switching circuit, and the converter
are operated in two phases of a normal phase and a reverse
phase.
13. The frequency converting circuit according to claim 10,
wherein: the amplifying portion comprises a plurality of first
amplifiers which are connected to a first power source potential in
cascade, and a plurality of second amplifiers which are connected
in cascade and receive outputs of the first amplifiers and which
are connected to a second power source potential; and transistors
forming the plurality of the first amplifiers connected to the
first power source potential have drain terminals connected to the
first power source potential and have source terminals commonly
connected, and transistors forming a plurality of the second
amplifiers connected to the second power source potential have
drain terminals commonly connected and have source terminals
connected to the second power source potential.
14. A receiver comprising: an antenna which receives an input
signal; an amplifying portion which amplifies the input signal and
generates an amplified signal; and a frequency converting circuit
according to claim 12 which multiplies the amplified signal by a
local signal and generates a multiplied signal.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present invention claims the benefit of the priority
application of Japanese Patent Application No. 2010-153151, filed
on Jul. 5, 2010. This application is hereby incorporated by
reference in its entirety.
FIELD
[0002] One embodiment relates to a frequency converting circuit, a
signal processing circuit and a receiver.
BACKGROUND
[0003] When the amplitude of an input signal is small, the
frequency converter is susceptible to the influence of noise and
has a problem that it is not possible to correctly convert the
frequency of the input signal.
[0004] Conventionally known frequency converters additionally input
a current in a voltage-current converter to provide the difference
between the amount of a direct current which flows into a switching
step and the amount of a current which flows into the
voltage-current converter. Consequently, it is possible to reduce
noise that is produced in the switching step and to operate the
switching step even with a local signal having small amplitude.
[0005] However, the conventional frequency converters additionally
supply the current to the voltage-current converter, and therefore
increase power consumption.
[0006] Therefore the present invention provides a frequency
converting circuit, a signal processing circuit and a receiver
which can convert the frequency even if the amplitude of a local
signal is small and which can suppress an increase of power
consumption.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1A is a view illustrating a signal processing circuit
according to a first embodiment;
[0008] FIG. 1B is a circuit diagram illustrating an example of an
amplifier according to the first embodiment;
[0009] FIG. 1C is a view illustrating an example of an impedance
element according to the first embodiment;
[0010] FIG. 1D is a view illustrating an example of a
current-voltage converting circuit;
[0011] FIG. 2A is a view illustrating a signal processing circuit
according to a second embodiment;
[0012] FIG. 2B is a view illustrating an example of a controlling
portion;
[0013] FIG. 3 is a view illustrating a signal processing circuit
according to a third embodiment;
[0014] FIG. 4A is a view illustrating a signal processing circuit
according to a fourth embodiment;
[0015] FIG. 4B is a view illustrating an example of an amplifier
according to the fourth embodiment;
[0016] FIG. 4C is a view illustrating an example of an impedance
element according to the fourth embodiment;
[0017] FIG. 5 is a view illustrating a signal processing circuit
according to a fifth embodiment;
[0018] FIG. 6 is a view illustrating a signal processing circuit
according to a first modified example of the fifth embodiment;
[0019] FIG. 7 is a view illustrating a signal processing circuit
according to a second modified example of the fifth embodiment;
[0020] FIG. 8 is a view illustrating a signal processing circuit
according to a third modified example of the fifth embodiment;
[0021] FIG. 9 is a view illustrating a signal processing circuit
according to a fourth modified example of the fifth embodiment;
and
[0022] FIG. 10 is a view illustrating a receiver according to a
sixth embodiment.
DETAILED DESCRIPTION
[0023] According to one embodiment, a frequency converting circuit
which generates a multiplied signal obtained by multiplying a local
signal by an amplified signal generated by an amplifying portion
comprising a first transistor having a drain terminal connected to
a first power source potential, the frequency converting circuit
comprising: a converter which comprises a second transistor of
which gate terminal is connected to the amplifying portion and
which converts the amplified signal inputted to the gate terminal
into a current signal; a switching circuit which comprises two
third-transistors of which a source terminal is connected each
other and which multiplies the current signal by the local signal
and generates the multiplied signal; and an impedance element which
comprises a first terminal connected to a source terminal of the
first transistor, a second terminal connected to a drain terminal
of the second transistor and a third terminal connected to the
source terminal of the third transistor, which inputs a first
direct current inputted from the source terminal of the first
transistor and a second direct current inputted from the source
terminal of the third transistor into the drain terminal of the
second transistor, of which impedance is an ACwise high impedance
between the first terminal and the second terminal.
[0024] Hereinafter, embodiments of the present invention will be
described with reference to the drawings. In each drawing, the same
components are designated by the same reference numerals, and
descriptions thereof will not be repeated.
First Embodiment
[0025] FIG. 1A is a circuit diagram of a signal processing circuit
100 according to the first embodiment. The signal processing
circuit 100 illustrated in FIG. 1A has an amplifying portion 110
which outputs an amplified signal obtained by amplifying an input
signal, and a frequency converting circuit 120 which outputs a
multiplied voltage signal obtained by converting the frequency of
the amplified signal.
[0026] The amplifying portion 110 has an amplifier 111. FIG. 1B is
a circuit diagram illustrating an example of the amplifier 111. The
amplifier 111 has a transistor M4. A drain terminal of the
transistor M4 is connected to a first terminal which has a first
power source potential (Vdd) through an inductance element L1. A
source terminal of the transistor M4 is connected to a second
terminal b. The source terminal of the transistor M4 and second
terminal b are DCwise short-circuited. Further, the source terminal
of the transistor M4 is connected to a ground through a capacitor
C2, and is thereby ACwise grounded. The gate terminal of the
transistor M4 is connected to a third terminal c. Between the gate
terminal of the transistor M4 and third terminal c, a resistance R
is provided having one end connected to the third terminal c and
gate terminal of the transistor M4 and the other end applied to a
bias voltage V.sub.BIAS. Further, the drain terminal of the
transistor M4 is connected to a fourth terminal d through the
capacitor C1 provided between the inductance element L1 and drain
terminal of the transistor M4.
[0027] Currents flowing into the amplifier 111 will be described in
terms of a direct current and alternate current, respectively.
[0028] First, the alternate current flowing into the amplifier 111
will be described.
[0029] The amplifier 111 amplifies an input signal f(.omega..sub.1)
which is an alternate current signal, and generates an amplified
signal G.sub.1f(.omega..sub.1) which is an alternate current
signal. The amplifier 111 amplifies the input signal
f(.omega..sub.1) inputted from the third terminal c to generate the
amplified signal G.sub.1f(.omega..sub.1), and outputs the amplified
signal from the fourth terminal d. Here, G.sub.1 is gain of the
amplifier 111. The amplified signal G.sub.1f(.omega..sub.1)
outputted from the fourth terminal d is inputted in the frequency
converting circuit 120.
[0030] Next, the direct current flowing into the amplifier 111 will
be described.
[0031] The amplifier 111 receives an input of a direct current
I.sub.mixer required to drive the amplifier 111 at the first
terminal a, and outputs the direct current from the second terminal
b. The direct current I.sub.mixer outputted from the second
terminal b is inputted to the frequency converting circuit 120.
[0032] Referring back to FIG. 1A, the frequency converting circuit
120 has a converter 124, an impedance element 121, a switching
circuit 122 and a current-voltage converting circuit 123.
[0033] The converter 124 is a circuit which converts the inputted
amplified signal G.sub.1f(.omega..sub.1) from the voltage into the
current, and generates a current signal. Hence, the converter 124
will also be referred to as "voltage-current converter 124"
hereafter.
[0034] The voltage-current converter 124 has a transistor M1. A
gate terminal of the transistor M1 is connected to the fourth
terminal d of the amplifier 111. A source terminal of the
transistor M1 is grounded, and the drain terminal is connected to a
terminal j of the impedance element 121.
[0035] The impedance element 121 has a terminal i connected to the
terminal b of the amplifier 111, a terminal h connected to the
switching circuit 122 and the terminal j connected to the
voltage-current converter 124. The impedance element 121 provides
an ACwise high impedance and provides a ACwise low impedance
between the terminals h and i and between the terminals i and j.
That is, the impedance element 121 connects the source terminal of
the amplifier 111 and frequency converting circuit 120 with an
ACwise high impedance and DCwise low impedance. With this
connection, the current I.sub.mixer used to drive the amplifier 111
of the amplifying portion 110 is supplied to the voltage-current
converter 124 of the frequency converting circuit 120 through the
impedance element 121.
[0036] By contrast, an ACwise high impedance is provided between
the terminals h and i and between the terminals i and j, and
therefore an alternate current signal (for example, the
above-mentioned current signal) which is an alternate current
signal flowing into the frequency converting circuit 120 and which
flows between the terminals h and j is prevented from flowing
outside the frequency converting circuit 120 (amplifier 111)
through the terminal i. Further, the alternate current signal is
also prevented from flowing into the frequency converting circuit
120 from outside (amplifier 111) through the terminal i. The
impedance is both ACwise and DCwise low between the terminals h and
j. That is, the impedance element 121 connects the switching
circuit 122 and voltage-current converter 124 with both ACwise and
DCwise low impedances.
[0037] Further, when seen from the terminal i, the impedance
element 121 operates as if the impedance element 121 is ACwise
grounded. That is, when seen from the source terminal of the
transistor M4 of the amplifier 111, the impedance element 121 is
ACwise grounded. With this connection, it is possible to adjust the
source terminal of the transistor M4 of the amplifier 111 to a
constant potential (ground in the present embodiment), and keep the
constant potential between the drain terminal and source terminal
of the transistor M4 of the amplifier 111.
[0038] FIG. 1C is a circuit diagram illustrating an example of the
impedance element 121. The terminals h, i and j in FIG. 1C
respectively correspond to the terminals h, i and j in FIG. 1A.
[0039] The impedance element 121 illustrated in FIG. 1C has an
inductance element L2 having one end connected to the terminal i
and having the other end connected to the terminal h and terminal
j, and a capacitor C3 having the one end connected to the terminal
i and having the other end grounded. That is, the impedance element
121 in FIG. 1C directly connects the switching element 122 and
voltage-current converter 124, and connects the amplifying portion
110 and switching circuit 122, and the switching circuit 122 and
voltage-current converter 124 through the inductance element L2. By
this means, it is possible to provide both ACwise and DCwise low
impedances between the terminals h and j, and provide an ACwise
high impedance and DCwise low impedance between the terminals i and
j.
[0040] Further, the terminal i is grounded through the capacitor
C3. The capacitor C3 has an ACwise low impedance and DCwise high
impedance. Thus, the terminal i is ACwise grounded.
[0041] The switching circuit 122 has two transistors M2 and M3, and
outputs a multiplied signal by multiplying an amplified signal with
a local signal (alternate current signal). As described later, the
switching circuit 122 performs a switching operation of passing or
blocking the current according to the magnitude of the given local
signal.
[0042] The two transistors M2 and M3 of the switching circuit 122
are aligned in parallel. The gate terminals of the transistors M2
and M3 receive local signals -g(.omega..sub.2) and
g(.omega..sub.2), respectively. The source terminals of the
transistors M2 and M3 are connected to the terminal h of the
impedance element 121. The drain terminals of the transistors M2
and M3 are connected to terminals f and g of the current-voltage
converting circuit 123, respectively.
[0043] The current-voltage converting circuit 123 converts the
multiplied signal (current) outputted from the switching circuit
122 into the voltage, and outputs the multiplied voltage signal.
The terminal e of the current-voltage converting circuit 123 is
connected to the first power source potential (Vdd). The multiplied
voltage signals are outputted from the terminal f and terminal g of
the current-voltage converting circuit 123.
[0044] FIG. 1D illustrates an example of the current-voltage
converting circuit 123. The current-voltage converting circuit 123
in FIG. 1D has current sources 123a and 123b. Both of the current
sources 123a and 123b have one ends connected to the terminal e.
The other end of the current source 123a is connected to the
terminal f. The other end of the current source 123b is connected
to the terminal g. The terminals e, f and g respectively correspond
to the terminals e, f and g in FIG. 1A.
[0045] Next, signals flowing into the frequency converting circuit
120 will be described in terms of a direct current signal and
alternate current signal using FIG. 1A.
[0046] First, the alternate current signal flowing into the
frequency converting circuit 120 will be described.
[0047] The amplified signal G.sub.1 f(.omega..sub.1) amplified by
the amplifying portion 110 is inputted to the voltage-current
converter 124. The voltage-current converter 124 converts the
amplified signal G.sub.1f(.omega..sub.1) into the current signal
G.sub.M1G.sub.1f(.omega..sub.1). Here, G.sub.M1 is a conversion
gain of the transistor M1 (voltage-current converter 124). The
current signal G.sub.M1G.sub.1f(.omega..sub.1) is inputted in the
switching circuit 122 through the impedance element 121. The
transistors M2 and M3 of the switching circuit 122 pass the
inputted current signal G.sub.1 f(.omega.) between the drain and
source when the potentials of the gate given from the respective
local signals -g(.omega..sub.2) and g(.omega..sub.2) are high.
[0048] By contrast, the transistors M2 and M3 block the current
between the drain and source when the potentials of the gate are
low. By this means, the current signal G.sub.M1G.sub.1 f(.omega.)
is multiplied by local signals g(.omega..sub.2) and
-g(.omega..sub.2) to generate a multiplied signal. The multiplied
signal outputted from the switching circuit 122 is converted into a
multiplied voltage signal by the current-voltage converting circuit
123. The multiplied voltage signal which is the final output signal
of the frequency converting circuit 120 is represented by
2G.sub.1G.sub.2 f(.omega..sub.1).times.g(.omega..sub.2)
(=G.sub.1G.sub.2
f(.omega.1).times.g(.omega..sub.2)-[-G.sub.1G.sub.2
f(.omega..sub.1).times.g(.omega..sub.2)]). G.sub.2 is the final
frequency conversion gain of the frequency converting circuit
120.
[0049] The above-described amplified signal, current signal, local
signal, multiplied signal, and multiplied voltage signal are all
alternate current signals. In this way, the alternate current
amplified signal inputted in the frequency converting circuit 120
is multiplied by the local signal and the resultant is
outputted.
[0050] Next, a direct current flowing into the frequency converting
circuit 120 will be described.
[0051] Direct currents flow into the transistors M2 and M3 of the
switching circuit 122, respectively. The amount of the direct
current flowing into one of these transistors M2 and M3 are
represented by 1/2*I.sub.SW. That is, the total amount of the
direct currents flowing into the switching circuit 122 is
represented by I.sub.SW.
[0052] This direct current I.sub.SW is also inputted in the
voltage-current converter 124 connected in series through the
impedance element 121. In the voltage-current converter 124, the
direct current I.sub.mixer consumed to drive the amplifier 111
further flows through the impedance element 121. Hence, the direct
current flowing into the voltage-current converter 124 is
represented by I.sub.SW+I.sub.mixer.
[0053] Thus, the direct current flowing into the voltage-current
converter 124 is greater, by the amount of the direct current
I.sub.mixer inputted from the amplifier 111, than the direct
current flowing in the switching circuit 122. Thus, providing the
difference between the total amounts of direct currents flowing
into the voltage-current converter 124 is preferable for circuit
characteristics of a frequency converting circuit. This reason will
be described using FIG. 1A.
[0054] In many cases, the voltage-current converter 124 is required
to linearly convert the amplified signal G f(.omega.) which is an
inputted voltage signal into a current signal. Therefore, there is
a desired value of a direct current applied in advance between the
drain and source of the transistor M1 of the voltage-current
converter 124. By contrast, the direct currents to be applied
between the drains and sources of the transistors M2 and M3 of the
switching circuit 122 are preferably smaller than the desired value
of the voltage-current converter 124. When the direct current
flowing into the switching circuit 122 is small, the demand for the
voltage amplitude of the local signal g is relaxed and a desired
switching operation can be realized even if the amplitude is small.
It is also possible to suppress thermal noise caused by the direct
currents flowing between the drains and sources of the transistors
M2 and M3 of the switching circuit 122.
[0055] By causing the total amount of the direct current flowing
between the drain and source of the transistor M1 of the
voltage-current converter 124 to be larger than the total amount of
the direct currents flowing between the drains and sources of the
transistors M2 and M3 of the switching circuit 122, it is possible
not only to adjust to a desired value the direct current flowing
between the drain and source of the transistor M1 of the
voltage-current converter 124, but also to reduce the direct
currents flowing between the drain and source of the transistors M2
and M3 of the switching circuit 122.
[0056] Consequently, by causing the total amount of the direct
current flowing between the drain and source of the transistor M1
of the voltage-current converter 124 to be larger than the total
amount of the direct currents flowing between the drains and
sources of the transistors M2 and M3 of the switching circuit 122,
it is possible not only to perform linear conversion in the
voltage-current converter 124, but also to reduce the amplitude of
the local signal of the switching circuit 122 and suppress noise.
That is, the characteristics of the entire frequency conversion
circuit 120 are improved.
[0057] With the present embodiment, by supplying the direct current
I.sub.mixer used to drive the amplifying portion 110 to the
voltage-current converter 124 through the impedance element 121,
the difference corresponding to I.sub.mixer is provided between the
total amount of the direct current flowing between the drain and
source of the transistor M1 of the voltage-current converter 124
and the total amount of the direct current flowing between the
drains and sources in the switching circuit 122. That is, the
current which is used to drive the amplifier 111 is applied to
improve characteristics of the frequency converting circuit 120. By
so doing, it is possible to improve the characteristics of the
frequency converting circuit 120 without providing an additional
current source in the frequency converting circuit 120.
[0058] As described above, the frequency converting circuit and
signal processing circuit of the present embodiment can provide a
frequency converting circuit which can convert the frequency even
if the amplitude of a local signal is small and can suppress an
increase of power consumption. Further, the frequency converting
circuit and signal processing circuit can improve the conversion
gain and noise characteristics at the same time.
[0059] In addition, although the terminal i is configured to be
grounded through the capacitor C3 having an ACwise low impedance
with the present embodiment, the terminal i does not need to be
grounded. The terminal b of the amplifying portion only needs to be
connected to a portion having a constant potential (no fluctuation
in the potential) through an element having an ACwise low
impedance. That is, for example, the terminal b only needs to be
ACwise grounded.
Second Embodiment
[0060] Next, signal processing circuit 200 according to a second
embodiment of the present invention will be described. FIG. 2A is a
circuit diagram of the signal processing circuit 200 according to
the second embodiment. The signal processing circuit 200 employs a
configuration in which a controlling portion 210 is further added
to the signal processing circuit according to the first embodiment.
The other configurations are the same as those in FIG. 1. In
addition, although the controlling portion 210 is configured to be
provided outside the frequency converting circuit 120, the
controlling portion 210 may be configured to be provided inside the
frequency converting circuit 120.
[0061] The controlling portion 210 has terminals k and l which
receive inputs of local signals (alternate current signals). The
controlling portion 210 has a terminal o which receives an input of
a reference voltage V.sub.REF (direct current signal) which is
given from the outside. The controlling portion 210 has a terminal
m and a terminal n which output the inputted local signals as they
are.
[0062] The controlling portion 210 monitors the first potential
through the terminal p connected to, for example, a connecting
portion Q between the terminal b of the amplifier 111 and the
terminal i of the impedance element 121. The controlling portion
210 compares the reference voltage V.sub.REF and the first
potential of the connecting portion Q, and superimposes the direct
current voltages from the terminals m and n on a local signal such
that the first potential of the connecting portion Q and the
reference voltage match, and outputs the direct voltages. That is,
the controlling portion 210 inputs the signal, that is obtained by
superimposing the local signal and direct current voltage, to the
transistor M3 through the terminal m and to the transistor M2
through the terminal n. The reference voltage is a potential
required to cause the amplifier 111 to perform a desired operation
such as linear amplification at a desired amplification factor, and
is determined in advance. The reference voltage is designed such
that the rate of the magnitude of the direct current flowing into
the voltage-current converter 124 to the magnitude of the direct
current flowing into the switching current 122 becomes a desired
value.
[0063] The direct current voltage outputted from the controlling
portion 210 adjusts the total amount I.sub.SW of the direct current
flowing into the switching circuit 122 by controlling the voltages
of the respective gate terminals of the transistor M2 and M3 of the
switching circuit 122. The controlling portion 210 controls the
current flowing into the voltage-current converter 124 by adjusting
the direct current I.sub.SW. Further, the controlling portion 210
controls the first potential of the connecting portion Q by
adjusting the direct current I.sub.SW. Hereinafter, the reason why
the first potential of the connecting portion Q can be controlled
by adjusting the direct current I.sub.SW by the controlling portion
210 will be described.
[0064] The voltage-current converter 124 receives an input of a
current I.sub.VI of the sum of the direct current I.sub.SW and the
direct current I.sub.mixer inputted from the amplifying portion
111. The first potential of the connecting portion Q is determined
based on the sum of the voltage drop between the terminals i and j
of the impedance element 121 and the voltage drop of the
voltage-current converter 124. As described above, the voltage drop
between the terminals i and j of the impedance element 121 is
DCwise very small. Hence, if the voltage drop between the terminals
i and j of the impedance element 121 is neglected, the potential of
the connecting portion Q is determined based on the voltage drop of
the voltage-current converter 124. The voltage drop of the
voltage-current converter 124 is determined based on the
characteristics of the transistor M1 and the current I.sub.VI
flowing into the transistor M1. As described above, the current
I.sub.VI is represented by I.sub.mixer+I.sub.SW. The direct current
I.sub.mixer is determined according to the first potential of the
connecting portion Q. Although the direct current I.sub.mixer
cannot be controlled directly, the value of I.sub.mixer can be
controlled by adjusting I.sub.SW. Consequently, the current
I.sub.VI is changed by adjusting the direct current I.sub.SW. By
this means, it is possible to control the first potential of the
connecting portion Q.
[0065] Further, when the potential of the connecting portion Q is
finally determined, the direct current I.sub.mixer flowing into the
amplifier 111 is determined. When the potential of the connecting
portion Q becomes a desired value, the rate of the total amount
I.sub.SW of the direct current flowing into the switching circuit
122 to the direct current I.sub.VI=I.sub.SW+I.sub.mixer flowing
into the voltage-current converter 124 becomes a desired value.
[0066] As described above, the operation points of the all circuits
are fixed by providing the controlling portion 210. By this means,
even if the manufacturing state, environmental temperature and
power source voltage of circuits fluctuate, the bias of the
switching circuit 122 is automatically adjusted such that the
connecting portion Q is kept at a desired potential and the desired
direct current I.sub.mixer flows into the amplifier 111. Further,
by adjusting the direct current voltage inputted to the gate
terminals of the transistors M2 and M3, it is possible to determine
the current I.sub.SW flowing into the switching circuit 122
irrespectively of the sizes of the transistors M2 and M3, the
manufacturing state, or the environmental temperature of the
circuits.
[0067] Next, an example of a detailed configuration of the
controlling portion 210 will be described.
[0068] The controlling portion 210 illustrated in FIG. 2B has a
controlling circuit 230 and a reference voltage generating circuit
220. In addition, although the controlling portion 210 employs a
configuration including the reference voltage generating circuit
220 in FIG. 2B, the controlling portion 210 may be configured to be
provided outside the signal processing circuit 200 as illustrated
in FIG. 2A and input the reference voltage in the controlling
portion 210.
[0069] The reference voltage generating circuit 220 has a MOS
transistor 221 and a current source 222, and generates the
reference voltage V.sub.REF. The drain terminal and gate terminal
of the MOS transistor 221 are connected to the first power source
potential Vdd. The source terminal of the MOS transistor 221 is
connected to one end of the current source 222. The other end of
the current source 222 is connected to the second power source
potential (ground in FIG. 2B). The source terminal of the MOS
transistor 221 and one end of the current source 222 are connected
to the terminal o of the controlling circuit 230. The reference
voltage generating circuit 220 outputs the reference voltage
V.sub.REF from the source terminal of the MOS transistor 221.
[0070] By adjusting the size of the MOS transistor 221 and the
condition of the current amount of the current source 222, the
reference voltage generating circuit 220 reproduces desired states
of the direct current voltages I.sub.mixer and I.sub.VI of the
amplifier 111 and voltage-current converter 124. That is, the
reference voltage generating circuit 220 operates as a dummy for
the amplifier 111 and voltage-current converter 124. The reference
voltage generating circuit 230 outputs the first voltage of the
connecting portion Q in FIG. 2 when the amplifier 111 and
voltage-current converter 124 are operating in ideal states.
[0071] The controlling circuit 230 has resistances 231-1 and 231-2
and a computing amplifier 232. The terminal o of the computing
amplifier 232 is connected with the source of the MOS transistor
221 and one end of the current source 222. The terminal p of the
computing amplifier 232 is connected to the connecting portion Q in
FIG. 2A. The output terminal of the computing amplifier 232 is
connected to the terminals k and l and the terminals m and n
through the resistances 231-1 and 231-2. In addition, the terminal
k and terminal m, and the terminal I and terminal n are
short-circuited, respectively.
[0072] The terminal o of the computing amplifier 232 receives an
input of the reference voltage V.sub.REF, and the terminal p
receives an input of the first voltage of the connecting portion Q
in FIG. 2A.
[0073] The terminals k and l of the controlling portion 210 receive
an input of a local signal from outside. The terminals m and n of
the controlling portion 210 output signals obtained by
superimposing the direct current voltage outputted from the
computing amplifier 232 and local signal.
[0074] The controlling portion 210 has a feedback route reaching
the terminal p from the terminals m and n through the switching
circuit 122 and impedance element 121. When the potential of the
connecting portion Q is different from the reference voltage
V.sub.REF, according to the virtual short-circuiting effect of the
computing amplifier 232, the direct current voltage levels of the
terminals in and n are adjusted such that the potential of the
connecting portion Q and the reference voltage V.sub.REF become
equal, so that the direct current I.sub.SW changes and, as a
result, the potential of the connecting portion Q becomes a desired
value.
[0075] The frequency converting circuit 120 and signal processing
circuit 200 according to the present embodiment can achieve the
same effect as in the first embodiment. That is, the frequency
converting circuit 120 and signal processing circuit 200 according
to the present embodiment can convert the frequency even if the
amplitude of a local signal is small, suppress an increase of power
consumption and improve the gain conversion and noise
characteristics.
[0076] Further, the frequency converting circuit 120 and signal
processing circuit 200 according to the present embodiment can
adjust to a desired value the first potential at the connecting
portion Q which connects the amplifier 111 and the voltage-current
converter 124 through the impedance element 121, and operate the
amplifier 111 within a desired range (the range where the amplifier
111 linearly operates at a desired amplification factor).
[0077] It is possible to perform a control action such that the
rate of the magnitude of the direct current I.sub.VI flowing into
the voltage-current converter 124 to the magnitude of the direct
current I.sub.SW flowing into the switching circuit 122 becomes a
desired value. this means, it is possible to adjust to a desired
value of the magnitude of the direct current I.sub.VI flowing into
the voltage-current converter 124, and reduce the direct current
I.sub.SW flowing into the switching circuit 122. As a result, the
voltage-current converter 124 can linearly convert an amplified
signal, which is an inputted voltage signal, into a current signal.
In addition, the switching circuit 122 can decrease the voltage
amplitude of a local signal and reduce thermal noise of the
switching circuit 122 resulting from the direct currents flowing
between the source terminals and drain terminals of the transistors
M2 and M3 of the switching circuit 122.
Third Embodiment
[0078] Next, a signal processing circuit 300 according to a third
embodiment will be described. FIG. 3 is a circuit diagram of the
signal processing circuit 300. The signal processing circuit 300
has an amplifying portion 310 and the frequency converting circuit
120. The signal processing circuit 300 differs from the signal
processing circuit 100 according to the first embodiment in that
the amplifying portion 310 has two amplifiers 111-1 and 111-2.
[0079] Each configuration of the amplifiers 111-1 and 111-2 is the
same as the configuration of the amplifier 111 described in the
first embodiment.
[0080] The source terminal of the transistor M4 of the amplifier
111-1 and the drain terminal of the transistor M4 of the amplifier
111-2 are DCwise connected. Further, the source terminal of the
amplifier 111-1 and the drain terminal of the amplifier 111-2 are
connected to the impedance element 121 of the frequency converting
circuit 120.
[0081] The drain terminal of the amplifier 111-1 is connected to
the first power source potential Vdd, and the source terminal of
the amplifier 111-2 is connected to the second power source
potential (ground).
[0082] The input terminal c of the amplifier 111-1 receives an
input of an input signal f(.omega..sub.1) which is an alternate
current signal. The output terminal d of the amplifier 111-1 is
connected to the input terminal c of the amplifier 111-2. That is,
the amplifier 111-1 and amplifier 111-2 are connected in cascade in
terms of high frequency small signal processing. The output
terminal of the amplifier 111-2 is connected to the gate terminal
of the voltage-current converter 124 of the frequency converting
circuit 120.
[0083] The flow of currents of the direct current and alternate
current in the signal processing circuit 300 according to the
present embodiment will be respectively described below.
[0084] First, an alternate current signal will be described.
[0085] The amplifier 111-1 receives an input of the input signal
which is an alternate current signal. The input signal is inputted
to the input terminal of the amplifier 111-1, is amplifier by the
amplifier 111-1, and is converted into a first amplified signal.
The first amplified signal is inputted to the amplifier 111-2, is
amplified by the amplifier 111-2, and is converted into a second
amplified signal. The second amplified signal is inputted to the
gate terminal of the transistor M1 of the voltage-current converter
124 of the frequency converting circuit 120 as the output signal of
an amplifying portion 310.
[0086] Next, the direct current signal will be described.
[0087] The direct current I.sub.amp+I.sub.mixer flows between the
source terminal and drain terminal of the transistor M4 of the
amplifier 111-1. The amplifier 111-1 is driven by the direct
current I.sub.amp+I.sub.mixer. I.sub.amp of the direct current
I.sub.amp+I.sub.mixer flows between the source terminal and drain
terminal of the transistor M4 of the amplifier 111-2. The amplifier
111-2 is driven by I.sub.amp. The other I.sub.mixer of the direct
current I.sub.amp+I.sub.mixer is supplied to the voltage-current
converter 124 through the impedance element 121.
[0088] As described above, the signal processing circuit 300
reduces power consumption by using the current having been used to
drive the amplifier 111-1 to drive the amplifier 111-2 at a later
stage. Further, similar to the first embodiment, by applying for
the frequency converter 124 the current used to drive the amplifier
111-1, it is possible to provide a circuit which improves
performance of a frequency converting circuit without additional
power consumption.
Fourth Embodiment
[0089] Next, a signal processing circuit 400 according to the
fourth embodiment will be described. FIG. 4A is a circuit diagram
illustrating the signal processing circuit 400, and FIG. 4B is a
view illustrating an example of an amplifier 411-1 of an amplifying
portion 410 of the signal processing circuit 400. The signal
processing circuit 400 according to the fourth embodiment is
configured as a differential circuit using the configuration in
which the controlling portion 210 illustrated in FIG. 2 is added to
the signal processing circuit 300 illustrated in FIG. 3.
[0090] The signal processing circuit 400 will be described below
mainly based on the difference from the configuration when a
single-phase circuit is configured as a differential circuit.
[0091] The signal processing circuit 400 illustrated in FIG. 4A has
the amplifying portion 410 and a frequency converting circuit 420.
The amplifying portion 410 has amplifiers 411-1 and 411-2.
[0092] The amplifier 411-1 receives an input of a differential
signal (normal phase and reverse phase). FIG. 4B illustrates an
example of the amplifier 411-1.
[0093] The amplifier 411-1 has a transistor M4-1 in which the gate
terminal is inputted to an input terminal c-1, the drain terminal
is connected to a terminal a through an inductance element L11, and
the source terminal is connected to a terminal b. The amplifier
411-1 also has a transistor M4-2 in which the gate terminal is
inputted to an input terminal c-2, the drain terminal is connected
to the terminal a through an inductance element L12, and he source
terminal is connected to the terminal b.
[0094] The terminal d-1 is connected between the inductance element
L11 and transistor M4-1 through a capacitor C11. A terminal d-2 is
connected between the inductance element L12 and transistor M4-2
through a capacitor C12. Further, the amplifier 411-1 has a
resistance R1 having one terminal connected to the terminal c-1 and
gate terminal of the transistor M4-1 and having the other end
applied the bias voltage V.sub.BIAS, and a resistance R2 having one
end connected to the terminal c-2 and gate terminal of the
transistor M4-2 and having the other terminal applied the bias
voltage V.sub.BIAS.
[0095] The amplifier 411-1 receives an input of differential
signals from the input terminals c-1 and c-2. The normal phase
signal of the differential signals is inputted to the input
terminal c-1 and the reverse phase signal is inputted to the input
terminal c-2. The transistor M4-1 amplifies the normal phase
signal, and outputs a first normal phase amplified signal from the
terminal d-1. The transistor M4-2 amplifies the reverse signal of
input signals, and outputs the first reverse phase amplified signal
from the terminal d-2. The first normal phase amplified signal and
first reverse phase amplified signal are collectively referred to
as "first amplified signal."
[0096] The configuration of the amplifier 411-2 is the same as the
configuration of the amplifier 411-1. The amplifier 411-2 amplifies
the inputted first amplified signal, and outputs the second normal
phase amplified signal and second reverse phase amplified signal
(hereinafter referred to as "second amplified signal").
[0097] The terminal b of the amplifier 411-1 is connected with each
source terminal of the transistors M4-1 and M4-2, and is thereby
ACwise grounded. The terminal a of the amplifier 411-2 is connected
with the terminal b of the amplifier 411-1, and is thereby ACwise
grounded.
[0098] Next, the configuration of the frequency converting circuit
420 will be described. The frequency converting circuit 420 has a
voltage-current converter 424, an impedance element 421, a
switching circuit 422, and the current-voltage converting circuit
123.
[0099] The voltage-current converter 424 has two transistors M1-1
and M1-2. The transistor M1-1 converts the second normal phase
amplified signal into a current signal, and outputs a normal phase
current signal. The transistor M1-2 converts the second reverse
phase amplified signal into a current signal, and outputs a reverse
phase current signal. The normal phase current signal and reverse
phase current signal will be collectively referred to as "current
signal."
[0100] The switching circuit 422 has four transistors M2-1, M2-2,
M3-1, and M3-2.
[0101] The transistors M2-1 and M3-1 receive inputs of normal phase
current signals from the source terminals, and receive inputs of
normal phase local signals from the gate terminals. The transistors
M2-2 and M3-2 receive inputs of reverse phase current signals from
the source terminals, and receive inputs of reverse phase local
signals from the gate terminals. The transistors M2-1 and M3-1
multiply normal phase current signals by normal phase local
signals, and generate normal phase multiplied signals. The
transistors M2-2 and M3-2 multiply reverse phase current signals by
reverse phase local signals, and generate reverse phase multiplied
signals. The normal phase multiplied signal and reverse phase
multiplied signal will be collectively referred to as "multiplied
signal."
[0102] The current-voltage converting circuit 123 converts the
multiplied signal into the voltage to generate a multiplied voltage
signal.
[0103] FIG. 4C illustrates an example of a circuit configuration of
the impedance element 421. The impedance element 421 employs the
same configuration as the impedance element 121 according to the
first embodiment except that the capacitor C3 is not provided.
[0104] The impedance element 421 has an inductance element L3
having one end connected to the terminal i and having the other end
connected to the terminal h and terminal j. The impedance element
421 directly connects the switching circuit 422 and voltage-current
converting circuit 424, and connects the amplifying portion 410,
switching circuit 422, and voltage-current converting circuit 424
through the inductance element L3. By this means, it is possible to
provide both ACwise and DCwise low impedances between terminals h
and j, and provide an ACwise high impedance and DCwise low
impedance between the terminals i and j. In addition, unlike the
impedance element 121 described in the first embodiment, the
impedance element 421 does not need to be provided with the
capacitor C3 and ACwise grounded. This is because the amplifier
411-1 receives inputs of a normal phase signal and a reverse phase
signal and therefore the terminal b where the normal phase signal
and reverse phase signal cross is ACwise grounded.
[0105] The signal processing circuit 400 according to the present
embodiment employs the same operation as in a case where the
controlling portion 210 is applied to the configuration according
to the third embodiment, except that a differential signal is
used.
[0106] That is, the direct current I.sub.mixer used to drive the
amplifying portion 411-1 is supplied to the voltage-current
converter 424 through the impedance element 421. Further, the
controlling portion 210 controls the potential of the connecting
portion Q and the current flowing into the switching circuit 422 to
adjust the rate to the current flowing in the voltage-current
converter 424. Consequently, it is possible to drive all circuits
according to a local signal of a low voltage without additional
power consumption, and realize a signal processing circuit having
good conversion gain and noise characteristics.
[0107] Further, it is also possible to use the direct current
having been used to drive the amplifier 411-1 to drive the
amplifier 411-2 of a later stage and, consequently, reduce power
consumption.
[0108] In addition, in the present embodiment, although the
configuration in which a controlling portion is applied to the
signal processing circuit 300 illustrated in FIG. 3 is changed to a
differential circuit, the signal processing circuit illustrated in
FIGS. 1 to 3 may be configured as a differential circuit.
Fifth Embodiment
[0109] Next, a signal processing circuit 500 according to a fifth
embodiment will be described. FIG. 5 is a view illustrating the
signal processing circuit 500 according to the fifth
embodiment.
[0110] The signal processing circuit 500 has an amplifying portion
510 and a frequency converting circuit 120. Unlike the signal
processing circuit 100 according to the first embodiment, the
amplifying portion 510 of the signal processing circuit 500 has N
amplifiers 111-1 to 111-N (N is an integer of 3 or more). The other
configurations are the same as those of the signal processing
circuit 100 described in the first embodiment.
[0111] Each configuration of the amplifiers 111-1 to 111-N is the
same as the configuration of the amplifier 111 described in the
first embodiment.
[0112] The drain terminal of the kth (wherein k is an integer of
0<k<N) amplifier 111-k of the amplifiers 111-1 to 111-N is
connected to the gate terminal of the (k+1)th amplifier 111-k+1,
and the amplifier 111-k+1 amplifies the amplified signal amplified
in the amplifier 111-k. In terms of the alternate current, the
amplifiers 111-1 to 111-N are connected with each other in
cascade.
[0113] The drain terminals of transistors provided in circuits of M
amplifiers 111-1 to 111-M (M is an integer equal to or more than 2
and equal to or less than N) among the amplifiers 111-1 to 111-N
are respectively connected to the first power source (Vdd).
Further, the source terminals of the transistors of the amplifiers
111-1 to 111-M are connected with each other. Consequently, the
transistors of the amplifiers 111-1 to 111-M are DCwise connected
in parallel in terms of the direct current. The amplifiers 111-1 to
111-M will be referred to as "upper amplifying stage."
[0114] The drain terminals of transistors provided in circuits of
N-M amplifiers 111-M+1 to 111-N (referred to as "lower amplifying
stage") of the amplifiers 111-1 to 111-N are connected with each
other. The source terminals of transistors in the lower amplifying
stage are connected to the second power source potential (ground).
Hence, the lower amplifying stage is DCwise connected in parallel
in terms of the direct current. The drain terminals of transistors
in the lower amplifying stage are commonly connected with source
terminals of transistors in the upper amplifying stage, and
therefore the upper amplifying stage and lower amplifying stage are
DCwise connected in series in terms of the direct current
signal.
[0115] Further, source terminals of transistors in the upper
amplifying stage and drain terminals in the lower amplifying stage
are connected to the voltage-current converter 124 through the
impedance element 121 of the frequency converting circuit 120. In
terms of the direct current signal, the voltage-current converter
124 is DCwise connected in series with the upper amplifying stage,
and is DCwise connected in parallel with the lower amplifying
stage.
[0116] In addition, as is clear from FIG. 5, the voltage-current
converter 124 is also DCwise connected in series with the switching
circuit 122 through the impedance element 121.
[0117] Hereinafter, currents flowing in the amplifying portion 510
will be described in terms of a direct current and alternate
current, respectively. First, the flow of an alternate current
signal will be described.
[0118] The amplifier 111-1 receives an input of an input signal
which is an alternate current signal through the terminal c. The
amplifier 111-1 amplifies the input signal, and generates a first
amplified alternate current signal to output it from the terminal
d. The first amplified alternate current signal is inputted to the
terminal c of the amplifier 111-2. The amplifier 111-2 amplifies
the first amplified alternate current signal, and generates the
second amplified alternate current signal to output it from the
terminal d. Then, the amplifiers 111-3 to 111-M also perform the
same processing, and the amplifier 111-M generates an Mth amplified
alternate current signal. The Mth amplified alternate current
signal is inputted to the terminal c of the amplifier 111-M+1 in
the lower stage. The amplifier 111-M+1 amplifies the Mth amplified
alternate current signal, and generates a (M+1)th amplified
alternate current signal to output it from the terminal d. The
(M+1)th amplified alternate current signal is inputted to the
terminal c of the amplifier 111-M+2. The amplifier 111-M+2
amplifies the (M+1)th amplified alternate current signal, and
generates a (M+2)th amplified alternate current signal to output it
from the terminal d. Then, the amplifiers 111-M+3 to 111-N also
perform the same processing, and the amplifier 111-N generates an
Nth amplified alternate current signal. The Nth amplified alternate
current signal is inputted to the gate terminal of the transistor
M1 of the voltage-current converter 124 of the frequency converter
120 as the output signal of the amplifying portion 510 (referred to
as "amplified signal"). The subsequent flow of the alternate
current signal is the same as that of the first embodiment, and
therefore, description thereof will not be repeated.
[0119] Next, the flow of the direct current signal will be
described.
[0120] Assume that direct currents I.sub.mixer, I.sub.amp1,
I.sub.amp2, . . . and I.sub.ampM flow between drain terminals and
source terminals of transistors in the upper amplifying stage. In
this case, I.sub.mixer+I.sub.amp1+I.sub.amp2+ . . . I.sub.ampM are
outputted from the upper amplifying stage. Part of the current
(I.sub.mixer) of I.sub.mixer+I.sub.amp1+I.sub.amp2+ . . .
I.sub.ampM is supplied to the voltage-current converter 124, and
the rest of the currents (I.sub.amp1+I.sub.amp2+ . . . I.sub.ampM)
flow between drain terminals and sources of transistors of 111-M+1
to 111-N in the lower amplifying stage.
[0121] Similar to the first embodiment, the total amount of the
direct currents flowing into the switching circuit 122 is herein
represented by I.sub.SW. This direct current I.sub.SW is also
inputted to the voltage-current converter 124 connected in series
through the impedance element 121. Accordingly, the direct current
I.sub.SW+I.sub.mixer flows into the voltage-current converter
124.
[0122] With the signal processing circuit 500 and frequency
converting circuit 120 according to the present embodiment, the
direct current I.sub.VI flowing into the voltage-current converter
124 is greater, by an amount of the direct current I.sub.mixer
inputted from the amplifying portion 510, than the direct current
I.sub.SW flowing into the switching circuit 122. Consequently, it
is possible to reduce noise produced in the switching circuit 122
while maintaining the linearity of the voltage-current converter
124, and decrease the amplitude of a local signal required to drive
the switching circuit 122.
[0123] Further, the signal processing circuit 500 according to the
present embodiment can also use the direct currents
(I.sub.amp1+I.sub.amp2+ . . . I.sub.ampM) having been used to drive
amplifiers in the upper amplifying stage in order to drive
amplifiers in the lower amplifying stage, and, consequently, reduce
power consumption of the amplifying portion 510. cl First Modified
Example
[0124] Next, a signal processing circuit 600 according to a first
modified example of the fifth embodiment will be described. FIG. 6
is a circuit diagram of the signal processing circuit 600 according
to the first modified example of the fifth embodiment. As
illustrated in FIG. 6, the signal processing circuit 600 according
to the first modified example differs from the signal processing
circuit 500 according to the fifth embodiment in that the signal
processing circuit 600 further has a controlling portion 210.
[0125] The configuration and function of the controlling portion
210 are the same as the configuration and function of the
controlling portion 210 of the signal processing circuit 200
according to the second embodiment. However, the controlling
portion 210 of the signal processing circuit 600 differs from the
signal processing circuit 200 according to the second embodiment in
the condition of the reference voltage V.sub.ref for determining
the potential of the connecting portion Q. With the signal
processing circuit 200 of the second embodiment, the condition of
the reference voltage V.sub.ref is a potential required to cause
the amplifier 111 to perform a desired operation. However, with the
signal processing circuit 600, the reference voltage V.sub.ref is a
potential required to cause the amplifiers 111-1 to 111-N to
perform a desired operation.
[0126] To be more precise, with the signal processing circuit 200
according to the second embodiment, the potential of the connecting
portion Q determines the potential of the source terminal of the
transistor of the amplifier 111, however, with the signal
processing circuit 600, the potential of the connecting portion Q
determines potentials of source terminals of transistors of the
amplifiers 111-1 to 111-M in the upper amplifying stage and
determines potentials of drain terminals of transistors of
amplifiers 111-M+1 to 111-N in the lower amplifying stage. Hence,
the reference voltage V.sub.ref is set to such a voltage that the
potential of the connecting portion Q is a potential of source
terminals which allows transistors in the upper amplifying stage to
perform a desired operation and a potential of the drain terminals
which allows transistors in the lower amplifying stage to perform a
desired operation.
Second Modified Example
[0127] Next, a signal processing circuit 700 according to a second
modified example of the fifth embodiment will be described. FIG. 7
is a circuit diagram of the signal processing circuit 700 according
to the second modified example of the fifth embodiment. As
illustrated in FIG. 7, the configuration of the signal processing
circuit 600 according to the first embodiment is further configured
as a differential circuit. The differential circuit has been
described in the fourth embodiment, and therefore, description
thereof will not be repeated. In addition, the signal processing
circuit 700 employs the same configuration as the signal processing
circuit described in the fourth embodiment except that amplifiers
are N amplifiers 411-1 to 411-N.
Third Modified Example
[0128] Next, a signal processing circuit 800 according to a third
modified example of the fifth embodiment will be described. FIG. 8
is a circuit diagram of the signal processing circuit 800 according
to the third modified example of the fifth embodiment.
[0129] Although, with the signal processing circuit 500 according
to the fifth embodiment, the amplifying portion 510 has a plurality
of amplifiers 111-1 to 111-N and a signal amplified by the kth
amplifier is amplified by the (k+1)th amplifier, amplifiers 111-1
to 111-N of an amplifier 810 according to the present modified
example receive inputs of different signals and amplify different
signals.
[0130] That is, the drain terminal of the kth (wherein k is an
integer of 0<k<N) amplifier 111-k of the amplifiers 111-1 to
111-N is not connected to the gate terminal of the (k+1)th
amplifier 111-k+1. The other configurations are the same as those
of the signal processing circuit 500.
[0131] Hereinafter, the flow of an alternate current signal of the
amplifying portion 810 of the signal processing circuit 800 will be
described. The alternate current signal flowing into the frequency
converting circuit 120 and direct current signal flowing into the
amplifying portion are the same as those in the signal processing
circuit 500, and therefore, description thereof will not be
repeated.
[0132] The amplifiers 111-1 to 111-N-1 respectively receive inputs
of alternate current signals INPUT.sub.1 to INPUT.sub.n-1 from
outside through the terminal c. The amplifiers 111-1 to 111-N-1
respectively amplify alternate current signals INPUT.sub.1 to
INPUT.sub.n-1 and generate amplified alternate current signals
OUTPUT.sub.1 to OUTPUT.sub.n-1. The amplifiers 111-1 to 111-N-1
respectively output the amplified alternate current signals
OUTPUT.sub.1 to OUTPUT.sub.n-1 to outside through the terminal
d.
[0133] With the example of FIG. 8, the amplifier 111-N amplifies
the input signal INPUT.sub.N inputted from the terminal c, and
generates an amplified signal. The amplifier 111-N outputs the
amplified signal from the terminal d to the gate terminal of the
transistor M1 of the voltage-current converter 124.
[0134] Although an example has been described with the above
example where all amplifiers 111-1 to 111-N respectively amplify
different signals, a configuration where some of amplifiers are
connected in cascade and sequentially amplify input signals may be
employed. That is, a configuration where the drain terminal of the
kth (wherein k is an integer of 0<k<N) amplifier 111-k of
some of the amplifiers 111-1 to 111-N is connected to the gate
terminal of the (k+1)th amplifier 111-k+1.
[0135] Further, although a configuration has been described with
the example in FIG. 8 where the amplified signal generated by the
amplifier 111-N is inputted to the voltage-current converter 124,
amplified alternate current signals generated by the other
amplifiers 111-1 to 111-N-1 may be used as inputs of the
voltage-current converter 124.
Fourth Modified Example
[0136] Next, a signal processing circuit 900 according to a fourth
modified example of the fifth embodiment will be described using
FIG. 9.
[0137] The signal processing circuit 900 differs from the signal
processing circuit 500 in that the upper amplifying stage and lower
amplifying stage are not connected in cascade in a case of the
alternate current signal. Further, the signal processing circuit
900 differs from the signal processing circuit 500 according to the
fifth embodiment in that the signal processing circuit 900
amplifies the input signal in the lower amplifying stage and
amplifies, in the upper amplifying stage, the multiplied voltage
signal which is an output of the frequency converting circuit 920.
Hereinafter, these will be described in detail.
[0138] First, the configuration of an amplifying portion 910 will
be described. With the amplifying portion 910, the upper amplifying
stage and lower amplifying stage are not connected in cascade in
the case of the alternate current signal. To be more specific, the
drain terminal of the amplifier 111-M in the upper amplifying stage
and the gate terminal of the amplifier 111-M+1 in the lower
amplifying stage are not connected.
[0139] All amplifiers 111-1 to 111-M in the upper stage are
connected in cascade. That is, the drain terminal of the kth
(wherein k is an integer of 0<k<M) amplifier 111-k is
connected to the gate terminal of the (k+1)th amplifier 111-k+1.
Further, all amplifiers 111-M+1 to 111-N in the lower stage are
connected in cascade. That is, the drain terminal of the kth
(wherein k is an integer of M<k<N) amplifier 111-k is
connected to the gate terminal of the (k+1)th amplifier
111-k+1.
[0140] Further, the terminal c of the amplifier 411-1 in the upper
amplifying stage is connected to the terminals f and g of the
current-voltage converting circuit 123 through an impedance element
930. Further, the terminal c of the amplifier 411-M+1 in the lower
amplifying stage receives an input of an input signal. The terminal
d of the amplifier 411-N in the lower amplifying stage is connected
to the voltage-current converter 424.
[0141] Next, the flow of an alternate current signal will be
described. The flow of the direct current is the same as that of
the signal processing circuit 500, and therefore, description
thereof will not be repeated.
[0142] The input signal is inputted through the terminal c of the
amplifier 411-M+1 in the lower stage. The amplifier 411-M+1 to
amplifier 411-N amplify the input signals, and output amplified
signal from the terminal d of the amplifier 411-N. The amplified
signal is outputted to the voltage-current converter 124. Next, the
amplified signal is converted into a multiplied voltage signal by
the frequency converting circuit 920. Subsequently, the multiplied
voltage signal is inputted to the terminal c of the amplifier 411-1
in the upper stage through the impedance element 930. The amplifier
411-1 to amplifier 411-M in the upper stage amplify the multiplied
voltage signals and output the amplified multiplied voltage signals
from the terminal d of the amplifier 411-M. That is, the signal
processing circuit 900 according to the fourth modified example
employs a configuration where the amplifiers 411-M+1 to 411-N in
the lower stage operate as an amplifying portion at a stage before
the frequency converting circuit 920, and the amplifiers 411-1 to
411-M in the upper stage operate as an amplifying portion in the
later stage.
[0143] In addition, a configuration may be employed where the
amplifiers 411-1 to 411-M in the upper stage operate as the
amplifying portion at the stage before the frequency converting
circuit 920, and the amplifiers 411-M+1 to 411-N in the lower stage
operate as an amplifying portion.
Sixth Embodiment
[0144] Next, a receiver 1500 according to a sixth embodiment will
be described using FIG. 10.
[0145] The receiver 1500 according to the sixth embodiment uses a
signal processing circuit 400 as a LNA (Low-Noise Amplifier)
built-in mixer, and has an orthogonal demodulation function of the
superheterodyne system.
[0146] The receiver 1500 has an antenna 1510 which receives a high
frequency signal (input signal); a first local oscillator 1520
which generates a first local signal; the signal processing circuit
400 which amplifies an input signal, generates an amplified signal,
and generates a multiplied voltage signal by multiplying the
amplified signal by a first local signal; a second local oscillator
1560 which generates a second local oscillation signal; a phase
shifter 1570 which generates a third local oscillation signal
obtained by shifting the phase of the second local oscillation
signal by 90 degrees; a mixer 1530-1 which multiplies the
multiplied voltage signal by a second local signal and generates a
first demodulated signal; a mixer 1530-2 which multiplies the
multiplied voltage signal by a third local signal and generates a
second demodulated signal; a lowpass filter 1540-1 which extracts a
signal of a desired band from the first demodulated signal and
generates a first extracted signal; a lowpass filter 1540-2 which
extracts a signal of a desired band from the second demodulated
signal, and generates a second extracted signal; a variable gain
amplifier 1550-1 which amplifies the first extracted signal and
generates a first output signal; and a variable gain amplifier
1550-2 which amplifies the second extracted signal and generates a
second output signal. The first output signal and second output
signal are outputted to a signal processing portion which is not
illustrated. The signal processing portion performs signal
processing such as A/D conversion of the output signals.
[0147] As illustrated in FIG. 4, the signal processing circuit 400
employs a configuration including the amplifying portion 410 which
amplifies an input signal and generates an amplified signal, and a
frequency converting circuit 420 which generates a multiplied
voltage signal from the amplified signal.
[0148] The receiver 1500 according to the present embodiment can
realize a mixer which can be driven by a local signal of a low
voltage without additional power consumption, using the signal
processing circuit 400 as the LNA (Low-Noise Amplifier) build-in
mixer, and provide good conversion gain and noise
characteristics.
[0149] Although the receiver 1500 employs the configuration using
the signal processing circuit 400 with the present embodiment, any
one of the signal processing circuits 100 to 900 may be used.
[0150] Further, although the receiver 1500 has an orthogonal
demodulation function of the superheterodyne system with the
present embodiment, the configuration of the receiver is not
limited to this.
[0151] While certain embodiments have been described, these
embodiments have been presented by way of example only, and are not
intended to limit the scope of the inventions. Indeed, the novel
embodiments described herein may be embodied in a variety of other
forms; furthermore, various omissions, substitutions and changes in
the form of the embodiments described herein may be made without
departing from the spirit of the inventions. The accompanying
claims and their equivalents are intended to cover such forms or
modifications as would fall within the scope and sprit of the
inventions.
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