U.S. patent application number 12/819109 was filed with the patent office on 2011-12-22 for trench mos barrier schottky rectifier with a planar surface using cmp techniques.
Invention is credited to Thomas E. Grebs.
Application Number | 20110309470 12/819109 |
Document ID | / |
Family ID | 45327921 |
Filed Date | 2011-12-22 |
United States Patent
Application |
20110309470 |
Kind Code |
A1 |
Grebs; Thomas E. |
December 22, 2011 |
Trench MOS Barrier Schottky Rectifier With A Planar Surface Using
CMP Techniques
Abstract
High Efficiency Diode (HED) rectifiers with improved performance
including reduced reverse leakage current, reliable solderability
properties, and higher manufacturing yields are fabricated by
minimizing topography variation at various stages of fabrication.
Variations in the topography are minimized by using a CMP process
to planarize the HED rectifier after the field oxide, polysilicon
and/or solderable top metal are formed.
Inventors: |
Grebs; Thomas E.; (South
Jordan, UT) |
Family ID: |
45327921 |
Appl. No.: |
12/819109 |
Filed: |
June 18, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12819023 |
Jun 18, 2010 |
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12819109 |
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Current U.S.
Class: |
257/520 ;
257/E21.546; 257/E29.02; 438/430; 438/691 |
Current CPC
Class: |
H01L 29/0619 20130101;
H01L 29/66143 20130101; H01L 29/8725 20130101 |
Class at
Publication: |
257/520 ;
438/430; 438/691; 257/E21.546; 257/E29.02 |
International
Class: |
H01L 29/06 20060101
H01L029/06; H01L 21/762 20060101 H01L021/762 |
Claims
1-9. (canceled)
10. A method of forming a semiconductor device, comprising: forming
a field oxide in an epitaxial layer; wherein the field oxide
extends into the epitaxial layer and above the epitaxial layer;
planarizing the field oxide using chemical mechanical planarization
(CMP) to generate a substantially planar surface comprising
substantially planar regions of field oxide and epitaxial layer;
forming a plurality of trenches in the epitaxial layer separated by
mesas, the plurality of trenches comprising sidewalls and a bottom;
forming a shield dielectric that lines the sidewalls and bottom of
the trenches and substantially covers the mesas and field oxide
region; depositing polysilicon to substantially fill the plurality
of trenches and substantially cover the shield dielectric.
11. The method of claim 10 further comprising planarizing the
polysilicon using chemical mechanical planarization (CMP) to
generate a substantially planar surface comprising substantially
planar regions of polysilicon, shield dielectric, and mesas.
12. The method of claim 10 wherein forming the field oxide
comprises: forming a pad oxide layer over a substrate; forming a
nitride layer over the pad oxide layer; etching the pad oxide layer
and nitride layer, according to a pattern; gowning the field oxide
in the pattern and recessed into the substrate; and removing the
pad oxide layer and nitride layer from active areas.
13. A method of forming a semiconductor device, comprising: forming
a field oxide in an epitaxial layer; wherein the field oxide
extends into the epitaxial layer and above the epitaxial layer;
forming a plurality of trenches in the epitaxial layer separated by
mesas, the plurality of trenches comprising sidewalls and a bottom;
forming a shield dielectric that lines the sidewalls and bottom of
the trenches and substantially covers the mesas and field oxide
region; depositing polysilicon to substantially fill the plurality
of trenches and substantially cover the shield dielectric; forming
a top metal over the polysilicon and over a portion of the shield
dielectric layer; forming a dielectric layer over a first portion
of the top metal; forming a solderable top metal (STM) layer over a
second portion of the top metal; and planarizing the STM layer
using chemical mechanical planarization (CMP) to generate a
substantially planar surface comprising substantially planar
regions of the STM material and dielectric material.
14. The method of claim 13 further comprising planarizing the field
oxide using chemical mechanical planarization (CMP) to generate a
substantially planar surface comprising substantially planar
regions of field oxide and epitaxial layer.
15. The method of claim 13 further comprising planarizing the
polysilicon using chemical mechanical planarization (CMP) to
generate a substantially planar surface comprising substantially
planar regions of polysilicon, shield dielectric and mesas.
16. The method of claim 13 further comprising: planarizing the
field oxide using chemical mechanical planarization (CMP) to
generate a substantially planar surface comprising substantially
planar regions of field oxide and epitaxial layer; and planarizing
the polysilicon using chemical mechanical planarization (CMP) to
generate a substantially planar surface comprising substantially
planar regions of polysilicon, shield dielectric and mesas.
17. The method of claim 13 further comprising forming a nickel
silicide (NiSi) layer over the plurality of trenches.
18. The method of claim 17 wherein the top metal is formed over a
portion of the NiSi layer and over a portion of the shield
dielectric layer deposited on the field oxide layer.
19. The method of claim 13 wherein the dielectric layer comprise
polyimide.
20-23. (canceled)
24. A semiconductor device comprising: an epitaxial layer; a field
oxide region disposed in the epitaxial layer, wherein the field
oxide extends into the epitaxial layer and forms a substantially
planar first surface comprising substantially planar regions of
field oxide and epitaxial layer; a plurality of trenches comprising
sidewalls and a bottom disposed in the epitaxial layer, the
plurality of trenches separated by a plurality of mesas; a shield
dielectric that lines the trench sidewalls and bottom of the
trenches and covers the field oxide region; and a polysilicon that
substantially fills the plurality of trenches.
25. The semiconductor device of claim 24 wherein the first surface
is formed using chemical mechanical planarization (CMP).
26. The semiconductor device of claim 24 wherein the top surface of
the field oxide and the top surface of the epitaxial layer form a
contiguous surface.
27. The semiconductor device of claim 24 further comprising a
substantially planar second surface comprising substantially planar
regions of polysilicon, shield dielectric and mesas, the second
surface is formed using CMP.
28. A semiconductor device comprising: an epitaxial layer; a field
oxide region disposed in the epitaxial layer, wherein the field
oxide extends into the epitaxial layer; a plurality of trenches
comprising sidewalls and a bottom disposed in the epitaxial layer,
the plurality of trenches separated by a plurality of mesas; a
shield dielectric that lines the trench sidewalls and bottom of the
trenches and covers the field oxide region; a polysilicon that
substantially fills the plurality of trenches; a top metal that
covers a portion of the shield dielectric layer; a dielectric layer
that covers a first portion of the top metal; a solderable top
metal (STM) layer disposed adjacent to the dielectric layer and
covering a second portion of the top metal; and a substantially
planar first surface comprising substantially planar regions of the
STM material and dielectric material.
29. The semiconductor device of claim 28 wherein the substantially
planar first surface is formed using chemical mechanical
planarization (CMP).
30. The semiconductor device of claim 28 further comprising a
substantially planar second surface comprising substantially planar
regions of field oxide and epitaxial layer, the substantially
planar second surface formed using chemical mechanical
planarization (CMP).
31. The semiconductor device of claim 28 further comprising a
substantially planar third surface comprising substantially planar
regions of polysilicon, shield dielectric and mesas, the
substantially planar third surface formed using chemical mechanical
planarization (CMP).
32. The semiconductor device of claim 28 further comprising: a
substantially planar second surface comprising substantially planar
regions of field oxide and epitaxial layer, the substantially
planar second surface formed using chemical mechanical
planarization (CMP); and a substantially planar third surface
comprising substantially planar regions of polysilicon, shield
dielectric and mesas, the substantially planar third surface formed
using chemical mechanical planarization (CMP).
33. The semiconductor device of claim 28 wherein the dielectric
layer comprises polyimide.
34. The semiconductor device of claim 28 wherein the STM metal
comprises Ti/NiV/Ag or Ta/Cu.
Description
BACKGROUND
[0001] The present invention relates to semiconductor power device
technology and more particularly to improved trench MOS (metal
oxide semiconductor) barrier Schottky rectifiers with planar
surfaces and fabrication processes for forming the same.
[0002] Trench MOS barrier Schottky (TMBS) rectifiers are Schottky
diodes that have been integrated with trench gate shielding
structures (e.g., TMBS rectifiers or monolithically integrated
trench gate FET and Schottky diode devices). An integrated TMBS,
which typically includes a Schottky diode array that has been
interspersed between MOS trenches, generally comprises a mesa
structure formed in a semiconductor epitaxial layer of a
semiconductor substrate. The mesa is defined by the region between
one or more trenches, which are disposed in the epitaxial layer. In
TMBS devices, charge coupling between majority charge carriers in a
mesa disposed between trenches in the epitaxial/drift region and
conductors on the sidewalls of the trenches changes the electric
field profile under the Schottky contact which reduces reverse
leakage current and improves breakdown properties.
[0003] Existing techniques used to fabricate TMBS rectifiers
produce topographies between device structures. For example, in an
active array the tops of the polysilicon gates, silicon mesa and
field dielectric are irregular and not substantially flat. This
irregular topography can include abrupt changes which can
significantly affect device performance by increasing reverse
leakage current. Further, topographies which are created between
the polysilicon gates and the mesa regions or the field dielectric
to the active array propagate to layers that are subsequently
formed on top of the polysilicon gates and mesa regions or the
field dielectric and active array. These topographies propagate to
the top surfaces of the TMBS rectifiers which end up having similar
topographies. The top surfaces of the TMBS rectifier can include
layers such as nitride layers and solderable top metal (STM) layers
which are prone to developing cracks when they have substantially
non-planar topographies. The cracks that develop in the nitride and
STM layers on the top of the TMBS rectifiers can propagate to the
bottom part of the nitride and STM layers and reach the metal pad
layer. These cracks can then increase the reverse leakage current
in the TMBS rectifier which make the TMBS rectifier inoperable or
reduce its performance.
[0004] These topographies can also reduce the effectiveness of
solder connections made with the STM to the package. The
topographies can reduce the integrity of the solder connection
because the non-coplanar surface on the STM layer on top of the
TMBS rectifier is not as conducive to soldering as a planar
surface. Since these topographies reduce the integrity of the
solder connection, the topographies also reduce the reliability of
the TMBS rectifier because the solder connections on the STM
surface having non-coplanar topography are not as reliable.
[0005] Further, variations in topographies which are created
between the polysilicon gates and mesa can increase the chances of
inducing plasma damage to the structure (shield dielectric). The
damage is caused by plasma etching the polysilicon gates, which has
a non-planar surface between the polysilicon and mesa regions. This
plasma induced damage can further damage the TMBS rectifier while
it is being fabricated. The non-uniform topographies can increase
the chances of damage occurring during processes such as plasma
etching. Non-uniform contours can cause charge build up during
processes such as etching which can cause arcing and damage to the
TMBS rectifier as it is being fabricated. Damages that occur during
fabrication can reduce yields which can increase the cost of
manufacturing TMBS rectifiers. Variations in the topography can
also make it difficult to uniformly deposit onto or etch material
from the surface. For example, variations in topography make it
difficult to bring the entire surface of the substrate in the depth
of field of photolithography systems, or selectively remove
material based on position. These variations that occur during
fabrication can lead to variations in the electrical performance of
the TMBS rectifier.
[0006] Therefore, there is a need for cost effective fabrication
processes and substrate structures that reduce variations in the
topography surface between termination and active cells and assists
in reducing reverse leakage current and improves solderability
properties.
SUMMARY
[0007] Embodiments of the present invention provide techniques for
fabricating High Efficiency Diode (HED) rectifiers that reduce
variations in the topography surface between termination and active
cells and assists in reducing reverse leakage current and improves
solderability properties. Embodiments of the invention also provide
embodiments of HED rectifiers structures made using these
techniques.
[0008] In one embodiment, a method of forming a semiconductor
device includes forming a field oxide region in an epitaxial layer,
forming a plurality of trenches that have sidewalls and a bottom in
the epitaxial layer separated by mesas, forming a shield dielectric
that lines the sidewalls and bottom of the trenches and
substantially covers the mesas and field oxide region, depositing
polysilicon to substantially fill the plurality of trenches and
substantially cover the shield dielectric, and planarizing the
polysilicon using chemical mechanical planarization (CMP) to
generate a substantially planar surface including substantially
planar regions of polysilicon, shield dielectric, and mesa regions.
The field oxide region extends into the epitaxial layer and above
the epitaxial layer. The regions of polysilicon, shield dielectric
and mesa regions can be formed by planarization to form a
substantially flat contiguous surface.
[0009] In another embodiment, the method further includes forming a
top metal layer, a dielectric layer, and a solderable top metal
(STM) layer over the top metal. The tops of the dielectric layer
and the STM layer are substantially coplanar. The top metal can
include a Schottky contact. The top metal can be formed over a
portion of a NiSi layer and over a portion of the shield dielectric
layer deposited on the field oxide layer. The dielectric layer can
include polyimide. The dielectric layer can also be selected from
the group consisting of polyimide and deposited silicon nitride,
polyimide and deposited silicon dioxide, polyimide and deposited
silicon oxy-nitride, silicon nitride, silicon oxy-nitride, and
silicon dioxide. A portion of the dielectric layer can be a street
which is used to separate the semiconductor devices made on a
single wafer.
[0010] In another embodiment of the method, forming the STM metal
includes depositing Ti/NiV/Ag or Ta/Cu over the top metal.
[0011] In another embodiment, a second method of forming a
semiconductor device includes forming a field oxide in an epitaxial
layer, planarizing the field oxide using chemical mechanical
planarization (CMP) to generate a substantially planar surface that
includes substantially planar regions of field oxide and epitaxial
layer, forming a plurality of trenches that have sidewalls and a
bottom in the epitaxial layer separated by mesas, forming a shield
dielectric that lines the sidewalls and bottom of the trenches and
substantially covers the mesas and field oxide region, and
depositing polysilicon to substantially fill the plurality of
trenches and substantially cover the shield dielectric. The field
oxide extends into the epitaxial layer and above the epitaxial
layer. The polysilicon can be planarized using chemical mechanical
planarization (CMP) to generate a substantially planar surface that
includes substantially planar regions of polysilicon, shield
dielectric, and mesas.
[0012] In yet another embodiment of the second method, forming the
field oxide includes forming a pad oxide layer over a substrate,
forming a nitride layer over the pad oxide layer, etching the pad
oxide layer and nitride layer according to a pattern, gowning the
field oxide in the pattern and recessed into the substrate, and
removing the pad oxide layer and nitride layer from active
areas.
[0013] In another embodiment, a third method of forming a
semiconductor device includes forming a field oxide in an epitaxial
layer, forming a plurality of trenches that have sidewalls and a
bottom in the epitaxial layer separated by mesas, forming a shield
dielectric that lines the sidewalls and bottom of the trenches and
substantially covers the mesas and field oxide region, depositing
polysilicon to substantially fill the plurality of trenches and
substantially cover the shield dielectric, forming a top metal over
the polysilicon and over a portion of the shield dielectric layer,
forming a dielectric layer over a first portion of the top metal,
forming a solderable top metal (STM) layer over a second portion of
the top metal, and planarizing the STM layer using chemical
mechanical planarization (CMP) to generate a substantially planar
surface that includes substantially planar regions of the STM
material and dielectric material. The field oxide extends into the
epitaxial layer and above the epitaxial layer. The dielectric layer
can include polyimide.
[0014] In yet another embodiment, the third method further includes
planarizing the field oxide using chemical mechanical planarization
(CMP) to generate a substantially planar surface including
substantially planar regions of field oxide and epitaxial
layer.
[0015] In yet another embodiment, the third method further includes
planarizing the polysilicon using chemical mechanical planarization
(CMP) to generate a substantially planar surface including
substantially planar regions of polysilicon, shield dielectric and
mesas.
[0016] In yet another embodiment, the third method further includes
planarizing the field oxide using chemical mechanical planarization
(CMP) to generate a substantially planar surface including
substantially planar regions of field oxide and epitaxial layer,
and planarizing the polysilicon using chemical mechanical
planarization (CMP) to generate a substantially planar surface
including substantially planar regions of polysilicon, shield
dielectric and mesas.
[0017] In yet another embodiment, the third method further includes
forming a nickel silicide (NiSi) layer over the plurality of
trenches. The top metal can be formed over a portion of the NiSi
layer and over a portion of the shield dielectric layer deposited
on the field oxide layer.
[0018] In another embodiment, a semiconductor device includes an
epitaxial layer, a field oxide region disposed in the epitaxial
layer, a plurality of trenches that include sidewalls and a bottom
disposed in the epitaxial layer, the plurality of trenches are
separated by a plurality of mesas, a shield dielectric that lines
the trench sidewalls and bottom of the trenches and covers the
field oxide region, a polysilicon that substantially fills the
plurality of trenches, and a substantially planar surface that
includes substantially planar regions of polysilicon, shield
dielectric and mesas. The substantially planar surface can be
formed using chemical mechanical planarization (CMP). The field
oxide extends into the epitaxial layer. The substantially planar
surface can be contiguous with polysilicon, shield dielectric and
mesas.
[0019] In yet another embodiment, the semiconductor device further
includes a top metal, a dielectric layer and a solderable top metal
(STM) layer disposed over the top metal. The tops of the dielectric
layer and the STM layer are substantially coplanar.
[0020] In another embodiment, a second semiconductor device
includes an epitaxial layer, and a field oxide region disposed in
the epitaxial layer. The field oxide extends into the epitaxial
layer and forms a substantially planar first surface including
substantially planar regions of field oxide and epitaxial layer, a
plurality of trenches including sidewalls and a bottom disposed in
the epitaxial layer, the plurality of trenches separated by a
plurality of mesas, a shield dielectric that lines the trench
sidewalls and bottom of the trenches and covers the field oxide
region, and a polysilicon that substantially fills the plurality of
trenches. The first surface can be formed using chemical mechanical
planarization (CMP). The top surface of the field oxide and the top
surface of the epitaxial layer can form a contiguous surface.
[0021] In yet another embodiment, the second semiconductor device
further includes a substantially planar second surface including
substantially planar regions of polysilicon, shield dielectric and
mesas, the second surface is formed using CMP.
[0022] In another embodiment, a third semiconductor device includes
an epitaxial layer, a field oxide region disposed in the epitaxial
layer, a plurality of trenches including sidewalls and a bottom
disposed in the epitaxial layer, a shield dielectric that lines the
trench sidewalls and bottom of the trenches and covers the field
oxide region, a polysilicon that substantially fills the plurality
of trenches, a top metal that covers a portion of the shield
dielectric layer, a dielectric layer that covers a first portion of
the top metal, a solderable top metal (STM) layer disposed adjacent
to the dielectric layer and covering a second portion of the top
metal, and a substantially planar first surface that includes
substantially planar regions of the STM material and dielectric
material. The substantially planar first surface can be formed
using chemical mechanical planarization (CMP). The field oxide
extends into the epitaxial layer. The plurality of trenches is
separated by a plurality of mesas. The dielectric layer can be any
dielectric materials such as polyimide, polymer dielectrics, know
semiconductor dielectrics, or combinations thereof. For example,
the dielectric layer can be selected from the group consisting of
polyimide and deposited silicon nitride, polyimide and deposited
silicon dioxide, polyimide and deposited silicon oxy-nitride,
silicon nitride, silicon oxy-nitride, and silicon dioxide. The STM
metal can include Ti/NiV/Ag or Ta/Cu.
[0023] In yet another embodiment, a third semiconductor device
further includes a substantially planar second surface including
substantially planar regions of field oxide and epitaxial layer,
the substantially planar second surface formed using chemical
mechanical planarization (CMP).
[0024] In yet another embodiment, a third semiconductor device
further includes a substantially planar third surface including
substantially planar regions of polysilicon, shield dielectric and
mesas, the substantially planar third surface formed using chemical
mechanical planarization (CMP).
[0025] In yet another embodiment, a third semiconductor device
further includes a substantially planar second surface including
substantially planar regions of field oxide and epitaxial layer,
and a substantially planar third surface including substantially
planar regions of polysilicon, shield dielectric and mesas. The
substantially planar second surface is formed using chemical
mechanical planarization (CMP). The substantially planar third
surface is formed using chemical mechanical planarization
(CMP).
[0026] The embodiments described above and herein are not the only
embodiments of this invention. Features found in particular
embodiments described herein can be combined with other embodiments
described herein. Further areas of applicability of the present
disclosure will become apparent from the detailed description
provided hereinafter. It should be understood that the detailed
description and specific examples, while indicating various
embodiments, are intended for purposes of illustration only and are
not intended to necessarily limit the scope of the disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] A further understanding of the nature and advantages of the
invention may be realized by reference to the remaining portions of
the specification and the drawings, presented below. The Figures
are incorporated into the detailed description portion of the
invention.
[0028] FIG. 1 illustrates a cross section of an HED rectifier with
significant topography variations at the surface.
[0029] FIG. 2A is an illustration of a top view of an HED rectifier
that is made to have a planar structure between edge termination to
trenches and trenches to mesa regions.
[0030] FIGS. 2B-2C are expanded views of one of the HED rectifier
corners showing active devices separated by streets.
[0031] FIGS. 3A-3K are simplified cross section views at various
stages of a process for forming a HED rectifier, in accordance with
one embodiment of the invention.
[0032] FIG. 4 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarized polysilicon deposited
in trenches and above an epitaxial layer of a substrate.
[0033] FIG. 5 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarize an oxide layer and
using CMP to planarized polysilicon deposited in trenches and above
an epitaxial layer disposed on a substrate.
[0034] FIG. 6 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarize an oxide layer.
[0035] FIG. 7 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarize an oxide layer, using
CMP to planarized polysilicon deposited in trenches and above an
epitaxial layer disposed on a substrate, and using CMP to
planarized a STM layer.
[0036] FIG. 8 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarized polysilicon deposited
in trenches and above an epitaxial layer disposed above a substrate
and using CMP to planarized a STM layer.
[0037] FIG. 9 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarize an oxide layer and
using CMP to planarized a STM layer.
[0038] FIG. 10 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarized a STM layer.
[0039] FIG. 11 illustrates a cross section view of a semiconductor
device made in accordance with the methods described above with
reference to FIGS. 3-10.
DETAILED DESCRIPTION
[0040] In the following description, for the purposes of
explanation, specific details are set forth in order to provide a
thorough understanding of the invention. However, it will be
apparent that the invention may be practiced without these specific
details.
[0041] Embodiments of the present invention provide HED rectifiers
with improved performance including reduced reverse leakage
current, reliable solderability properties, and higher
manufacturing yields. The improved HED rectifier has a reduce
topography variation across the surface between termination and
active cells which assists in reducing reverse leakage current and
significantly improves solderability depending on packaging
methodology. The reverse leakage current is reduced by creating a
planar surface between shield dielectric, polysilicon and mesas,
prior to Schottky metallization. The reduced topography variation
produces a more uniform surface across the device which eliminates
plasma etch damage caused by traditional contact etch methods and
improves the uniformity of layers within the device. A CMP process
can also be used to keep the shield electrode and dielectric intact
to reduce the electric field at the top corners of the cell
structure. A low stress metallic Schottky contact region is formed
with the mesa that is co-planar with the shield electrode and
dielectric. A recessed field oxide is produced using a LOCal
Oxidation of Silicon (LOCOS) process. A chemical mechanical
planarization process can be used to form the termination
dielectric which provides a planar surface from street to active
area. The shield polysilicon electrode is processed using CMP to
produce a planarized surface across the active cell structure
(shield polysilicon, shield dielectric and active silicon mesa
area). The solderable metal surface can also be processed using CMP
to help planarize the solderable surface.
[0042] FIG. 1 illustrates a cross section of an HED rectifier with
significant topography variations at the surface that are caused by
height variations between the shield dielectric layer, polysilicon
gates, and field oxide layers. The HED rectifier includes a
substrate 100, an epitaxial layer 102, a field oxide region 120, an
implant region 125, trenches 135 shield dielectric layer 140,
polysilicon 145, a nickel silicide layer (NiSi) 160, a top metal
165, a nitride layer 175, a solderable top metal (STM) layer 185,
and regions 190A-190E. Region 190A is a region showing the
irregularity in the nickel silicide layer (NiSi) 160, which causes
reverse leakage current. The irregularities shows in the region
190A are caused by height variations between the trenches 135 and
the mesas between the trenches 135. Regions 190B-190E are regions
where the nitride layer 175 is prone to cracking because of the
topography of the nitride layer 175 in these regions. The
variations in topography on the nitride layer 175 at the surface of
the HED rectifier, which are illustrated in regions 190A-190E,
originated because of height variations between the field oxide
layers 120, shield dielectric layer 140, and polysilicon 145 gates.
These height variations between the field oxide layers 120, shield
dielectric layer 140, and polysilicon 145 gates are propagated when
a layer is deposited on top of these layers until the variations
are manifested on the surface of the HED rectifier.
[0043] Because of its topography, region 190A can cause significant
reverse leakage current in the HED rectifier, which can reduce its
performance or render it inoperable. In one embodiment, the field
oxide region 120 is planarized using a CMP process to generate a
substantially planar surface having substantially planar regions at
the top of the trenches with field oxide and epitaxial layer, which
significantly reduces reverse leakage current. Further details of
this CMP process are discussed with reference to FIGS. 3-10
below.
[0044] Also, because of its topography the other regions 190B-190E
can develop a primary crack that can propagate to the bottom part
of the nitride 175, which can increase the reverse leakage current
in the HED rectifier reducing its performance or rendering it
inoperable. The chances of this primary crack developing can be
significantly reduced by reducing the variation in topography in
region 190A. The chances of this primary crack developing can also
be significantly reduced by reducing the variation in topography in
regions 190B-190E. In one embodiment the variation in topography in
regions 190B-190E is reduced by using CMP to planarize the field
oxide layers 120, shield dielectric layer 140, and polysilicon 145
gates. Once these layers are planarized, their height variation
will be significantly reduced and therefore will not propagate and
manifest itself on the surface of the HED rectifier. Further
details of this CMP process are discussed with reference to FIGS.
3-10 below. In another embodiment the variation in topography is
reduced by using polyimide instead of nitride in layer 175, as is
also discussed in further detail with reference to FIGS. 3-10
below. As an alternative to using polyimide, the following
compounds can also be used: polyimide and deposited silicon
nitride, polyimide and deposited silicon dioxide, polyimide and
deposited silicon oxy-nitride, silicon nitride, silicon
oxy-nitride, and silicon dioxide.
[0045] FIG. 2A is an illustration of a top view of a die 200 having
HED rectifiers which are made to have a planar structure between
edge termination to trenches and trenches to mesa regions. The HED
rectifiers in die 200 have a reduced reverse leakage current caused
by non-planarity. Die 200 includes diagonal opposite corners
210A-210D that have the same layout, regions 215A-215E which can
include active devices, and street 220. In other embodiments, only
some of the diagonal opposite corners 210A-210D have the same
layout.
[0046] FIGS. 2B and 2C are expanded views of one of the corners
210A-210D showing active devices 215A-215E with street separation
220. The expanded views of the top of the die 200 include a
solderable top metal (STM) 230, a dielectric opening 240, an end of
the STM 245, a contact opening 250, and an aluminum under
dielectric region 255. The STM layer can be a (Ti--NiV-Ag) pad with
topography lines of contact and aluminum layers. In some
embodiments, the Ag layer is slightly etched back from the NiV
layer resulting in two topography lines. FIG. 2C shows one
representative location where cross sections along lines A-A' can
be taken as illustrated in FIGS. 3A-3K.
[0047] FIGS. 3A-3K are simplified cross section views at various
stages of a process for forming a HED rectifier, in accordance with
one embodiment of the invention. FIGS. 3A-3K illustrate the process
of forming the region of the HED rectifier identified in region
A-A' as illustrated in FIG. 2C. However, the techniques illustrated
in FIGS. 3A-3K are applicable for forming HED rectifiers located in
other regions of die 200. In FIGS. 3A-3K, various operations are
performed on an epitaxial layer 302, which is disposed on a
substrate 300, to form an HED rectifier having a planar structure
between edge termination to trenches and trenches to mesa regions,
which reduces reverse leakage current caused by non-planarity. Many
HED rectifiers similar to that shown in FIGS. 3A-3K are typically
dispersed throughout the active region of the die 200 in a
predetermined frequency.
[0048] FIG. 3A, which illustrates a partially fabricated HED
rectifier along the cutline A-A', includes a substrate 300, an
epitaxial layer 302, a pad oxide layer 305, a nitride layer 310,
exposed photo resist coat 315A, and a field oxide region 320. The
substrate 300 can be an N-type wafer which has been previously
scribed with a laser to include information such as device type,
lot number, and wafer number. The substrate 300 can also be a
highly doped N+ substrate. The epitaxial layer 302, which is formed
over the substrate 300, can be made of the same conductivity or
different conductivity than the substrate 300. MOSFETs are formed
when the substrate 300 and epitaxial layer 302 are of the same
conductivity type, and IGBTs are formed when the substrate 300 has
the opposite conductivity type to that of the epitaxial layer 302.
In some embodiments, the epitaxial layer 302 is made of lightly
doped n-type material. The semiconductor region is a lightly doped
n-type epitaxial layer 302 formed over a highly doped substrate
300. A pad oxide layer 305 ranging from 200 .ANG. to 400 .ANG. is
grown on the epitaxial layer 302 using an oxidation process. The
epitaxial layer 302 is epitaxially grown on a substrate 300. The
pad oxide layer 305 is used for adherence and stress relief for
subsequently deposited layers. In some embodiments the substrate is
cleaned prior to forming the pad oxide layer 305. The nitride layer
310, which ranges from 500 .ANG. to 2000 .ANG., is deposited over
the pad oxide layer 305. In some embodiments, the nitride layer 310
is maintained between 1000 .ANG. to 1500 .ANG.. The nitride layer
310 is used to protect the active area of the device during the
field oxidation process. The exposed photo resist coat 315A is used
for field photolithography and defines future field oxide and
alignment targets. The exposed photo resist 315A is shown as
exposed and developed. The field oxide region 320 is formed by
first etching the nitride layer 310, and then the oxide layer 305,
and may extend into the epitaxial layer 302, which will eventually
become part of the field oxide region 320, stripping the masks used
to perform the etching, cleaning the device and then growing the
field oxide region 320 to be recessed in the silicon substrate with
some of the field oxide region being above the top surface of the
epitaxial layer 302.
[0049] FIG. 3B, which illustrates a further partially fabricated
HED rectifier along the cutline A-A', includes the substrate 300,
an epitaxial layer 302, exposed photo resist coat 315B, the field
oxide region 320 and an implant region 325. The exposed photo
resist coat 315B is used for field photolithography and defining
the subsequent implant regions. The exposed photo resist 315B is
shown as exposed and developed. In one embodiment a chemical
mechanical planarization (CMP) process is performed on the HED
rectifier illustrated in FIG. 3A to planarize the field oxide to
silicon mesa portions. The implant region 325 is produced by
implanting boron into the regions that are not covered by the
exposed photoresist 315B. In one embodiment boron is implanted
using a dosage ranging from 1e13 to 1e14 ions/cm2 and an energy
ranging from 40 to 200 KeV. In some embodiments, the implantation
energy is increased in order to produce a P-iso under the field
oxide layer 320. After the boron is implanted, the exposed photo
resist 315B is removed using oxygen plasma resist strip. After the
oxygen plasma strip, the HED rectifier is cleaned using
combinations of H.sub.2SO.sub.4/H.sub.2O.sub.2, mega Sonics,
NH.sub.4OH, H.sub.2O.sub.2, and DI Water. In some embodiments, the
implant regions 325 are omitted. In the embodiments where implant
regions 325 are omitted, the following FIGS. 3C-3K would also have
the implant regions 325 omitted.
[0050] FIG. 3C, which illustrates a further partially fabricated
HED rectifier along the cutline A-A', includes the substrate 300,
an epitaxial layer 302, the field oxide region 320, an implant
region 325, and a hard mask layer 330. In one embodiment a P-Iso
drive is performed. The hard mask layer 330 is also grown over the
substrate 300, the epitaxial layer 302, the field oxide region 320
and the implant region 325. The hard mask 330 is used later to
define trench etch areas. The thickness of the hard mask 330
depends upon photo resist type and thickness used to define trench
critical dimensions (CD) and depth. In one embodiment, the hard
mask oxide is thermally grown. In another embodiment the hard mask
oxide is deposited (i.e sputter, CVD, PVD, ALD, or combination of
deposition and thermal growth). This hard mask 330 is produced with
an oxidation process that may cause film thickness variations
between field and active regions causing non-uniform trench
dimensions in areas of trench termination (i.e. CD change of
5%).
[0051] FIG. 3D illustrates one way of forming trenches in a
partially fabricated HED rectifier. FIG. 3D, which illustrates this
formation, as seen along cutline A-A' includes the substrate 300,
an epitaxial layer 302, the field oxide region 320, an implant
region 325, the hard mask layer 330, an exposed photoresist 315C,
and trenches 335. The exposed photo resist coat 315C is used for
field photolithography and defining the subsequent formed trenches
335. The exposed photo resist 315C is shown as exposed and
developed. A plasma etch is used to open the hard mask layer 330
where trenches will be etched later. After the trench 335 openings
are formed in the hard mask layer 330, in one embodiment the
exposed photo resist 315C is removed using oxygen plasma resist
strip prior to etching trenches 335. The trenches 335 are formed by
etching. The etching process can involve using gaseous etchants
such as, for example, SF.sub.6/He/O.sub.2 chemistries. The depth of
the trenches can range from 0.5 to 10 .mu.m. In some embodiments,
the trenches are etched to a depth of approximately 1.20 um. The
etching process is selected so that the etching is selective to
silicon rather than the hard mask layer 330 material.
[0052] FIG. 3E illustrates an alternative to the methods
illustrated in FIGS. 3C-3D for P-iso driving and trench formation.
FIG. 3E, which illustrates this formation, as seen along cutline
A-A' includes the substrate 300, the epitaxial layer 302, the field
oxide region 320, an implant region 325, an exposed photoresist
315D, and trenches 335. A comparison of FIG. 3E with FIGS. 3C-3D
shows that the method illustrated in FIG. 3E does not use a hard
mask layer 330 which results in fewer processing steps and a
potentially more planar surface between the field regions and
active regions of the final HED rectifier device. The P-iso drive
is performed in nitrogen at ambient pressure. Since the exposed
photoresist 315D pattern will be used as an etch mask and a hard
mask layer 330 is not formed, this process reduces or eliminates
oxide thickness variations between field oxide region 320 and the
oxide hard mask layer 330. The etching process is selected so that
the etching is selective to silicon rather than the exposed
photoresist 315D material.
[0053] FIG. 3F illustrates the formation of a shield dielectric
layer and polysilicon in a partially fabricated HED rectifier
having trenches already formed. FIG. 3F, which illustrates the
formation of the shield dielectric layer and polysilicon, as seen
along cutline A-A' includes the substrate 300, the epitaxial layer
302, the field oxide region 320, an implant region 325, trenches
335 shield dielectric layer 340, and polysilicon 345. Before the
shield dielectric layer 340 is deposited, the partially fabricated
HED rectifier is cleaned. The cleaning process can include a
hydrogen fluoride (HF) etch and second soft etch, which can clean
the trenches 335 and remove residual polymer. Once the HED
rectifier is cleaned, the shield dielectric layer 340, also know as
the gate oxide, is formed. In some embodiments the shield
dielectric layer 340 can be thermally grown, deposited using atomic
layer deposition, physical vapor deposition, chemical vapor
deposition, or combination thereof. In one embodiment, the shield
dielectric layer 340 can have a thickness of approximately
400.+-.50 .ANG.. However the thickness of the shield dielectric
layer 340 can range from 200 to 5000 .ANG., depending on the
specific application. The shield dielectric layer quality and
thickness determines the device capability for electric field and
breakdown voltage. The shield dielectric layer 340 is deposited so
that it follows the contours of the trench and the substrate. The
shield dielectric layer 340 is deposited along the bottom and
sidewalls of the trench 335 and along the top of the epitaxial
layer 302, the field oxide region 320 and an implant region 325. In
some embodiments, the shield dielectric layer 340 can form a
contiguous film along the bottom and sidewalls of the trench 335
and along the top of the epitaxial layer 302, the field oxide
region 320 and the implant region 325. The shield dielectric layer
340 can be formed by exposing the HED rectifier to oxygen diluted
in an inert gas such as argon, helium, or xenon at high
temperatures over 1000.degree. C. The shield dielectric layer 340
can form a thick bottom oxide (TBO) in the trenches 335 to improve
breakdown voltage capabilities.
[0054] After the shield dielectric layer 340 is deposited, the
polysilicon 345 material is deposited inside the trench 335 and
over the top of the shield dielectric layer 340. The polysilicon
material which is deposited into the trenches 335 and over the
shield dielectric layer 340 is amorphous undoped polysilicon and
has a thickness of approximately 5500 .ANG..+-.500 .ANG.. The
polysilicon material is then doped by implanting boron. In one
embodiment, boron is implanted into the undoped polysilicon
material using a high carrier concentration.
[0055] FIG. 3G illustrates the process of annealing the
polysilicon, removing the excess polysilicon and etching recesses
in a partially fabricated HED rectifier shown in FIG. 3F. FIG. 3G,
which illustrates annealing the polysilicon, removing the excess
polysilicon and etching recesses, as seen along cutline A-A',
includes the substrate 300, the epitaxial layer 302, the field
oxide region 320, the implant region 325, trenches 335 shield
dielectric layer 340, and polysilicon 345. Once the HED rectifier
is cleaned, the polysilicon 345 material is annealed by heating the
partial HED rectifier. The excess polysilicon 335 material is then
removed using CMP. The CMP process removes the excess polysilicon
335 material disposed on top of the shield dielectric layer 340
outside of the trenches 335 with the use of a chemical slurry and
abrasive grinding pad specially designed for removing polysilicon
film. The CMP tool dispenses a chemical slurry mixture onto the top
surface of the wafer. The grinder head, which has an abrasive pad
attached to the head, is then lowered to come into contact with
upper polysilicon surface and the slurry. The slight chemical etch
provided by the slurry coupled with the force of the abrasive pad
provided by the head causes the polysilicon to be planarized to the
shield dielectric surface. The CMP process can also be used to
remove some of the shield dielectric layer 340 disposed outside of
the trench 335, leaving behind a thinner shield dielectric layer
340 outside of trenches 335 than inside of trenches 335. After the
partial HED rectifier has been processed with CMP, the resulting
partial HED rectifier has the shield dielectric layer 340 partially
extending above the epitaxial layer 302, and trenches 335 with the
polysilicon 345 material filling the trenches 335 up to the shield
dielectric layer 340 and flush with the top of the shield
dielectric layer 340.
[0056] In other embodiments, a CMP process can be used to further
remove the remaining shield dielectric on the tops of the mesas. In
this embodiment an end point detector can be used to determine when
the polysilicon has been removed. After the polysilicon is removed
the CMP process can be changed to a different CMP process to remove
the shield dielectric layer. Changing to a different CMP process
can include changing the slurry composition and pad abrasiveness to
one which is designed to etch oxides. Once the CMP setup and
process is changed the shield dielectric is removed from the mesa
surface using this new CMP process. This new CMP process is stopped
when silicon is exposed.
[0057] FIG. 3H, which illustrates the partially fabricated HED
rectifier after having several metallic layers deposited, as seen
along cutline A-A', includes the substrate 300, the epitaxial layer
302, the field oxide region 320, the implant region 325, trenches
335 shield dielectric layer 340, and polysilicon 345, a nickel
silicide layer (NiSi) 360, a top metal 365 and an opening 370. The
NiSi layer 360 is formed by depositing nickel over the planarized
region having exposed polysilicon 345 in the trenches 335 and
exposed silicon which forms the mesas between the trenches 335.
Nickel silicide (NiSi) forms when the nickel is exposed to the
silicon from substrate 300 and some subsequent heat treatment
ranging from 250.degree. C. to 550.degree. C. is applied. The
un-reacted nickel is removed from the oxide areas. In some cases,
the un-reacted nickel can be left behind. In some embodiments that
NiSi layer can be sputter deposited and the thickness can be
approximately 600 .ANG.. In other embodiments the thickness of the
NiSi layer can range from 100 .ANG. to 1000 .ANG.. In some
embodiments the NiSi layer can be etched to clean the surface
before additional steps are performed. The NiSi layer 360 can
alternatively be other materials that form a Schottky layer such as
platinum, cobalt, etc. The top layer 365 is formed by depositing
Al/Si/Cu over the NiSi layer 360 and the shield dielectric layer
340 which has been deposited over the field oxide region 320. After
the top layer 365 is formed, a portion of the top layer 365 is
etched to form opening 370. In this etching process, the top layer
365 is etched down to the field oxide region 320. In some
embodiments, the un-reacted nickel can also be etched at this time
thus minimizing potential aluminum spiking over active cells and
reducing the number of processing steps.
[0058] FIG. 3I, which illustrates the partially fabricated HED
rectifier after formation of the top layer 365 with opening 370, as
seen along cutline A-A', includes the substrate 300, the epitaxial
layer 302, the field oxide region 320, the implant region 325,
trenches 335 shield dielectric layer 340, and polysilicon 345, a
NiSi layer 360, a top metal 365, a dielectric layer 375 and a mask
layer 380. The dielectric layer 375 is formed by depositing over
the entire structure illustrated in FIG. 3H a dielectric material.
The dielectric material can be polyimide, BCB, nitride, oxy-nitride
films that act as a dielectric material, polyimide and deposited
silicon nitride, polyimide and deposited silicon dioxide, polyimide
and deposited silicon oxy-nitride, silicon nitride, silicon
oxy-nitride, or silicon dioxide. After the dielectric material is
deposited, a mask layer 380 is applied over the dielectric layer
and a portion of the dielectric layer is etched leaving behind
dielectric material over most of the field oxide region 320 and
over a portion of the top metal but not over the trenches 335. The
device can then be alloyed by subjecting the device to temperatures
ranging between 350.degree. C.-500.degree. C. in the presence of
forming gas or Hydrogen containing gas to allow any interface layer
that may exist between the metal and Si or metal to metal to be
consumed. This alloying forms an improved contact through
interdiffusion between the silicon substrate 300, the NiSi layer
360 and the top layer 365. This alloy step can also is used to
anneal out any surface states (i.e. interfaces trap at the oxide to
silicon interface).
[0059] FIG. 3J illustrates the partially fabricated HED rectifier
shown in FIG. 3I after forming the patterned dielectric layer 375.
FIG. 3J, which illustrates the partially fabricated HED rectifier
after formation of the patterned dielectric layer 375, as seen
along cutline A-A', includes the substrate 300, the epitaxial layer
302, the field oxide region 320, the implant region 325, trenches
335, shield dielectric layer 340, and polysilicon 345, a NiSi layer
360, a top metal 365, a dielectric layer 375 and a solderable top
metal (STM) layer 385. Before the STM layer 385 is formed, the HED
rectifier shown in FIG. 3I is cleaned to remove thin AlO.sub.3
films that may have formed. The STM layer 385 is formed by
depositing a solderable material such as Ti/NiV/Ag, Ta/Cu, tin or
other solderable metals. The STM layer 385 can be formed using
various deposition methods such as electroless deposition. After
the STM layer 385 is deposited, a pattern can be formed on top for
later bonding. In some embodiments, the STM layer 385 can be
further etched or processed using CMP. In some embodiments, the
tops of the dielectric layer 375 and the STM layer 385 are
substantially coplanar.
[0060] FIG. 3K illustrates the partially fabricated HED rectifier
shown in FIG. 3J after forming the STM layer 385, as seen along
cutline A-A', and includes the substrate 300, the epitaxial layer
302, the field oxide region 320, the implant region 325, trenches
335 shield dielectric layer 340, polysilicon 345, NiSi layer 360, a
top metal 365, a dielectric layer 375, an STM layer 385, and a back
metal 390. Before the back layer 390 is formed, the bottom of the
substrate 300 undergoes a mechanical back grinding process that
grinds off a portion the substrate 300. After the grinding process,
the back metal 390 is formed. The back metal 390 can include layers
of Ti, NiV and Ag as well as other metals and is not limited to
these specific metallic films.
[0061] FIG. 4 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarized polysilicon deposited
in trenches and above an epitaxial layer deposited on a substrate.
The semiconductor device made using CMP to planarized the
polysilicon has a planar structure between edge termination to
trenches and trenches to mesa regions to reduce reverse leakage
current caused by non-planarity. The method starts in operation 405
when a substrate is provided. The substrate can be N-Type wafer
with an epitaxial layer deposited on top. Next in operation 440, a
hard mask oxide is grown. The hard mask will be used in subsequent
operations to form various features including trenches 335. In
operation 445 the hard mask is patterned. In operation 450,
trenches 335 are formed using an etch process. In one embodiment
the trenches 335 have a pitch ranging from 0.8-1.0 um, a critical
dimension ranging from 0.4-0.6 um, and a depth ranging from 0.5-5.0
um. However, in other embodiments the trenches can have values for
the pitch, critical dimension, and depth which are outside of these
ranges. In operation 455, the hard mask is removed. The hard mask
can be removed using various techniques or combinations of
techniques such as etching, wet BOE, which just removes the
remaining hard mask oxide, or CMP which planarizes the field to
active regions. In some embodiments, operation 455 is optional and
the hard mask can be left on for future removal post polysilicon
etch.
[0062] In operation 460, the shield dielectric layer 340 is formed
so that it follows the contours of the trench and the substrate.
The shield dielectric layer 340 can be formed by growing the oxide
layer, depositing the oxide layer or combinations of growing and
depositing the oxide. The shield dielectric layer 340 is formed
along the bottom and sidewalls of the trench 335 and along the top
of the epitaxial layer 302, and an implant region 325. The shield
dielectric layer 340 can have a thickness ranging from 200 .ANG. to
5000 .ANG. depending on the breakdown voltage of the device. In one
embodiment, the shield dielectric layer 340 can have a thickness of
approximately 400.+-.50 .ANG.. In some embodiments, the shield
dielectric layer 340 can form a contiguous film along the bottom
and sidewalls of the trench 335 and along the top of the epitaxial
layer 302, and the implant region 325. The shied oxide layer 340
can be formed by exposing the HED rectifier to oxygen diluted in an
inert gas such as argon, helium, or xenon at elevated temperatures.
In operation 465, the polysilicon 345 material is deposited inside
the trench 335 and over the top of the shield dielectric layer 340.
In one embodiment the polysilicon material is amorphous undoped
polysilicon and has a thickness of approximately 5500 .ANG..+-.500
.ANG.. The polysilicon can be doped by several methods, such as
vapor phase doping of polysilicon or implanting of dopant ions with
dopant species such as boron, phosphorous, arsenic (the doping
species are not limited to these examples). In another embodiment,
the polysilicon could be a single crystal polysilicon. In another
embodiment, the polysilicon could be insitu doped polysilicon using
dopant gases during a deposition cycle. In operation 470, excess
polysilicon 335 material is removed and the polysilicon to silicon
mesa regions are planarized. In one embodiment, this planarization
is performed using CMP. The CMP process removes the excess
polysilicon 335 material disposed on top of the shield dielectric
layer 340 outside of the trenches 335. The CMP process can also be
used to remove some of the shield dielectric layer 340 disposed
outside of the trench 335, leaving behind a thinner shield
dielectric layer 340 outside of trenches 335 than inside of
trenches 335. After the partial HED rectifier has been processed
with CMP, the resulting partial HED rectifier has the shield
dielectric layer 340 partially extending above the epitaxial layer
302 and trenches 335 with the polysilicon 345 material filling the
trenches 335 up to the shield dielectric layer 340 and flush with
the top of the shield dielectric layer 340. Planarizing the
polysilicon using CMP generates a substantially planar surface
having substantially planar regions of polysilicon and gate oxide.
The regions of polysilicon and gate oxide formed by planarizing
form a substantially flat contiguous surface.
[0063] Next in operation 472, a field dielectric region 320, which
can be an oxide region, is formed in the epitaxial layer 302 and is
recessed into the epitaxial layer 302 with some of the field
dielectric region 320 being above the epitaxial layer 302 plane. In
one embodiment, the field dielectric region 320 is deposited. In
operation 475, a Schottky metallization layer is deposited. Next in
operation 480, a Schottky barrier silicide is formed. In some
embodiments, the Schottky metallization layer is omitted and
operations 475 and 480 are not used. In operation 485 a top metal
365 containing aluminum is formed. The top metal 365 is formed over
a Schottky metallization layer and over a portion of the gate oxide
layer. In operation 490 a dielectric layer 375 and STM layer 385
are formed. The dielectric can be polyimide, PECVD oxy-nitride,
PECVD nitride, BCB, oxy-nitride films that act as a dielectric
material, polyimide and deposited silicon nitride, polyimide and
deposited silicon dioxide, polyimide and deposited silicon
oxy-nitride, silicon nitride, silicon oxy-nitride, silicon dioxide,
or some other dielectric. The dielectric layer 375 is formed
according to a pattern and the STM layer 385 is formed over the top
metal 365. Finally, in operation 498, the HED rectifier is
completed.
[0064] FIG. 5 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarize a field oxide layer and
using CMP to planarized polysilicon deposited in trenches and above
an epitaxial layer. The semiconductor device made using CMP to
planarize the field oxide layer and the polysilicon has a planar
structure between edge termination to trenches and trenches to mesa
regions to reduce reverse leakage current caused by non-planarity.
The method starts in operation 505 when a substrate is provided.
The substrate can be N-Type wafer with an epitaxial layer deposited
on top. Next in operation 510 a field termination region is created
using LOCOS oxidation methods. Next in operation 515 a pad oxide
layer 305 is formed over the substrate using an oxidation process.
The thickness of the pad oxide layer 305 can range from 200 .ANG.
to 400 .ANG.. In operation 520, a nitride layer 310 is deposited
over the pad oxide layer 305. The thickness of the nitride layer
310 ranges from 1000 .ANG. to 1500 .ANG.. In operation 525, a
pattern is formed in the pad oxide layer 305 and nitride layer 310
using photolithography and etching. The photoresist is also removed
in this operation. After the pattern is formed, in operation 530, a
field oxide region 320 is formed in the epitaxial layer 302 and is
recessed into the epitaxial layer 302 with some of the field oxide
region 320 being above the epitaxial layer 302 plane. In operation
535, the field oxide region is planarized using a CMP etch process
to generate a substantially planar surface having substantially
planar regions of field oxide and epitaxial layer.
[0065] In operation 540, a hard mask oxide is deposited or grown.
The hard mask will be used in subsequent operations to form various
features including trenches 335. In operation 545 the hard mask is
patterned. In operation 550, trenches 335 are formed using an etch
process. In one embodiment the trenches 335 have a pitch ranging
from 0.8-1.0 um, a critical dimension ranging from 0.4-0.6 um, and
a depth ranging from 0.5-5.0 um. However, in other embodiments the
trenches can have values for the pitch, critical dimension, and
depth which are outside of these ranges. In operation 555, the hard
mask is removed. The hard mask can be removed using various
techniques or combinations of techniques such as etching, wet BOE,
which just removes the remaining hard mask oxide with minimum
attack to field oxide, or CMP which planarizes the field to active
regions. In some embodiments, operation 555 is optional and the
hard mask can be left on for future removal post polysilicon
etch.
[0066] In operation 560, the shield dielectric layer 340 is formed
so that it follows the contours of the trench and the substrate.
The shield dielectric layer 340 can be formed by growing the oxide
layer, depositing the oxide layer or combinations of growing and
depositing the oxide. The shield dielectric layer 340 is formed
along the bottom and sidewalls of the trench 335 and along the top
of the epitaxial layer 302, the field oxide region 320 and an
implant region 325. The shield dielectric layer 340 can have a
thickness of approximately 400.+-.50 .ANG.. In some embodiments,
the shield dielectric layer 340 can form a contiguous film along
the bottom and sidewalls of the trench 335 and along the top of the
epitaxial layer 302, the field oxide region 320 and the implant
region 325. The shied oxide layer 340 can be formed by exposing the
HED rectifier to oxygen diluted in an inert gas such as argon,
helium, or xenon at high temperatures. In operation 565, the
polysilicon 345 material is deposited inside the trench 335 and
over the top of the shield dielectric layer 340. The polysilicon
material is amorphous undoped polysilicon and has a thickness of
approximately 5500 .ANG..+-.500 .ANG.. The polysilicon material can
then be doped by implanting boron. In operation 570, excess
polysilicon 335 material is removed and the polysilicon to silicon
mesa regions are planarized. In one embodiment this planarization
is performed using CMP. The CMP process removes the excess
polysilicon 335 material disposed on top of the shield dielectric
layer 340 outside of the trenches 335. The CMP process can also be
used to remove some of the shield dielectric layer 340 disposed
outside of the trench 335, leaving behind a thinner shield
dielectric layer 340 outside of trenches 335 than inside of
trenches 335. After the partial HED rectifier has been processed
with CMP, the resulting partial HED rectifier has the shield
dielectric layer 340 partially extending above the epitaxial layer
302 and trenches 335 with the polysilicon 345 material filling the
trenches 335 up to the shield dielectric layer 340 and flush with
the top of the shield dielectric layer 340. Planarizing the
polysilicon using CMP generates a substantially planar surface
having substantially planar regions of polysilicon, gate oxide and
field oxide. The regions of polysilicon, gate oxide and field oxide
formed by planarizing form a substantially flat contiguous surface.
This process can be performed with or without a photo pattern.
[0067] In operation 575, a Schottky metallization layer is
deposited. Next in operation 580, a Schottky barrier silicide is
formed. In operation 585 a top metal 365 containing aluminum is
formed. The top metal 365 is formed over a Schottky metallization
layer and over a portion of the gate oxide layer. In operation 590
a dielectric layer 375 and STM layer 385 are formed. The dielectric
layer 375 is formed according to a pattern and the STM layer 385 is
formed over the top metal 365. In some embodiments the dielectric
layer 375 is polyimide. Alternatively, the dielectric layer 375 can
be PECVD oxy-nitride, PECVD nitride, BCB, oxy-nitride films that
act as a dielectric material, polyimide and deposited silicon
nitride, polyimide and deposited silicon dioxide, polyimide and
deposited silicon oxy-nitride, silicon nitride, silicon
oxy-nitride, silicon dioxide, or some other dielectric. Finally, in
operation 598, the HED rectifier is completed.
[0068] FIG. 6 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarize an oxide layer. The
semiconductor device made using CMP to planarize the oxide layer
has a planar structure between edge termination to trenches and
trenches to mesa regions to reduce reverse leakage current caused
by non-planarity. The method starts in operation 605 when a
substrate is provided. The substrate can be an N-Type wafer with an
epitaxial layer deposited on top. Next in operation 610 a field
termination region is created using LOCOS oxidation methods. Next
in operation 615 a pad oxide layer 305 is formed over the substrate
using an oxidation process. The thickness of the pad oxide layer
305 can range from 200 .ANG. to 400 .ANG.. In operation 620, a
nitride layer 310 is deposited over the pad oxide layer 305. The
thickness of the nitride layer 310 ranges from 1000 .ANG. to 1500
.ANG.. In operation 625, a pattern is formed in the pad oxide layer
305 and nitride layer 310 using photolithography and etching. The
photoresist is also removed in this operation. After the pattern is
formed, in operation 630, a field oxide region 320 is formed in the
epitaxial layer 302 and is recessed into the epitaxial layer 302
with some of the field oxide region 320 being above the epitaxial
layer 302 plane. In operation 635, the field oxide region is
planarized using a CMP etch process to generate a substantially
planar surface having substantially planar regions of field oxide
and epitaxial layer.
[0069] In operation 640, a hard mask oxide is grown. The hard mask
will be used in subsequent operations to form various features
including trenches 335. In operation 645 the hard mask is
patterned. In operation 650, trenches 335 are formed using an etch
process. In one embodiment the trenches 335 have a pitch ranging
from 0.8-1.0 um, a critical dimension ranging from 0.4-0.6 um, and
a depth ranging from 0.5-5.0 um. However, in other embodiments the
trenches can have values for the pitch, critical dimension, and
depth which are outside of these ranges. In operation 655, the hard
mask is removed. The hard mask can be removed using various
techniques or combinations of techniques such as etching, wet BOE,
which just removes the remaining hard mask oxide with minimum
attack to field oxide, or CMP which planarizes the field to active
regions. In some embodiments, operation 655 is optional and the
hard mask can be left on for future removal post polysilicon
etch.
[0070] In operation 660, the shield dielectric layer 340 is formed
so that it follows the contours of the trench and the substrate.
The shield dielectric layer 340 can be formed by growing the oxide
layer, depositing the oxide layer or combinations of growing and
depositing the oxide. The shield dielectric layer 340 is formed
along the bottom and sidewalls of the trench 335 and along the top
of the epitaxial layer 302, the field oxide region 320 and an
implant region 325. The shield dielectric layer 340 can have a
thickness of approximately 400.+-.50 .ANG.. In some embodiments,
the shield dielectric layer 340 can form a contiguous film along
the bottom and sidewalls of the trench 335 and along the top of the
epitaxial layer 302, the field oxide region 320 and the implant
region 325. The shied oxide layer 340 can be formed by exposing the
HED rectifier to oxygen diluted in an inert gas such as argon,
helium, or xenon at high temperatures. In operation 665, the
polysilicon 345 material is deposited inside the trench 335 and
over the top of the shield dielectric layer 340. The polysilicon
material is amorphous undoped polysilicon and has a thickness of
approximately 5500 .ANG..+-.500 .ANG.. The polysilicon material can
then be doped by implanting boron. In operation 670, excess
polysilicon 335 material is removed. In one embodiment, the excess
polysilicon 335 is removed using an Oxide/Nitride/Oxide (ONO) etch
process. This process can be performed with or without a photo
pattern.
[0071] In operation 675, a Schottky metallization layer is
deposited. Next in operation 680, a Schottky barrier silicide is
formed. In operation 685 a top metal 365 containing aluminum is
formed. The top metal 365 is formed over a Schottky metallization
layer and over a portion of the gate oxide layer. In operation 690
a dielectric layer 375 and STM layer 385 are formed. The dielectric
layer 375 can be polyimide, PECVD oxy-nitride, PECVD nitride, BCB,
oxy-nitride films that act as a dielectric material, polyimide and
deposited silicon nitride, polyimide and deposited silicon dioxide,
polyimide and deposited silicon oxy-nitride, silicon nitride,
silicon oxy-nitride, silicon dioxide, or some other dielectric. The
dielectric layer 375 is formed according to a pattern and the STM
layer 385 is formed over the top metal 365. Finally, in operation
698, the HED rectifier is completed.
[0072] FIG. 7 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarize a field oxide layer,
using CMP to planarized polysilicon deposited in trenches and above
an epitaxial layer, and using CMP to planarized a STM layer. The
semiconductor device made using CMP to planarized the field oxide
layer, the polysilicon and the STM layer has a planar structure
between edge termination to trenches and trenches to mesa regions
to reduce reverse leakage current caused by non-planarity. The
method starts in operation 705 when a substrate is provided. The
substrate can be an N-Type wafer with an epitaxial layer deposited
on top. Next in operation 710 a field termination region is created
using LOCOS oxidation methods. Next in operation 715 a pad oxide
layer 305 is formed over the substrate using an oxidation process.
The thickness of the pad oxide layer 305 can range from 200 .ANG.
to 400 .ANG.. In operation 720, a nitride layer 310 is deposited
over the pad oxide layer 305. The thickness of the nitride layer
310 ranges from 1000 .ANG. to 1500 .ANG.. In operation 725, a
pattern is formed in the pad oxide layer 305 and nitride layer 310
using photolithography and etching. The photoresist is also removed
in this operation. After the pattern is formed, in operation 730, a
field oxide region 320 is formed in the epitaxial layer 302 and is
recessed into the epitaxial layer 302 with some of the field oxide
region 320 being above the epitaxial layer 302 plane. In operation
735, the field oxide region is planarized using a CMP etch process
to generate a substantially planar surface having substantially
planar regions of field oxide and epitaxial layer.
[0073] In operation 740, a hard mask oxide is grown. The hard mask
will be used in subsequent operations to form various features
including trenches 335. In operation 745 the hard mask is
patterned. In operation 750, trenches 335 are formed using an etch
process. In one embodiment the trenches 335 have a pitch ranging
from 0.8-1.0 um, a critical dimension ranging from 0.4-0.6 um, and
a depth ranging from 0.5-5.0 um. However, in other embodiments the
trenches can have values for the pitch, critical dimension, and
depth which are outside of these ranges. In operation 755, the hard
mask is removed. The hard mask can be removed using various
techniques or combinations of techniques such as etching, wet BOE,
which just removes the remaining hard mask oxide with minimum
attack to field oxide, or CMP which planarizes the field to active
regions. In some embodiments, operation 755 is optional and the
hard mask can be left on for future removal post polysilicon
etch.
[0074] In operation 760, the shield dielectric layer 340 is formed
so that it follows the contours of the trench and the substrate.
The shield dielectric layer 340 can be formed by growing the oxide
layer, depositing the oxide layer or combinations of growing and
depositing the oxide. The shield dielectric layer 340 is formed
along the bottom and sidewalls of the trench 335 and along the top
of the epitaxial layer 302, the field oxide region 320 and an
implant region 325. The shield dielectric layer 340 can have a
thickness of approximately 400.+-.50 .ANG.. In some embodiments,
the shield dielectric layer 340 can form a contiguous film along
the bottom and sidewalls of the trench 335 and along the top of the
epitaxial layer 302, the field oxide region 320 and the implant
region 325. The shied oxide layer 340 can be formed by exposing the
HED rectifier to oxygen diluted in an inert gas such as argon,
helium, or xenon at high temperatures. In operation 765, the
polysilicon 345 material is deposited inside the trench 335 and
over the top of the shield dielectric layer 340. The polysilicon
material is amorphous undoped polysilicon and has a thickness of
approximately 5500 .ANG..+-.500 .ANG.. The polysilicon material can
then be doped by implanting boron. In operation 770, excess
polysilicon 335 material is removed and the polysilicon to silicon
mesa regions are planarized. In one embodiment this planarization
is performed using CMP. The CMP process removes the excess
polysilicon 335 material disposed on top of the shield dielectric
layer 340 outside of the trenches 335. The CMP process can also be
used to remove some of the shield dielectric layer 340 disposed
outside of the trench 335, leaving behind a thinner shield
dielectric layer 340 outside of trenches 335 than inside of
trenches 335. After the partial HED rectifier has been processed
with CMP, the resulting partial HED rectifier has the shield
dielectric layer 340 partially extending above the epitaxial layer
302 and trenches 335 with the polysilicon 345 material filling the
trenches 335 up to the shield dielectric layer 340 and flush with
the top of the shield dielectric layer 340. Planarizing the
polysilicon using CMP generates a substantially planar surface
having substantially planar regions of polysilicon, gate oxide and
field oxide. The regions of polysilicon, gate oxide and field oxide
formed by planarizing form a substantially flat contiguous surface.
This process can be performed with or without a photo pattern.
[0075] In operation 775, a Schottky metallization layer is
deposited. Next in operation 780, a Schottky barrier silicide is
formed. In operation 785 a top metal 365 containing aluminum is
formed. The top metal 365 is formed over a Schottky metallization
layer and over a portion of the gate oxide layer. In operation 790
a dielectric layer 375 and STM layer 385 are formed. The dielectric
layer 375 is formed according to a pattern and the STM layer 385 is
formed over the top metal 365. In some embodiments the dielectric
layer 375 is polyimide. Alternatively, the dielectric layer 375 can
be PECVD oxy-nitride, PECVD nitride, BCB, oxy-nitride films that
act as a dielectric material, polyimide and deposited silicon
nitride, polyimide and deposited silicon dioxide, polyimide and
deposited silicon oxy-nitride, silicon nitride, silicon
oxy-nitride, silicon dioxide, or some other dielectric. In
operation 795, STM layer 385 material is removed using CMP. The CMP
process removes the excess STM layer 385 material disposed on top
of the top metal 365 and next to the dielectric layer 375. After
the partial HED rectifier has been processed with CMP, the
resulting partial HED rectifier has dielectric layer 375 and the
STM layer 385 substantially co-planar so that both form a flush top
surface. Planarizing the STM layer 385 using CMP generates a
substantially planar surface having substantially planar regions of
dielectric layer 375 material and STM layer 385 material. The
regions of dielectric layer 375 material and STM layer 385 material
formed by planarizing form a substantially flat contiguous surface.
Finally, in operation 798, the HED rectifier is completed.
[0076] FIG. 8 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarize polysilicon deposited
in trenches and above an epitaxial layer and using CMP to
planarized a STM layer. The semiconductor device made using CMP to
planarize the polysilicon and the STM layer has a planar structure
between edge termination to trenches and trenches to mesa regions
to reduce reverse leakage current caused by non-planarity. The
method starts in operation 805 when a substrate is provided. The
substrate can be an N-Type wafer with an epitaxial layer deposited
on top. Next in operation 840, a hard mask oxide is grown. The hard
mask will be used in subsequent operations to form various features
including trenches 335. In operation 845 the hard mask is
patterned. In operation 850, trenches 335 are formed using an etch
process. In one embodiment the trenches 335 have a pitch ranging
from 0.8-1.0 um, a critical dimension ranging from 0.4-0.6 um, and
a depth ranging from 0.5-5.0 um. However, in other embodiments the
trenches can have values for the pitch, critical dimension, and
depth which are outside of these ranges. In operation 855, the hard
mask is removed. The hard mask can be removed using various
techniques or combinations of techniques such as etching, wet BOE,
which just removes the remaining hard mask oxide, or CMP which
planarizes the field to active regions. In some embodiments,
operation 855 is optional and the hard mask can be left on for
future removal post polysilicon etch.
[0077] In operation 860, the shield dielectric layer 340 is formed
so that it follows the contours of the trench and the substrate.
The shield dielectric layer 340 can be formed by growing the oxide
layer, depositing the oxide layer or combinations of growing and
depositing the oxide. The shield dielectric layer 340 is formed
along the bottom and sidewalls of the trench 335 and along the top
of the epitaxial layer 302, and an implant region 325. The shield
dielectric layer 340 can have a thickness of approximately
400.+-.50 .ANG.. In some embodiments, the shield dielectric layer
340 can form a contiguous film along the bottom and sidewalls of
the trench 335 and along the top of the epitaxial layer 302, and
the implant region 325. The shied oxide layer 340 can be formed by
exposing the HED rectifier to oxygen diluted in an inert gas such
as argon, helium, or xenon at high temperatures. In operation 865,
the polysilicon 345 material is deposited inside the trench 335 and
over the top of the shield dielectric layer 340. The polysilicon
material is amorphous undoped polysilicon and has a thickness of
approximately 5500 .ANG..+-.500 .ANG.. The polysilicon material can
then be doped by implanting boron. In operation 870, excess
polysilicon 335 material is removed and the polysilicon to silicon
mesa regions are planarized. In one embodiment this planarization
is performed using CMP. The CMP process removes the excess
polysilicon 335 material disposed on top of the shield dielectric
layer 340 outside of the trenches 335. The CMP process can also be
used to remove some of the shield dielectric layer 340 disposed
outside of the trench 335, leaving behind a thinner shield
dielectric layer 340 outside of trenches 335 than inside of
trenches 335. After the partial HED rectifier has been processed
with CMP, the resulting partial HED rectifier has the shield
dielectric layer 340 partially extending above the epitaxial layer
302 and trenches 335 with the polysilicon 345 material filling the
trenches 335 up to the shield dielectric layer 340 and flush with
the top of the shield dielectric layer 340. Planarizing the
polysilicon using CMP generates a substantially planar surface
having substantially planar regions of polysilicon, and gate oxide.
The regions of polysilicon and gate oxide formed by planarizing
form a substantially flat contiguous surface. This process can be
performed with or without a photo pattern.
[0078] Next in operation 872, a field dielectric region 320, which
can be an oxide region, is formed in the epitaxial layer 302 and is
recessed into the epitaxial layer 302 with some of the field
dielectric region 320 being above the epitaxial layer 302 plane. In
operation 875, a Schottky metallization layer is deposited. Next in
operation 880, a Schottky barrier silicide is formed. In operation
885 a top metal 365 containing aluminum is formed. The top metal
365 is formed over a Schottky metallization layer and over a
portion of the gate oxide layer. In operation 890 a dielectric
layer 375 and STM layer 385 are formed. In some embodiments the
dielectric layer 375 is polyimide. Alternatively, the dielectric
layer 375 can be PECVD oxy-nitride, PECVD nitride, BCB, oxy-nitride
films that act as a dielectric material, polyimide and deposited
silicon nitride, polyimide and deposited silicon dioxide, polyimide
and deposited silicon oxy-nitride, silicon nitride, silicon
oxy-nitride, silicon dioxide, or some other dielectric. The
dielectric layer 375 is formed according to a pattern and the STM
layer 385 is formed over the top metal 365. In operation 895, STM
layer 385 material is removed using CMP. The CMP process removes
the excess STM layer 385 material disposed on top of the top metal
365 and next to the dielectric layer 375. After the partial HED
rectifier has been processed with CMP, the resulting partial HED
rectifier has dielectric layer 375 and the STM layer 385
substantially co-planar so that both form a flush top surface.
Planarizing the STM layer 385 using CMP generates a substantially
planar surface having substantially planar regions of dielectric
layer 375 material and STM layer 385 material. The regions of
dielectric layer 375 material and STM layer 385 material formed by
planarizing form a substantially flat contiguous surface. Finally,
in operation 898, the HED rectifier is completed.
[0079] FIG. 9 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarize an oxide layer and
using CMP to planarized a STM layer. The semiconductor device made
using CMP to planarize the oxide layer and the STM layer has a
planar structure between edge termination to trenches and trenches
to mesa regions to reduce reverse leakage current caused by
non-planarity. The method starts in operation 905 when a substrate
is provided. The substrate can be an N-Type wafer with an epitaxial
layer deposited on top. Next in operation 910 a field termination
region is created using LOCOS oxidation methods. Next in operation
915 a pad oxide layer 305 is formed over the substrate using an
oxidation process. The thickness of the pad oxide layer 305 can
range from 200 .ANG. to 400 .ANG.. In operation 920, a nitride
layer 310 is deposited over the pad oxide layer 305. The thickness
of the nitride layer 310 ranges from 1000 .ANG. to 1500 .ANG.. In
operation 925, a pattern is formed in the pad oxide layer 305 and
nitride layer 310 using photolithography and etching. The
photoresist is also removed in this operation. After the pattern is
formed, in operation 930, a field oxide region 320 is formed in the
epitaxial layer 302 and is recessed into the epitaxial layer 302
with some of the field oxide region 320 being above the epitaxial
layer 302 plane. In operation 935, the field oxide region is
planarized using a CMP etch process to generate a substantially
planar surface having substantially planar regions of field oxide
and epitaxial layer.
[0080] In operation 940, a hard mask oxide is grown. The hard mask
will be used in subsequent operations to form various features
including trenches 335. In operation 945 the hard mask is
patterned. In operation 950, trenches 335 are formed using an etch
process. In one embodiment the trenches 335 have a pitch ranging
from 0.8-1.0 um, a critical dimension ranging from 0.4-0.6 um, and
a depth ranging from 0.5-5.0 um. However, in other embodiments the
trenches can have values for the pitch, critical dimension, and
depth which are outside of these ranges. In operation 955, the hard
mask is removed. The hard mask can be removed using various
techniques or combinations of techniques such as etching, wet BOE,
which just removes the remaining hard mask oxide with minimum
attack to field oxide, or CMP which planarizes the field to active
regions. In some embodiments, operation 955 is optional and the
hard mask can be left on for future removal post polysilicon
etch.
[0081] In operation 960, the shield dielectric layer 340 is formed
so that it follows the contours of the trench and the substrate.
The shield dielectric layer 340 can be formed by growing the oxide
layer, depositing the oxide layer or combinations of growing and
depositing the oxide. The shield dielectric layer 340 is formed
along the bottom and sidewalls of the trench 335 and along the top
of the epitaxial layer 302, the field oxide region 320 and an
implant region 325. The shield dielectric layer 340 can have a
thickness of approximately 400.+-.50 .ANG.. In some embodiments,
the shield dielectric layer 340 can form a contiguous film along
the bottom and sidewalls of the trench 335 and along the top of the
epitaxial layer 302, the field oxide region 320 and the implant
region 325. The shied oxide layer 340 can be formed by exposing the
HED rectifier to oxygen diluted in an inert gas such as argon,
helium, or xenon at high temperatures. In operation 965, the
polysilicon 345 material is deposited inside the trench 335 and
over the top of the shield dielectric layer 340. The polysilicon
material is amorphous undoped polysilicon and has a thickness of
approximately 5500 .ANG..+-.500 .ANG.. The polysilicon material can
then be doped by implanting boron. In operation 970, excess
polysilicon 335 material is removed. In one embodiment, the excess
polysilicon 335 is removed using an ONO etch process. This process
can be performed with or without a photo pattern.
[0082] In operation 975, a Schottky metallization layer is
deposited. Next in operation 980, a Schottky barrier silicide is
formed. In operation 985 a top metal 365 containing aluminum is
formed. The top metal 365 is formed over a Schottky metallization
layer and over a portion of the gate oxide layer. In operation 990
a dielectric layer 375 and STM layer 385 are formed. The dielectric
layer 375 is formed according to a pattern and the STM layer 385 is
formed over the top metal 365. In operation 995, STM layer 385
material is removed using CMP. The CMP process removes the excess
STM layer 385 material disposed on top of the top metal 365 and
next to the dielectric layer 375. After the partial HED rectifier
has been processed with CMP, the resulting partial HED rectifier
has dielectric layer 375 and the STM layer 385 substantially
co-planar so that both form a flush top surface. Planarizing the
STM layer 385 using CMP generates a substantially planar surface
having substantially planar regions of dielectric layer 375
material and STM layer 385 material. The regions of dielectric
layer 375 material and STM layer 385 material formed by planarizing
form a substantially flat contiguous surface. In some embodiments
the dielectric layer 375 is polyimide. Alternatively, the
dielectric layer 375 can be PECVD oxy-nitride, PECVD nitride, BCB,
oxy-nitride films that act as a dielectric material, polyimide and
deposited silicon nitride, polyimide and deposited silicon dioxide,
polyimide and deposited silicon oxy-nitride, silicon nitride,
silicon oxy-nitride, silicon dioxide, or some other dielectric.
Finally, in operation 998, the HED rectifier is completed.
[0083] FIG. 10 is a flowchart illustrating a method of forming a
semiconductor device using CMP to planarized a STM layer. The
semiconductor device made using CMP to planarize the STM layer has
a planar structure between edge termination to trenches and
trenches to mesa regions to reduce reverse leakage current caused
by non-planarity. The method starts in operation 1005 when a
substrate is provided. The substrate can be an N-Type wafer with an
epitaxial layer deposited on top. Next in operation 1040, a hard
mask oxide is grown. The hard mask will be used in subsequent
operations to form various features including trenches 335. In
operation 1045 the hard mask is patterned. In operation 1050,
trenches 335 are formed using an etch process. In one embodiment
the trenches 335 have a pitch ranging from 0.8-1.0 um, a critical
dimension ranging from 0.4-0.6 um, and a depth ranging from 0.5-5.0
um. However, in other embodiments the trenches can have values for
the pitch, critical dimension, and depth which are outside of these
ranges. In operation 1055, the hard mask is removed. The hard mask
can be removed using various techniques or combinations of
techniques such as etching, wet BOE, which just removes the
remaining hard mask oxide, or CMP which planarizes the field to
active regions. In some embodiments, operation 1055 is optional and
the hard mask can be left on for future removal post polysilicon
etch.
[0084] In operation 1060, the shield dielectric layer 340 is formed
so that it follows the contours of the trench and the substrate.
The shield dielectric layer 340 can be formed by growing the oxide
layer, depositing the oxide layer or combinations of growing and
depositing the oxide. The shield dielectric layer 340 is formed
along the bottom and sidewalls of the trench 335 and along the top
of the epitaxial layer 302, and an implant region 325. The shield
dielectric layer 340 can have a thickness of approximately
400.+-.50 .ANG.. In some embodiments, the shield dielectric layer
340 can form a contiguous film along the bottom and sidewalls of
the trench 335 and along the top of the epitaxial layer 302, and
the implant region 325. The shied oxide layer 340 can be formed by
exposing the HED rectifier to oxygen diluted in an inert gas such
as argon, helium, or xenon at high temperatures. In operation 1065,
the polysilicon 345 material is deposited inside the trench 335 and
over the top of the shield dielectric layer 340. The polysilicon
material is amorphous undoped polysilicon and has a thickness of
approximately 5500 .ANG..+-.500 .ANG.. The polysilicon material can
then be doped by implanting boron. In operation 1070, excess
polysilicon 335 material is removed. In one embodiment, the excess
polysilicon 335 is removed using an ONO etch process. This process
can be performed with or without a photo pattern.
[0085] Next in operation 1072, a field dielectric region 320, which
can be an oxide region, is formed in the epitaxial layer 302 and is
recessed into the epitaxial layer 302 with some of the field
dielectric region 320 being above the epitaxial layer 302 plane. In
operation 1075, a Schottky metallization layer is deposited. Next
in operation 1080, a Schottky barrier silicide is formed. In
operation 1085 a top metal 365 containing aluminum is formed. The
top metal 365 is formed over a Schottky metallization layer and
over a portion of the gate oxide layer. In operation 1090 a
dielectric layer 375 and STM layer 385 are formed. In some
embodiments the dielectric layer 375 is polyimide. Alternatively,
the dielectric layer 375 can be PECVD oxy-nitride, PECVD nitride,
BCB, oxy-nitride films that act as a dielectric material, polyimide
and deposited silicon nitride, polyimide and deposited silicon
dioxide, polyimide and deposited silicon oxy-nitride, silicon
nitride, silicon oxy-nitride, silicon dioxide, or some other
dielectric. The dielectric layer 375 is formed according to a
pattern and the STM layer 385 is formed over the top metal 365. In
operation 1095, STM layer 385 material is removed using CMP. The
CMP process removes the excess STM layer 385 material disposed on
top of the top metal 365 and next to the dielectric layer 375.
After the partial HED rectifier has been processed with CMP, the
resulting partial HED rectifier has dielectric layer 375 and the
STM layer 385 substantially co-planar so that both form a flush top
surface. Planarizing the STM layer 385 using CMP generates a
substantially planar surface having substantially planar regions of
dielectric layer 375 material and STM layer 385 material. The
regions of dielectric layer 375 material and STM layer 385 material
formed by planarizing form a substantially flat contiguous surface.
Finally, in operation 1098, the HED rectifier is completed.
[0086] FIG. 11 illustrates a cross section view of a semiconductor
device made along cutline A-A' illustrated in FIG. 2C, in
accordance with the methods described above with reference to FIGS.
3-10. The semiconductor device illustrated in FIG. 11 is an HED
rectifier made using CMP to planarized the field oxide layer, the
polysilicon and/or the STM layer. The semiconductor device has a
planar structure between edge termination to trenches and trenches
to mesa regions to reduce reverse leakage current caused by
non-planarity. The semiconductor device includes a substrate 1100,
an epitaxial layer 1102, a field oxide region 1120, an implant
region 1125, trenches 1135, a shield dielectric layer 1140,
polysilicon 1145, a NiSi layer 1160, a top metal 1165, a dielectric
layer 1175, an STM layer 1185, and a back metal 1190. The substrate
1100 can be an N-type wafer which has been previously scribed with
a laser to include information such as device type, lot number, and
wafer number. The substrate 1100 can also be a highly doped N+
substrate. The epitaxial layer 1102, which is formed over the
substrate 1100, can be made of the same conductivity or different
conductivity than the substrate 1100. MOSFETs are formed when the
substrate 1100 and epitaxial layer 1102 are of the same
conductivity type, and IGBTs are formed when the substrate 1100 has
the opposite conductivity type to that of the epitaxial layer 1102.
In some embodiments, the epitaxial layer 1102 is made of lightly
doped n-type material. The field oxide region 1120 extends into the
epitaxial layer 1102 and has a top surface that is coplanar with a
top surface of the epitaxial layer 1102. In some embodiments this
coplanar surface is produced using CMP.
[0087] The implant region 1125 is produced by implanting boron into
the epitaxial layer 1102. In some embodiments, the implantation
energy is increased in order to produce a P-iso under the field
oxide layer 1120. The trenches 1135 are formed by etching and have
a final thickness that ranges from about 2250 .ANG. to about 2450
.ANG. and the final depth that ranges from about 1275 nm to about
1555 nm. The width and depth of the trenches can vary outside of
these ranges. In one embodiment the depth of the trenches is
approximately 1415 nm. The shield dielectric layer 1140 can have a
thickness of approximately 400.+-.50 .ANG. and follows the contours
of the trench and the substrate. The shield dielectric layer 1140
is grown so that it lines the bottom and sidewalls of the trench
1135 and along the top of the epitaxial layer 1102, the field oxide
region 1120 and an implant region 1125. In some embodiments, the
shield dielectric layer 1140 can form a contiguous film along the
bottom and sidewalls of the trench 1135 and along the top of the
epitaxial layer 1102, the field oxide region 1120 and the implant
region 1125. The polysilicon material 1145 which is deposited into
the trenches 1135 and over the shield dielectric layer 1140 is
amorphous undoped polysilicon and has a thickness of approximately
5500 .ANG..+-.500 .ANG.. The polysilicon material 1145 is then
doped by implanting boron. The polysilicon material 1145
substantially fills the trenches 1135 and produces a structure
where the polysilicon material 1145 has a top surface that is
coplanar with top surfaces of the gate oxide and/or the field oxide
1120. In some embodiments this coplanar surface is produced using
CMP.
[0088] The NiSi layer 1160 is formed by first depositing nickel
over the planarized region having exposed polysilicon 1145 in the
trenches 1135 and exposed silicon which form the mesas between the
trenches 1135, and then subjecting the nickel to external heat
generated by sources such as rapid thermal anneal (RTA), hot chuck,
and furnace sources (other heat sources can be used and the heat
sources are not limited to these). NiSi forms when the nickel is
exposed to the silicon from substrate 1100 and is subjected to
external heat generated by sources such as rapid thermal anneal
(RTA), hot chuck, and furnace sources (other heat sources can be
used and the heat sources are not limited to these). In some
embodiments un-reacted residual nickel is present. In some
embodiments that Nickel layer can be sputter deposited and the
thickness can be approximately 600 .ANG.. The top layer 1165 is
made of Al/Si/Cu, which is formed over the NiSi layer 1160 and the
shield dielectric layer 1140, which has been deposited over the
field oxide region 1120. The top layer 1165 includes an opening
which is filled with dielectric layer 1175. In one embodiment, the
dielectric layer 1175 is polyimide. Alternatively, the dielectric
layer 1175 can be PECVD oxy-nitride, PECVD nitride, BCB,
oxy-nitride films that act as a dielectric material, polyimide and
deposited silicon nitride, polyimide and deposited silicon dioxide,
polyimide and deposited silicon oxy-nitride, silicon nitride,
silicon oxy-nitride, silicon dioxide, or some other dielectric. The
dielectric layer 1175 is deposited over a portion of the top layer
1165 and fills the opening. The STM layer 1185 is made of a
solderable material such as Ti/NiV/Ag, Ta/Cu, tin or other
solderable metals. The STM layer 1185 can be formed using various
deposition methods such as electroless deposition. The dielectric
layer 1175 and the STM layer 1185 form a substantially planar
surface which can be produced using CMP. The back metal 1190 is
formed on the back side of the substrate 1100. The back metal 1190
can include layers of Ti, NiV and Ag or other solderable metals,
which are formed on the back of the substrate 1100 after the back
of the substrate 1100 has undergone a mechanical back grinding
process that grinds off a portion the substrate 1100.
[0089] Although specific embodiments of the invention have been
described, various modifications, alterations, alternative
constructions, and equivalents are also encompassed within the
scope of the invention. The described invention is not restricted
to operation within certain specific embodiments, but is free to
operate within other embodiments configurations as it should be
apparent to those skilled in the art that the scope of the present
invention is not limited to the described series of transactions
and steps.
[0090] The specification and drawings are, accordingly, to be
regarded in an illustrative rather than a restrictive sense. It
will, however, be evident that additions, subtractions, deletions,
and other modifications and changes may be made thereunto without
departing from the broader spirit and scope of the invention as set
forth in the claims.
* * * * *